Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for msm7k serial device and console
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 */
9
10#include <linux/kernel.h>
11#include <linux/atomic.h>
12#include <linux/dma-mapping.h>
13#include <linux/dmaengine.h>
14#include <linux/module.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/console.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22#include <linux/serial_core.h>
23#include <linux/slab.h>
24#include <linux/clk.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/wait.h>
30
31#define UART_MR1 0x0000
32
33#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
34#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
35#define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
36#define UART_MR1_RX_RDY_CTL BIT(7)
37#define UART_MR1_CTS_CTL BIT(6)
38
39#define UART_MR2 0x0004
40#define UART_MR2_ERROR_MODE BIT(6)
41#define UART_MR2_BITS_PER_CHAR 0x30
42#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
43#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
44#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
45#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
46#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
47#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
48#define UART_MR2_PARITY_MODE_NONE 0x0
49#define UART_MR2_PARITY_MODE_ODD 0x1
50#define UART_MR2_PARITY_MODE_EVEN 0x2
51#define UART_MR2_PARITY_MODE_SPACE 0x3
52#define UART_MR2_PARITY_MODE 0x3
53
54#define UART_CSR 0x0008
55
56#define UART_TF 0x000C
57#define UARTDM_TF 0x0070
58
59#define UART_CR 0x0010
60#define UART_CR_CMD_NULL (0 << 4)
61#define UART_CR_CMD_RESET_RX (1 << 4)
62#define UART_CR_CMD_RESET_TX (2 << 4)
63#define UART_CR_CMD_RESET_ERR (3 << 4)
64#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
65#define UART_CR_CMD_START_BREAK (5 << 4)
66#define UART_CR_CMD_STOP_BREAK (6 << 4)
67#define UART_CR_CMD_RESET_CTS (7 << 4)
68#define UART_CR_CMD_RESET_STALE_INT (8 << 4)
69#define UART_CR_CMD_PACKET_MODE (9 << 4)
70#define UART_CR_CMD_MODE_RESET (12 << 4)
71#define UART_CR_CMD_SET_RFR (13 << 4)
72#define UART_CR_CMD_RESET_RFR (14 << 4)
73#define UART_CR_CMD_PROTECTION_EN (16 << 4)
74#define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
75#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
76#define UART_CR_CMD_FORCE_STALE (4 << 8)
77#define UART_CR_CMD_RESET_TX_READY (3 << 8)
78#define UART_CR_TX_DISABLE BIT(3)
79#define UART_CR_TX_ENABLE BIT(2)
80#define UART_CR_RX_DISABLE BIT(1)
81#define UART_CR_RX_ENABLE BIT(0)
82#define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
83
84#define UART_IMR 0x0014
85#define UART_IMR_TXLEV BIT(0)
86#define UART_IMR_RXSTALE BIT(3)
87#define UART_IMR_RXLEV BIT(4)
88#define UART_IMR_DELTA_CTS BIT(5)
89#define UART_IMR_CURRENT_CTS BIT(6)
90#define UART_IMR_RXBREAK_START BIT(10)
91
92#define UART_IPR_RXSTALE_LAST 0x20
93#define UART_IPR_STALE_LSB 0x1F
94#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
95#define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
96
97#define UART_IPR 0x0018
98#define UART_TFWR 0x001C
99#define UART_RFWR 0x0020
100#define UART_HCR 0x0024
101
102#define UART_MREG 0x0028
103#define UART_NREG 0x002C
104#define UART_DREG 0x0030
105#define UART_MNDREG 0x0034
106#define UART_IRDA 0x0038
107#define UART_MISR_MODE 0x0040
108#define UART_MISR_RESET 0x0044
109#define UART_MISR_EXPORT 0x0048
110#define UART_MISR_VAL 0x004C
111#define UART_TEST_CTRL 0x0050
112
113#define UART_SR 0x0008
114#define UART_SR_HUNT_CHAR BIT(7)
115#define UART_SR_RX_BREAK BIT(6)
116#define UART_SR_PAR_FRAME_ERR BIT(5)
117#define UART_SR_OVERRUN BIT(4)
118#define UART_SR_TX_EMPTY BIT(3)
119#define UART_SR_TX_READY BIT(2)
120#define UART_SR_RX_FULL BIT(1)
121#define UART_SR_RX_READY BIT(0)
122
123#define UART_RF 0x000C
124#define UARTDM_RF 0x0070
125#define UART_MISR 0x0010
126#define UART_ISR 0x0014
127#define UART_ISR_TX_READY BIT(7)
128
129#define UARTDM_RXFS 0x50
130#define UARTDM_RXFS_BUF_SHIFT 0x7
131#define UARTDM_RXFS_BUF_MASK 0x7
132
133#define UARTDM_DMEN 0x3C
134#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
135#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
136
137#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
138#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
139
140#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
141#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
142
143#define UARTDM_DMRX 0x34
144#define UARTDM_NCF_TX 0x40
145#define UARTDM_RX_TOTAL_SNAP 0x38
146
147#define UARTDM_BURST_SIZE 16 /* in bytes */
148#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
149#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
150#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
151
152enum {
153 UARTDM_1P1 = 1,
154 UARTDM_1P2,
155 UARTDM_1P3,
156 UARTDM_1P4,
157};
158
159struct msm_dma {
160 struct dma_chan *chan;
161 enum dma_data_direction dir;
162 dma_addr_t phys;
163 unsigned char *virt;
164 dma_cookie_t cookie;
165 u32 enable_bit;
166 unsigned int count;
167 struct dma_async_tx_descriptor *desc;
168};
169
170struct msm_port {
171 struct uart_port uart;
172 char name[16];
173 struct clk *clk;
174 struct clk *pclk;
175 unsigned int imr;
176 int is_uartdm;
177 unsigned int old_snap_state;
178 bool break_detected;
179 struct msm_dma tx_dma;
180 struct msm_dma rx_dma;
181};
182
183#define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
184
185static
186void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
187{
188 writel_relaxed(val, port->membase + off);
189}
190
191static
192unsigned int msm_read(struct uart_port *port, unsigned int off)
193{
194 return readl_relaxed(port->membase + off);
195}
196
197/*
198 * Setup the MND registers to use the TCXO clock.
199 */
200static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
201{
202 msm_write(port, 0x06, UART_MREG);
203 msm_write(port, 0xF1, UART_NREG);
204 msm_write(port, 0x0F, UART_DREG);
205 msm_write(port, 0x1A, UART_MNDREG);
206 port->uartclk = 1843200;
207}
208
209/*
210 * Setup the MND registers to use the TCXO clock divided by 4.
211 */
212static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
213{
214 msm_write(port, 0x18, UART_MREG);
215 msm_write(port, 0xF6, UART_NREG);
216 msm_write(port, 0x0F, UART_DREG);
217 msm_write(port, 0x0A, UART_MNDREG);
218 port->uartclk = 1843200;
219}
220
221static void msm_serial_set_mnd_regs(struct uart_port *port)
222{
223 struct msm_port *msm_port = UART_TO_MSM(port);
224
225 /*
226 * These registers don't exist so we change the clk input rate
227 * on uartdm hardware instead
228 */
229 if (msm_port->is_uartdm)
230 return;
231
232 if (port->uartclk == 19200000)
233 msm_serial_set_mnd_regs_tcxo(port);
234 else if (port->uartclk == 4800000)
235 msm_serial_set_mnd_regs_tcxoby4(port);
236}
237
238static void msm_handle_tx(struct uart_port *port);
239static void msm_start_rx_dma(struct msm_port *msm_port);
240
241static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
242{
243 struct device *dev = port->dev;
244 unsigned int mapped;
245 u32 val;
246
247 mapped = dma->count;
248 dma->count = 0;
249
250 dmaengine_terminate_all(dma->chan);
251
252 /*
253 * DMA Stall happens if enqueue and flush command happens concurrently.
254 * For example before changing the baud rate/protocol configuration and
255 * sending flush command to ADM, disable the channel of UARTDM.
256 * Note: should not reset the receiver here immediately as it is not
257 * suggested to do disable/reset or reset/disable at the same time.
258 */
259 val = msm_read(port, UARTDM_DMEN);
260 val &= ~dma->enable_bit;
261 msm_write(port, val, UARTDM_DMEN);
262
263 if (mapped)
264 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
265}
266
267static void msm_release_dma(struct msm_port *msm_port)
268{
269 struct msm_dma *dma;
270
271 dma = &msm_port->tx_dma;
272 if (dma->chan) {
273 msm_stop_dma(&msm_port->uart, dma);
274 dma_release_channel(dma->chan);
275 }
276
277 memset(dma, 0, sizeof(*dma));
278
279 dma = &msm_port->rx_dma;
280 if (dma->chan) {
281 msm_stop_dma(&msm_port->uart, dma);
282 dma_release_channel(dma->chan);
283 kfree(dma->virt);
284 }
285
286 memset(dma, 0, sizeof(*dma));
287}
288
289static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
290{
291 struct device *dev = msm_port->uart.dev;
292 struct dma_slave_config conf;
293 struct msm_dma *dma;
294 u32 crci = 0;
295 int ret;
296
297 dma = &msm_port->tx_dma;
298
299 /* allocate DMA resources, if available */
300 dma->chan = dma_request_chan(dev, "tx");
301 if (IS_ERR(dma->chan))
302 goto no_tx;
303
304 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
305
306 memset(&conf, 0, sizeof(conf));
307 conf.direction = DMA_MEM_TO_DEV;
308 conf.device_fc = true;
309 conf.dst_addr = base + UARTDM_TF;
310 conf.dst_maxburst = UARTDM_BURST_SIZE;
311 conf.slave_id = crci;
312
313 ret = dmaengine_slave_config(dma->chan, &conf);
314 if (ret)
315 goto rel_tx;
316
317 dma->dir = DMA_TO_DEVICE;
318
319 if (msm_port->is_uartdm < UARTDM_1P4)
320 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
321 else
322 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
323
324 return;
325
326rel_tx:
327 dma_release_channel(dma->chan);
328no_tx:
329 memset(dma, 0, sizeof(*dma));
330}
331
332static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
333{
334 struct device *dev = msm_port->uart.dev;
335 struct dma_slave_config conf;
336 struct msm_dma *dma;
337 u32 crci = 0;
338 int ret;
339
340 dma = &msm_port->rx_dma;
341
342 /* allocate DMA resources, if available */
343 dma->chan = dma_request_chan(dev, "rx");
344 if (IS_ERR(dma->chan))
345 goto no_rx;
346
347 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
348
349 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
350 if (!dma->virt)
351 goto rel_rx;
352
353 memset(&conf, 0, sizeof(conf));
354 conf.direction = DMA_DEV_TO_MEM;
355 conf.device_fc = true;
356 conf.src_addr = base + UARTDM_RF;
357 conf.src_maxburst = UARTDM_BURST_SIZE;
358 conf.slave_id = crci;
359
360 ret = dmaengine_slave_config(dma->chan, &conf);
361 if (ret)
362 goto err;
363
364 dma->dir = DMA_FROM_DEVICE;
365
366 if (msm_port->is_uartdm < UARTDM_1P4)
367 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
368 else
369 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
370
371 return;
372err:
373 kfree(dma->virt);
374rel_rx:
375 dma_release_channel(dma->chan);
376no_rx:
377 memset(dma, 0, sizeof(*dma));
378}
379
380static inline void msm_wait_for_xmitr(struct uart_port *port)
381{
382 unsigned int timeout = 500000;
383
384 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
385 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
386 break;
387 udelay(1);
388 if (!timeout--)
389 break;
390 }
391 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
392}
393
394static void msm_stop_tx(struct uart_port *port)
395{
396 struct msm_port *msm_port = UART_TO_MSM(port);
397
398 msm_port->imr &= ~UART_IMR_TXLEV;
399 msm_write(port, msm_port->imr, UART_IMR);
400}
401
402static void msm_start_tx(struct uart_port *port)
403{
404 struct msm_port *msm_port = UART_TO_MSM(port);
405 struct msm_dma *dma = &msm_port->tx_dma;
406
407 /* Already started in DMA mode */
408 if (dma->count)
409 return;
410
411 msm_port->imr |= UART_IMR_TXLEV;
412 msm_write(port, msm_port->imr, UART_IMR);
413}
414
415static void msm_reset_dm_count(struct uart_port *port, int count)
416{
417 msm_wait_for_xmitr(port);
418 msm_write(port, count, UARTDM_NCF_TX);
419 msm_read(port, UARTDM_NCF_TX);
420}
421
422static void msm_complete_tx_dma(void *args)
423{
424 struct msm_port *msm_port = args;
425 struct uart_port *port = &msm_port->uart;
426 struct circ_buf *xmit = &port->state->xmit;
427 struct msm_dma *dma = &msm_port->tx_dma;
428 struct dma_tx_state state;
429 unsigned long flags;
430 unsigned int count;
431 u32 val;
432
433 spin_lock_irqsave(&port->lock, flags);
434
435 /* Already stopped */
436 if (!dma->count)
437 goto done;
438
439 dmaengine_tx_status(dma->chan, dma->cookie, &state);
440
441 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
442
443 val = msm_read(port, UARTDM_DMEN);
444 val &= ~dma->enable_bit;
445 msm_write(port, val, UARTDM_DMEN);
446
447 if (msm_port->is_uartdm > UARTDM_1P3) {
448 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
449 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
450 }
451
452 count = dma->count - state.residue;
453 port->icount.tx += count;
454 dma->count = 0;
455
456 xmit->tail += count;
457 xmit->tail &= UART_XMIT_SIZE - 1;
458
459 /* Restore "Tx FIFO below watermark" interrupt */
460 msm_port->imr |= UART_IMR_TXLEV;
461 msm_write(port, msm_port->imr, UART_IMR);
462
463 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
464 uart_write_wakeup(port);
465
466 msm_handle_tx(port);
467done:
468 spin_unlock_irqrestore(&port->lock, flags);
469}
470
471static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
472{
473 struct circ_buf *xmit = &msm_port->uart.state->xmit;
474 struct uart_port *port = &msm_port->uart;
475 struct msm_dma *dma = &msm_port->tx_dma;
476 void *cpu_addr;
477 int ret;
478 u32 val;
479
480 cpu_addr = &xmit->buf[xmit->tail];
481
482 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
483 ret = dma_mapping_error(port->dev, dma->phys);
484 if (ret)
485 return ret;
486
487 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
488 count, DMA_MEM_TO_DEV,
489 DMA_PREP_INTERRUPT |
490 DMA_PREP_FENCE);
491 if (!dma->desc) {
492 ret = -EIO;
493 goto unmap;
494 }
495
496 dma->desc->callback = msm_complete_tx_dma;
497 dma->desc->callback_param = msm_port;
498
499 dma->cookie = dmaengine_submit(dma->desc);
500 ret = dma_submit_error(dma->cookie);
501 if (ret)
502 goto unmap;
503
504 /*
505 * Using DMA complete for Tx FIFO reload, no need for
506 * "Tx FIFO below watermark" one, disable it
507 */
508 msm_port->imr &= ~UART_IMR_TXLEV;
509 msm_write(port, msm_port->imr, UART_IMR);
510
511 dma->count = count;
512
513 val = msm_read(port, UARTDM_DMEN);
514 val |= dma->enable_bit;
515
516 if (msm_port->is_uartdm < UARTDM_1P4)
517 msm_write(port, val, UARTDM_DMEN);
518
519 msm_reset_dm_count(port, count);
520
521 if (msm_port->is_uartdm > UARTDM_1P3)
522 msm_write(port, val, UARTDM_DMEN);
523
524 dma_async_issue_pending(dma->chan);
525 return 0;
526unmap:
527 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
528 return ret;
529}
530
531static void msm_complete_rx_dma(void *args)
532{
533 struct msm_port *msm_port = args;
534 struct uart_port *port = &msm_port->uart;
535 struct tty_port *tport = &port->state->port;
536 struct msm_dma *dma = &msm_port->rx_dma;
537 int count = 0, i, sysrq;
538 unsigned long flags;
539 u32 val;
540
541 spin_lock_irqsave(&port->lock, flags);
542
543 /* Already stopped */
544 if (!dma->count)
545 goto done;
546
547 val = msm_read(port, UARTDM_DMEN);
548 val &= ~dma->enable_bit;
549 msm_write(port, val, UARTDM_DMEN);
550
551 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
552 port->icount.overrun++;
553 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
554 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
555 }
556
557 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
558
559 port->icount.rx += count;
560
561 dma->count = 0;
562
563 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
564
565 for (i = 0; i < count; i++) {
566 char flag = TTY_NORMAL;
567
568 if (msm_port->break_detected && dma->virt[i] == 0) {
569 port->icount.brk++;
570 flag = TTY_BREAK;
571 msm_port->break_detected = false;
572 if (uart_handle_break(port))
573 continue;
574 }
575
576 if (!(port->read_status_mask & UART_SR_RX_BREAK))
577 flag = TTY_NORMAL;
578
579 spin_unlock_irqrestore(&port->lock, flags);
580 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
581 spin_lock_irqsave(&port->lock, flags);
582 if (!sysrq)
583 tty_insert_flip_char(tport, dma->virt[i], flag);
584 }
585
586 msm_start_rx_dma(msm_port);
587done:
588 spin_unlock_irqrestore(&port->lock, flags);
589
590 if (count)
591 tty_flip_buffer_push(tport);
592}
593
594static void msm_start_rx_dma(struct msm_port *msm_port)
595{
596 struct msm_dma *dma = &msm_port->rx_dma;
597 struct uart_port *uart = &msm_port->uart;
598 u32 val;
599 int ret;
600
601 if (!dma->chan)
602 return;
603
604 dma->phys = dma_map_single(uart->dev, dma->virt,
605 UARTDM_RX_SIZE, dma->dir);
606 ret = dma_mapping_error(uart->dev, dma->phys);
607 if (ret)
608 goto sw_mode;
609
610 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
611 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
612 DMA_PREP_INTERRUPT);
613 if (!dma->desc)
614 goto unmap;
615
616 dma->desc->callback = msm_complete_rx_dma;
617 dma->desc->callback_param = msm_port;
618
619 dma->cookie = dmaengine_submit(dma->desc);
620 ret = dma_submit_error(dma->cookie);
621 if (ret)
622 goto unmap;
623 /*
624 * Using DMA for FIFO off-load, no need for "Rx FIFO over
625 * watermark" or "stale" interrupts, disable them
626 */
627 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
628
629 /*
630 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
631 * we need RXSTALE to flush input DMA fifo to memory
632 */
633 if (msm_port->is_uartdm < UARTDM_1P4)
634 msm_port->imr |= UART_IMR_RXSTALE;
635
636 msm_write(uart, msm_port->imr, UART_IMR);
637
638 dma->count = UARTDM_RX_SIZE;
639
640 dma_async_issue_pending(dma->chan);
641
642 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
643 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
644
645 val = msm_read(uart, UARTDM_DMEN);
646 val |= dma->enable_bit;
647
648 if (msm_port->is_uartdm < UARTDM_1P4)
649 msm_write(uart, val, UARTDM_DMEN);
650
651 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
652
653 if (msm_port->is_uartdm > UARTDM_1P3)
654 msm_write(uart, val, UARTDM_DMEN);
655
656 return;
657unmap:
658 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
659
660sw_mode:
661 /*
662 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN),
663 * receiver must be reset.
664 */
665 msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR);
666 msm_write(uart, UART_CR_RX_ENABLE, UART_CR);
667
668 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
669 msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
670 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
671
672 /* Re-enable RX interrupts */
673 msm_port->imr |= (UART_IMR_RXLEV | UART_IMR_RXSTALE);
674 msm_write(uart, msm_port->imr, UART_IMR);
675}
676
677static void msm_stop_rx(struct uart_port *port)
678{
679 struct msm_port *msm_port = UART_TO_MSM(port);
680 struct msm_dma *dma = &msm_port->rx_dma;
681
682 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
683 msm_write(port, msm_port->imr, UART_IMR);
684
685 if (dma->chan)
686 msm_stop_dma(port, dma);
687}
688
689static void msm_enable_ms(struct uart_port *port)
690{
691 struct msm_port *msm_port = UART_TO_MSM(port);
692
693 msm_port->imr |= UART_IMR_DELTA_CTS;
694 msm_write(port, msm_port->imr, UART_IMR);
695}
696
697static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
698 __must_hold(&port->lock)
699{
700 struct tty_port *tport = &port->state->port;
701 unsigned int sr;
702 int count = 0;
703 struct msm_port *msm_port = UART_TO_MSM(port);
704
705 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
706 port->icount.overrun++;
707 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
708 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
709 }
710
711 if (misr & UART_IMR_RXSTALE) {
712 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
713 msm_port->old_snap_state;
714 msm_port->old_snap_state = 0;
715 } else {
716 count = 4 * (msm_read(port, UART_RFWR));
717 msm_port->old_snap_state += count;
718 }
719
720 /* TODO: Precise error reporting */
721
722 port->icount.rx += count;
723
724 while (count > 0) {
725 unsigned char buf[4];
726 int sysrq, r_count, i;
727
728 sr = msm_read(port, UART_SR);
729 if ((sr & UART_SR_RX_READY) == 0) {
730 msm_port->old_snap_state -= count;
731 break;
732 }
733
734 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
735 r_count = min_t(int, count, sizeof(buf));
736
737 for (i = 0; i < r_count; i++) {
738 char flag = TTY_NORMAL;
739
740 if (msm_port->break_detected && buf[i] == 0) {
741 port->icount.brk++;
742 flag = TTY_BREAK;
743 msm_port->break_detected = false;
744 if (uart_handle_break(port))
745 continue;
746 }
747
748 if (!(port->read_status_mask & UART_SR_RX_BREAK))
749 flag = TTY_NORMAL;
750
751 spin_unlock(&port->lock);
752 sysrq = uart_handle_sysrq_char(port, buf[i]);
753 spin_lock(&port->lock);
754 if (!sysrq)
755 tty_insert_flip_char(tport, buf[i], flag);
756 }
757 count -= r_count;
758 }
759
760 tty_flip_buffer_push(tport);
761
762 if (misr & (UART_IMR_RXSTALE))
763 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
764 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
765 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
766
767 /* Try to use DMA */
768 msm_start_rx_dma(msm_port);
769}
770
771static void msm_handle_rx(struct uart_port *port)
772 __must_hold(&port->lock)
773{
774 struct tty_port *tport = &port->state->port;
775 unsigned int sr;
776
777 /*
778 * Handle overrun. My understanding of the hardware is that overrun
779 * is not tied to the RX buffer, so we handle the case out of band.
780 */
781 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
782 port->icount.overrun++;
783 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
784 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
785 }
786
787 /* and now the main RX loop */
788 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
789 unsigned int c;
790 char flag = TTY_NORMAL;
791 int sysrq;
792
793 c = msm_read(port, UART_RF);
794
795 if (sr & UART_SR_RX_BREAK) {
796 port->icount.brk++;
797 if (uart_handle_break(port))
798 continue;
799 } else if (sr & UART_SR_PAR_FRAME_ERR) {
800 port->icount.frame++;
801 } else {
802 port->icount.rx++;
803 }
804
805 /* Mask conditions we're ignorning. */
806 sr &= port->read_status_mask;
807
808 if (sr & UART_SR_RX_BREAK)
809 flag = TTY_BREAK;
810 else if (sr & UART_SR_PAR_FRAME_ERR)
811 flag = TTY_FRAME;
812
813 spin_unlock(&port->lock);
814 sysrq = uart_handle_sysrq_char(port, c);
815 spin_lock(&port->lock);
816 if (!sysrq)
817 tty_insert_flip_char(tport, c, flag);
818 }
819
820 tty_flip_buffer_push(tport);
821}
822
823static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
824{
825 struct circ_buf *xmit = &port->state->xmit;
826 struct msm_port *msm_port = UART_TO_MSM(port);
827 unsigned int num_chars;
828 unsigned int tf_pointer = 0;
829 void __iomem *tf;
830
831 if (msm_port->is_uartdm)
832 tf = port->membase + UARTDM_TF;
833 else
834 tf = port->membase + UART_TF;
835
836 if (tx_count && msm_port->is_uartdm)
837 msm_reset_dm_count(port, tx_count);
838
839 while (tf_pointer < tx_count) {
840 int i;
841 char buf[4] = { 0 };
842
843 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
844 break;
845
846 if (msm_port->is_uartdm)
847 num_chars = min(tx_count - tf_pointer,
848 (unsigned int)sizeof(buf));
849 else
850 num_chars = 1;
851
852 for (i = 0; i < num_chars; i++) {
853 buf[i] = xmit->buf[xmit->tail + i];
854 port->icount.tx++;
855 }
856
857 iowrite32_rep(tf, buf, 1);
858 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
859 tf_pointer += num_chars;
860 }
861
862 /* disable tx interrupts if nothing more to send */
863 if (uart_circ_empty(xmit))
864 msm_stop_tx(port);
865
866 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
867 uart_write_wakeup(port);
868}
869
870static void msm_handle_tx(struct uart_port *port)
871{
872 struct msm_port *msm_port = UART_TO_MSM(port);
873 struct circ_buf *xmit = &msm_port->uart.state->xmit;
874 struct msm_dma *dma = &msm_port->tx_dma;
875 unsigned int pio_count, dma_count, dma_min;
876 char buf[4] = { 0 };
877 void __iomem *tf;
878 int err = 0;
879
880 if (port->x_char) {
881 if (msm_port->is_uartdm)
882 tf = port->membase + UARTDM_TF;
883 else
884 tf = port->membase + UART_TF;
885
886 buf[0] = port->x_char;
887
888 if (msm_port->is_uartdm)
889 msm_reset_dm_count(port, 1);
890
891 iowrite32_rep(tf, buf, 1);
892 port->icount.tx++;
893 port->x_char = 0;
894 return;
895 }
896
897 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
898 msm_stop_tx(port);
899 return;
900 }
901
902 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
903 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
904
905 dma_min = 1; /* Always DMA */
906 if (msm_port->is_uartdm > UARTDM_1P3) {
907 dma_count = UARTDM_TX_AIGN(dma_count);
908 dma_min = UARTDM_BURST_SIZE;
909 } else {
910 if (dma_count > UARTDM_TX_MAX)
911 dma_count = UARTDM_TX_MAX;
912 }
913
914 if (pio_count > port->fifosize)
915 pio_count = port->fifosize;
916
917 if (!dma->chan || dma_count < dma_min)
918 msm_handle_tx_pio(port, pio_count);
919 else
920 err = msm_handle_tx_dma(msm_port, dma_count);
921
922 if (err) /* fall back to PIO mode */
923 msm_handle_tx_pio(port, pio_count);
924}
925
926static void msm_handle_delta_cts(struct uart_port *port)
927{
928 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
929 port->icount.cts++;
930 wake_up_interruptible(&port->state->port.delta_msr_wait);
931}
932
933static irqreturn_t msm_uart_irq(int irq, void *dev_id)
934{
935 struct uart_port *port = dev_id;
936 struct msm_port *msm_port = UART_TO_MSM(port);
937 struct msm_dma *dma = &msm_port->rx_dma;
938 unsigned long flags;
939 unsigned int misr;
940 u32 val;
941
942 spin_lock_irqsave(&port->lock, flags);
943 misr = msm_read(port, UART_MISR);
944 msm_write(port, 0, UART_IMR); /* disable interrupt */
945
946 if (misr & UART_IMR_RXBREAK_START) {
947 msm_port->break_detected = true;
948 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
949 }
950
951 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
952 if (dma->count) {
953 val = UART_CR_CMD_STALE_EVENT_DISABLE;
954 msm_write(port, val, UART_CR);
955 val = UART_CR_CMD_RESET_STALE_INT;
956 msm_write(port, val, UART_CR);
957 /*
958 * Flush DMA input fifo to memory, this will also
959 * trigger DMA RX completion
960 */
961 dmaengine_terminate_all(dma->chan);
962 } else if (msm_port->is_uartdm) {
963 msm_handle_rx_dm(port, misr);
964 } else {
965 msm_handle_rx(port);
966 }
967 }
968 if (misr & UART_IMR_TXLEV)
969 msm_handle_tx(port);
970 if (misr & UART_IMR_DELTA_CTS)
971 msm_handle_delta_cts(port);
972
973 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
974 spin_unlock_irqrestore(&port->lock, flags);
975
976 return IRQ_HANDLED;
977}
978
979static unsigned int msm_tx_empty(struct uart_port *port)
980{
981 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
982}
983
984static unsigned int msm_get_mctrl(struct uart_port *port)
985{
986 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
987}
988
989static void msm_reset(struct uart_port *port)
990{
991 struct msm_port *msm_port = UART_TO_MSM(port);
992 unsigned int mr;
993
994 /* reset everything */
995 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
996 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
997 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
998 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
999 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
1000 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1001 mr = msm_read(port, UART_MR1);
1002 mr &= ~UART_MR1_RX_RDY_CTL;
1003 msm_write(port, mr, UART_MR1);
1004
1005 /* Disable DM modes */
1006 if (msm_port->is_uartdm)
1007 msm_write(port, 0, UARTDM_DMEN);
1008}
1009
1010static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1011{
1012 unsigned int mr;
1013
1014 mr = msm_read(port, UART_MR1);
1015
1016 if (!(mctrl & TIOCM_RTS)) {
1017 mr &= ~UART_MR1_RX_RDY_CTL;
1018 msm_write(port, mr, UART_MR1);
1019 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1020 } else {
1021 mr |= UART_MR1_RX_RDY_CTL;
1022 msm_write(port, mr, UART_MR1);
1023 }
1024}
1025
1026static void msm_break_ctl(struct uart_port *port, int break_ctl)
1027{
1028 if (break_ctl)
1029 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1030 else
1031 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1032}
1033
1034struct msm_baud_map {
1035 u16 divisor;
1036 u8 code;
1037 u8 rxstale;
1038};
1039
1040static const struct msm_baud_map *
1041msm_find_best_baud(struct uart_port *port, unsigned int baud,
1042 unsigned long *rate)
1043{
1044 struct msm_port *msm_port = UART_TO_MSM(port);
1045 unsigned int divisor, result;
1046 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1047 const struct msm_baud_map *entry, *end, *best;
1048 static const struct msm_baud_map table[] = {
1049 { 1, 0xff, 31 },
1050 { 2, 0xee, 16 },
1051 { 3, 0xdd, 8 },
1052 { 4, 0xcc, 6 },
1053 { 6, 0xbb, 6 },
1054 { 8, 0xaa, 6 },
1055 { 12, 0x99, 6 },
1056 { 16, 0x88, 1 },
1057 { 24, 0x77, 1 },
1058 { 32, 0x66, 1 },
1059 { 48, 0x55, 1 },
1060 { 96, 0x44, 1 },
1061 { 192, 0x33, 1 },
1062 { 384, 0x22, 1 },
1063 { 768, 0x11, 1 },
1064 { 1536, 0x00, 1 },
1065 };
1066
1067 best = table; /* Default to smallest divider */
1068 target = clk_round_rate(msm_port->clk, 16 * baud);
1069 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1070
1071 end = table + ARRAY_SIZE(table);
1072 entry = table;
1073 while (entry < end) {
1074 if (entry->divisor <= divisor) {
1075 result = target / entry->divisor / 16;
1076 diff = abs(result - baud);
1077
1078 /* Keep track of best entry */
1079 if (diff < best_diff) {
1080 best_diff = diff;
1081 best = entry;
1082 best_rate = target;
1083 }
1084
1085 if (result == baud)
1086 break;
1087 } else if (entry->divisor > divisor) {
1088 old = target;
1089 target = clk_round_rate(msm_port->clk, old + 1);
1090 /*
1091 * The rate didn't get any faster so we can't do
1092 * better at dividing it down
1093 */
1094 if (target == old)
1095 break;
1096
1097 /* Start the divisor search over at this new rate */
1098 entry = table;
1099 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1100 continue;
1101 }
1102 entry++;
1103 }
1104
1105 *rate = best_rate;
1106 return best;
1107}
1108
1109static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1110 unsigned long *saved_flags)
1111{
1112 unsigned int rxstale, watermark, mask;
1113 struct msm_port *msm_port = UART_TO_MSM(port);
1114 const struct msm_baud_map *entry;
1115 unsigned long flags, rate;
1116
1117 flags = *saved_flags;
1118 spin_unlock_irqrestore(&port->lock, flags);
1119
1120 entry = msm_find_best_baud(port, baud, &rate);
1121 clk_set_rate(msm_port->clk, rate);
1122 baud = rate / 16 / entry->divisor;
1123
1124 spin_lock_irqsave(&port->lock, flags);
1125 *saved_flags = flags;
1126 port->uartclk = rate;
1127
1128 msm_write(port, entry->code, UART_CSR);
1129
1130 /* RX stale watermark */
1131 rxstale = entry->rxstale;
1132 watermark = UART_IPR_STALE_LSB & rxstale;
1133 if (msm_port->is_uartdm) {
1134 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1135 } else {
1136 watermark |= UART_IPR_RXSTALE_LAST;
1137 mask = UART_IPR_STALE_TIMEOUT_MSB;
1138 }
1139
1140 watermark |= mask & (rxstale << 2);
1141
1142 msm_write(port, watermark, UART_IPR);
1143
1144 /* set RX watermark */
1145 watermark = (port->fifosize * 3) / 4;
1146 msm_write(port, watermark, UART_RFWR);
1147
1148 /* set TX watermark */
1149 msm_write(port, 10, UART_TFWR);
1150
1151 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1152 msm_reset(port);
1153
1154 /* Enable RX and TX */
1155 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1156
1157 /* turn on RX and CTS interrupts */
1158 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1159 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1160
1161 msm_write(port, msm_port->imr, UART_IMR);
1162
1163 if (msm_port->is_uartdm) {
1164 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1165 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1166 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1167 }
1168
1169 return baud;
1170}
1171
1172static void msm_init_clock(struct uart_port *port)
1173{
1174 struct msm_port *msm_port = UART_TO_MSM(port);
1175
1176 clk_prepare_enable(msm_port->clk);
1177 clk_prepare_enable(msm_port->pclk);
1178 msm_serial_set_mnd_regs(port);
1179}
1180
1181static int msm_startup(struct uart_port *port)
1182{
1183 struct msm_port *msm_port = UART_TO_MSM(port);
1184 unsigned int data, rfr_level, mask;
1185 int ret;
1186
1187 snprintf(msm_port->name, sizeof(msm_port->name),
1188 "msm_serial%d", port->line);
1189
1190 msm_init_clock(port);
1191
1192 if (likely(port->fifosize > 12))
1193 rfr_level = port->fifosize - 12;
1194 else
1195 rfr_level = port->fifosize;
1196
1197 /* set automatic RFR level */
1198 data = msm_read(port, UART_MR1);
1199
1200 if (msm_port->is_uartdm)
1201 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1202 else
1203 mask = UART_MR1_AUTO_RFR_LEVEL1;
1204
1205 data &= ~mask;
1206 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1207 data |= mask & (rfr_level << 2);
1208 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1209 msm_write(port, data, UART_MR1);
1210
1211 if (msm_port->is_uartdm) {
1212 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1213 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1214 }
1215
1216 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1217 msm_port->name, port);
1218 if (unlikely(ret))
1219 goto err_irq;
1220
1221 return 0;
1222
1223err_irq:
1224 if (msm_port->is_uartdm)
1225 msm_release_dma(msm_port);
1226
1227 clk_disable_unprepare(msm_port->pclk);
1228 clk_disable_unprepare(msm_port->clk);
1229
1230 return ret;
1231}
1232
1233static void msm_shutdown(struct uart_port *port)
1234{
1235 struct msm_port *msm_port = UART_TO_MSM(port);
1236
1237 msm_port->imr = 0;
1238 msm_write(port, 0, UART_IMR); /* disable interrupts */
1239
1240 if (msm_port->is_uartdm)
1241 msm_release_dma(msm_port);
1242
1243 clk_disable_unprepare(msm_port->clk);
1244
1245 free_irq(port->irq, port);
1246}
1247
1248static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1249 struct ktermios *old)
1250{
1251 struct msm_port *msm_port = UART_TO_MSM(port);
1252 struct msm_dma *dma = &msm_port->rx_dma;
1253 unsigned long flags;
1254 unsigned int baud, mr;
1255
1256 spin_lock_irqsave(&port->lock, flags);
1257
1258 if (dma->chan) /* Terminate if any */
1259 msm_stop_dma(port, dma);
1260
1261 /* calculate and set baud rate */
1262 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1263 baud = msm_set_baud_rate(port, baud, &flags);
1264 if (tty_termios_baud_rate(termios))
1265 tty_termios_encode_baud_rate(termios, baud, baud);
1266
1267 /* calculate parity */
1268 mr = msm_read(port, UART_MR2);
1269 mr &= ~UART_MR2_PARITY_MODE;
1270 if (termios->c_cflag & PARENB) {
1271 if (termios->c_cflag & PARODD)
1272 mr |= UART_MR2_PARITY_MODE_ODD;
1273 else if (termios->c_cflag & CMSPAR)
1274 mr |= UART_MR2_PARITY_MODE_SPACE;
1275 else
1276 mr |= UART_MR2_PARITY_MODE_EVEN;
1277 }
1278
1279 /* calculate bits per char */
1280 mr &= ~UART_MR2_BITS_PER_CHAR;
1281 switch (termios->c_cflag & CSIZE) {
1282 case CS5:
1283 mr |= UART_MR2_BITS_PER_CHAR_5;
1284 break;
1285 case CS6:
1286 mr |= UART_MR2_BITS_PER_CHAR_6;
1287 break;
1288 case CS7:
1289 mr |= UART_MR2_BITS_PER_CHAR_7;
1290 break;
1291 case CS8:
1292 default:
1293 mr |= UART_MR2_BITS_PER_CHAR_8;
1294 break;
1295 }
1296
1297 /* calculate stop bits */
1298 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1299 if (termios->c_cflag & CSTOPB)
1300 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1301 else
1302 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1303
1304 /* set parity, bits per char, and stop bit */
1305 msm_write(port, mr, UART_MR2);
1306
1307 /* calculate and set hardware flow control */
1308 mr = msm_read(port, UART_MR1);
1309 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1310 if (termios->c_cflag & CRTSCTS) {
1311 mr |= UART_MR1_CTS_CTL;
1312 mr |= UART_MR1_RX_RDY_CTL;
1313 }
1314 msm_write(port, mr, UART_MR1);
1315
1316 /* Configure status bits to ignore based on termio flags. */
1317 port->read_status_mask = 0;
1318 if (termios->c_iflag & INPCK)
1319 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1320 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1321 port->read_status_mask |= UART_SR_RX_BREAK;
1322
1323 uart_update_timeout(port, termios->c_cflag, baud);
1324
1325 /* Try to use DMA */
1326 msm_start_rx_dma(msm_port);
1327
1328 spin_unlock_irqrestore(&port->lock, flags);
1329}
1330
1331static const char *msm_type(struct uart_port *port)
1332{
1333 return "MSM";
1334}
1335
1336static void msm_release_port(struct uart_port *port)
1337{
1338 struct platform_device *pdev = to_platform_device(port->dev);
1339 struct resource *uart_resource;
1340 resource_size_t size;
1341
1342 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1343 if (unlikely(!uart_resource))
1344 return;
1345 size = resource_size(uart_resource);
1346
1347 release_mem_region(port->mapbase, size);
1348 iounmap(port->membase);
1349 port->membase = NULL;
1350}
1351
1352static int msm_request_port(struct uart_port *port)
1353{
1354 struct platform_device *pdev = to_platform_device(port->dev);
1355 struct resource *uart_resource;
1356 resource_size_t size;
1357 int ret;
1358
1359 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1360 if (unlikely(!uart_resource))
1361 return -ENXIO;
1362
1363 size = resource_size(uart_resource);
1364
1365 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1366 return -EBUSY;
1367
1368 port->membase = ioremap(port->mapbase, size);
1369 if (!port->membase) {
1370 ret = -EBUSY;
1371 goto fail_release_port;
1372 }
1373
1374 return 0;
1375
1376fail_release_port:
1377 release_mem_region(port->mapbase, size);
1378 return ret;
1379}
1380
1381static void msm_config_port(struct uart_port *port, int flags)
1382{
1383 int ret;
1384
1385 if (flags & UART_CONFIG_TYPE) {
1386 port->type = PORT_MSM;
1387 ret = msm_request_port(port);
1388 if (ret)
1389 return;
1390 }
1391}
1392
1393static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1394{
1395 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1396 return -EINVAL;
1397 if (unlikely(port->irq != ser->irq))
1398 return -EINVAL;
1399 return 0;
1400}
1401
1402static void msm_power(struct uart_port *port, unsigned int state,
1403 unsigned int oldstate)
1404{
1405 struct msm_port *msm_port = UART_TO_MSM(port);
1406
1407 switch (state) {
1408 case 0:
1409 clk_prepare_enable(msm_port->clk);
1410 clk_prepare_enable(msm_port->pclk);
1411 break;
1412 case 3:
1413 clk_disable_unprepare(msm_port->clk);
1414 clk_disable_unprepare(msm_port->pclk);
1415 break;
1416 default:
1417 pr_err("msm_serial: Unknown PM state %d\n", state);
1418 }
1419}
1420
1421#ifdef CONFIG_CONSOLE_POLL
1422static int msm_poll_get_char_single(struct uart_port *port)
1423{
1424 struct msm_port *msm_port = UART_TO_MSM(port);
1425 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1426
1427 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1428 return NO_POLL_CHAR;
1429
1430 return msm_read(port, rf_reg) & 0xff;
1431}
1432
1433static int msm_poll_get_char_dm(struct uart_port *port)
1434{
1435 int c;
1436 static u32 slop;
1437 static int count;
1438 unsigned char *sp = (unsigned char *)&slop;
1439
1440 /* Check if a previous read had more than one char */
1441 if (count) {
1442 c = sp[sizeof(slop) - count];
1443 count--;
1444 /* Or if FIFO is empty */
1445 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1446 /*
1447 * If RX packing buffer has less than a word, force stale to
1448 * push contents into RX FIFO
1449 */
1450 count = msm_read(port, UARTDM_RXFS);
1451 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1452 if (count) {
1453 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1454 slop = msm_read(port, UARTDM_RF);
1455 c = sp[0];
1456 count--;
1457 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1458 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1459 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1460 UART_CR);
1461 } else {
1462 c = NO_POLL_CHAR;
1463 }
1464 /* FIFO has a word */
1465 } else {
1466 slop = msm_read(port, UARTDM_RF);
1467 c = sp[0];
1468 count = sizeof(slop) - 1;
1469 }
1470
1471 return c;
1472}
1473
1474static int msm_poll_get_char(struct uart_port *port)
1475{
1476 u32 imr;
1477 int c;
1478 struct msm_port *msm_port = UART_TO_MSM(port);
1479
1480 /* Disable all interrupts */
1481 imr = msm_read(port, UART_IMR);
1482 msm_write(port, 0, UART_IMR);
1483
1484 if (msm_port->is_uartdm)
1485 c = msm_poll_get_char_dm(port);
1486 else
1487 c = msm_poll_get_char_single(port);
1488
1489 /* Enable interrupts */
1490 msm_write(port, imr, UART_IMR);
1491
1492 return c;
1493}
1494
1495static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1496{
1497 u32 imr;
1498 struct msm_port *msm_port = UART_TO_MSM(port);
1499
1500 /* Disable all interrupts */
1501 imr = msm_read(port, UART_IMR);
1502 msm_write(port, 0, UART_IMR);
1503
1504 if (msm_port->is_uartdm)
1505 msm_reset_dm_count(port, 1);
1506
1507 /* Wait until FIFO is empty */
1508 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1509 cpu_relax();
1510
1511 /* Write a character */
1512 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1513
1514 /* Wait until FIFO is empty */
1515 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1516 cpu_relax();
1517
1518 /* Enable interrupts */
1519 msm_write(port, imr, UART_IMR);
1520}
1521#endif
1522
1523static const struct uart_ops msm_uart_pops = {
1524 .tx_empty = msm_tx_empty,
1525 .set_mctrl = msm_set_mctrl,
1526 .get_mctrl = msm_get_mctrl,
1527 .stop_tx = msm_stop_tx,
1528 .start_tx = msm_start_tx,
1529 .stop_rx = msm_stop_rx,
1530 .enable_ms = msm_enable_ms,
1531 .break_ctl = msm_break_ctl,
1532 .startup = msm_startup,
1533 .shutdown = msm_shutdown,
1534 .set_termios = msm_set_termios,
1535 .type = msm_type,
1536 .release_port = msm_release_port,
1537 .request_port = msm_request_port,
1538 .config_port = msm_config_port,
1539 .verify_port = msm_verify_port,
1540 .pm = msm_power,
1541#ifdef CONFIG_CONSOLE_POLL
1542 .poll_get_char = msm_poll_get_char,
1543 .poll_put_char = msm_poll_put_char,
1544#endif
1545};
1546
1547static struct msm_port msm_uart_ports[] = {
1548 {
1549 .uart = {
1550 .iotype = UPIO_MEM,
1551 .ops = &msm_uart_pops,
1552 .flags = UPF_BOOT_AUTOCONF,
1553 .fifosize = 64,
1554 .line = 0,
1555 },
1556 },
1557 {
1558 .uart = {
1559 .iotype = UPIO_MEM,
1560 .ops = &msm_uart_pops,
1561 .flags = UPF_BOOT_AUTOCONF,
1562 .fifosize = 64,
1563 .line = 1,
1564 },
1565 },
1566 {
1567 .uart = {
1568 .iotype = UPIO_MEM,
1569 .ops = &msm_uart_pops,
1570 .flags = UPF_BOOT_AUTOCONF,
1571 .fifosize = 64,
1572 .line = 2,
1573 },
1574 },
1575};
1576
1577#define UART_NR ARRAY_SIZE(msm_uart_ports)
1578
1579static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1580{
1581 return &msm_uart_ports[line].uart;
1582}
1583
1584#ifdef CONFIG_SERIAL_MSM_CONSOLE
1585static void __msm_console_write(struct uart_port *port, const char *s,
1586 unsigned int count, bool is_uartdm)
1587{
1588 int i;
1589 int num_newlines = 0;
1590 bool replaced = false;
1591 void __iomem *tf;
1592 int locked = 1;
1593
1594 if (is_uartdm)
1595 tf = port->membase + UARTDM_TF;
1596 else
1597 tf = port->membase + UART_TF;
1598
1599 /* Account for newlines that will get a carriage return added */
1600 for (i = 0; i < count; i++)
1601 if (s[i] == '\n')
1602 num_newlines++;
1603 count += num_newlines;
1604
1605 if (port->sysrq)
1606 locked = 0;
1607 else if (oops_in_progress)
1608 locked = spin_trylock(&port->lock);
1609 else
1610 spin_lock(&port->lock);
1611
1612 if (is_uartdm)
1613 msm_reset_dm_count(port, count);
1614
1615 i = 0;
1616 while (i < count) {
1617 int j;
1618 unsigned int num_chars;
1619 char buf[4] = { 0 };
1620
1621 if (is_uartdm)
1622 num_chars = min(count - i, (unsigned int)sizeof(buf));
1623 else
1624 num_chars = 1;
1625
1626 for (j = 0; j < num_chars; j++) {
1627 char c = *s;
1628
1629 if (c == '\n' && !replaced) {
1630 buf[j] = '\r';
1631 j++;
1632 replaced = true;
1633 }
1634 if (j < num_chars) {
1635 buf[j] = c;
1636 s++;
1637 replaced = false;
1638 }
1639 }
1640
1641 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1642 cpu_relax();
1643
1644 iowrite32_rep(tf, buf, 1);
1645 i += num_chars;
1646 }
1647
1648 if (locked)
1649 spin_unlock(&port->lock);
1650}
1651
1652static void msm_console_write(struct console *co, const char *s,
1653 unsigned int count)
1654{
1655 struct uart_port *port;
1656 struct msm_port *msm_port;
1657
1658 BUG_ON(co->index < 0 || co->index >= UART_NR);
1659
1660 port = msm_get_port_from_line(co->index);
1661 msm_port = UART_TO_MSM(port);
1662
1663 __msm_console_write(port, s, count, msm_port->is_uartdm);
1664}
1665
1666static int msm_console_setup(struct console *co, char *options)
1667{
1668 struct uart_port *port;
1669 int baud = 115200;
1670 int bits = 8;
1671 int parity = 'n';
1672 int flow = 'n';
1673
1674 if (unlikely(co->index >= UART_NR || co->index < 0))
1675 return -ENXIO;
1676
1677 port = msm_get_port_from_line(co->index);
1678
1679 if (unlikely(!port->membase))
1680 return -ENXIO;
1681
1682 msm_init_clock(port);
1683
1684 if (options)
1685 uart_parse_options(options, &baud, &parity, &bits, &flow);
1686
1687 pr_info("msm_serial: console setup on port #%d\n", port->line);
1688
1689 return uart_set_options(port, co, baud, parity, bits, flow);
1690}
1691
1692static void
1693msm_serial_early_write(struct console *con, const char *s, unsigned n)
1694{
1695 struct earlycon_device *dev = con->data;
1696
1697 __msm_console_write(&dev->port, s, n, false);
1698}
1699
1700static int __init
1701msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1702{
1703 if (!device->port.membase)
1704 return -ENODEV;
1705
1706 device->con->write = msm_serial_early_write;
1707 return 0;
1708}
1709OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1710 msm_serial_early_console_setup);
1711
1712static void
1713msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1714{
1715 struct earlycon_device *dev = con->data;
1716
1717 __msm_console_write(&dev->port, s, n, true);
1718}
1719
1720static int __init
1721msm_serial_early_console_setup_dm(struct earlycon_device *device,
1722 const char *opt)
1723{
1724 if (!device->port.membase)
1725 return -ENODEV;
1726
1727 device->con->write = msm_serial_early_write_dm;
1728 return 0;
1729}
1730OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1731 msm_serial_early_console_setup_dm);
1732
1733static struct uart_driver msm_uart_driver;
1734
1735static struct console msm_console = {
1736 .name = "ttyMSM",
1737 .write = msm_console_write,
1738 .device = uart_console_device,
1739 .setup = msm_console_setup,
1740 .flags = CON_PRINTBUFFER,
1741 .index = -1,
1742 .data = &msm_uart_driver,
1743};
1744
1745#define MSM_CONSOLE (&msm_console)
1746
1747#else
1748#define MSM_CONSOLE NULL
1749#endif
1750
1751static struct uart_driver msm_uart_driver = {
1752 .owner = THIS_MODULE,
1753 .driver_name = "msm_serial",
1754 .dev_name = "ttyMSM",
1755 .nr = UART_NR,
1756 .cons = MSM_CONSOLE,
1757};
1758
1759static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1760
1761static const struct of_device_id msm_uartdm_table[] = {
1762 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1763 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1764 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1765 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1766 { }
1767};
1768
1769static int msm_serial_probe(struct platform_device *pdev)
1770{
1771 struct msm_port *msm_port;
1772 struct resource *resource;
1773 struct uart_port *port;
1774 const struct of_device_id *id;
1775 int irq, line;
1776
1777 if (pdev->dev.of_node)
1778 line = of_alias_get_id(pdev->dev.of_node, "serial");
1779 else
1780 line = pdev->id;
1781
1782 if (line < 0)
1783 line = atomic_inc_return(&msm_uart_next_id) - 1;
1784
1785 if (unlikely(line < 0 || line >= UART_NR))
1786 return -ENXIO;
1787
1788 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1789
1790 port = msm_get_port_from_line(line);
1791 port->dev = &pdev->dev;
1792 msm_port = UART_TO_MSM(port);
1793
1794 id = of_match_device(msm_uartdm_table, &pdev->dev);
1795 if (id)
1796 msm_port->is_uartdm = (unsigned long)id->data;
1797 else
1798 msm_port->is_uartdm = 0;
1799
1800 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1801 if (IS_ERR(msm_port->clk))
1802 return PTR_ERR(msm_port->clk);
1803
1804 if (msm_port->is_uartdm) {
1805 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1806 if (IS_ERR(msm_port->pclk))
1807 return PTR_ERR(msm_port->pclk);
1808 }
1809
1810 port->uartclk = clk_get_rate(msm_port->clk);
1811 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1812
1813 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1814 if (unlikely(!resource))
1815 return -ENXIO;
1816 port->mapbase = resource->start;
1817
1818 irq = platform_get_irq(pdev, 0);
1819 if (unlikely(irq < 0))
1820 return -ENXIO;
1821 port->irq = irq;
1822 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
1823
1824 platform_set_drvdata(pdev, port);
1825
1826 return uart_add_one_port(&msm_uart_driver, port);
1827}
1828
1829static int msm_serial_remove(struct platform_device *pdev)
1830{
1831 struct uart_port *port = platform_get_drvdata(pdev);
1832
1833 uart_remove_one_port(&msm_uart_driver, port);
1834
1835 return 0;
1836}
1837
1838static const struct of_device_id msm_match_table[] = {
1839 { .compatible = "qcom,msm-uart" },
1840 { .compatible = "qcom,msm-uartdm" },
1841 {}
1842};
1843MODULE_DEVICE_TABLE(of, msm_match_table);
1844
1845static int __maybe_unused msm_serial_suspend(struct device *dev)
1846{
1847 struct msm_port *port = dev_get_drvdata(dev);
1848
1849 uart_suspend_port(&msm_uart_driver, &port->uart);
1850
1851 return 0;
1852}
1853
1854static int __maybe_unused msm_serial_resume(struct device *dev)
1855{
1856 struct msm_port *port = dev_get_drvdata(dev);
1857
1858 uart_resume_port(&msm_uart_driver, &port->uart);
1859
1860 return 0;
1861}
1862
1863static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1864 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1865};
1866
1867static struct platform_driver msm_platform_driver = {
1868 .remove = msm_serial_remove,
1869 .probe = msm_serial_probe,
1870 .driver = {
1871 .name = "msm_serial",
1872 .pm = &msm_serial_dev_pm_ops,
1873 .of_match_table = msm_match_table,
1874 },
1875};
1876
1877static int __init msm_serial_init(void)
1878{
1879 int ret;
1880
1881 ret = uart_register_driver(&msm_uart_driver);
1882 if (unlikely(ret))
1883 return ret;
1884
1885 ret = platform_driver_register(&msm_platform_driver);
1886 if (unlikely(ret))
1887 uart_unregister_driver(&msm_uart_driver);
1888
1889 pr_info("msm_serial: driver initialized\n");
1890
1891 return ret;
1892}
1893
1894static void __exit msm_serial_exit(void)
1895{
1896 platform_driver_unregister(&msm_platform_driver);
1897 uart_unregister_driver(&msm_uart_driver);
1898}
1899
1900module_init(msm_serial_init);
1901module_exit(msm_serial_exit);
1902
1903MODULE_AUTHOR("Robert Love <rlove@google.com>");
1904MODULE_DESCRIPTION("Driver for msm7x serial device");
1905MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for msm7k serial device and console
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 */
9
10#include <linux/kernel.h>
11#include <linux/atomic.h>
12#include <linux/dma/qcom_adm.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmaengine.h>
15#include <linux/module.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20#include <linux/console.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24#include <linux/slab.h>
25#include <linux/clk.h>
26#include <linux/platform_device.h>
27#include <linux/pm_opp.h>
28#include <linux/delay.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/wait.h>
32
33#define MSM_UART_MR1 0x0000
34
35#define MSM_UART_MR1_AUTO_RFR_LEVEL0 0x3F
36#define MSM_UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
37#define MSM_UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
38#define MSM_UART_MR1_RX_RDY_CTL BIT(7)
39#define MSM_UART_MR1_CTS_CTL BIT(6)
40
41#define MSM_UART_MR2 0x0004
42#define MSM_UART_MR2_ERROR_MODE BIT(6)
43#define MSM_UART_MR2_BITS_PER_CHAR 0x30
44#define MSM_UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
45#define MSM_UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
46#define MSM_UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
47#define MSM_UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
48#define MSM_UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
49#define MSM_UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
50#define MSM_UART_MR2_PARITY_MODE_NONE 0x0
51#define MSM_UART_MR2_PARITY_MODE_ODD 0x1
52#define MSM_UART_MR2_PARITY_MODE_EVEN 0x2
53#define MSM_UART_MR2_PARITY_MODE_SPACE 0x3
54#define MSM_UART_MR2_PARITY_MODE 0x3
55
56#define MSM_UART_CSR 0x0008
57
58#define MSM_UART_TF 0x000C
59#define UARTDM_TF 0x0070
60
61#define MSM_UART_CR 0x0010
62#define MSM_UART_CR_CMD_NULL (0 << 4)
63#define MSM_UART_CR_CMD_RESET_RX (1 << 4)
64#define MSM_UART_CR_CMD_RESET_TX (2 << 4)
65#define MSM_UART_CR_CMD_RESET_ERR (3 << 4)
66#define MSM_UART_CR_CMD_RESET_BREAK_INT (4 << 4)
67#define MSM_UART_CR_CMD_START_BREAK (5 << 4)
68#define MSM_UART_CR_CMD_STOP_BREAK (6 << 4)
69#define MSM_UART_CR_CMD_RESET_CTS (7 << 4)
70#define MSM_UART_CR_CMD_RESET_STALE_INT (8 << 4)
71#define MSM_UART_CR_CMD_PACKET_MODE (9 << 4)
72#define MSM_UART_CR_CMD_MODE_RESET (12 << 4)
73#define MSM_UART_CR_CMD_SET_RFR (13 << 4)
74#define MSM_UART_CR_CMD_RESET_RFR (14 << 4)
75#define MSM_UART_CR_CMD_PROTECTION_EN (16 << 4)
76#define MSM_UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
77#define MSM_UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
78#define MSM_UART_CR_CMD_FORCE_STALE (4 << 8)
79#define MSM_UART_CR_CMD_RESET_TX_READY (3 << 8)
80#define MSM_UART_CR_TX_DISABLE BIT(3)
81#define MSM_UART_CR_TX_ENABLE BIT(2)
82#define MSM_UART_CR_RX_DISABLE BIT(1)
83#define MSM_UART_CR_RX_ENABLE BIT(0)
84#define MSM_UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
85
86#define MSM_UART_IMR 0x0014
87#define MSM_UART_IMR_TXLEV BIT(0)
88#define MSM_UART_IMR_RXSTALE BIT(3)
89#define MSM_UART_IMR_RXLEV BIT(4)
90#define MSM_UART_IMR_DELTA_CTS BIT(5)
91#define MSM_UART_IMR_CURRENT_CTS BIT(6)
92#define MSM_UART_IMR_RXBREAK_START BIT(10)
93
94#define MSM_UART_IPR_RXSTALE_LAST 0x20
95#define MSM_UART_IPR_STALE_LSB 0x1F
96#define MSM_UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
97#define MSM_UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
98
99#define MSM_UART_IPR 0x0018
100#define MSM_UART_TFWR 0x001C
101#define MSM_UART_RFWR 0x0020
102#define MSM_UART_HCR 0x0024
103
104#define MSM_UART_MREG 0x0028
105#define MSM_UART_NREG 0x002C
106#define MSM_UART_DREG 0x0030
107#define MSM_UART_MNDREG 0x0034
108#define MSM_UART_IRDA 0x0038
109#define MSM_UART_MISR_MODE 0x0040
110#define MSM_UART_MISR_RESET 0x0044
111#define MSM_UART_MISR_EXPORT 0x0048
112#define MSM_UART_MISR_VAL 0x004C
113#define MSM_UART_TEST_CTRL 0x0050
114
115#define MSM_UART_SR 0x0008
116#define MSM_UART_SR_HUNT_CHAR BIT(7)
117#define MSM_UART_SR_RX_BREAK BIT(6)
118#define MSM_UART_SR_PAR_FRAME_ERR BIT(5)
119#define MSM_UART_SR_OVERRUN BIT(4)
120#define MSM_UART_SR_TX_EMPTY BIT(3)
121#define MSM_UART_SR_TX_READY BIT(2)
122#define MSM_UART_SR_RX_FULL BIT(1)
123#define MSM_UART_SR_RX_READY BIT(0)
124
125#define MSM_UART_RF 0x000C
126#define UARTDM_RF 0x0070
127#define MSM_UART_MISR 0x0010
128#define MSM_UART_ISR 0x0014
129#define MSM_UART_ISR_TX_READY BIT(7)
130
131#define UARTDM_RXFS 0x50
132#define UARTDM_RXFS_BUF_SHIFT 0x7
133#define UARTDM_RXFS_BUF_MASK 0x7
134
135#define UARTDM_DMEN 0x3C
136#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
137#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
138
139#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
140#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
141
142#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
143#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
144
145#define UARTDM_DMRX 0x34
146#define UARTDM_NCF_TX 0x40
147#define UARTDM_RX_TOTAL_SNAP 0x38
148
149#define UARTDM_BURST_SIZE 16 /* in bytes */
150#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
151#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
152#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
153
154enum {
155 UARTDM_1P1 = 1,
156 UARTDM_1P2,
157 UARTDM_1P3,
158 UARTDM_1P4,
159};
160
161struct msm_dma {
162 struct dma_chan *chan;
163 enum dma_data_direction dir;
164 union {
165 struct {
166 dma_addr_t phys;
167 unsigned char *virt;
168 unsigned int count;
169 } rx;
170 struct scatterlist tx_sg;
171 };
172 dma_cookie_t cookie;
173 u32 enable_bit;
174 struct dma_async_tx_descriptor *desc;
175};
176
177struct msm_port {
178 struct uart_port uart;
179 char name[16];
180 struct clk *clk;
181 struct clk *pclk;
182 unsigned int imr;
183 int is_uartdm;
184 unsigned int old_snap_state;
185 bool break_detected;
186 struct msm_dma tx_dma;
187 struct msm_dma rx_dma;
188};
189
190static inline struct msm_port *to_msm_port(struct uart_port *up)
191{
192 return container_of(up, struct msm_port, uart);
193}
194
195static
196void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
197{
198 writel_relaxed(val, port->membase + off);
199}
200
201static
202unsigned int msm_read(struct uart_port *port, unsigned int off)
203{
204 return readl_relaxed(port->membase + off);
205}
206
207/*
208 * Setup the MND registers to use the TCXO clock.
209 */
210static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
211{
212 msm_write(port, 0x06, MSM_UART_MREG);
213 msm_write(port, 0xF1, MSM_UART_NREG);
214 msm_write(port, 0x0F, MSM_UART_DREG);
215 msm_write(port, 0x1A, MSM_UART_MNDREG);
216 port->uartclk = 1843200;
217}
218
219/*
220 * Setup the MND registers to use the TCXO clock divided by 4.
221 */
222static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
223{
224 msm_write(port, 0x18, MSM_UART_MREG);
225 msm_write(port, 0xF6, MSM_UART_NREG);
226 msm_write(port, 0x0F, MSM_UART_DREG);
227 msm_write(port, 0x0A, MSM_UART_MNDREG);
228 port->uartclk = 1843200;
229}
230
231static void msm_serial_set_mnd_regs(struct uart_port *port)
232{
233 struct msm_port *msm_port = to_msm_port(port);
234
235 /*
236 * These registers don't exist so we change the clk input rate
237 * on uartdm hardware instead
238 */
239 if (msm_port->is_uartdm)
240 return;
241
242 if (port->uartclk == 19200000)
243 msm_serial_set_mnd_regs_tcxo(port);
244 else if (port->uartclk == 4800000)
245 msm_serial_set_mnd_regs_tcxoby4(port);
246}
247
248static void msm_handle_tx(struct uart_port *port);
249static void msm_start_rx_dma(struct msm_port *msm_port);
250
251static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
252{
253 struct device *dev = port->dev;
254 unsigned int mapped;
255 u32 val;
256
257 if (dma->dir == DMA_TO_DEVICE) {
258 mapped = sg_dma_len(&dma->tx_sg);
259 } else {
260 mapped = dma->rx.count;
261 dma->rx.count = 0;
262 }
263
264 dmaengine_terminate_all(dma->chan);
265
266 /*
267 * DMA Stall happens if enqueue and flush command happens concurrently.
268 * For example before changing the baud rate/protocol configuration and
269 * sending flush command to ADM, disable the channel of UARTDM.
270 * Note: should not reset the receiver here immediately as it is not
271 * suggested to do disable/reset or reset/disable at the same time.
272 */
273 val = msm_read(port, UARTDM_DMEN);
274 val &= ~dma->enable_bit;
275 msm_write(port, val, UARTDM_DMEN);
276
277 if (mapped) {
278 if (dma->dir == DMA_TO_DEVICE) {
279 dma_unmap_sg(dev, &dma->tx_sg, 1, dma->dir);
280 sg_init_table(&dma->tx_sg, 1);
281 } else
282 dma_unmap_single(dev, dma->rx.phys, mapped, dma->dir);
283 }
284}
285
286static void msm_release_dma(struct msm_port *msm_port)
287{
288 struct msm_dma *dma;
289
290 dma = &msm_port->tx_dma;
291 if (dma->chan) {
292 msm_stop_dma(&msm_port->uart, dma);
293 dma_release_channel(dma->chan);
294 }
295
296 memset(dma, 0, sizeof(*dma));
297
298 dma = &msm_port->rx_dma;
299 if (dma->chan) {
300 msm_stop_dma(&msm_port->uart, dma);
301 dma_release_channel(dma->chan);
302 kfree(dma->rx.virt);
303 }
304
305 memset(dma, 0, sizeof(*dma));
306}
307
308static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
309{
310 struct device *dev = msm_port->uart.dev;
311 struct dma_slave_config conf;
312 struct qcom_adm_peripheral_config periph_conf = {};
313 struct msm_dma *dma;
314 u32 crci = 0;
315 int ret;
316
317 dma = &msm_port->tx_dma;
318
319 /* allocate DMA resources, if available */
320 dma->chan = dma_request_chan(dev, "tx");
321 if (IS_ERR(dma->chan))
322 goto no_tx;
323
324 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
325
326 memset(&conf, 0, sizeof(conf));
327 conf.direction = DMA_MEM_TO_DEV;
328 conf.device_fc = true;
329 conf.dst_addr = base + UARTDM_TF;
330 conf.dst_maxburst = UARTDM_BURST_SIZE;
331 if (crci) {
332 conf.peripheral_config = &periph_conf;
333 conf.peripheral_size = sizeof(periph_conf);
334 periph_conf.crci = crci;
335 }
336
337 ret = dmaengine_slave_config(dma->chan, &conf);
338 if (ret)
339 goto rel_tx;
340
341 dma->dir = DMA_TO_DEVICE;
342
343 if (msm_port->is_uartdm < UARTDM_1P4)
344 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
345 else
346 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
347
348 return;
349
350rel_tx:
351 dma_release_channel(dma->chan);
352no_tx:
353 memset(dma, 0, sizeof(*dma));
354}
355
356static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
357{
358 struct device *dev = msm_port->uart.dev;
359 struct dma_slave_config conf;
360 struct qcom_adm_peripheral_config periph_conf = {};
361 struct msm_dma *dma;
362 u32 crci = 0;
363 int ret;
364
365 dma = &msm_port->rx_dma;
366
367 /* allocate DMA resources, if available */
368 dma->chan = dma_request_chan(dev, "rx");
369 if (IS_ERR(dma->chan))
370 goto no_rx;
371
372 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
373
374 dma->rx.virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
375 if (!dma->rx.virt)
376 goto rel_rx;
377
378 memset(&conf, 0, sizeof(conf));
379 conf.direction = DMA_DEV_TO_MEM;
380 conf.device_fc = true;
381 conf.src_addr = base + UARTDM_RF;
382 conf.src_maxburst = UARTDM_BURST_SIZE;
383 if (crci) {
384 conf.peripheral_config = &periph_conf;
385 conf.peripheral_size = sizeof(periph_conf);
386 periph_conf.crci = crci;
387 }
388
389 ret = dmaengine_slave_config(dma->chan, &conf);
390 if (ret)
391 goto err;
392
393 dma->dir = DMA_FROM_DEVICE;
394
395 if (msm_port->is_uartdm < UARTDM_1P4)
396 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
397 else
398 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
399
400 return;
401err:
402 kfree(dma->rx.virt);
403rel_rx:
404 dma_release_channel(dma->chan);
405no_rx:
406 memset(dma, 0, sizeof(*dma));
407}
408
409static inline void msm_wait_for_xmitr(struct uart_port *port)
410{
411 unsigned int timeout = 500000;
412
413 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY)) {
414 if (msm_read(port, MSM_UART_ISR) & MSM_UART_ISR_TX_READY)
415 break;
416 udelay(1);
417 if (!timeout--)
418 break;
419 }
420 msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR);
421}
422
423static void msm_stop_tx(struct uart_port *port)
424{
425 struct msm_port *msm_port = to_msm_port(port);
426
427 msm_port->imr &= ~MSM_UART_IMR_TXLEV;
428 msm_write(port, msm_port->imr, MSM_UART_IMR);
429}
430
431static void msm_start_tx(struct uart_port *port)
432{
433 struct msm_port *msm_port = to_msm_port(port);
434 struct msm_dma *dma = &msm_port->tx_dma;
435
436 /* Already started in DMA mode */
437 if (sg_dma_len(&dma->tx_sg))
438 return;
439
440 msm_port->imr |= MSM_UART_IMR_TXLEV;
441 msm_write(port, msm_port->imr, MSM_UART_IMR);
442}
443
444static void msm_reset_dm_count(struct uart_port *port, int count)
445{
446 msm_wait_for_xmitr(port);
447 msm_write(port, count, UARTDM_NCF_TX);
448 msm_read(port, UARTDM_NCF_TX);
449}
450
451static void msm_complete_tx_dma(void *args)
452{
453 struct msm_port *msm_port = args;
454 struct uart_port *port = &msm_port->uart;
455 struct tty_port *tport = &port->state->port;
456 struct msm_dma *dma = &msm_port->tx_dma;
457 struct dma_tx_state state;
458 unsigned long flags;
459 unsigned int count;
460 u32 val;
461
462 uart_port_lock_irqsave(port, &flags);
463
464 /* Already stopped */
465 if (!sg_dma_len(&dma->tx_sg))
466 goto done;
467
468 dmaengine_tx_status(dma->chan, dma->cookie, &state);
469
470 dma_unmap_sg(port->dev, &dma->tx_sg, 1, dma->dir);
471
472 val = msm_read(port, UARTDM_DMEN);
473 val &= ~dma->enable_bit;
474 msm_write(port, val, UARTDM_DMEN);
475
476 if (msm_port->is_uartdm > UARTDM_1P3) {
477 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
478 msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR);
479 }
480
481 count = sg_dma_len(&dma->tx_sg) - state.residue;
482 uart_xmit_advance(port, count);
483 sg_init_table(&dma->tx_sg, 1);
484
485 /* Restore "Tx FIFO below watermark" interrupt */
486 msm_port->imr |= MSM_UART_IMR_TXLEV;
487 msm_write(port, msm_port->imr, MSM_UART_IMR);
488
489 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
490 uart_write_wakeup(port);
491
492 msm_handle_tx(port);
493done:
494 uart_port_unlock_irqrestore(port, flags);
495}
496
497static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
498{
499 struct uart_port *port = &msm_port->uart;
500 struct tty_port *tport = &port->state->port;
501 struct msm_dma *dma = &msm_port->tx_dma;
502 unsigned int mapped;
503 int ret;
504 u32 val;
505
506 sg_init_table(&dma->tx_sg, 1);
507 kfifo_dma_out_prepare(&tport->xmit_fifo, &dma->tx_sg, 1, count);
508
509 mapped = dma_map_sg(port->dev, &dma->tx_sg, 1, dma->dir);
510 if (!mapped) {
511 ret = -EIO;
512 goto zero_sg;
513 }
514
515 dma->desc = dmaengine_prep_slave_sg(dma->chan, &dma->tx_sg, 1,
516 DMA_MEM_TO_DEV,
517 DMA_PREP_INTERRUPT |
518 DMA_PREP_FENCE);
519 if (!dma->desc) {
520 ret = -EIO;
521 goto unmap;
522 }
523
524 dma->desc->callback = msm_complete_tx_dma;
525 dma->desc->callback_param = msm_port;
526
527 dma->cookie = dmaengine_submit(dma->desc);
528 ret = dma_submit_error(dma->cookie);
529 if (ret)
530 goto unmap;
531
532 /*
533 * Using DMA complete for Tx FIFO reload, no need for
534 * "Tx FIFO below watermark" one, disable it
535 */
536 msm_port->imr &= ~MSM_UART_IMR_TXLEV;
537 msm_write(port, msm_port->imr, MSM_UART_IMR);
538
539 val = msm_read(port, UARTDM_DMEN);
540 val |= dma->enable_bit;
541
542 if (msm_port->is_uartdm < UARTDM_1P4)
543 msm_write(port, val, UARTDM_DMEN);
544
545 msm_reset_dm_count(port, count);
546
547 if (msm_port->is_uartdm > UARTDM_1P3)
548 msm_write(port, val, UARTDM_DMEN);
549
550 dma_async_issue_pending(dma->chan);
551 return 0;
552unmap:
553 dma_unmap_sg(port->dev, &dma->tx_sg, 1, dma->dir);
554zero_sg:
555 sg_init_table(&dma->tx_sg, 1);
556 return ret;
557}
558
559static void msm_complete_rx_dma(void *args)
560{
561 struct msm_port *msm_port = args;
562 struct uart_port *port = &msm_port->uart;
563 struct tty_port *tport = &port->state->port;
564 struct msm_dma *dma = &msm_port->rx_dma;
565 int count = 0, i, sysrq;
566 unsigned long flags;
567 u32 val;
568
569 uart_port_lock_irqsave(port, &flags);
570
571 /* Already stopped */
572 if (!dma->rx.count)
573 goto done;
574
575 val = msm_read(port, UARTDM_DMEN);
576 val &= ~dma->enable_bit;
577 msm_write(port, val, UARTDM_DMEN);
578
579 if (msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN) {
580 port->icount.overrun++;
581 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
582 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
583 }
584
585 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
586
587 port->icount.rx += count;
588
589 dma->rx.count = 0;
590
591 dma_unmap_single(port->dev, dma->rx.phys, UARTDM_RX_SIZE, dma->dir);
592
593 for (i = 0; i < count; i++) {
594 char flag = TTY_NORMAL;
595
596 if (msm_port->break_detected && dma->rx.virt[i] == 0) {
597 port->icount.brk++;
598 flag = TTY_BREAK;
599 msm_port->break_detected = false;
600 if (uart_handle_break(port))
601 continue;
602 }
603
604 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
605 flag = TTY_NORMAL;
606
607 sysrq = uart_prepare_sysrq_char(port, dma->rx.virt[i]);
608 if (!sysrq)
609 tty_insert_flip_char(tport, dma->rx.virt[i], flag);
610 }
611
612 msm_start_rx_dma(msm_port);
613done:
614 uart_unlock_and_check_sysrq_irqrestore(port, flags);
615
616 if (count)
617 tty_flip_buffer_push(tport);
618}
619
620static void msm_start_rx_dma(struct msm_port *msm_port)
621{
622 struct msm_dma *dma = &msm_port->rx_dma;
623 struct uart_port *uart = &msm_port->uart;
624 u32 val;
625 int ret;
626
627 if (IS_ENABLED(CONFIG_CONSOLE_POLL))
628 return;
629
630 if (!dma->chan)
631 return;
632
633 dma->rx.phys = dma_map_single(uart->dev, dma->rx.virt,
634 UARTDM_RX_SIZE, dma->dir);
635 ret = dma_mapping_error(uart->dev, dma->rx.phys);
636 if (ret)
637 goto sw_mode;
638
639 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->rx.phys,
640 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
641 DMA_PREP_INTERRUPT);
642 if (!dma->desc)
643 goto unmap;
644
645 dma->desc->callback = msm_complete_rx_dma;
646 dma->desc->callback_param = msm_port;
647
648 dma->cookie = dmaengine_submit(dma->desc);
649 ret = dma_submit_error(dma->cookie);
650 if (ret)
651 goto unmap;
652 /*
653 * Using DMA for FIFO off-load, no need for "Rx FIFO over
654 * watermark" or "stale" interrupts, disable them
655 */
656 msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
657
658 /*
659 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
660 * we need RXSTALE to flush input DMA fifo to memory
661 */
662 if (msm_port->is_uartdm < UARTDM_1P4)
663 msm_port->imr |= MSM_UART_IMR_RXSTALE;
664
665 msm_write(uart, msm_port->imr, MSM_UART_IMR);
666
667 dma->rx.count = UARTDM_RX_SIZE;
668
669 dma_async_issue_pending(dma->chan);
670
671 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
672 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
673
674 val = msm_read(uart, UARTDM_DMEN);
675 val |= dma->enable_bit;
676
677 if (msm_port->is_uartdm < UARTDM_1P4)
678 msm_write(uart, val, UARTDM_DMEN);
679
680 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
681
682 if (msm_port->is_uartdm > UARTDM_1P3)
683 msm_write(uart, val, UARTDM_DMEN);
684
685 return;
686unmap:
687 dma_unmap_single(uart->dev, dma->rx.phys, UARTDM_RX_SIZE, dma->dir);
688
689sw_mode:
690 /*
691 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN),
692 * receiver must be reset.
693 */
694 msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
695 msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
696
697 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
698 msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
699 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
700
701 /* Re-enable RX interrupts */
702 msm_port->imr |= MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE;
703 msm_write(uart, msm_port->imr, MSM_UART_IMR);
704}
705
706static void msm_stop_rx(struct uart_port *port)
707{
708 struct msm_port *msm_port = to_msm_port(port);
709 struct msm_dma *dma = &msm_port->rx_dma;
710
711 msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
712 msm_write(port, msm_port->imr, MSM_UART_IMR);
713
714 if (dma->chan)
715 msm_stop_dma(port, dma);
716}
717
718static void msm_enable_ms(struct uart_port *port)
719{
720 struct msm_port *msm_port = to_msm_port(port);
721
722 msm_port->imr |= MSM_UART_IMR_DELTA_CTS;
723 msm_write(port, msm_port->imr, MSM_UART_IMR);
724}
725
726static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
727 __must_hold(&port->lock)
728{
729 struct tty_port *tport = &port->state->port;
730 unsigned int sr;
731 int count = 0;
732 struct msm_port *msm_port = to_msm_port(port);
733
734 if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
735 port->icount.overrun++;
736 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
737 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
738 }
739
740 if (misr & MSM_UART_IMR_RXSTALE) {
741 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
742 msm_port->old_snap_state;
743 msm_port->old_snap_state = 0;
744 } else {
745 count = 4 * (msm_read(port, MSM_UART_RFWR));
746 msm_port->old_snap_state += count;
747 }
748
749 /* TODO: Precise error reporting */
750
751 port->icount.rx += count;
752
753 while (count > 0) {
754 unsigned char buf[4];
755 int sysrq, r_count, i;
756
757 sr = msm_read(port, MSM_UART_SR);
758 if ((sr & MSM_UART_SR_RX_READY) == 0) {
759 msm_port->old_snap_state -= count;
760 break;
761 }
762
763 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
764 r_count = min_t(int, count, sizeof(buf));
765
766 for (i = 0; i < r_count; i++) {
767 char flag = TTY_NORMAL;
768
769 if (msm_port->break_detected && buf[i] == 0) {
770 port->icount.brk++;
771 flag = TTY_BREAK;
772 msm_port->break_detected = false;
773 if (uart_handle_break(port))
774 continue;
775 }
776
777 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
778 flag = TTY_NORMAL;
779
780 sysrq = uart_prepare_sysrq_char(port, buf[i]);
781 if (!sysrq)
782 tty_insert_flip_char(tport, buf[i], flag);
783 }
784 count -= r_count;
785 }
786
787 tty_flip_buffer_push(tport);
788
789 if (misr & (MSM_UART_IMR_RXSTALE))
790 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
791 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
792 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
793
794 /* Try to use DMA */
795 msm_start_rx_dma(msm_port);
796}
797
798static void msm_handle_rx(struct uart_port *port)
799 __must_hold(&port->lock)
800{
801 struct tty_port *tport = &port->state->port;
802 unsigned int sr;
803
804 /*
805 * Handle overrun. My understanding of the hardware is that overrun
806 * is not tied to the RX buffer, so we handle the case out of band.
807 */
808 if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
809 port->icount.overrun++;
810 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
811 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
812 }
813
814 /* and now the main RX loop */
815 while ((sr = msm_read(port, MSM_UART_SR)) & MSM_UART_SR_RX_READY) {
816 unsigned int c;
817 char flag = TTY_NORMAL;
818 int sysrq;
819
820 c = msm_read(port, MSM_UART_RF);
821
822 if (sr & MSM_UART_SR_RX_BREAK) {
823 port->icount.brk++;
824 if (uart_handle_break(port))
825 continue;
826 } else if (sr & MSM_UART_SR_PAR_FRAME_ERR) {
827 port->icount.frame++;
828 } else {
829 port->icount.rx++;
830 }
831
832 /* Mask conditions we're ignoring. */
833 sr &= port->read_status_mask;
834
835 if (sr & MSM_UART_SR_RX_BREAK)
836 flag = TTY_BREAK;
837 else if (sr & MSM_UART_SR_PAR_FRAME_ERR)
838 flag = TTY_FRAME;
839
840 sysrq = uart_prepare_sysrq_char(port, c);
841 if (!sysrq)
842 tty_insert_flip_char(tport, c, flag);
843 }
844
845 tty_flip_buffer_push(tport);
846}
847
848static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
849{
850 struct msm_port *msm_port = to_msm_port(port);
851 struct tty_port *tport = &port->state->port;
852 unsigned int num_chars;
853 unsigned int tf_pointer = 0;
854 void __iomem *tf;
855
856 if (msm_port->is_uartdm)
857 tf = port->membase + UARTDM_TF;
858 else
859 tf = port->membase + MSM_UART_TF;
860
861 if (tx_count && msm_port->is_uartdm)
862 msm_reset_dm_count(port, tx_count);
863
864 while (tf_pointer < tx_count) {
865 unsigned char buf[4] = { 0 };
866
867 if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
868 break;
869
870 if (msm_port->is_uartdm)
871 num_chars = min(tx_count - tf_pointer,
872 (unsigned int)sizeof(buf));
873 else
874 num_chars = 1;
875
876 num_chars = uart_fifo_out(port, buf, num_chars);
877 iowrite32_rep(tf, buf, 1);
878 tf_pointer += num_chars;
879 }
880
881 /* disable tx interrupts if nothing more to send */
882 if (kfifo_is_empty(&tport->xmit_fifo))
883 msm_stop_tx(port);
884
885 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
886 uart_write_wakeup(port);
887}
888
889static void msm_handle_tx(struct uart_port *port)
890{
891 struct msm_port *msm_port = to_msm_port(port);
892 struct tty_port *tport = &port->state->port;
893 struct msm_dma *dma = &msm_port->tx_dma;
894 unsigned int pio_count, dma_count, dma_min;
895 char buf[4] = { 0 };
896 void __iomem *tf;
897 int err = 0;
898
899 if (port->x_char) {
900 if (msm_port->is_uartdm)
901 tf = port->membase + UARTDM_TF;
902 else
903 tf = port->membase + MSM_UART_TF;
904
905 buf[0] = port->x_char;
906
907 if (msm_port->is_uartdm)
908 msm_reset_dm_count(port, 1);
909
910 iowrite32_rep(tf, buf, 1);
911 port->icount.tx++;
912 port->x_char = 0;
913 return;
914 }
915
916 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
917 msm_stop_tx(port);
918 return;
919 }
920
921 dma_count = pio_count = kfifo_out_linear(&tport->xmit_fifo, NULL,
922 UART_XMIT_SIZE);
923
924 dma_min = 1; /* Always DMA */
925 if (msm_port->is_uartdm > UARTDM_1P3) {
926 dma_count = UARTDM_TX_AIGN(dma_count);
927 dma_min = UARTDM_BURST_SIZE;
928 } else {
929 if (dma_count > UARTDM_TX_MAX)
930 dma_count = UARTDM_TX_MAX;
931 }
932
933 if (pio_count > port->fifosize)
934 pio_count = port->fifosize;
935
936 if (!dma->chan || dma_count < dma_min)
937 msm_handle_tx_pio(port, pio_count);
938 else
939 err = msm_handle_tx_dma(msm_port, dma_count);
940
941 if (err) /* fall back to PIO mode */
942 msm_handle_tx_pio(port, pio_count);
943}
944
945static void msm_handle_delta_cts(struct uart_port *port)
946{
947 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
948 port->icount.cts++;
949 wake_up_interruptible(&port->state->port.delta_msr_wait);
950}
951
952static irqreturn_t msm_uart_irq(int irq, void *dev_id)
953{
954 struct uart_port *port = dev_id;
955 struct msm_port *msm_port = to_msm_port(port);
956 struct msm_dma *dma = &msm_port->rx_dma;
957 unsigned int misr;
958 u32 val;
959
960 uart_port_lock(port);
961 misr = msm_read(port, MSM_UART_MISR);
962 msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */
963
964 if (misr & MSM_UART_IMR_RXBREAK_START) {
965 msm_port->break_detected = true;
966 msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR);
967 }
968
969 if (misr & (MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE)) {
970 if (dma->rx.count) {
971 val = MSM_UART_CR_CMD_STALE_EVENT_DISABLE;
972 msm_write(port, val, MSM_UART_CR);
973 val = MSM_UART_CR_CMD_RESET_STALE_INT;
974 msm_write(port, val, MSM_UART_CR);
975 /*
976 * Flush DMA input fifo to memory, this will also
977 * trigger DMA RX completion
978 */
979 dmaengine_terminate_all(dma->chan);
980 } else if (msm_port->is_uartdm) {
981 msm_handle_rx_dm(port, misr);
982 } else {
983 msm_handle_rx(port);
984 }
985 }
986 if (misr & MSM_UART_IMR_TXLEV)
987 msm_handle_tx(port);
988 if (misr & MSM_UART_IMR_DELTA_CTS)
989 msm_handle_delta_cts(port);
990
991 msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */
992 uart_unlock_and_check_sysrq(port);
993
994 return IRQ_HANDLED;
995}
996
997static unsigned int msm_tx_empty(struct uart_port *port)
998{
999 return (msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
1000}
1001
1002static unsigned int msm_get_mctrl(struct uart_port *port)
1003{
1004 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
1005}
1006
1007static void msm_reset(struct uart_port *port)
1008{
1009 struct msm_port *msm_port = to_msm_port(port);
1010 unsigned int mr;
1011
1012 /* reset everything */
1013 msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
1014 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
1015 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
1016 msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR);
1017 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
1018 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1019 mr = msm_read(port, MSM_UART_MR1);
1020 mr &= ~MSM_UART_MR1_RX_RDY_CTL;
1021 msm_write(port, mr, MSM_UART_MR1);
1022
1023 /* Disable DM modes */
1024 if (msm_port->is_uartdm)
1025 msm_write(port, 0, UARTDM_DMEN);
1026}
1027
1028static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1029{
1030 unsigned int mr;
1031
1032 mr = msm_read(port, MSM_UART_MR1);
1033
1034 if (!(mctrl & TIOCM_RTS)) {
1035 mr &= ~MSM_UART_MR1_RX_RDY_CTL;
1036 msm_write(port, mr, MSM_UART_MR1);
1037 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1038 } else {
1039 mr |= MSM_UART_MR1_RX_RDY_CTL;
1040 msm_write(port, mr, MSM_UART_MR1);
1041 }
1042}
1043
1044static void msm_break_ctl(struct uart_port *port, int break_ctl)
1045{
1046 if (break_ctl)
1047 msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR);
1048 else
1049 msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR);
1050}
1051
1052struct msm_baud_map {
1053 u16 divisor;
1054 u8 code;
1055 u8 rxstale;
1056};
1057
1058static const struct msm_baud_map *
1059msm_find_best_baud(struct uart_port *port, unsigned int baud,
1060 unsigned long *rate)
1061{
1062 struct msm_port *msm_port = to_msm_port(port);
1063 unsigned int divisor, result;
1064 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1065 const struct msm_baud_map *entry, *end, *best;
1066 static const struct msm_baud_map table[] = {
1067 { 1, 0xff, 31 },
1068 { 2, 0xee, 16 },
1069 { 3, 0xdd, 8 },
1070 { 4, 0xcc, 6 },
1071 { 6, 0xbb, 6 },
1072 { 8, 0xaa, 6 },
1073 { 12, 0x99, 6 },
1074 { 16, 0x88, 1 },
1075 { 24, 0x77, 1 },
1076 { 32, 0x66, 1 },
1077 { 48, 0x55, 1 },
1078 { 96, 0x44, 1 },
1079 { 192, 0x33, 1 },
1080 { 384, 0x22, 1 },
1081 { 768, 0x11, 1 },
1082 { 1536, 0x00, 1 },
1083 };
1084
1085 best = table; /* Default to smallest divider */
1086 target = clk_round_rate(msm_port->clk, 16 * baud);
1087 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1088
1089 end = table + ARRAY_SIZE(table);
1090 entry = table;
1091 while (entry < end) {
1092 if (entry->divisor <= divisor) {
1093 result = target / entry->divisor / 16;
1094 diff = abs(result - baud);
1095
1096 /* Keep track of best entry */
1097 if (diff < best_diff) {
1098 best_diff = diff;
1099 best = entry;
1100 best_rate = target;
1101 }
1102
1103 if (result == baud)
1104 break;
1105 } else if (entry->divisor > divisor) {
1106 old = target;
1107 target = clk_round_rate(msm_port->clk, old + 1);
1108 /*
1109 * The rate didn't get any faster so we can't do
1110 * better at dividing it down
1111 */
1112 if (target == old)
1113 break;
1114
1115 /* Start the divisor search over at this new rate */
1116 entry = table;
1117 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1118 continue;
1119 }
1120 entry++;
1121 }
1122
1123 *rate = best_rate;
1124 return best;
1125}
1126
1127static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1128 unsigned long *saved_flags)
1129 __must_hold(&port->lock)
1130{
1131 unsigned int rxstale, watermark, mask;
1132 struct msm_port *msm_port = to_msm_port(port);
1133 const struct msm_baud_map *entry;
1134 unsigned long flags, rate;
1135
1136 flags = *saved_flags;
1137 uart_port_unlock_irqrestore(port, flags);
1138
1139 entry = msm_find_best_baud(port, baud, &rate);
1140 dev_pm_opp_set_rate(port->dev, rate);
1141 baud = rate / 16 / entry->divisor;
1142
1143 uart_port_lock_irqsave(port, &flags);
1144 *saved_flags = flags;
1145 port->uartclk = rate;
1146
1147 msm_write(port, entry->code, MSM_UART_CSR);
1148
1149 /* RX stale watermark */
1150 rxstale = entry->rxstale;
1151 watermark = MSM_UART_IPR_STALE_LSB & rxstale;
1152 if (msm_port->is_uartdm) {
1153 mask = MSM_UART_DM_IPR_STALE_TIMEOUT_MSB;
1154 } else {
1155 watermark |= MSM_UART_IPR_RXSTALE_LAST;
1156 mask = MSM_UART_IPR_STALE_TIMEOUT_MSB;
1157 }
1158
1159 watermark |= mask & (rxstale << 2);
1160
1161 msm_write(port, watermark, MSM_UART_IPR);
1162
1163 /* set RX watermark */
1164 watermark = (port->fifosize * 3) / 4;
1165 msm_write(port, watermark, MSM_UART_RFWR);
1166
1167 /* set TX watermark */
1168 msm_write(port, 10, MSM_UART_TFWR);
1169
1170 msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR);
1171 msm_reset(port);
1172
1173 /* Enable RX and TX */
1174 msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
1175
1176 /* turn on RX and CTS interrupts */
1177 msm_port->imr = MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE |
1178 MSM_UART_IMR_CURRENT_CTS | MSM_UART_IMR_RXBREAK_START;
1179
1180 msm_write(port, msm_port->imr, MSM_UART_IMR);
1181
1182 if (msm_port->is_uartdm) {
1183 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1184 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1185 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1186 }
1187
1188 return baud;
1189}
1190
1191static void msm_init_clock(struct uart_port *port)
1192{
1193 struct msm_port *msm_port = to_msm_port(port);
1194
1195 dev_pm_opp_set_rate(port->dev, port->uartclk);
1196 clk_prepare_enable(msm_port->clk);
1197 clk_prepare_enable(msm_port->pclk);
1198 msm_serial_set_mnd_regs(port);
1199}
1200
1201static int msm_startup(struct uart_port *port)
1202{
1203 struct msm_port *msm_port = to_msm_port(port);
1204 unsigned int data, rfr_level, mask;
1205 int ret;
1206
1207 snprintf(msm_port->name, sizeof(msm_port->name),
1208 "msm_serial%d", port->line);
1209
1210 msm_init_clock(port);
1211
1212 if (likely(port->fifosize > 12))
1213 rfr_level = port->fifosize - 12;
1214 else
1215 rfr_level = port->fifosize;
1216
1217 /* set automatic RFR level */
1218 data = msm_read(port, MSM_UART_MR1);
1219
1220 if (msm_port->is_uartdm)
1221 mask = MSM_UART_DM_MR1_AUTO_RFR_LEVEL1;
1222 else
1223 mask = MSM_UART_MR1_AUTO_RFR_LEVEL1;
1224
1225 data &= ~mask;
1226 data &= ~MSM_UART_MR1_AUTO_RFR_LEVEL0;
1227 data |= mask & (rfr_level << 2);
1228 data |= MSM_UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1229 msm_write(port, data, MSM_UART_MR1);
1230
1231 if (msm_port->is_uartdm) {
1232 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1233 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1234 }
1235
1236 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1237 msm_port->name, port);
1238 if (unlikely(ret))
1239 goto err_irq;
1240
1241 return 0;
1242
1243err_irq:
1244 if (msm_port->is_uartdm)
1245 msm_release_dma(msm_port);
1246
1247 clk_disable_unprepare(msm_port->pclk);
1248 clk_disable_unprepare(msm_port->clk);
1249 dev_pm_opp_set_rate(port->dev, 0);
1250
1251 return ret;
1252}
1253
1254static void msm_shutdown(struct uart_port *port)
1255{
1256 struct msm_port *msm_port = to_msm_port(port);
1257
1258 msm_port->imr = 0;
1259 msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */
1260
1261 if (msm_port->is_uartdm)
1262 msm_release_dma(msm_port);
1263
1264 clk_disable_unprepare(msm_port->clk);
1265 dev_pm_opp_set_rate(port->dev, 0);
1266
1267 free_irq(port->irq, port);
1268}
1269
1270static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1271 const struct ktermios *old)
1272{
1273 struct msm_port *msm_port = to_msm_port(port);
1274 struct msm_dma *dma = &msm_port->rx_dma;
1275 unsigned long flags;
1276 unsigned int baud, mr;
1277
1278 uart_port_lock_irqsave(port, &flags);
1279
1280 if (dma->chan) /* Terminate if any */
1281 msm_stop_dma(port, dma);
1282
1283 /* calculate and set baud rate */
1284 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1285 baud = msm_set_baud_rate(port, baud, &flags);
1286 if (tty_termios_baud_rate(termios))
1287 tty_termios_encode_baud_rate(termios, baud, baud);
1288
1289 /* calculate parity */
1290 mr = msm_read(port, MSM_UART_MR2);
1291 mr &= ~MSM_UART_MR2_PARITY_MODE;
1292 if (termios->c_cflag & PARENB) {
1293 if (termios->c_cflag & PARODD)
1294 mr |= MSM_UART_MR2_PARITY_MODE_ODD;
1295 else if (termios->c_cflag & CMSPAR)
1296 mr |= MSM_UART_MR2_PARITY_MODE_SPACE;
1297 else
1298 mr |= MSM_UART_MR2_PARITY_MODE_EVEN;
1299 }
1300
1301 /* calculate bits per char */
1302 mr &= ~MSM_UART_MR2_BITS_PER_CHAR;
1303 switch (termios->c_cflag & CSIZE) {
1304 case CS5:
1305 mr |= MSM_UART_MR2_BITS_PER_CHAR_5;
1306 break;
1307 case CS6:
1308 mr |= MSM_UART_MR2_BITS_PER_CHAR_6;
1309 break;
1310 case CS7:
1311 mr |= MSM_UART_MR2_BITS_PER_CHAR_7;
1312 break;
1313 case CS8:
1314 default:
1315 mr |= MSM_UART_MR2_BITS_PER_CHAR_8;
1316 break;
1317 }
1318
1319 /* calculate stop bits */
1320 mr &= ~(MSM_UART_MR2_STOP_BIT_LEN_ONE | MSM_UART_MR2_STOP_BIT_LEN_TWO);
1321 if (termios->c_cflag & CSTOPB)
1322 mr |= MSM_UART_MR2_STOP_BIT_LEN_TWO;
1323 else
1324 mr |= MSM_UART_MR2_STOP_BIT_LEN_ONE;
1325
1326 /* set parity, bits per char, and stop bit */
1327 msm_write(port, mr, MSM_UART_MR2);
1328
1329 /* calculate and set hardware flow control */
1330 mr = msm_read(port, MSM_UART_MR1);
1331 mr &= ~(MSM_UART_MR1_CTS_CTL | MSM_UART_MR1_RX_RDY_CTL);
1332 if (termios->c_cflag & CRTSCTS) {
1333 mr |= MSM_UART_MR1_CTS_CTL;
1334 mr |= MSM_UART_MR1_RX_RDY_CTL;
1335 }
1336 msm_write(port, mr, MSM_UART_MR1);
1337
1338 /* Configure status bits to ignore based on termio flags. */
1339 port->read_status_mask = 0;
1340 if (termios->c_iflag & INPCK)
1341 port->read_status_mask |= MSM_UART_SR_PAR_FRAME_ERR;
1342 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1343 port->read_status_mask |= MSM_UART_SR_RX_BREAK;
1344
1345 uart_update_timeout(port, termios->c_cflag, baud);
1346
1347 /* Try to use DMA */
1348 msm_start_rx_dma(msm_port);
1349
1350 uart_port_unlock_irqrestore(port, flags);
1351}
1352
1353static const char *msm_type(struct uart_port *port)
1354{
1355 return "MSM";
1356}
1357
1358static void msm_release_port(struct uart_port *port)
1359{
1360 struct platform_device *pdev = to_platform_device(port->dev);
1361 struct resource *uart_resource;
1362 resource_size_t size;
1363
1364 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1365 if (unlikely(!uart_resource))
1366 return;
1367 size = resource_size(uart_resource);
1368
1369 release_mem_region(port->mapbase, size);
1370 iounmap(port->membase);
1371 port->membase = NULL;
1372}
1373
1374static int msm_request_port(struct uart_port *port)
1375{
1376 struct platform_device *pdev = to_platform_device(port->dev);
1377 struct resource *uart_resource;
1378 resource_size_t size;
1379 int ret;
1380
1381 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1382 if (unlikely(!uart_resource))
1383 return -ENXIO;
1384
1385 size = resource_size(uart_resource);
1386
1387 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1388 return -EBUSY;
1389
1390 port->membase = ioremap(port->mapbase, size);
1391 if (!port->membase) {
1392 ret = -EBUSY;
1393 goto fail_release_port;
1394 }
1395
1396 return 0;
1397
1398fail_release_port:
1399 release_mem_region(port->mapbase, size);
1400 return ret;
1401}
1402
1403static void msm_config_port(struct uart_port *port, int flags)
1404{
1405 int ret;
1406
1407 if (flags & UART_CONFIG_TYPE) {
1408 port->type = PORT_MSM;
1409 ret = msm_request_port(port);
1410 if (ret)
1411 return;
1412 }
1413}
1414
1415static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1416{
1417 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1418 return -EINVAL;
1419 if (unlikely(port->irq != ser->irq))
1420 return -EINVAL;
1421 return 0;
1422}
1423
1424static void msm_power(struct uart_port *port, unsigned int state,
1425 unsigned int oldstate)
1426{
1427 struct msm_port *msm_port = to_msm_port(port);
1428
1429 switch (state) {
1430 case 0:
1431 dev_pm_opp_set_rate(port->dev, port->uartclk);
1432 clk_prepare_enable(msm_port->clk);
1433 clk_prepare_enable(msm_port->pclk);
1434 break;
1435 case 3:
1436 clk_disable_unprepare(msm_port->clk);
1437 dev_pm_opp_set_rate(port->dev, 0);
1438 clk_disable_unprepare(msm_port->pclk);
1439 break;
1440 default:
1441 pr_err("msm_serial: Unknown PM state %d\n", state);
1442 }
1443}
1444
1445#ifdef CONFIG_CONSOLE_POLL
1446static int msm_poll_get_char_single(struct uart_port *port)
1447{
1448 struct msm_port *msm_port = to_msm_port(port);
1449 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : MSM_UART_RF;
1450
1451 if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY))
1452 return NO_POLL_CHAR;
1453
1454 return msm_read(port, rf_reg) & 0xff;
1455}
1456
1457static int msm_poll_get_char_dm(struct uart_port *port)
1458{
1459 int c;
1460 static u32 slop;
1461 static int count;
1462 unsigned char *sp = (unsigned char *)&slop;
1463
1464 /* Check if a previous read had more than one char */
1465 if (count) {
1466 c = sp[sizeof(slop) - count];
1467 count--;
1468 /* Or if FIFO is empty */
1469 } else if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) {
1470 /*
1471 * If RX packing buffer has less than a word, force stale to
1472 * push contents into RX FIFO
1473 */
1474 count = msm_read(port, UARTDM_RXFS);
1475 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1476 if (count) {
1477 msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR);
1478 slop = msm_read(port, UARTDM_RF);
1479 c = sp[0];
1480 count--;
1481 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1482 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1483 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1484 } else {
1485 c = NO_POLL_CHAR;
1486 }
1487 /* FIFO has a word */
1488 } else {
1489 slop = msm_read(port, UARTDM_RF);
1490 c = sp[0];
1491 count = sizeof(slop) - 1;
1492 }
1493
1494 return c;
1495}
1496
1497static int msm_poll_get_char(struct uart_port *port)
1498{
1499 u32 imr;
1500 int c;
1501 struct msm_port *msm_port = to_msm_port(port);
1502
1503 /* Disable all interrupts */
1504 imr = msm_read(port, MSM_UART_IMR);
1505 msm_write(port, 0, MSM_UART_IMR);
1506
1507 if (msm_port->is_uartdm)
1508 c = msm_poll_get_char_dm(port);
1509 else
1510 c = msm_poll_get_char_single(port);
1511
1512 /* Enable interrupts */
1513 msm_write(port, imr, MSM_UART_IMR);
1514
1515 return c;
1516}
1517
1518static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1519{
1520 u32 imr;
1521 struct msm_port *msm_port = to_msm_port(port);
1522
1523 /* Disable all interrupts */
1524 imr = msm_read(port, MSM_UART_IMR);
1525 msm_write(port, 0, MSM_UART_IMR);
1526
1527 if (msm_port->is_uartdm)
1528 msm_reset_dm_count(port, 1);
1529
1530 /* Wait until FIFO is empty */
1531 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1532 cpu_relax();
1533
1534 /* Write a character */
1535 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF);
1536
1537 /* Wait until FIFO is empty */
1538 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1539 cpu_relax();
1540
1541 /* Enable interrupts */
1542 msm_write(port, imr, MSM_UART_IMR);
1543}
1544#endif
1545
1546static const struct uart_ops msm_uart_pops = {
1547 .tx_empty = msm_tx_empty,
1548 .set_mctrl = msm_set_mctrl,
1549 .get_mctrl = msm_get_mctrl,
1550 .stop_tx = msm_stop_tx,
1551 .start_tx = msm_start_tx,
1552 .stop_rx = msm_stop_rx,
1553 .enable_ms = msm_enable_ms,
1554 .break_ctl = msm_break_ctl,
1555 .startup = msm_startup,
1556 .shutdown = msm_shutdown,
1557 .set_termios = msm_set_termios,
1558 .type = msm_type,
1559 .release_port = msm_release_port,
1560 .request_port = msm_request_port,
1561 .config_port = msm_config_port,
1562 .verify_port = msm_verify_port,
1563 .pm = msm_power,
1564#ifdef CONFIG_CONSOLE_POLL
1565 .poll_get_char = msm_poll_get_char,
1566 .poll_put_char = msm_poll_put_char,
1567#endif
1568};
1569
1570static struct msm_port msm_uart_ports[] = {
1571 {
1572 .uart = {
1573 .iotype = UPIO_MEM,
1574 .ops = &msm_uart_pops,
1575 .flags = UPF_BOOT_AUTOCONF,
1576 .fifosize = 64,
1577 .line = 0,
1578 },
1579 },
1580 {
1581 .uart = {
1582 .iotype = UPIO_MEM,
1583 .ops = &msm_uart_pops,
1584 .flags = UPF_BOOT_AUTOCONF,
1585 .fifosize = 64,
1586 .line = 1,
1587 },
1588 },
1589 {
1590 .uart = {
1591 .iotype = UPIO_MEM,
1592 .ops = &msm_uart_pops,
1593 .flags = UPF_BOOT_AUTOCONF,
1594 .fifosize = 64,
1595 .line = 2,
1596 },
1597 },
1598};
1599
1600#define MSM_UART_NR ARRAY_SIZE(msm_uart_ports)
1601
1602static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1603{
1604 return &msm_uart_ports[line].uart;
1605}
1606
1607#ifdef CONFIG_SERIAL_MSM_CONSOLE
1608static void __msm_console_write(struct uart_port *port, const char *s,
1609 unsigned int count, bool is_uartdm)
1610{
1611 unsigned long flags;
1612 int i;
1613 int num_newlines = 0;
1614 bool replaced = false;
1615 void __iomem *tf;
1616 int locked = 1;
1617
1618 if (is_uartdm)
1619 tf = port->membase + UARTDM_TF;
1620 else
1621 tf = port->membase + MSM_UART_TF;
1622
1623 /* Account for newlines that will get a carriage return added */
1624 for (i = 0; i < count; i++)
1625 if (s[i] == '\n')
1626 num_newlines++;
1627 count += num_newlines;
1628
1629 if (oops_in_progress)
1630 locked = uart_port_trylock_irqsave(port, &flags);
1631 else
1632 uart_port_lock_irqsave(port, &flags);
1633
1634 if (is_uartdm)
1635 msm_reset_dm_count(port, count);
1636
1637 i = 0;
1638 while (i < count) {
1639 int j;
1640 unsigned int num_chars;
1641 char buf[4] = { 0 };
1642
1643 if (is_uartdm)
1644 num_chars = min(count - i, (unsigned int)sizeof(buf));
1645 else
1646 num_chars = 1;
1647
1648 for (j = 0; j < num_chars; j++) {
1649 char c = *s;
1650
1651 if (c == '\n' && !replaced) {
1652 buf[j] = '\r';
1653 j++;
1654 replaced = true;
1655 }
1656 if (j < num_chars) {
1657 buf[j] = c;
1658 s++;
1659 replaced = false;
1660 }
1661 }
1662
1663 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1664 cpu_relax();
1665
1666 iowrite32_rep(tf, buf, 1);
1667 i += num_chars;
1668 }
1669
1670 if (locked)
1671 uart_port_unlock_irqrestore(port, flags);
1672}
1673
1674static void msm_console_write(struct console *co, const char *s,
1675 unsigned int count)
1676{
1677 struct uart_port *port;
1678 struct msm_port *msm_port;
1679
1680 BUG_ON(co->index < 0 || co->index >= MSM_UART_NR);
1681
1682 port = msm_get_port_from_line(co->index);
1683 msm_port = to_msm_port(port);
1684
1685 __msm_console_write(port, s, count, msm_port->is_uartdm);
1686}
1687
1688static int msm_console_setup(struct console *co, char *options)
1689{
1690 struct uart_port *port;
1691 int baud = 115200;
1692 int bits = 8;
1693 int parity = 'n';
1694 int flow = 'n';
1695
1696 if (unlikely(co->index >= MSM_UART_NR || co->index < 0))
1697 return -ENXIO;
1698
1699 port = msm_get_port_from_line(co->index);
1700
1701 if (unlikely(!port->membase))
1702 return -ENXIO;
1703
1704 msm_init_clock(port);
1705
1706 if (options)
1707 uart_parse_options(options, &baud, &parity, &bits, &flow);
1708
1709 pr_info("msm_serial: console setup on port #%d\n", port->line);
1710
1711 return uart_set_options(port, co, baud, parity, bits, flow);
1712}
1713
1714static void
1715msm_serial_early_write(struct console *con, const char *s, unsigned n)
1716{
1717 struct earlycon_device *dev = con->data;
1718
1719 __msm_console_write(&dev->port, s, n, false);
1720}
1721
1722static int __init
1723msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1724{
1725 if (!device->port.membase)
1726 return -ENODEV;
1727
1728 device->con->write = msm_serial_early_write;
1729 return 0;
1730}
1731OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1732 msm_serial_early_console_setup);
1733
1734static void
1735msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1736{
1737 struct earlycon_device *dev = con->data;
1738
1739 __msm_console_write(&dev->port, s, n, true);
1740}
1741
1742static int __init
1743msm_serial_early_console_setup_dm(struct earlycon_device *device,
1744 const char *opt)
1745{
1746 if (!device->port.membase)
1747 return -ENODEV;
1748
1749 device->con->write = msm_serial_early_write_dm;
1750 return 0;
1751}
1752OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1753 msm_serial_early_console_setup_dm);
1754
1755static struct uart_driver msm_uart_driver;
1756
1757static struct console msm_console = {
1758 .name = "ttyMSM",
1759 .write = msm_console_write,
1760 .device = uart_console_device,
1761 .setup = msm_console_setup,
1762 .flags = CON_PRINTBUFFER,
1763 .index = -1,
1764 .data = &msm_uart_driver,
1765};
1766
1767#define MSM_CONSOLE (&msm_console)
1768
1769#else
1770#define MSM_CONSOLE NULL
1771#endif
1772
1773static struct uart_driver msm_uart_driver = {
1774 .owner = THIS_MODULE,
1775 .driver_name = "msm_serial",
1776 .dev_name = "ttyMSM",
1777 .nr = MSM_UART_NR,
1778 .cons = MSM_CONSOLE,
1779};
1780
1781static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1782
1783static const struct of_device_id msm_uartdm_table[] = {
1784 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1785 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1786 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1787 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1788 { }
1789};
1790
1791static int msm_serial_probe(struct platform_device *pdev)
1792{
1793 struct msm_port *msm_port;
1794 struct resource *resource;
1795 struct uart_port *port;
1796 const struct of_device_id *id;
1797 int irq, line, ret;
1798
1799 if (pdev->dev.of_node)
1800 line = of_alias_get_id(pdev->dev.of_node, "serial");
1801 else
1802 line = pdev->id;
1803
1804 if (line < 0)
1805 line = atomic_inc_return(&msm_uart_next_id) - 1;
1806
1807 if (unlikely(line < 0 || line >= MSM_UART_NR))
1808 return -ENXIO;
1809
1810 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1811
1812 port = msm_get_port_from_line(line);
1813 port->dev = &pdev->dev;
1814 msm_port = to_msm_port(port);
1815
1816 id = of_match_device(msm_uartdm_table, &pdev->dev);
1817 if (id)
1818 msm_port->is_uartdm = (unsigned long)id->data;
1819 else
1820 msm_port->is_uartdm = 0;
1821
1822 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1823 if (IS_ERR(msm_port->clk))
1824 return PTR_ERR(msm_port->clk);
1825
1826 if (msm_port->is_uartdm) {
1827 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1828 if (IS_ERR(msm_port->pclk))
1829 return PTR_ERR(msm_port->pclk);
1830 }
1831
1832 ret = devm_pm_opp_set_clkname(&pdev->dev, "core");
1833 if (ret)
1834 return ret;
1835
1836 /* OPP table is optional */
1837 ret = devm_pm_opp_of_add_table(&pdev->dev);
1838 if (ret && ret != -ENODEV)
1839 return dev_err_probe(&pdev->dev, ret, "invalid OPP table\n");
1840
1841 port->uartclk = clk_get_rate(msm_port->clk);
1842 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1843
1844 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1845 if (unlikely(!resource))
1846 return -ENXIO;
1847 port->mapbase = resource->start;
1848
1849 irq = platform_get_irq(pdev, 0);
1850 if (unlikely(irq < 0))
1851 return -ENXIO;
1852 port->irq = irq;
1853 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
1854
1855 platform_set_drvdata(pdev, port);
1856
1857 return uart_add_one_port(&msm_uart_driver, port);
1858}
1859
1860static void msm_serial_remove(struct platform_device *pdev)
1861{
1862 struct uart_port *port = platform_get_drvdata(pdev);
1863
1864 uart_remove_one_port(&msm_uart_driver, port);
1865}
1866
1867static const struct of_device_id msm_match_table[] = {
1868 { .compatible = "qcom,msm-uart" },
1869 { .compatible = "qcom,msm-uartdm" },
1870 {}
1871};
1872MODULE_DEVICE_TABLE(of, msm_match_table);
1873
1874static int __maybe_unused msm_serial_suspend(struct device *dev)
1875{
1876 struct msm_port *port = dev_get_drvdata(dev);
1877
1878 uart_suspend_port(&msm_uart_driver, &port->uart);
1879
1880 return 0;
1881}
1882
1883static int __maybe_unused msm_serial_resume(struct device *dev)
1884{
1885 struct msm_port *port = dev_get_drvdata(dev);
1886
1887 uart_resume_port(&msm_uart_driver, &port->uart);
1888
1889 return 0;
1890}
1891
1892static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1893 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1894};
1895
1896static struct platform_driver msm_platform_driver = {
1897 .remove = msm_serial_remove,
1898 .probe = msm_serial_probe,
1899 .driver = {
1900 .name = "msm_serial",
1901 .pm = &msm_serial_dev_pm_ops,
1902 .of_match_table = msm_match_table,
1903 },
1904};
1905
1906static int __init msm_serial_init(void)
1907{
1908 int ret;
1909
1910 ret = uart_register_driver(&msm_uart_driver);
1911 if (unlikely(ret))
1912 return ret;
1913
1914 ret = platform_driver_register(&msm_platform_driver);
1915 if (unlikely(ret))
1916 uart_unregister_driver(&msm_uart_driver);
1917
1918 pr_info("msm_serial: driver initialized\n");
1919
1920 return ret;
1921}
1922
1923static void __exit msm_serial_exit(void)
1924{
1925 platform_driver_unregister(&msm_platform_driver);
1926 uart_unregister_driver(&msm_uart_driver);
1927}
1928
1929module_init(msm_serial_init);
1930module_exit(msm_serial_exit);
1931
1932MODULE_AUTHOR("Robert Love <rlove@google.com>");
1933MODULE_DESCRIPTION("Driver for msm7x serial device");
1934MODULE_LICENSE("GPL");