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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Author: Damien Lespiau <damien.lespiau@intel.com>
24 *
25 */
26
27#include <linux/circ_buf.h>
28#include <linux/ctype.h>
29#include <linux/debugfs.h>
30#include <linux/seq_file.h>
31
32#include "intel_atomic.h"
33#include "intel_de.h"
34#include "intel_display_types.h"
35#include "intel_pipe_crc.h"
36
37static const char * const pipe_crc_sources[] = {
38 [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
39 [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
40 [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
41 [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
42 [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
43 [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
44 [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
45 [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
46 [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
47 [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
48 [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
49 [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
50 [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
51 [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
52};
53
54static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
55 u32 *val)
56{
57 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
58 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
59
60 switch (*source) {
61 case INTEL_PIPE_CRC_SOURCE_PIPE:
62 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
63 break;
64 case INTEL_PIPE_CRC_SOURCE_NONE:
65 *val = 0;
66 break;
67 default:
68 return -EINVAL;
69 }
70
71 return 0;
72}
73
74static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
75 enum pipe pipe,
76 enum intel_pipe_crc_source *source)
77{
78 struct drm_device *dev = &dev_priv->drm;
79 struct intel_encoder *encoder;
80 struct intel_crtc *crtc;
81 struct intel_digital_port *dig_port;
82 int ret = 0;
83
84 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
85
86 drm_modeset_lock_all(dev);
87 for_each_intel_encoder(dev, encoder) {
88 if (!encoder->base.crtc)
89 continue;
90
91 crtc = to_intel_crtc(encoder->base.crtc);
92
93 if (crtc->pipe != pipe)
94 continue;
95
96 switch (encoder->type) {
97 case INTEL_OUTPUT_TVOUT:
98 *source = INTEL_PIPE_CRC_SOURCE_TV;
99 break;
100 case INTEL_OUTPUT_DP:
101 case INTEL_OUTPUT_EDP:
102 dig_port = enc_to_dig_port(encoder);
103 switch (dig_port->base.port) {
104 case PORT_B:
105 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
106 break;
107 case PORT_C:
108 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
109 break;
110 case PORT_D:
111 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
112 break;
113 default:
114 drm_WARN(dev, 1, "nonexisting DP port %c\n",
115 port_name(dig_port->base.port));
116 break;
117 }
118 break;
119 default:
120 break;
121 }
122 }
123 drm_modeset_unlock_all(dev);
124
125 return ret;
126}
127
128static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
129 enum pipe pipe,
130 enum intel_pipe_crc_source *source,
131 u32 *val)
132{
133 bool need_stable_symbols = false;
134
135 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
136 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
137 if (ret)
138 return ret;
139 }
140
141 switch (*source) {
142 case INTEL_PIPE_CRC_SOURCE_PIPE:
143 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
144 break;
145 case INTEL_PIPE_CRC_SOURCE_DP_B:
146 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
147 need_stable_symbols = true;
148 break;
149 case INTEL_PIPE_CRC_SOURCE_DP_C:
150 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
151 need_stable_symbols = true;
152 break;
153 case INTEL_PIPE_CRC_SOURCE_DP_D:
154 if (!IS_CHERRYVIEW(dev_priv))
155 return -EINVAL;
156 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
157 need_stable_symbols = true;
158 break;
159 case INTEL_PIPE_CRC_SOURCE_NONE:
160 *val = 0;
161 break;
162 default:
163 return -EINVAL;
164 }
165
166 /*
167 * When the pipe CRC tap point is after the transcoders we need
168 * to tweak symbol-level features to produce a deterministic series of
169 * symbols for a given frame. We need to reset those features only once
170 * a frame (instead of every nth symbol):
171 * - DC-balance: used to ensure a better clock recovery from the data
172 * link (SDVO)
173 * - DisplayPort scrambling: used for EMI reduction
174 */
175 if (need_stable_symbols) {
176 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
177
178 tmp |= DC_BALANCE_RESET_VLV;
179 switch (pipe) {
180 case PIPE_A:
181 tmp |= PIPE_A_SCRAMBLE_RESET;
182 break;
183 case PIPE_B:
184 tmp |= PIPE_B_SCRAMBLE_RESET;
185 break;
186 case PIPE_C:
187 tmp |= PIPE_C_SCRAMBLE_RESET;
188 break;
189 default:
190 return -EINVAL;
191 }
192 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
193 }
194
195 return 0;
196}
197
198static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
199 enum pipe pipe,
200 enum intel_pipe_crc_source *source,
201 u32 *val)
202{
203 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
204 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
205 if (ret)
206 return ret;
207 }
208
209 switch (*source) {
210 case INTEL_PIPE_CRC_SOURCE_PIPE:
211 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
212 break;
213 case INTEL_PIPE_CRC_SOURCE_TV:
214 if (!SUPPORTS_TV(dev_priv))
215 return -EINVAL;
216 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
217 break;
218 case INTEL_PIPE_CRC_SOURCE_NONE:
219 *val = 0;
220 break;
221 default:
222 /*
223 * The DP CRC source doesn't work on g4x.
224 * It can be made to work to some degree by selecting
225 * the correct CRC source before the port is enabled,
226 * and not touching the CRC source bits again until
227 * the port is disabled. But even then the bits
228 * eventually get stuck and a reboot is needed to get
229 * working CRCs on the pipe again. Let's simply
230 * refuse to use DP CRCs on g4x.
231 */
232 return -EINVAL;
233 }
234
235 return 0;
236}
237
238static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
239 enum pipe pipe)
240{
241 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
242
243 switch (pipe) {
244 case PIPE_A:
245 tmp &= ~PIPE_A_SCRAMBLE_RESET;
246 break;
247 case PIPE_B:
248 tmp &= ~PIPE_B_SCRAMBLE_RESET;
249 break;
250 case PIPE_C:
251 tmp &= ~PIPE_C_SCRAMBLE_RESET;
252 break;
253 default:
254 return;
255 }
256 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
257 tmp &= ~DC_BALANCE_RESET_VLV;
258 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
259}
260
261static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
262 u32 *val)
263{
264 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
265 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
266
267 switch (*source) {
268 case INTEL_PIPE_CRC_SOURCE_PLANE1:
269 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
270 break;
271 case INTEL_PIPE_CRC_SOURCE_PLANE2:
272 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
273 break;
274 case INTEL_PIPE_CRC_SOURCE_PIPE:
275 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
276 break;
277 case INTEL_PIPE_CRC_SOURCE_NONE:
278 *val = 0;
279 break;
280 default:
281 return -EINVAL;
282 }
283
284 return 0;
285}
286
287static void
288intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
289{
290 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
291 struct intel_crtc_state *pipe_config;
292 struct drm_atomic_state *state;
293 struct drm_modeset_acquire_ctx ctx;
294 int ret;
295
296 drm_modeset_acquire_init(&ctx, 0);
297
298 state = drm_atomic_state_alloc(&dev_priv->drm);
299 if (!state) {
300 ret = -ENOMEM;
301 goto unlock;
302 }
303
304 state->acquire_ctx = &ctx;
305
306retry:
307 pipe_config = intel_atomic_get_crtc_state(state, crtc);
308 if (IS_ERR(pipe_config)) {
309 ret = PTR_ERR(pipe_config);
310 goto put_state;
311 }
312
313 pipe_config->uapi.mode_changed = pipe_config->has_psr;
314 pipe_config->crc_enabled = enable;
315
316 if (IS_HASWELL(dev_priv) &&
317 pipe_config->hw.active && crtc->pipe == PIPE_A &&
318 pipe_config->cpu_transcoder == TRANSCODER_EDP)
319 pipe_config->uapi.mode_changed = true;
320
321 ret = drm_atomic_commit(state);
322
323put_state:
324 if (ret == -EDEADLK) {
325 drm_atomic_state_clear(state);
326 drm_modeset_backoff(&ctx);
327 goto retry;
328 }
329
330 drm_atomic_state_put(state);
331unlock:
332 drm_WARN(&dev_priv->drm, ret,
333 "Toggling workaround to %i returns %i\n", enable, ret);
334 drm_modeset_drop_locks(&ctx);
335 drm_modeset_acquire_fini(&ctx);
336}
337
338static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
339 enum pipe pipe,
340 enum intel_pipe_crc_source *source,
341 u32 *val)
342{
343 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
344 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
345
346 switch (*source) {
347 case INTEL_PIPE_CRC_SOURCE_PLANE1:
348 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
349 break;
350 case INTEL_PIPE_CRC_SOURCE_PLANE2:
351 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
352 break;
353 case INTEL_PIPE_CRC_SOURCE_PIPE:
354 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
355 break;
356 case INTEL_PIPE_CRC_SOURCE_NONE:
357 *val = 0;
358 break;
359 default:
360 return -EINVAL;
361 }
362
363 return 0;
364}
365
366static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
367 enum pipe pipe,
368 enum intel_pipe_crc_source *source,
369 u32 *val)
370{
371 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
372 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
373
374 switch (*source) {
375 case INTEL_PIPE_CRC_SOURCE_PLANE1:
376 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
377 break;
378 case INTEL_PIPE_CRC_SOURCE_PLANE2:
379 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
380 break;
381 case INTEL_PIPE_CRC_SOURCE_PLANE3:
382 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
383 break;
384 case INTEL_PIPE_CRC_SOURCE_PLANE4:
385 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
386 break;
387 case INTEL_PIPE_CRC_SOURCE_PLANE5:
388 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
389 break;
390 case INTEL_PIPE_CRC_SOURCE_PLANE6:
391 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
392 break;
393 case INTEL_PIPE_CRC_SOURCE_PLANE7:
394 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
395 break;
396 case INTEL_PIPE_CRC_SOURCE_PIPE:
397 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
398 break;
399 case INTEL_PIPE_CRC_SOURCE_NONE:
400 *val = 0;
401 break;
402 default:
403 return -EINVAL;
404 }
405
406 return 0;
407}
408
409static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
410 enum pipe pipe,
411 enum intel_pipe_crc_source *source, u32 *val)
412{
413 if (DISPLAY_VER(dev_priv) == 2)
414 return i8xx_pipe_crc_ctl_reg(source, val);
415 else if (DISPLAY_VER(dev_priv) < 5)
416 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
417 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
418 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
419 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
420 return ilk_pipe_crc_ctl_reg(source, val);
421 else if (DISPLAY_VER(dev_priv) < 9)
422 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
423 else
424 return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
425}
426
427static int
428display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
429{
430 int i;
431
432 if (!buf) {
433 *s = INTEL_PIPE_CRC_SOURCE_NONE;
434 return 0;
435 }
436
437 i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
438 if (i < 0)
439 return i;
440
441 *s = i;
442 return 0;
443}
444
445void intel_crtc_crc_init(struct intel_crtc *crtc)
446{
447 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
448
449 spin_lock_init(&pipe_crc->lock);
450}
451
452static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
453 const enum intel_pipe_crc_source source)
454{
455 switch (source) {
456 case INTEL_PIPE_CRC_SOURCE_PIPE:
457 case INTEL_PIPE_CRC_SOURCE_NONE:
458 return 0;
459 default:
460 return -EINVAL;
461 }
462}
463
464static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
465 const enum intel_pipe_crc_source source)
466{
467 switch (source) {
468 case INTEL_PIPE_CRC_SOURCE_PIPE:
469 case INTEL_PIPE_CRC_SOURCE_TV:
470 case INTEL_PIPE_CRC_SOURCE_NONE:
471 return 0;
472 default:
473 return -EINVAL;
474 }
475}
476
477static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
478 const enum intel_pipe_crc_source source)
479{
480 switch (source) {
481 case INTEL_PIPE_CRC_SOURCE_PIPE:
482 case INTEL_PIPE_CRC_SOURCE_DP_B:
483 case INTEL_PIPE_CRC_SOURCE_DP_C:
484 case INTEL_PIPE_CRC_SOURCE_DP_D:
485 case INTEL_PIPE_CRC_SOURCE_NONE:
486 return 0;
487 default:
488 return -EINVAL;
489 }
490}
491
492static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
493 const enum intel_pipe_crc_source source)
494{
495 switch (source) {
496 case INTEL_PIPE_CRC_SOURCE_PIPE:
497 case INTEL_PIPE_CRC_SOURCE_PLANE1:
498 case INTEL_PIPE_CRC_SOURCE_PLANE2:
499 case INTEL_PIPE_CRC_SOURCE_NONE:
500 return 0;
501 default:
502 return -EINVAL;
503 }
504}
505
506static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
507 const enum intel_pipe_crc_source source)
508{
509 switch (source) {
510 case INTEL_PIPE_CRC_SOURCE_PIPE:
511 case INTEL_PIPE_CRC_SOURCE_PLANE1:
512 case INTEL_PIPE_CRC_SOURCE_PLANE2:
513 case INTEL_PIPE_CRC_SOURCE_NONE:
514 return 0;
515 default:
516 return -EINVAL;
517 }
518}
519
520static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
521 const enum intel_pipe_crc_source source)
522{
523 switch (source) {
524 case INTEL_PIPE_CRC_SOURCE_PIPE:
525 case INTEL_PIPE_CRC_SOURCE_PLANE1:
526 case INTEL_PIPE_CRC_SOURCE_PLANE2:
527 case INTEL_PIPE_CRC_SOURCE_PLANE3:
528 case INTEL_PIPE_CRC_SOURCE_PLANE4:
529 case INTEL_PIPE_CRC_SOURCE_PLANE5:
530 case INTEL_PIPE_CRC_SOURCE_PLANE6:
531 case INTEL_PIPE_CRC_SOURCE_PLANE7:
532 case INTEL_PIPE_CRC_SOURCE_NONE:
533 return 0;
534 default:
535 return -EINVAL;
536 }
537}
538
539static int
540intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
541 const enum intel_pipe_crc_source source)
542{
543 if (DISPLAY_VER(dev_priv) == 2)
544 return i8xx_crc_source_valid(dev_priv, source);
545 else if (DISPLAY_VER(dev_priv) < 5)
546 return i9xx_crc_source_valid(dev_priv, source);
547 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
548 return vlv_crc_source_valid(dev_priv, source);
549 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
550 return ilk_crc_source_valid(dev_priv, source);
551 else if (DISPLAY_VER(dev_priv) < 9)
552 return ivb_crc_source_valid(dev_priv, source);
553 else
554 return skl_crc_source_valid(dev_priv, source);
555}
556
557const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
558 size_t *count)
559{
560 *count = ARRAY_SIZE(pipe_crc_sources);
561 return pipe_crc_sources;
562}
563
564int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
565 size_t *values_cnt)
566{
567 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
568 enum intel_pipe_crc_source source;
569
570 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
571 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
572 return -EINVAL;
573 }
574
575 if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
576 intel_is_valid_crc_source(dev_priv, source) == 0) {
577 *values_cnt = 5;
578 return 0;
579 }
580
581 return -EINVAL;
582}
583
584int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
585{
586 struct intel_crtc *crtc = to_intel_crtc(_crtc);
587 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
588 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
589 enum intel_display_power_domain power_domain;
590 enum intel_pipe_crc_source source;
591 enum pipe pipe = crtc->pipe;
592 intel_wakeref_t wakeref;
593 u32 val = 0; /* shut up gcc */
594 int ret = 0;
595 bool enable;
596
597 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
598 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
599 return -EINVAL;
600 }
601
602 power_domain = POWER_DOMAIN_PIPE(pipe);
603 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
604 if (!wakeref) {
605 drm_dbg_kms(&dev_priv->drm,
606 "Trying to capture CRC while pipe is off\n");
607 return -EIO;
608 }
609
610 enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
611 if (enable)
612 intel_crtc_crc_setup_workarounds(crtc, true);
613
614 ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
615 if (ret != 0)
616 goto out;
617
618 pipe_crc->source = source;
619 intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
620 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
621
622 if (!source) {
623 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
624 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
625 }
626
627 pipe_crc->skipped = 0;
628
629out:
630 if (!enable)
631 intel_crtc_crc_setup_workarounds(crtc, false);
632
633 intel_display_power_put(dev_priv, power_domain, wakeref);
634
635 return ret;
636}
637
638void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
639{
640 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
641 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
642 enum pipe pipe = crtc->pipe;
643 u32 val = 0;
644
645 if (!crtc->base.crc.opened)
646 return;
647
648 if (get_new_crc_ctl_reg(dev_priv, pipe, &pipe_crc->source, &val) < 0)
649 return;
650
651 /* Don't need pipe_crc->lock here, IRQs are not generated. */
652 pipe_crc->skipped = 0;
653
654 intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
655 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
656}
657
658void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
659{
660 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
661 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
662 enum pipe pipe = crtc->pipe;
663
664 /* Swallow crc's until we stop generating them. */
665 spin_lock_irq(&pipe_crc->lock);
666 pipe_crc->skipped = INT_MIN;
667 spin_unlock_irq(&pipe_crc->lock);
668
669 intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), 0);
670 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
671 intel_synchronize_irq(dev_priv);
672}
1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Author: Damien Lespiau <damien.lespiau@intel.com>
24 *
25 */
26
27#include <linux/ctype.h>
28#include <linux/debugfs.h>
29#include <linux/seq_file.h>
30
31#include "i915_irq.h"
32#include "i915_reg.h"
33#include "intel_atomic.h"
34#include "intel_de.h"
35#include "intel_display_irq.h"
36#include "intel_display_types.h"
37#include "intel_pipe_crc.h"
38#include "intel_pipe_crc_regs.h"
39
40static const char * const pipe_crc_sources[] = {
41 [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
42 [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
43 [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
44 [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
45 [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
46 [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
47 [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
48 [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
49 [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
50 [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
51 [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
52 [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
53 [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
54 [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
55};
56
57static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
58 u32 *val)
59{
60 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
61 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
62
63 switch (*source) {
64 case INTEL_PIPE_CRC_SOURCE_PIPE:
65 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
66 break;
67 case INTEL_PIPE_CRC_SOURCE_NONE:
68 *val = 0;
69 break;
70 default:
71 return -EINVAL;
72 }
73
74 return 0;
75}
76
77static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
78 enum pipe pipe,
79 enum intel_pipe_crc_source *source)
80{
81 struct intel_encoder *encoder;
82 struct intel_crtc *crtc;
83 struct intel_digital_port *dig_port;
84
85 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
86
87 drm_modeset_lock_all(&dev_priv->drm);
88 for_each_intel_encoder(&dev_priv->drm, encoder) {
89 if (!encoder->base.crtc)
90 continue;
91
92 crtc = to_intel_crtc(encoder->base.crtc);
93
94 if (crtc->pipe != pipe)
95 continue;
96
97 switch (encoder->type) {
98 case INTEL_OUTPUT_TVOUT:
99 *source = INTEL_PIPE_CRC_SOURCE_TV;
100 break;
101 case INTEL_OUTPUT_DP:
102 case INTEL_OUTPUT_EDP:
103 dig_port = enc_to_dig_port(encoder);
104 switch (dig_port->base.port) {
105 case PORT_B:
106 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
107 break;
108 case PORT_C:
109 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
110 break;
111 case PORT_D:
112 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
113 break;
114 default:
115 drm_WARN(&dev_priv->drm, 1, "nonexisting DP port %c\n",
116 port_name(dig_port->base.port));
117 break;
118 }
119 break;
120 default:
121 break;
122 }
123 }
124 drm_modeset_unlock_all(&dev_priv->drm);
125}
126
127static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
128 enum pipe pipe,
129 enum intel_pipe_crc_source *source,
130 u32 *val)
131{
132 bool need_stable_symbols = false;
133
134 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
135 i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
136
137 switch (*source) {
138 case INTEL_PIPE_CRC_SOURCE_PIPE:
139 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
140 break;
141 case INTEL_PIPE_CRC_SOURCE_DP_B:
142 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
143 need_stable_symbols = true;
144 break;
145 case INTEL_PIPE_CRC_SOURCE_DP_C:
146 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
147 need_stable_symbols = true;
148 break;
149 case INTEL_PIPE_CRC_SOURCE_DP_D:
150 if (!IS_CHERRYVIEW(dev_priv))
151 return -EINVAL;
152 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
153 need_stable_symbols = true;
154 break;
155 case INTEL_PIPE_CRC_SOURCE_NONE:
156 *val = 0;
157 break;
158 default:
159 return -EINVAL;
160 }
161
162 /*
163 * When the pipe CRC tap point is after the transcoders we need
164 * to tweak symbol-level features to produce a deterministic series of
165 * symbols for a given frame. We need to reset those features only once
166 * a frame (instead of every nth symbol):
167 * - DC-balance: used to ensure a better clock recovery from the data
168 * link (SDVO)
169 * - DisplayPort scrambling: used for EMI reduction
170 */
171 if (need_stable_symbols) {
172 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv));
173
174 tmp |= DC_BALANCE_RESET_VLV;
175 switch (pipe) {
176 case PIPE_A:
177 tmp |= PIPE_A_SCRAMBLE_RESET;
178 break;
179 case PIPE_B:
180 tmp |= PIPE_B_SCRAMBLE_RESET;
181 break;
182 case PIPE_C:
183 tmp |= PIPE_C_SCRAMBLE_RESET;
184 break;
185 default:
186 return -EINVAL;
187 }
188 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp);
189 }
190
191 return 0;
192}
193
194static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
195 enum pipe pipe,
196 enum intel_pipe_crc_source *source,
197 u32 *val)
198{
199 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
200 i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
201
202 switch (*source) {
203 case INTEL_PIPE_CRC_SOURCE_PIPE:
204 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
205 break;
206 case INTEL_PIPE_CRC_SOURCE_TV:
207 if (!SUPPORTS_TV(dev_priv))
208 return -EINVAL;
209 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
210 break;
211 case INTEL_PIPE_CRC_SOURCE_NONE:
212 *val = 0;
213 break;
214 default:
215 /*
216 * The DP CRC source doesn't work on g4x.
217 * It can be made to work to some degree by selecting
218 * the correct CRC source before the port is enabled,
219 * and not touching the CRC source bits again until
220 * the port is disabled. But even then the bits
221 * eventually get stuck and a reboot is needed to get
222 * working CRCs on the pipe again. Let's simply
223 * refuse to use DP CRCs on g4x.
224 */
225 return -EINVAL;
226 }
227
228 return 0;
229}
230
231static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
232 enum pipe pipe)
233{
234 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv));
235
236 switch (pipe) {
237 case PIPE_A:
238 tmp &= ~PIPE_A_SCRAMBLE_RESET;
239 break;
240 case PIPE_B:
241 tmp &= ~PIPE_B_SCRAMBLE_RESET;
242 break;
243 case PIPE_C:
244 tmp &= ~PIPE_C_SCRAMBLE_RESET;
245 break;
246 default:
247 return;
248 }
249 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
250 tmp &= ~DC_BALANCE_RESET_VLV;
251 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp);
252}
253
254static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
255 u32 *val)
256{
257 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
258 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
259
260 switch (*source) {
261 case INTEL_PIPE_CRC_SOURCE_PLANE1:
262 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
263 break;
264 case INTEL_PIPE_CRC_SOURCE_PLANE2:
265 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
266 break;
267 case INTEL_PIPE_CRC_SOURCE_PIPE:
268 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
269 break;
270 case INTEL_PIPE_CRC_SOURCE_NONE:
271 *val = 0;
272 break;
273 default:
274 return -EINVAL;
275 }
276
277 return 0;
278}
279
280static void
281intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
282{
283 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
284 struct intel_crtc_state *pipe_config;
285 struct drm_atomic_state *state;
286 struct drm_modeset_acquire_ctx ctx;
287 int ret;
288
289 if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
290 i915gm_irq_cstate_wa(dev_priv, enable);
291
292 drm_modeset_acquire_init(&ctx, 0);
293
294 state = drm_atomic_state_alloc(&dev_priv->drm);
295 if (!state) {
296 ret = -ENOMEM;
297 goto unlock;
298 }
299
300 state->acquire_ctx = &ctx;
301 to_intel_atomic_state(state)->internal = true;
302
303retry:
304 pipe_config = intel_atomic_get_crtc_state(state, crtc);
305 if (IS_ERR(pipe_config)) {
306 ret = PTR_ERR(pipe_config);
307 goto put_state;
308 }
309
310 pipe_config->uapi.mode_changed = pipe_config->has_psr;
311 pipe_config->crc_enabled = enable;
312
313 if (IS_HASWELL(dev_priv) &&
314 pipe_config->hw.active && crtc->pipe == PIPE_A &&
315 pipe_config->cpu_transcoder == TRANSCODER_EDP)
316 pipe_config->uapi.mode_changed = true;
317
318 ret = drm_atomic_commit(state);
319
320put_state:
321 if (ret == -EDEADLK) {
322 drm_atomic_state_clear(state);
323 drm_modeset_backoff(&ctx);
324 goto retry;
325 }
326
327 drm_atomic_state_put(state);
328unlock:
329 drm_WARN(&dev_priv->drm, ret,
330 "Toggling workaround to %i returns %i\n", enable, ret);
331 drm_modeset_drop_locks(&ctx);
332 drm_modeset_acquire_fini(&ctx);
333}
334
335static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
336 enum pipe pipe,
337 enum intel_pipe_crc_source *source,
338 u32 *val)
339{
340 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
341 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
342
343 switch (*source) {
344 case INTEL_PIPE_CRC_SOURCE_PLANE1:
345 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
346 break;
347 case INTEL_PIPE_CRC_SOURCE_PLANE2:
348 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
349 break;
350 case INTEL_PIPE_CRC_SOURCE_PIPE:
351 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
352 break;
353 case INTEL_PIPE_CRC_SOURCE_NONE:
354 *val = 0;
355 break;
356 default:
357 return -EINVAL;
358 }
359
360 return 0;
361}
362
363static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
364 enum pipe pipe,
365 enum intel_pipe_crc_source *source,
366 u32 *val)
367{
368 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
369 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
370
371 switch (*source) {
372 case INTEL_PIPE_CRC_SOURCE_PLANE1:
373 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
374 break;
375 case INTEL_PIPE_CRC_SOURCE_PLANE2:
376 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
377 break;
378 case INTEL_PIPE_CRC_SOURCE_PLANE3:
379 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
380 break;
381 case INTEL_PIPE_CRC_SOURCE_PLANE4:
382 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
383 break;
384 case INTEL_PIPE_CRC_SOURCE_PLANE5:
385 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
386 break;
387 case INTEL_PIPE_CRC_SOURCE_PLANE6:
388 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
389 break;
390 case INTEL_PIPE_CRC_SOURCE_PLANE7:
391 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
392 break;
393 case INTEL_PIPE_CRC_SOURCE_PIPE:
394 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
395 break;
396 case INTEL_PIPE_CRC_SOURCE_NONE:
397 *val = 0;
398 break;
399 default:
400 return -EINVAL;
401 }
402
403 return 0;
404}
405
406static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
407 enum pipe pipe,
408 enum intel_pipe_crc_source *source, u32 *val)
409{
410 if (DISPLAY_VER(dev_priv) == 2)
411 return i8xx_pipe_crc_ctl_reg(source, val);
412 else if (DISPLAY_VER(dev_priv) < 5)
413 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
414 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
415 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
416 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
417 return ilk_pipe_crc_ctl_reg(source, val);
418 else if (DISPLAY_VER(dev_priv) < 9)
419 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
420 else
421 return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
422}
423
424static int
425display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
426{
427 int i;
428
429 if (!buf) {
430 *s = INTEL_PIPE_CRC_SOURCE_NONE;
431 return 0;
432 }
433
434 i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
435 if (i < 0)
436 return i;
437
438 *s = i;
439 return 0;
440}
441
442void intel_crtc_crc_init(struct intel_crtc *crtc)
443{
444 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
445
446 spin_lock_init(&pipe_crc->lock);
447}
448
449static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
450 const enum intel_pipe_crc_source source)
451{
452 switch (source) {
453 case INTEL_PIPE_CRC_SOURCE_PIPE:
454 case INTEL_PIPE_CRC_SOURCE_NONE:
455 return 0;
456 default:
457 return -EINVAL;
458 }
459}
460
461static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
462 const enum intel_pipe_crc_source source)
463{
464 switch (source) {
465 case INTEL_PIPE_CRC_SOURCE_PIPE:
466 case INTEL_PIPE_CRC_SOURCE_TV:
467 case INTEL_PIPE_CRC_SOURCE_NONE:
468 return 0;
469 default:
470 return -EINVAL;
471 }
472}
473
474static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
475 const enum intel_pipe_crc_source source)
476{
477 switch (source) {
478 case INTEL_PIPE_CRC_SOURCE_PIPE:
479 case INTEL_PIPE_CRC_SOURCE_DP_B:
480 case INTEL_PIPE_CRC_SOURCE_DP_C:
481 case INTEL_PIPE_CRC_SOURCE_DP_D:
482 case INTEL_PIPE_CRC_SOURCE_NONE:
483 return 0;
484 default:
485 return -EINVAL;
486 }
487}
488
489static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
490 const enum intel_pipe_crc_source source)
491{
492 switch (source) {
493 case INTEL_PIPE_CRC_SOURCE_PIPE:
494 case INTEL_PIPE_CRC_SOURCE_PLANE1:
495 case INTEL_PIPE_CRC_SOURCE_PLANE2:
496 case INTEL_PIPE_CRC_SOURCE_NONE:
497 return 0;
498 default:
499 return -EINVAL;
500 }
501}
502
503static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
504 const enum intel_pipe_crc_source source)
505{
506 switch (source) {
507 case INTEL_PIPE_CRC_SOURCE_PIPE:
508 case INTEL_PIPE_CRC_SOURCE_PLANE1:
509 case INTEL_PIPE_CRC_SOURCE_PLANE2:
510 case INTEL_PIPE_CRC_SOURCE_NONE:
511 return 0;
512 default:
513 return -EINVAL;
514 }
515}
516
517static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
518 const enum intel_pipe_crc_source source)
519{
520 switch (source) {
521 case INTEL_PIPE_CRC_SOURCE_PIPE:
522 case INTEL_PIPE_CRC_SOURCE_PLANE1:
523 case INTEL_PIPE_CRC_SOURCE_PLANE2:
524 case INTEL_PIPE_CRC_SOURCE_PLANE3:
525 case INTEL_PIPE_CRC_SOURCE_PLANE4:
526 case INTEL_PIPE_CRC_SOURCE_PLANE5:
527 case INTEL_PIPE_CRC_SOURCE_PLANE6:
528 case INTEL_PIPE_CRC_SOURCE_PLANE7:
529 case INTEL_PIPE_CRC_SOURCE_NONE:
530 return 0;
531 default:
532 return -EINVAL;
533 }
534}
535
536static int
537intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
538 const enum intel_pipe_crc_source source)
539{
540 if (DISPLAY_VER(dev_priv) == 2)
541 return i8xx_crc_source_valid(dev_priv, source);
542 else if (DISPLAY_VER(dev_priv) < 5)
543 return i9xx_crc_source_valid(dev_priv, source);
544 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
545 return vlv_crc_source_valid(dev_priv, source);
546 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
547 return ilk_crc_source_valid(dev_priv, source);
548 else if (DISPLAY_VER(dev_priv) < 9)
549 return ivb_crc_source_valid(dev_priv, source);
550 else
551 return skl_crc_source_valid(dev_priv, source);
552}
553
554const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
555 size_t *count)
556{
557 *count = ARRAY_SIZE(pipe_crc_sources);
558 return pipe_crc_sources;
559}
560
561int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
562 size_t *values_cnt)
563{
564 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
565 enum intel_pipe_crc_source source;
566
567 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
568 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
569 return -EINVAL;
570 }
571
572 if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
573 intel_is_valid_crc_source(dev_priv, source) == 0) {
574 *values_cnt = 5;
575 return 0;
576 }
577
578 return -EINVAL;
579}
580
581int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
582{
583 struct intel_crtc *crtc = to_intel_crtc(_crtc);
584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
585 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
586 enum intel_display_power_domain power_domain;
587 enum intel_pipe_crc_source source;
588 enum pipe pipe = crtc->pipe;
589 intel_wakeref_t wakeref;
590 u32 val = 0; /* shut up gcc */
591 int ret = 0;
592 bool enable;
593
594 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
595 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
596 return -EINVAL;
597 }
598
599 power_domain = POWER_DOMAIN_PIPE(pipe);
600 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
601 if (!wakeref) {
602 drm_dbg_kms(&dev_priv->drm,
603 "Trying to capture CRC while pipe is off\n");
604 return -EIO;
605 }
606
607 enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
608 if (enable)
609 intel_crtc_crc_setup_workarounds(crtc, true);
610
611 ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
612 if (ret != 0)
613 goto out;
614
615 pipe_crc->source = source;
616 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
617 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
618
619 if (!source) {
620 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
621 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
622 }
623
624 pipe_crc->skipped = 0;
625
626out:
627 if (!enable)
628 intel_crtc_crc_setup_workarounds(crtc, false);
629
630 intel_display_power_put(dev_priv, power_domain, wakeref);
631
632 return ret;
633}
634
635void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
636{
637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
638 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
639 enum pipe pipe = crtc->pipe;
640 u32 val = 0;
641
642 if (!crtc->base.crc.opened)
643 return;
644
645 if (get_new_crc_ctl_reg(dev_priv, pipe, &pipe_crc->source, &val) < 0)
646 return;
647
648 /* Don't need pipe_crc->lock here, IRQs are not generated. */
649 pipe_crc->skipped = 0;
650
651 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
652 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
653}
654
655void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
656{
657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
658 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
659 enum pipe pipe = crtc->pipe;
660
661 /* Swallow crc's until we stop generating them. */
662 spin_lock_irq(&pipe_crc->lock);
663 pipe_crc->skipped = INT_MIN;
664 spin_unlock_irq(&pipe_crc->lock);
665
666 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0);
667 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
668 intel_synchronize_irq(dev_priv);
669}