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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include "amdgpu.h"
37#include "amdgpu_trace.h"
38#include "amdgpu_amdkfd.h"
39#include "amdgpu_gmc.h"
40#include "amdgpu_xgmi.h"
41#include "amdgpu_dma_buf.h"
42#include "amdgpu_res_cursor.h"
43#include "kfd_svm.h"
44
45/**
46 * DOC: GPUVM
47 *
48 * GPUVM is similar to the legacy gart on older asics, however
49 * rather than there being a single global gart table
50 * for the entire GPU, there are multiple VM page tables active
51 * at any given time. The VM page tables can contain a mix
52 * vram pages and system memory pages and system memory pages
53 * can be mapped as snooped (cached system pages) or unsnooped
54 * (uncached system pages).
55 * Each VM has an ID associated with it and there is a page table
56 * associated with each VMID. When execting a command buffer,
57 * the kernel tells the the ring what VMID to use for that command
58 * buffer. VMIDs are allocated dynamically as commands are submitted.
59 * The userspace drivers maintain their own address space and the kernel
60 * sets up their pages tables accordingly when they submit their
61 * command buffers and a VMID is assigned.
62 * Cayman/Trinity support up to 8 active VMs at any given time;
63 * SI supports 16.
64 */
65
66#define START(node) ((node)->start)
67#define LAST(node) ((node)->last)
68
69INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
70 START, LAST, static, amdgpu_vm_it)
71
72#undef START
73#undef LAST
74
75/**
76 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
77 */
78struct amdgpu_prt_cb {
79
80 /**
81 * @adev: amdgpu device
82 */
83 struct amdgpu_device *adev;
84
85 /**
86 * @cb: callback
87 */
88 struct dma_fence_cb cb;
89};
90
91/*
92 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
93 * happens while holding this lock anywhere to prevent deadlocks when
94 * an MMU notifier runs in reclaim-FS context.
95 */
96static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
97{
98 mutex_lock(&vm->eviction_lock);
99 vm->saved_flags = memalloc_noreclaim_save();
100}
101
102static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
103{
104 if (mutex_trylock(&vm->eviction_lock)) {
105 vm->saved_flags = memalloc_noreclaim_save();
106 return 1;
107 }
108 return 0;
109}
110
111static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
112{
113 memalloc_noreclaim_restore(vm->saved_flags);
114 mutex_unlock(&vm->eviction_lock);
115}
116
117/**
118 * amdgpu_vm_level_shift - return the addr shift for each level
119 *
120 * @adev: amdgpu_device pointer
121 * @level: VMPT level
122 *
123 * Returns:
124 * The number of bits the pfn needs to be right shifted for a level.
125 */
126static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
127 unsigned level)
128{
129 switch (level) {
130 case AMDGPU_VM_PDB2:
131 case AMDGPU_VM_PDB1:
132 case AMDGPU_VM_PDB0:
133 return 9 * (AMDGPU_VM_PDB0 - level) +
134 adev->vm_manager.block_size;
135 case AMDGPU_VM_PTB:
136 return 0;
137 default:
138 return ~0;
139 }
140}
141
142/**
143 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
144 *
145 * @adev: amdgpu_device pointer
146 * @level: VMPT level
147 *
148 * Returns:
149 * The number of entries in a page directory or page table.
150 */
151static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
152 unsigned level)
153{
154 unsigned shift = amdgpu_vm_level_shift(adev,
155 adev->vm_manager.root_level);
156
157 if (level == adev->vm_manager.root_level)
158 /* For the root directory */
159 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
160 >> shift;
161 else if (level != AMDGPU_VM_PTB)
162 /* Everything in between */
163 return 512;
164 else
165 /* For the page tables on the leaves */
166 return AMDGPU_VM_PTE_COUNT(adev);
167}
168
169/**
170 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
171 *
172 * @adev: amdgpu_device pointer
173 *
174 * Returns:
175 * The number of entries in the root page directory which needs the ATS setting.
176 */
177static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
178{
179 unsigned shift;
180
181 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
182 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
183}
184
185/**
186 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
187 *
188 * @adev: amdgpu_device pointer
189 * @level: VMPT level
190 *
191 * Returns:
192 * The mask to extract the entry number of a PD/PT from an address.
193 */
194static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
195 unsigned int level)
196{
197 if (level <= adev->vm_manager.root_level)
198 return 0xffffffff;
199 else if (level != AMDGPU_VM_PTB)
200 return 0x1ff;
201 else
202 return AMDGPU_VM_PTE_COUNT(adev) - 1;
203}
204
205/**
206 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
207 *
208 * @adev: amdgpu_device pointer
209 * @level: VMPT level
210 *
211 * Returns:
212 * The size of the BO for a page directory or page table in bytes.
213 */
214static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
215{
216 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
217}
218
219/**
220 * amdgpu_vm_bo_evicted - vm_bo is evicted
221 *
222 * @vm_bo: vm_bo which is evicted
223 *
224 * State for PDs/PTs and per VM BOs which are not at the location they should
225 * be.
226 */
227static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
228{
229 struct amdgpu_vm *vm = vm_bo->vm;
230 struct amdgpu_bo *bo = vm_bo->bo;
231
232 vm_bo->moved = true;
233 if (bo->tbo.type == ttm_bo_type_kernel)
234 list_move(&vm_bo->vm_status, &vm->evicted);
235 else
236 list_move_tail(&vm_bo->vm_status, &vm->evicted);
237}
238/**
239 * amdgpu_vm_bo_moved - vm_bo is moved
240 *
241 * @vm_bo: vm_bo which is moved
242 *
243 * State for per VM BOs which are moved, but that change is not yet reflected
244 * in the page tables.
245 */
246static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
247{
248 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
249}
250
251/**
252 * amdgpu_vm_bo_idle - vm_bo is idle
253 *
254 * @vm_bo: vm_bo which is now idle
255 *
256 * State for PDs/PTs and per VM BOs which have gone through the state machine
257 * and are now idle.
258 */
259static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
260{
261 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
262 vm_bo->moved = false;
263}
264
265/**
266 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
267 *
268 * @vm_bo: vm_bo which is now invalidated
269 *
270 * State for normal BOs which are invalidated and that change not yet reflected
271 * in the PTs.
272 */
273static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
274{
275 spin_lock(&vm_bo->vm->invalidated_lock);
276 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
277 spin_unlock(&vm_bo->vm->invalidated_lock);
278}
279
280/**
281 * amdgpu_vm_bo_relocated - vm_bo is reloacted
282 *
283 * @vm_bo: vm_bo which is relocated
284 *
285 * State for PDs/PTs which needs to update their parent PD.
286 * For the root PD, just move to idle state.
287 */
288static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
289{
290 if (vm_bo->bo->parent)
291 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
292 else
293 amdgpu_vm_bo_idle(vm_bo);
294}
295
296/**
297 * amdgpu_vm_bo_done - vm_bo is done
298 *
299 * @vm_bo: vm_bo which is now done
300 *
301 * State for normal BOs which are invalidated and that change has been updated
302 * in the PTs.
303 */
304static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
305{
306 spin_lock(&vm_bo->vm->invalidated_lock);
307 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
308 spin_unlock(&vm_bo->vm->invalidated_lock);
309}
310
311/**
312 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
313 *
314 * @base: base structure for tracking BO usage in a VM
315 * @vm: vm to which bo is to be added
316 * @bo: amdgpu buffer object
317 *
318 * Initialize a bo_va_base structure and add it to the appropriate lists
319 *
320 */
321static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
322 struct amdgpu_vm *vm,
323 struct amdgpu_bo *bo)
324{
325 base->vm = vm;
326 base->bo = bo;
327 base->next = NULL;
328 INIT_LIST_HEAD(&base->vm_status);
329
330 if (!bo)
331 return;
332 base->next = bo->vm_bo;
333 bo->vm_bo = base;
334
335 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
336 return;
337
338 vm->bulk_moveable = false;
339 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
340 amdgpu_vm_bo_relocated(base);
341 else
342 amdgpu_vm_bo_idle(base);
343
344 if (bo->preferred_domains &
345 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
346 return;
347
348 /*
349 * we checked all the prerequisites, but it looks like this per vm bo
350 * is currently evicted. add the bo to the evicted list to make sure it
351 * is validated on next vm use to avoid fault.
352 * */
353 amdgpu_vm_bo_evicted(base);
354}
355
356/**
357 * amdgpu_vm_pt_parent - get the parent page directory
358 *
359 * @pt: child page table
360 *
361 * Helper to get the parent entry for the child page table. NULL if we are at
362 * the root page directory.
363 */
364static struct amdgpu_vm_bo_base *amdgpu_vm_pt_parent(struct amdgpu_vm_bo_base *pt)
365{
366 struct amdgpu_bo *parent = pt->bo->parent;
367
368 if (!parent)
369 return NULL;
370
371 return parent->vm_bo;
372}
373
374/*
375 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
376 */
377struct amdgpu_vm_pt_cursor {
378 uint64_t pfn;
379 struct amdgpu_vm_bo_base *parent;
380 struct amdgpu_vm_bo_base *entry;
381 unsigned level;
382};
383
384/**
385 * amdgpu_vm_pt_start - start PD/PT walk
386 *
387 * @adev: amdgpu_device pointer
388 * @vm: amdgpu_vm structure
389 * @start: start address of the walk
390 * @cursor: state to initialize
391 *
392 * Initialize a amdgpu_vm_pt_cursor to start a walk.
393 */
394static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm, uint64_t start,
396 struct amdgpu_vm_pt_cursor *cursor)
397{
398 cursor->pfn = start;
399 cursor->parent = NULL;
400 cursor->entry = &vm->root;
401 cursor->level = adev->vm_manager.root_level;
402}
403
404/**
405 * amdgpu_vm_pt_descendant - go to child node
406 *
407 * @adev: amdgpu_device pointer
408 * @cursor: current state
409 *
410 * Walk to the child node of the current node.
411 * Returns:
412 * True if the walk was possible, false otherwise.
413 */
414static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
415 struct amdgpu_vm_pt_cursor *cursor)
416{
417 unsigned mask, shift, idx;
418
419 if ((cursor->level == AMDGPU_VM_PTB) || !cursor->entry ||
420 !cursor->entry->bo)
421 return false;
422
423 mask = amdgpu_vm_entries_mask(adev, cursor->level);
424 shift = amdgpu_vm_level_shift(adev, cursor->level);
425
426 ++cursor->level;
427 idx = (cursor->pfn >> shift) & mask;
428 cursor->parent = cursor->entry;
429 cursor->entry = &to_amdgpu_bo_vm(cursor->entry->bo)->entries[idx];
430 return true;
431}
432
433/**
434 * amdgpu_vm_pt_sibling - go to sibling node
435 *
436 * @adev: amdgpu_device pointer
437 * @cursor: current state
438 *
439 * Walk to the sibling node of the current node.
440 * Returns:
441 * True if the walk was possible, false otherwise.
442 */
443static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
444 struct amdgpu_vm_pt_cursor *cursor)
445{
446 unsigned shift, num_entries;
447
448 /* Root doesn't have a sibling */
449 if (!cursor->parent)
450 return false;
451
452 /* Go to our parents and see if we got a sibling */
453 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
454 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
455
456 if (cursor->entry == &to_amdgpu_bo_vm(cursor->parent->bo)->entries[num_entries - 1])
457 return false;
458
459 cursor->pfn += 1ULL << shift;
460 cursor->pfn &= ~((1ULL << shift) - 1);
461 ++cursor->entry;
462 return true;
463}
464
465/**
466 * amdgpu_vm_pt_ancestor - go to parent node
467 *
468 * @cursor: current state
469 *
470 * Walk to the parent node of the current node.
471 * Returns:
472 * True if the walk was possible, false otherwise.
473 */
474static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
475{
476 if (!cursor->parent)
477 return false;
478
479 --cursor->level;
480 cursor->entry = cursor->parent;
481 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
482 return true;
483}
484
485/**
486 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
487 *
488 * @adev: amdgpu_device pointer
489 * @cursor: current state
490 *
491 * Walk the PD/PT tree to the next node.
492 */
493static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
494 struct amdgpu_vm_pt_cursor *cursor)
495{
496 /* First try a newborn child */
497 if (amdgpu_vm_pt_descendant(adev, cursor))
498 return;
499
500 /* If that didn't worked try to find a sibling */
501 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
502 /* No sibling, go to our parents and grandparents */
503 if (!amdgpu_vm_pt_ancestor(cursor)) {
504 cursor->pfn = ~0ll;
505 return;
506 }
507 }
508}
509
510/**
511 * amdgpu_vm_pt_first_dfs - start a deep first search
512 *
513 * @adev: amdgpu_device structure
514 * @vm: amdgpu_vm structure
515 * @start: optional cursor to start with
516 * @cursor: state to initialize
517 *
518 * Starts a deep first traversal of the PD/PT tree.
519 */
520static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
521 struct amdgpu_vm *vm,
522 struct amdgpu_vm_pt_cursor *start,
523 struct amdgpu_vm_pt_cursor *cursor)
524{
525 if (start)
526 *cursor = *start;
527 else
528 amdgpu_vm_pt_start(adev, vm, 0, cursor);
529 while (amdgpu_vm_pt_descendant(adev, cursor));
530}
531
532/**
533 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
534 *
535 * @start: starting point for the search
536 * @entry: current entry
537 *
538 * Returns:
539 * True when the search should continue, false otherwise.
540 */
541static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
542 struct amdgpu_vm_bo_base *entry)
543{
544 return entry && (!start || entry != start->entry);
545}
546
547/**
548 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
549 *
550 * @adev: amdgpu_device structure
551 * @cursor: current state
552 *
553 * Move the cursor to the next node in a deep first search.
554 */
555static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
556 struct amdgpu_vm_pt_cursor *cursor)
557{
558 if (!cursor->entry)
559 return;
560
561 if (!cursor->parent)
562 cursor->entry = NULL;
563 else if (amdgpu_vm_pt_sibling(adev, cursor))
564 while (amdgpu_vm_pt_descendant(adev, cursor));
565 else
566 amdgpu_vm_pt_ancestor(cursor);
567}
568
569/*
570 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
571 */
572#define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
573 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
574 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
575 amdgpu_vm_pt_continue_dfs((start), (entry)); \
576 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
577
578/**
579 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
580 *
581 * @vm: vm providing the BOs
582 * @validated: head of validation list
583 * @entry: entry to add
584 *
585 * Add the page directory to the list of BOs to
586 * validate for command submission.
587 */
588void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
589 struct list_head *validated,
590 struct amdgpu_bo_list_entry *entry)
591{
592 entry->priority = 0;
593 entry->tv.bo = &vm->root.bo->tbo;
594 /* Two for VM updates, one for TTM and one for the CS job */
595 entry->tv.num_shared = 4;
596 entry->user_pages = NULL;
597 list_add(&entry->tv.head, validated);
598}
599
600/**
601 * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
602 *
603 * @bo: BO which was removed from the LRU
604 *
605 * Make sure the bulk_moveable flag is updated when a BO is removed from the
606 * LRU.
607 */
608void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
609{
610 struct amdgpu_bo *abo;
611 struct amdgpu_vm_bo_base *bo_base;
612
613 if (!amdgpu_bo_is_amdgpu_bo(bo))
614 return;
615
616 if (bo->pin_count)
617 return;
618
619 abo = ttm_to_amdgpu_bo(bo);
620 if (!abo->parent)
621 return;
622 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
623 struct amdgpu_vm *vm = bo_base->vm;
624
625 if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv)
626 vm->bulk_moveable = false;
627 }
628
629}
630/**
631 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
632 *
633 * @adev: amdgpu device pointer
634 * @vm: vm providing the BOs
635 *
636 * Move all BOs to the end of LRU and remember their positions to put them
637 * together.
638 */
639void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
640 struct amdgpu_vm *vm)
641{
642 struct amdgpu_vm_bo_base *bo_base;
643
644 if (vm->bulk_moveable) {
645 spin_lock(&adev->mman.bdev.lru_lock);
646 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
647 spin_unlock(&adev->mman.bdev.lru_lock);
648 return;
649 }
650
651 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
652
653 spin_lock(&adev->mman.bdev.lru_lock);
654 list_for_each_entry(bo_base, &vm->idle, vm_status) {
655 struct amdgpu_bo *bo = bo_base->bo;
656 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
657
658 if (!bo->parent)
659 continue;
660
661 ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource,
662 &vm->lru_bulk_move);
663 if (shadow)
664 ttm_bo_move_to_lru_tail(&shadow->tbo,
665 shadow->tbo.resource,
666 &vm->lru_bulk_move);
667 }
668 spin_unlock(&adev->mman.bdev.lru_lock);
669
670 vm->bulk_moveable = true;
671}
672
673/**
674 * amdgpu_vm_validate_pt_bos - validate the page table BOs
675 *
676 * @adev: amdgpu device pointer
677 * @vm: vm providing the BOs
678 * @validate: callback to do the validation
679 * @param: parameter for the validation callback
680 *
681 * Validate the page table BOs on command submission if neccessary.
682 *
683 * Returns:
684 * Validation result.
685 */
686int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
687 int (*validate)(void *p, struct amdgpu_bo *bo),
688 void *param)
689{
690 struct amdgpu_vm_bo_base *bo_base, *tmp;
691 int r;
692
693 vm->bulk_moveable &= list_empty(&vm->evicted);
694
695 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
696 struct amdgpu_bo *bo = bo_base->bo;
697 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
698
699 r = validate(param, bo);
700 if (r)
701 return r;
702 if (shadow) {
703 r = validate(param, shadow);
704 if (r)
705 return r;
706 }
707
708 if (bo->tbo.type != ttm_bo_type_kernel) {
709 amdgpu_vm_bo_moved(bo_base);
710 } else {
711 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
712 amdgpu_vm_bo_relocated(bo_base);
713 }
714 }
715
716 amdgpu_vm_eviction_lock(vm);
717 vm->evicting = false;
718 amdgpu_vm_eviction_unlock(vm);
719
720 return 0;
721}
722
723/**
724 * amdgpu_vm_ready - check VM is ready for updates
725 *
726 * @vm: VM to check
727 *
728 * Check if all VM PDs/PTs are ready for updates
729 *
730 * Returns:
731 * True if eviction list is empty.
732 */
733bool amdgpu_vm_ready(struct amdgpu_vm *vm)
734{
735 return list_empty(&vm->evicted);
736}
737
738/**
739 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
740 *
741 * @adev: amdgpu_device pointer
742 * @vm: VM to clear BO from
743 * @vmbo: BO to clear
744 * @immediate: use an immediate update
745 *
746 * Root PD needs to be reserved when calling this.
747 *
748 * Returns:
749 * 0 on success, errno otherwise.
750 */
751static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
752 struct amdgpu_vm *vm,
753 struct amdgpu_bo_vm *vmbo,
754 bool immediate)
755{
756 struct ttm_operation_ctx ctx = { true, false };
757 unsigned level = adev->vm_manager.root_level;
758 struct amdgpu_vm_update_params params;
759 struct amdgpu_bo *ancestor = &vmbo->bo;
760 struct amdgpu_bo *bo = &vmbo->bo;
761 unsigned entries, ats_entries;
762 uint64_t addr;
763 int r;
764
765 /* Figure out our place in the hierarchy */
766 if (ancestor->parent) {
767 ++level;
768 while (ancestor->parent->parent) {
769 ++level;
770 ancestor = ancestor->parent;
771 }
772 }
773
774 entries = amdgpu_bo_size(bo) / 8;
775 if (!vm->pte_support_ats) {
776 ats_entries = 0;
777
778 } else if (!bo->parent) {
779 ats_entries = amdgpu_vm_num_ats_entries(adev);
780 ats_entries = min(ats_entries, entries);
781 entries -= ats_entries;
782
783 } else {
784 struct amdgpu_vm_bo_base *pt;
785
786 pt = ancestor->vm_bo;
787 ats_entries = amdgpu_vm_num_ats_entries(adev);
788 if ((pt - to_amdgpu_bo_vm(vm->root.bo)->entries) >= ats_entries) {
789 ats_entries = 0;
790 } else {
791 ats_entries = entries;
792 entries = 0;
793 }
794 }
795
796 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
797 if (r)
798 return r;
799
800 if (vmbo->shadow) {
801 struct amdgpu_bo *shadow = vmbo->shadow;
802
803 r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx);
804 if (r)
805 return r;
806 }
807
808 r = vm->update_funcs->map_table(vmbo);
809 if (r)
810 return r;
811
812 memset(¶ms, 0, sizeof(params));
813 params.adev = adev;
814 params.vm = vm;
815 params.immediate = immediate;
816
817 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
818 if (r)
819 return r;
820
821 addr = 0;
822 if (ats_entries) {
823 uint64_t value = 0, flags;
824
825 flags = AMDGPU_PTE_DEFAULT_ATC;
826 if (level != AMDGPU_VM_PTB) {
827 /* Handle leaf PDEs as PTEs */
828 flags |= AMDGPU_PDE_PTE;
829 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
830 }
831
832 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, ats_entries,
833 value, flags);
834 if (r)
835 return r;
836
837 addr += ats_entries * 8;
838 }
839
840 if (entries) {
841 uint64_t value = 0, flags = 0;
842
843 if (adev->asic_type >= CHIP_VEGA10) {
844 if (level != AMDGPU_VM_PTB) {
845 /* Handle leaf PDEs as PTEs */
846 flags |= AMDGPU_PDE_PTE;
847 amdgpu_gmc_get_vm_pde(adev, level,
848 &value, &flags);
849 } else {
850 /* Workaround for fault priority problem on GMC9 */
851 flags = AMDGPU_PTE_EXECUTABLE;
852 }
853 }
854
855 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, entries,
856 value, flags);
857 if (r)
858 return r;
859 }
860
861 return vm->update_funcs->commit(¶ms, NULL);
862}
863
864/**
865 * amdgpu_vm_pt_create - create bo for PD/PT
866 *
867 * @adev: amdgpu_device pointer
868 * @vm: requesting vm
869 * @level: the page table level
870 * @immediate: use a immediate update
871 * @vmbo: pointer to the buffer object pointer
872 */
873static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
874 struct amdgpu_vm *vm,
875 int level, bool immediate,
876 struct amdgpu_bo_vm **vmbo)
877{
878 struct amdgpu_bo_param bp;
879 struct amdgpu_bo *bo;
880 struct dma_resv *resv;
881 unsigned int num_entries;
882 int r;
883
884 memset(&bp, 0, sizeof(bp));
885
886 bp.size = amdgpu_vm_bo_size(adev, level);
887 bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
888 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
889 bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
890 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
891 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
892
893 if (level < AMDGPU_VM_PTB)
894 num_entries = amdgpu_vm_num_entries(adev, level);
895 else
896 num_entries = 0;
897
898 bp.bo_ptr_size = struct_size((*vmbo), entries, num_entries);
899
900 if (vm->use_cpu_for_update)
901 bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
902
903 bp.type = ttm_bo_type_kernel;
904 bp.no_wait_gpu = immediate;
905 if (vm->root.bo)
906 bp.resv = vm->root.bo->tbo.base.resv;
907
908 r = amdgpu_bo_create_vm(adev, &bp, vmbo);
909 if (r)
910 return r;
911
912 bo = &(*vmbo)->bo;
913 if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) {
914 (*vmbo)->shadow = NULL;
915 return 0;
916 }
917
918 if (!bp.resv)
919 WARN_ON(dma_resv_lock(bo->tbo.base.resv,
920 NULL));
921 resv = bp.resv;
922 memset(&bp, 0, sizeof(bp));
923 bp.size = amdgpu_vm_bo_size(adev, level);
924 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
925 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
926 bp.type = ttm_bo_type_kernel;
927 bp.resv = bo->tbo.base.resv;
928 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
929
930 r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow);
931
932 if (!resv)
933 dma_resv_unlock(bo->tbo.base.resv);
934
935 if (r) {
936 amdgpu_bo_unref(&bo);
937 return r;
938 }
939
940 (*vmbo)->shadow->parent = amdgpu_bo_ref(bo);
941 amdgpu_bo_add_to_shadow_list(*vmbo);
942
943 return 0;
944}
945
946/**
947 * amdgpu_vm_alloc_pts - Allocate a specific page table
948 *
949 * @adev: amdgpu_device pointer
950 * @vm: VM to allocate page tables for
951 * @cursor: Which page table to allocate
952 * @immediate: use an immediate update
953 *
954 * Make sure a specific page table or directory is allocated.
955 *
956 * Returns:
957 * 1 if page table needed to be allocated, 0 if page table was already
958 * allocated, negative errno if an error occurred.
959 */
960static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
961 struct amdgpu_vm *vm,
962 struct amdgpu_vm_pt_cursor *cursor,
963 bool immediate)
964{
965 struct amdgpu_vm_bo_base *entry = cursor->entry;
966 struct amdgpu_bo *pt_bo;
967 struct amdgpu_bo_vm *pt;
968 int r;
969
970 if (entry->bo)
971 return 0;
972
973 r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
974 if (r)
975 return r;
976
977 /* Keep a reference to the root directory to avoid
978 * freeing them up in the wrong order.
979 */
980 pt_bo = &pt->bo;
981 pt_bo->parent = amdgpu_bo_ref(cursor->parent->bo);
982 amdgpu_vm_bo_base_init(entry, vm, pt_bo);
983 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
984 if (r)
985 goto error_free_pt;
986
987 return 0;
988
989error_free_pt:
990 amdgpu_bo_unref(&pt->shadow);
991 amdgpu_bo_unref(&pt_bo);
992 return r;
993}
994
995/**
996 * amdgpu_vm_free_table - fre one PD/PT
997 *
998 * @entry: PDE to free
999 */
1000static void amdgpu_vm_free_table(struct amdgpu_vm_bo_base *entry)
1001{
1002 struct amdgpu_bo *shadow;
1003
1004 if (!entry->bo)
1005 return;
1006 shadow = amdgpu_bo_shadowed(entry->bo);
1007 entry->bo->vm_bo = NULL;
1008 list_del(&entry->vm_status);
1009 amdgpu_bo_unref(&shadow);
1010 amdgpu_bo_unref(&entry->bo);
1011}
1012
1013/**
1014 * amdgpu_vm_free_pts - free PD/PT levels
1015 *
1016 * @adev: amdgpu device structure
1017 * @vm: amdgpu vm structure
1018 * @start: optional cursor where to start freeing PDs/PTs
1019 *
1020 * Free the page directory or page table level and all sub levels.
1021 */
1022static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
1023 struct amdgpu_vm *vm,
1024 struct amdgpu_vm_pt_cursor *start)
1025{
1026 struct amdgpu_vm_pt_cursor cursor;
1027 struct amdgpu_vm_bo_base *entry;
1028
1029 vm->bulk_moveable = false;
1030
1031 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
1032 amdgpu_vm_free_table(entry);
1033
1034 if (start)
1035 amdgpu_vm_free_table(start->entry);
1036}
1037
1038/**
1039 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
1040 *
1041 * @adev: amdgpu_device pointer
1042 */
1043void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
1044{
1045 const struct amdgpu_ip_block *ip_block;
1046 bool has_compute_vm_bug;
1047 struct amdgpu_ring *ring;
1048 int i;
1049
1050 has_compute_vm_bug = false;
1051
1052 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1053 if (ip_block) {
1054 /* Compute has a VM bug for GFX version < 7.
1055 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1056 if (ip_block->version->major <= 7)
1057 has_compute_vm_bug = true;
1058 else if (ip_block->version->major == 8)
1059 if (adev->gfx.mec_fw_version < 673)
1060 has_compute_vm_bug = true;
1061 }
1062
1063 for (i = 0; i < adev->num_rings; i++) {
1064 ring = adev->rings[i];
1065 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1066 /* only compute rings */
1067 ring->has_compute_vm_bug = has_compute_vm_bug;
1068 else
1069 ring->has_compute_vm_bug = false;
1070 }
1071}
1072
1073/**
1074 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1075 *
1076 * @ring: ring on which the job will be submitted
1077 * @job: job to submit
1078 *
1079 * Returns:
1080 * True if sync is needed.
1081 */
1082bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1083 struct amdgpu_job *job)
1084{
1085 struct amdgpu_device *adev = ring->adev;
1086 unsigned vmhub = ring->funcs->vmhub;
1087 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1088 struct amdgpu_vmid *id;
1089 bool gds_switch_needed;
1090 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1091
1092 if (job->vmid == 0)
1093 return false;
1094 id = &id_mgr->ids[job->vmid];
1095 gds_switch_needed = ring->funcs->emit_gds_switch && (
1096 id->gds_base != job->gds_base ||
1097 id->gds_size != job->gds_size ||
1098 id->gws_base != job->gws_base ||
1099 id->gws_size != job->gws_size ||
1100 id->oa_base != job->oa_base ||
1101 id->oa_size != job->oa_size);
1102
1103 if (amdgpu_vmid_had_gpu_reset(adev, id))
1104 return true;
1105
1106 return vm_flush_needed || gds_switch_needed;
1107}
1108
1109/**
1110 * amdgpu_vm_flush - hardware flush the vm
1111 *
1112 * @ring: ring to use for flush
1113 * @job: related job
1114 * @need_pipe_sync: is pipe sync needed
1115 *
1116 * Emit a VM flush when it is necessary.
1117 *
1118 * Returns:
1119 * 0 on success, errno otherwise.
1120 */
1121int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1122 bool need_pipe_sync)
1123{
1124 struct amdgpu_device *adev = ring->adev;
1125 unsigned vmhub = ring->funcs->vmhub;
1126 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1127 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1128 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1129 id->gds_base != job->gds_base ||
1130 id->gds_size != job->gds_size ||
1131 id->gws_base != job->gws_base ||
1132 id->gws_size != job->gws_size ||
1133 id->oa_base != job->oa_base ||
1134 id->oa_size != job->oa_size);
1135 bool vm_flush_needed = job->vm_needs_flush;
1136 struct dma_fence *fence = NULL;
1137 bool pasid_mapping_needed = false;
1138 unsigned patch_offset = 0;
1139 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1140 int r;
1141
1142 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1143 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1144
1145 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1146 gds_switch_needed = true;
1147 vm_flush_needed = true;
1148 pasid_mapping_needed = true;
1149 }
1150
1151 mutex_lock(&id_mgr->lock);
1152 if (id->pasid != job->pasid || !id->pasid_mapping ||
1153 !dma_fence_is_signaled(id->pasid_mapping))
1154 pasid_mapping_needed = true;
1155 mutex_unlock(&id_mgr->lock);
1156
1157 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1158 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1159 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1160 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1161 ring->funcs->emit_wreg;
1162
1163 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1164 return 0;
1165
1166 if (ring->funcs->init_cond_exec)
1167 patch_offset = amdgpu_ring_init_cond_exec(ring);
1168
1169 if (need_pipe_sync)
1170 amdgpu_ring_emit_pipeline_sync(ring);
1171
1172 if (vm_flush_needed) {
1173 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1174 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1175 }
1176
1177 if (pasid_mapping_needed)
1178 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1179
1180 if (vm_flush_needed || pasid_mapping_needed) {
1181 r = amdgpu_fence_emit(ring, &fence, 0);
1182 if (r)
1183 return r;
1184 }
1185
1186 if (vm_flush_needed) {
1187 mutex_lock(&id_mgr->lock);
1188 dma_fence_put(id->last_flush);
1189 id->last_flush = dma_fence_get(fence);
1190 id->current_gpu_reset_count =
1191 atomic_read(&adev->gpu_reset_counter);
1192 mutex_unlock(&id_mgr->lock);
1193 }
1194
1195 if (pasid_mapping_needed) {
1196 mutex_lock(&id_mgr->lock);
1197 id->pasid = job->pasid;
1198 dma_fence_put(id->pasid_mapping);
1199 id->pasid_mapping = dma_fence_get(fence);
1200 mutex_unlock(&id_mgr->lock);
1201 }
1202 dma_fence_put(fence);
1203
1204 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1205 id->gds_base = job->gds_base;
1206 id->gds_size = job->gds_size;
1207 id->gws_base = job->gws_base;
1208 id->gws_size = job->gws_size;
1209 id->oa_base = job->oa_base;
1210 id->oa_size = job->oa_size;
1211 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1212 job->gds_size, job->gws_base,
1213 job->gws_size, job->oa_base,
1214 job->oa_size);
1215 }
1216
1217 if (ring->funcs->patch_cond_exec)
1218 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1219
1220 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1221 if (ring->funcs->emit_switch_buffer) {
1222 amdgpu_ring_emit_switch_buffer(ring);
1223 amdgpu_ring_emit_switch_buffer(ring);
1224 }
1225 return 0;
1226}
1227
1228/**
1229 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1230 *
1231 * @vm: requested vm
1232 * @bo: requested buffer object
1233 *
1234 * Find @bo inside the requested vm.
1235 * Search inside the @bos vm list for the requested vm
1236 * Returns the found bo_va or NULL if none is found
1237 *
1238 * Object has to be reserved!
1239 *
1240 * Returns:
1241 * Found bo_va or NULL.
1242 */
1243struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1244 struct amdgpu_bo *bo)
1245{
1246 struct amdgpu_vm_bo_base *base;
1247
1248 for (base = bo->vm_bo; base; base = base->next) {
1249 if (base->vm != vm)
1250 continue;
1251
1252 return container_of(base, struct amdgpu_bo_va, base);
1253 }
1254 return NULL;
1255}
1256
1257/**
1258 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1259 *
1260 * @pages_addr: optional DMA address to use for lookup
1261 * @addr: the unmapped addr
1262 *
1263 * Look up the physical address of the page that the pte resolves
1264 * to.
1265 *
1266 * Returns:
1267 * The pointer for the page table entry.
1268 */
1269uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1270{
1271 uint64_t result;
1272
1273 /* page table offset */
1274 result = pages_addr[addr >> PAGE_SHIFT];
1275
1276 /* in case cpu page size != gpu page size*/
1277 result |= addr & (~PAGE_MASK);
1278
1279 result &= 0xFFFFFFFFFFFFF000ULL;
1280
1281 return result;
1282}
1283
1284/**
1285 * amdgpu_vm_update_pde - update a single level in the hierarchy
1286 *
1287 * @params: parameters for the update
1288 * @vm: requested vm
1289 * @entry: entry to update
1290 *
1291 * Makes sure the requested entry in parent is up to date.
1292 */
1293static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1294 struct amdgpu_vm *vm,
1295 struct amdgpu_vm_bo_base *entry)
1296{
1297 struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
1298 struct amdgpu_bo *bo = parent->bo, *pbo;
1299 uint64_t pde, pt, flags;
1300 unsigned level;
1301
1302 for (level = 0, pbo = bo->parent; pbo; ++level)
1303 pbo = pbo->parent;
1304
1305 level += params->adev->vm_manager.root_level;
1306 amdgpu_gmc_get_pde_for_bo(entry->bo, level, &pt, &flags);
1307 pde = (entry - to_amdgpu_bo_vm(parent->bo)->entries) * 8;
1308 return vm->update_funcs->update(params, to_amdgpu_bo_vm(bo), pde, pt,
1309 1, 0, flags);
1310}
1311
1312/**
1313 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1314 *
1315 * @adev: amdgpu_device pointer
1316 * @vm: related vm
1317 *
1318 * Mark all PD level as invalid after an error.
1319 */
1320static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1321 struct amdgpu_vm *vm)
1322{
1323 struct amdgpu_vm_pt_cursor cursor;
1324 struct amdgpu_vm_bo_base *entry;
1325
1326 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1327 if (entry->bo && !entry->moved)
1328 amdgpu_vm_bo_relocated(entry);
1329}
1330
1331/**
1332 * amdgpu_vm_update_pdes - make sure that all directories are valid
1333 *
1334 * @adev: amdgpu_device pointer
1335 * @vm: requested vm
1336 * @immediate: submit immediately to the paging queue
1337 *
1338 * Makes sure all directories are up to date.
1339 *
1340 * Returns:
1341 * 0 for success, error for failure.
1342 */
1343int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1344 struct amdgpu_vm *vm, bool immediate)
1345{
1346 struct amdgpu_vm_update_params params;
1347 int r;
1348
1349 if (list_empty(&vm->relocated))
1350 return 0;
1351
1352 memset(¶ms, 0, sizeof(params));
1353 params.adev = adev;
1354 params.vm = vm;
1355 params.immediate = immediate;
1356
1357 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1358 if (r)
1359 return r;
1360
1361 while (!list_empty(&vm->relocated)) {
1362 struct amdgpu_vm_bo_base *entry;
1363
1364 entry = list_first_entry(&vm->relocated,
1365 struct amdgpu_vm_bo_base,
1366 vm_status);
1367 amdgpu_vm_bo_idle(entry);
1368
1369 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1370 if (r)
1371 goto error;
1372 }
1373
1374 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1375 if (r)
1376 goto error;
1377 return 0;
1378
1379error:
1380 amdgpu_vm_invalidate_pds(adev, vm);
1381 return r;
1382}
1383
1384/*
1385 * amdgpu_vm_update_flags - figure out flags for PTE updates
1386 *
1387 * Make sure to set the right flags for the PTEs at the desired level.
1388 */
1389static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1390 struct amdgpu_bo_vm *pt, unsigned int level,
1391 uint64_t pe, uint64_t addr,
1392 unsigned int count, uint32_t incr,
1393 uint64_t flags)
1394
1395{
1396 if (level != AMDGPU_VM_PTB) {
1397 flags |= AMDGPU_PDE_PTE;
1398 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1399
1400 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1401 !(flags & AMDGPU_PTE_VALID) &&
1402 !(flags & AMDGPU_PTE_PRT)) {
1403
1404 /* Workaround for fault priority problem on GMC9 */
1405 flags |= AMDGPU_PTE_EXECUTABLE;
1406 }
1407
1408 params->vm->update_funcs->update(params, pt, pe, addr, count, incr,
1409 flags);
1410}
1411
1412/**
1413 * amdgpu_vm_fragment - get fragment for PTEs
1414 *
1415 * @params: see amdgpu_vm_update_params definition
1416 * @start: first PTE to handle
1417 * @end: last PTE to handle
1418 * @flags: hw mapping flags
1419 * @frag: resulting fragment size
1420 * @frag_end: end of this fragment
1421 *
1422 * Returns the first possible fragment for the start and end address.
1423 */
1424static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1425 uint64_t start, uint64_t end, uint64_t flags,
1426 unsigned int *frag, uint64_t *frag_end)
1427{
1428 /**
1429 * The MC L1 TLB supports variable sized pages, based on a fragment
1430 * field in the PTE. When this field is set to a non-zero value, page
1431 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1432 * flags are considered valid for all PTEs within the fragment range
1433 * and corresponding mappings are assumed to be physically contiguous.
1434 *
1435 * The L1 TLB can store a single PTE for the whole fragment,
1436 * significantly increasing the space available for translation
1437 * caching. This leads to large improvements in throughput when the
1438 * TLB is under pressure.
1439 *
1440 * The L2 TLB distributes small and large fragments into two
1441 * asymmetric partitions. The large fragment cache is significantly
1442 * larger. Thus, we try to use large fragments wherever possible.
1443 * Userspace can support this by aligning virtual base address and
1444 * allocation size to the fragment size.
1445 *
1446 * Starting with Vega10 the fragment size only controls the L1. The L2
1447 * is now directly feed with small/huge/giant pages from the walker.
1448 */
1449 unsigned max_frag;
1450
1451 if (params->adev->asic_type < CHIP_VEGA10)
1452 max_frag = params->adev->vm_manager.fragment_size;
1453 else
1454 max_frag = 31;
1455
1456 /* system pages are non continuously */
1457 if (params->pages_addr) {
1458 *frag = 0;
1459 *frag_end = end;
1460 return;
1461 }
1462
1463 /* This intentionally wraps around if no bit is set */
1464 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1465 if (*frag >= max_frag) {
1466 *frag = max_frag;
1467 *frag_end = end & ~((1ULL << max_frag) - 1);
1468 } else {
1469 *frag_end = start + (1 << *frag);
1470 }
1471}
1472
1473/**
1474 * amdgpu_vm_update_ptes - make sure that page tables are valid
1475 *
1476 * @params: see amdgpu_vm_update_params definition
1477 * @start: start of GPU address range
1478 * @end: end of GPU address range
1479 * @dst: destination address to map to, the next dst inside the function
1480 * @flags: mapping flags
1481 *
1482 * Update the page tables in the range @start - @end.
1483 *
1484 * Returns:
1485 * 0 for success, -EINVAL for failure.
1486 */
1487static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1488 uint64_t start, uint64_t end,
1489 uint64_t dst, uint64_t flags)
1490{
1491 struct amdgpu_device *adev = params->adev;
1492 struct amdgpu_vm_pt_cursor cursor;
1493 uint64_t frag_start = start, frag_end;
1494 unsigned int frag;
1495 int r;
1496
1497 /* figure out the initial fragment */
1498 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1499
1500 /* walk over the address space and update the PTs */
1501 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1502 while (cursor.pfn < end) {
1503 unsigned shift, parent_shift, mask;
1504 uint64_t incr, entry_end, pe_start;
1505 struct amdgpu_bo *pt;
1506
1507 if (!params->unlocked) {
1508 /* make sure that the page tables covering the
1509 * address range are actually allocated
1510 */
1511 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1512 &cursor, params->immediate);
1513 if (r)
1514 return r;
1515 }
1516
1517 shift = amdgpu_vm_level_shift(adev, cursor.level);
1518 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1519 if (params->unlocked) {
1520 /* Unlocked updates are only allowed on the leaves */
1521 if (amdgpu_vm_pt_descendant(adev, &cursor))
1522 continue;
1523 } else if (adev->asic_type < CHIP_VEGA10 &&
1524 (flags & AMDGPU_PTE_VALID)) {
1525 /* No huge page support before GMC v9 */
1526 if (cursor.level != AMDGPU_VM_PTB) {
1527 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1528 return -ENOENT;
1529 continue;
1530 }
1531 } else if (frag < shift) {
1532 /* We can't use this level when the fragment size is
1533 * smaller than the address shift. Go to the next
1534 * child entry and try again.
1535 */
1536 if (amdgpu_vm_pt_descendant(adev, &cursor))
1537 continue;
1538 } else if (frag >= parent_shift) {
1539 /* If the fragment size is even larger than the parent
1540 * shift we should go up one level and check it again.
1541 */
1542 if (!amdgpu_vm_pt_ancestor(&cursor))
1543 return -EINVAL;
1544 continue;
1545 }
1546
1547 pt = cursor.entry->bo;
1548 if (!pt) {
1549 /* We need all PDs and PTs for mapping something, */
1550 if (flags & AMDGPU_PTE_VALID)
1551 return -ENOENT;
1552
1553 /* but unmapping something can happen at a higher
1554 * level.
1555 */
1556 if (!amdgpu_vm_pt_ancestor(&cursor))
1557 return -EINVAL;
1558
1559 pt = cursor.entry->bo;
1560 shift = parent_shift;
1561 frag_end = max(frag_end, ALIGN(frag_start + 1,
1562 1ULL << shift));
1563 }
1564
1565 /* Looks good so far, calculate parameters for the update */
1566 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1567 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1568 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1569 entry_end = ((uint64_t)mask + 1) << shift;
1570 entry_end += cursor.pfn & ~(entry_end - 1);
1571 entry_end = min(entry_end, end);
1572
1573 do {
1574 struct amdgpu_vm *vm = params->vm;
1575 uint64_t upd_end = min(entry_end, frag_end);
1576 unsigned nptes = (upd_end - frag_start) >> shift;
1577 uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag);
1578
1579 /* This can happen when we set higher level PDs to
1580 * silent to stop fault floods.
1581 */
1582 nptes = max(nptes, 1u);
1583
1584 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1585 nptes, dst, incr, upd_flags,
1586 vm->task_info.pid,
1587 vm->immediate.fence_context);
1588 amdgpu_vm_update_flags(params, to_amdgpu_bo_vm(pt),
1589 cursor.level, pe_start, dst,
1590 nptes, incr, upd_flags);
1591
1592 pe_start += nptes * 8;
1593 dst += nptes * incr;
1594
1595 frag_start = upd_end;
1596 if (frag_start >= frag_end) {
1597 /* figure out the next fragment */
1598 amdgpu_vm_fragment(params, frag_start, end,
1599 flags, &frag, &frag_end);
1600 if (frag < shift)
1601 break;
1602 }
1603 } while (frag_start < entry_end);
1604
1605 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1606 /* Free all child entries.
1607 * Update the tables with the flags and addresses and free up subsequent
1608 * tables in the case of huge pages or freed up areas.
1609 * This is the maximum you can free, because all other page tables are not
1610 * completely covered by the range and so potentially still in use.
1611 */
1612 while (cursor.pfn < frag_start) {
1613 /* Make sure previous mapping is freed */
1614 if (cursor.entry->bo) {
1615 params->table_freed = true;
1616 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1617 }
1618 amdgpu_vm_pt_next(adev, &cursor);
1619 }
1620
1621 } else if (frag >= shift) {
1622 /* or just move on to the next on the same level. */
1623 amdgpu_vm_pt_next(adev, &cursor);
1624 }
1625 }
1626
1627 return 0;
1628}
1629
1630/**
1631 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1632 *
1633 * @adev: amdgpu_device pointer of the VM
1634 * @bo_adev: amdgpu_device pointer of the mapped BO
1635 * @vm: requested vm
1636 * @immediate: immediate submission in a page fault
1637 * @unlocked: unlocked invalidation during MM callback
1638 * @resv: fences we need to sync to
1639 * @start: start of mapped range
1640 * @last: last mapped entry
1641 * @flags: flags for the entries
1642 * @offset: offset into nodes and pages_addr
1643 * @res: ttm_resource to map
1644 * @pages_addr: DMA addresses to use for mapping
1645 * @fence: optional resulting fence
1646 * @table_freed: return true if page table is freed
1647 *
1648 * Fill in the page table entries between @start and @last.
1649 *
1650 * Returns:
1651 * 0 for success, -EINVAL for failure.
1652 */
1653int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1654 struct amdgpu_device *bo_adev,
1655 struct amdgpu_vm *vm, bool immediate,
1656 bool unlocked, struct dma_resv *resv,
1657 uint64_t start, uint64_t last,
1658 uint64_t flags, uint64_t offset,
1659 struct ttm_resource *res,
1660 dma_addr_t *pages_addr,
1661 struct dma_fence **fence,
1662 bool *table_freed)
1663{
1664 struct amdgpu_vm_update_params params;
1665 struct amdgpu_res_cursor cursor;
1666 enum amdgpu_sync_mode sync_mode;
1667 int r, idx;
1668
1669 if (!drm_dev_enter(&adev->ddev, &idx))
1670 return -ENODEV;
1671
1672 memset(¶ms, 0, sizeof(params));
1673 params.adev = adev;
1674 params.vm = vm;
1675 params.immediate = immediate;
1676 params.pages_addr = pages_addr;
1677 params.unlocked = unlocked;
1678
1679 /* Implicitly sync to command submissions in the same VM before
1680 * unmapping. Sync to moving fences before mapping.
1681 */
1682 if (!(flags & AMDGPU_PTE_VALID))
1683 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1684 else
1685 sync_mode = AMDGPU_SYNC_EXPLICIT;
1686
1687 amdgpu_vm_eviction_lock(vm);
1688 if (vm->evicting) {
1689 r = -EBUSY;
1690 goto error_unlock;
1691 }
1692
1693 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1694 struct dma_fence *tmp = dma_fence_get_stub();
1695
1696 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1697 swap(vm->last_unlocked, tmp);
1698 dma_fence_put(tmp);
1699 }
1700
1701 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1702 if (r)
1703 goto error_unlock;
1704
1705 amdgpu_res_first(pages_addr ? NULL : res, offset,
1706 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1707 while (cursor.remaining) {
1708 uint64_t tmp, num_entries, addr;
1709
1710 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1711 if (pages_addr) {
1712 bool contiguous = true;
1713
1714 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1715 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1716 uint64_t count;
1717
1718 contiguous = pages_addr[pfn + 1] ==
1719 pages_addr[pfn] + PAGE_SIZE;
1720
1721 tmp = num_entries /
1722 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1723 for (count = 2; count < tmp; ++count) {
1724 uint64_t idx = pfn + count;
1725
1726 if (contiguous != (pages_addr[idx] ==
1727 pages_addr[idx - 1] + PAGE_SIZE))
1728 break;
1729 }
1730 num_entries = count *
1731 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1732 }
1733
1734 if (!contiguous) {
1735 addr = cursor.start;
1736 params.pages_addr = pages_addr;
1737 } else {
1738 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1739 params.pages_addr = NULL;
1740 }
1741
1742 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1743 addr = bo_adev->vm_manager.vram_base_offset +
1744 cursor.start;
1745 } else {
1746 addr = 0;
1747 }
1748
1749 tmp = start + num_entries;
1750 r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags);
1751 if (r)
1752 goto error_unlock;
1753
1754 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1755 start = tmp;
1756 }
1757
1758 r = vm->update_funcs->commit(¶ms, fence);
1759
1760 if (table_freed)
1761 *table_freed = params.table_freed;
1762
1763error_unlock:
1764 amdgpu_vm_eviction_unlock(vm);
1765 drm_dev_exit(idx);
1766 return r;
1767}
1768
1769void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
1770 uint64_t *gtt_mem, uint64_t *cpu_mem)
1771{
1772 struct amdgpu_bo_va *bo_va, *tmp;
1773
1774 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
1775 if (!bo_va->base.bo)
1776 continue;
1777 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1778 gtt_mem, cpu_mem);
1779 }
1780 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
1781 if (!bo_va->base.bo)
1782 continue;
1783 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1784 gtt_mem, cpu_mem);
1785 }
1786 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
1787 if (!bo_va->base.bo)
1788 continue;
1789 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1790 gtt_mem, cpu_mem);
1791 }
1792 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1793 if (!bo_va->base.bo)
1794 continue;
1795 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1796 gtt_mem, cpu_mem);
1797 }
1798 spin_lock(&vm->invalidated_lock);
1799 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
1800 if (!bo_va->base.bo)
1801 continue;
1802 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1803 gtt_mem, cpu_mem);
1804 }
1805 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
1806 if (!bo_va->base.bo)
1807 continue;
1808 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1809 gtt_mem, cpu_mem);
1810 }
1811 spin_unlock(&vm->invalidated_lock);
1812}
1813/**
1814 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1815 *
1816 * @adev: amdgpu_device pointer
1817 * @bo_va: requested BO and VM object
1818 * @clear: if true clear the entries
1819 *
1820 * Fill in the page table entries for @bo_va.
1821 *
1822 * Returns:
1823 * 0 for success, -EINVAL for failure.
1824 */
1825int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1826 bool clear)
1827{
1828 struct amdgpu_bo *bo = bo_va->base.bo;
1829 struct amdgpu_vm *vm = bo_va->base.vm;
1830 struct amdgpu_bo_va_mapping *mapping;
1831 dma_addr_t *pages_addr = NULL;
1832 struct ttm_resource *mem;
1833 struct dma_fence **last_update;
1834 struct dma_resv *resv;
1835 uint64_t flags;
1836 struct amdgpu_device *bo_adev = adev;
1837 int r;
1838
1839 if (clear || !bo) {
1840 mem = NULL;
1841 resv = vm->root.bo->tbo.base.resv;
1842 } else {
1843 struct drm_gem_object *obj = &bo->tbo.base;
1844
1845 resv = bo->tbo.base.resv;
1846 if (obj->import_attach && bo_va->is_xgmi) {
1847 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1848 struct drm_gem_object *gobj = dma_buf->priv;
1849 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1850
1851 if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
1852 bo = gem_to_amdgpu_bo(gobj);
1853 }
1854 mem = bo->tbo.resource;
1855 if (mem->mem_type == TTM_PL_TT ||
1856 mem->mem_type == AMDGPU_PL_PREEMPT)
1857 pages_addr = bo->tbo.ttm->dma_address;
1858 }
1859
1860 if (bo) {
1861 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1862
1863 if (amdgpu_bo_encrypted(bo))
1864 flags |= AMDGPU_PTE_TMZ;
1865
1866 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1867 } else {
1868 flags = 0x0;
1869 }
1870
1871 if (clear || (bo && bo->tbo.base.resv ==
1872 vm->root.bo->tbo.base.resv))
1873 last_update = &vm->last_update;
1874 else
1875 last_update = &bo_va->last_pt_update;
1876
1877 if (!clear && bo_va->base.moved) {
1878 bo_va->base.moved = false;
1879 list_splice_init(&bo_va->valids, &bo_va->invalids);
1880
1881 } else if (bo_va->cleared != clear) {
1882 list_splice_init(&bo_va->valids, &bo_va->invalids);
1883 }
1884
1885 list_for_each_entry(mapping, &bo_va->invalids, list) {
1886 uint64_t update_flags = flags;
1887
1888 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1889 * but in case of something, we filter the flags in first place
1890 */
1891 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1892 update_flags &= ~AMDGPU_PTE_READABLE;
1893 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1894 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1895
1896 /* Apply ASIC specific mapping flags */
1897 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1898
1899 trace_amdgpu_vm_bo_update(mapping);
1900
1901 r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
1902 resv, mapping->start,
1903 mapping->last, update_flags,
1904 mapping->offset, mem,
1905 pages_addr, last_update, NULL);
1906 if (r)
1907 return r;
1908 }
1909
1910 /* If the BO is not in its preferred location add it back to
1911 * the evicted list so that it gets validated again on the
1912 * next command submission.
1913 */
1914 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1915 uint32_t mem_type = bo->tbo.resource->mem_type;
1916
1917 if (!(bo->preferred_domains &
1918 amdgpu_mem_type_to_domain(mem_type)))
1919 amdgpu_vm_bo_evicted(&bo_va->base);
1920 else
1921 amdgpu_vm_bo_idle(&bo_va->base);
1922 } else {
1923 amdgpu_vm_bo_done(&bo_va->base);
1924 }
1925
1926 list_splice_init(&bo_va->invalids, &bo_va->valids);
1927 bo_va->cleared = clear;
1928
1929 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1930 list_for_each_entry(mapping, &bo_va->valids, list)
1931 trace_amdgpu_vm_bo_mapping(mapping);
1932 }
1933
1934 return 0;
1935}
1936
1937/**
1938 * amdgpu_vm_update_prt_state - update the global PRT state
1939 *
1940 * @adev: amdgpu_device pointer
1941 */
1942static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1943{
1944 unsigned long flags;
1945 bool enable;
1946
1947 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1948 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1949 adev->gmc.gmc_funcs->set_prt(adev, enable);
1950 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1951}
1952
1953/**
1954 * amdgpu_vm_prt_get - add a PRT user
1955 *
1956 * @adev: amdgpu_device pointer
1957 */
1958static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1959{
1960 if (!adev->gmc.gmc_funcs->set_prt)
1961 return;
1962
1963 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1964 amdgpu_vm_update_prt_state(adev);
1965}
1966
1967/**
1968 * amdgpu_vm_prt_put - drop a PRT user
1969 *
1970 * @adev: amdgpu_device pointer
1971 */
1972static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1973{
1974 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1975 amdgpu_vm_update_prt_state(adev);
1976}
1977
1978/**
1979 * amdgpu_vm_prt_cb - callback for updating the PRT status
1980 *
1981 * @fence: fence for the callback
1982 * @_cb: the callback function
1983 */
1984static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1985{
1986 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1987
1988 amdgpu_vm_prt_put(cb->adev);
1989 kfree(cb);
1990}
1991
1992/**
1993 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1994 *
1995 * @adev: amdgpu_device pointer
1996 * @fence: fence for the callback
1997 */
1998static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1999 struct dma_fence *fence)
2000{
2001 struct amdgpu_prt_cb *cb;
2002
2003 if (!adev->gmc.gmc_funcs->set_prt)
2004 return;
2005
2006 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
2007 if (!cb) {
2008 /* Last resort when we are OOM */
2009 if (fence)
2010 dma_fence_wait(fence, false);
2011
2012 amdgpu_vm_prt_put(adev);
2013 } else {
2014 cb->adev = adev;
2015 if (!fence || dma_fence_add_callback(fence, &cb->cb,
2016 amdgpu_vm_prt_cb))
2017 amdgpu_vm_prt_cb(fence, &cb->cb);
2018 }
2019}
2020
2021/**
2022 * amdgpu_vm_free_mapping - free a mapping
2023 *
2024 * @adev: amdgpu_device pointer
2025 * @vm: requested vm
2026 * @mapping: mapping to be freed
2027 * @fence: fence of the unmap operation
2028 *
2029 * Free a mapping and make sure we decrease the PRT usage count if applicable.
2030 */
2031static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
2032 struct amdgpu_vm *vm,
2033 struct amdgpu_bo_va_mapping *mapping,
2034 struct dma_fence *fence)
2035{
2036 if (mapping->flags & AMDGPU_PTE_PRT)
2037 amdgpu_vm_add_prt_cb(adev, fence);
2038 kfree(mapping);
2039}
2040
2041/**
2042 * amdgpu_vm_prt_fini - finish all prt mappings
2043 *
2044 * @adev: amdgpu_device pointer
2045 * @vm: requested vm
2046 *
2047 * Register a cleanup callback to disable PRT support after VM dies.
2048 */
2049static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2050{
2051 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2052 struct dma_fence *excl, **shared;
2053 unsigned i, shared_count;
2054 int r;
2055
2056 r = dma_resv_get_fences(resv, &excl, &shared_count, &shared);
2057 if (r) {
2058 /* Not enough memory to grab the fence list, as last resort
2059 * block for all the fences to complete.
2060 */
2061 dma_resv_wait_timeout(resv, true, false,
2062 MAX_SCHEDULE_TIMEOUT);
2063 return;
2064 }
2065
2066 /* Add a callback for each fence in the reservation object */
2067 amdgpu_vm_prt_get(adev);
2068 amdgpu_vm_add_prt_cb(adev, excl);
2069
2070 for (i = 0; i < shared_count; ++i) {
2071 amdgpu_vm_prt_get(adev);
2072 amdgpu_vm_add_prt_cb(adev, shared[i]);
2073 }
2074
2075 kfree(shared);
2076}
2077
2078/**
2079 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2080 *
2081 * @adev: amdgpu_device pointer
2082 * @vm: requested vm
2083 * @fence: optional resulting fence (unchanged if no work needed to be done
2084 * or if an error occurred)
2085 *
2086 * Make sure all freed BOs are cleared in the PT.
2087 * PTs have to be reserved and mutex must be locked!
2088 *
2089 * Returns:
2090 * 0 for success.
2091 *
2092 */
2093int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2094 struct amdgpu_vm *vm,
2095 struct dma_fence **fence)
2096{
2097 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2098 struct amdgpu_bo_va_mapping *mapping;
2099 uint64_t init_pte_value = 0;
2100 struct dma_fence *f = NULL;
2101 int r;
2102
2103 while (!list_empty(&vm->freed)) {
2104 mapping = list_first_entry(&vm->freed,
2105 struct amdgpu_bo_va_mapping, list);
2106 list_del(&mapping->list);
2107
2108 if (vm->pte_support_ats &&
2109 mapping->start < AMDGPU_GMC_HOLE_START)
2110 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2111
2112 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
2113 resv, mapping->start,
2114 mapping->last, init_pte_value,
2115 0, NULL, NULL, &f, NULL);
2116 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2117 if (r) {
2118 dma_fence_put(f);
2119 return r;
2120 }
2121 }
2122
2123 if (fence && f) {
2124 dma_fence_put(*fence);
2125 *fence = f;
2126 } else {
2127 dma_fence_put(f);
2128 }
2129
2130 return 0;
2131
2132}
2133
2134/**
2135 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2136 *
2137 * @adev: amdgpu_device pointer
2138 * @vm: requested vm
2139 *
2140 * Make sure all BOs which are moved are updated in the PTs.
2141 *
2142 * Returns:
2143 * 0 for success.
2144 *
2145 * PTs have to be reserved!
2146 */
2147int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2148 struct amdgpu_vm *vm)
2149{
2150 struct amdgpu_bo_va *bo_va, *tmp;
2151 struct dma_resv *resv;
2152 bool clear;
2153 int r;
2154
2155 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2156 /* Per VM BOs never need to bo cleared in the page tables */
2157 r = amdgpu_vm_bo_update(adev, bo_va, false);
2158 if (r)
2159 return r;
2160 }
2161
2162 spin_lock(&vm->invalidated_lock);
2163 while (!list_empty(&vm->invalidated)) {
2164 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2165 base.vm_status);
2166 resv = bo_va->base.bo->tbo.base.resv;
2167 spin_unlock(&vm->invalidated_lock);
2168
2169 /* Try to reserve the BO to avoid clearing its ptes */
2170 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2171 clear = false;
2172 /* Somebody else is using the BO right now */
2173 else
2174 clear = true;
2175
2176 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2177 if (r)
2178 return r;
2179
2180 if (!clear)
2181 dma_resv_unlock(resv);
2182 spin_lock(&vm->invalidated_lock);
2183 }
2184 spin_unlock(&vm->invalidated_lock);
2185
2186 return 0;
2187}
2188
2189/**
2190 * amdgpu_vm_bo_add - add a bo to a specific vm
2191 *
2192 * @adev: amdgpu_device pointer
2193 * @vm: requested vm
2194 * @bo: amdgpu buffer object
2195 *
2196 * Add @bo into the requested vm.
2197 * Add @bo to the list of bos associated with the vm
2198 *
2199 * Returns:
2200 * Newly added bo_va or NULL for failure
2201 *
2202 * Object has to be reserved!
2203 */
2204struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2205 struct amdgpu_vm *vm,
2206 struct amdgpu_bo *bo)
2207{
2208 struct amdgpu_bo_va *bo_va;
2209
2210 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2211 if (bo_va == NULL) {
2212 return NULL;
2213 }
2214 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2215
2216 bo_va->ref_count = 1;
2217 INIT_LIST_HEAD(&bo_va->valids);
2218 INIT_LIST_HEAD(&bo_va->invalids);
2219
2220 if (!bo)
2221 return bo_va;
2222
2223 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
2224 bo_va->is_xgmi = true;
2225 /* Power up XGMI if it can be potentially used */
2226 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2227 }
2228
2229 return bo_va;
2230}
2231
2232
2233/**
2234 * amdgpu_vm_bo_insert_map - insert a new mapping
2235 *
2236 * @adev: amdgpu_device pointer
2237 * @bo_va: bo_va to store the address
2238 * @mapping: the mapping to insert
2239 *
2240 * Insert a new mapping into all structures.
2241 */
2242static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2243 struct amdgpu_bo_va *bo_va,
2244 struct amdgpu_bo_va_mapping *mapping)
2245{
2246 struct amdgpu_vm *vm = bo_va->base.vm;
2247 struct amdgpu_bo *bo = bo_va->base.bo;
2248
2249 mapping->bo_va = bo_va;
2250 list_add(&mapping->list, &bo_va->invalids);
2251 amdgpu_vm_it_insert(mapping, &vm->va);
2252
2253 if (mapping->flags & AMDGPU_PTE_PRT)
2254 amdgpu_vm_prt_get(adev);
2255
2256 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
2257 !bo_va->base.moved) {
2258 list_move(&bo_va->base.vm_status, &vm->moved);
2259 }
2260 trace_amdgpu_vm_bo_map(bo_va, mapping);
2261}
2262
2263/**
2264 * amdgpu_vm_bo_map - map bo inside a vm
2265 *
2266 * @adev: amdgpu_device pointer
2267 * @bo_va: bo_va to store the address
2268 * @saddr: where to map the BO
2269 * @offset: requested offset in the BO
2270 * @size: BO size in bytes
2271 * @flags: attributes of pages (read/write/valid/etc.)
2272 *
2273 * Add a mapping of the BO at the specefied addr into the VM.
2274 *
2275 * Returns:
2276 * 0 for success, error for failure.
2277 *
2278 * Object has to be reserved and unreserved outside!
2279 */
2280int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2281 struct amdgpu_bo_va *bo_va,
2282 uint64_t saddr, uint64_t offset,
2283 uint64_t size, uint64_t flags)
2284{
2285 struct amdgpu_bo_va_mapping *mapping, *tmp;
2286 struct amdgpu_bo *bo = bo_va->base.bo;
2287 struct amdgpu_vm *vm = bo_va->base.vm;
2288 uint64_t eaddr;
2289
2290 /* validate the parameters */
2291 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2292 size == 0 || size & ~PAGE_MASK)
2293 return -EINVAL;
2294
2295 /* make sure object fit at this offset */
2296 eaddr = saddr + size - 1;
2297 if (saddr >= eaddr ||
2298 (bo && offset + size > amdgpu_bo_size(bo)) ||
2299 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2300 return -EINVAL;
2301
2302 saddr /= AMDGPU_GPU_PAGE_SIZE;
2303 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2304
2305 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2306 if (tmp) {
2307 /* bo and tmp overlap, invalid addr */
2308 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2309 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2310 tmp->start, tmp->last + 1);
2311 return -EINVAL;
2312 }
2313
2314 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2315 if (!mapping)
2316 return -ENOMEM;
2317
2318 mapping->start = saddr;
2319 mapping->last = eaddr;
2320 mapping->offset = offset;
2321 mapping->flags = flags;
2322
2323 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2324
2325 return 0;
2326}
2327
2328/**
2329 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2330 *
2331 * @adev: amdgpu_device pointer
2332 * @bo_va: bo_va to store the address
2333 * @saddr: where to map the BO
2334 * @offset: requested offset in the BO
2335 * @size: BO size in bytes
2336 * @flags: attributes of pages (read/write/valid/etc.)
2337 *
2338 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2339 * mappings as we do so.
2340 *
2341 * Returns:
2342 * 0 for success, error for failure.
2343 *
2344 * Object has to be reserved and unreserved outside!
2345 */
2346int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2347 struct amdgpu_bo_va *bo_va,
2348 uint64_t saddr, uint64_t offset,
2349 uint64_t size, uint64_t flags)
2350{
2351 struct amdgpu_bo_va_mapping *mapping;
2352 struct amdgpu_bo *bo = bo_va->base.bo;
2353 uint64_t eaddr;
2354 int r;
2355
2356 /* validate the parameters */
2357 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2358 size == 0 || size & ~PAGE_MASK)
2359 return -EINVAL;
2360
2361 /* make sure object fit at this offset */
2362 eaddr = saddr + size - 1;
2363 if (saddr >= eaddr ||
2364 (bo && offset + size > amdgpu_bo_size(bo)) ||
2365 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2366 return -EINVAL;
2367
2368 /* Allocate all the needed memory */
2369 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2370 if (!mapping)
2371 return -ENOMEM;
2372
2373 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2374 if (r) {
2375 kfree(mapping);
2376 return r;
2377 }
2378
2379 saddr /= AMDGPU_GPU_PAGE_SIZE;
2380 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2381
2382 mapping->start = saddr;
2383 mapping->last = eaddr;
2384 mapping->offset = offset;
2385 mapping->flags = flags;
2386
2387 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2388
2389 return 0;
2390}
2391
2392/**
2393 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2394 *
2395 * @adev: amdgpu_device pointer
2396 * @bo_va: bo_va to remove the address from
2397 * @saddr: where to the BO is mapped
2398 *
2399 * Remove a mapping of the BO at the specefied addr from the VM.
2400 *
2401 * Returns:
2402 * 0 for success, error for failure.
2403 *
2404 * Object has to be reserved and unreserved outside!
2405 */
2406int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2407 struct amdgpu_bo_va *bo_va,
2408 uint64_t saddr)
2409{
2410 struct amdgpu_bo_va_mapping *mapping;
2411 struct amdgpu_vm *vm = bo_va->base.vm;
2412 bool valid = true;
2413
2414 saddr /= AMDGPU_GPU_PAGE_SIZE;
2415
2416 list_for_each_entry(mapping, &bo_va->valids, list) {
2417 if (mapping->start == saddr)
2418 break;
2419 }
2420
2421 if (&mapping->list == &bo_va->valids) {
2422 valid = false;
2423
2424 list_for_each_entry(mapping, &bo_va->invalids, list) {
2425 if (mapping->start == saddr)
2426 break;
2427 }
2428
2429 if (&mapping->list == &bo_va->invalids)
2430 return -ENOENT;
2431 }
2432
2433 list_del(&mapping->list);
2434 amdgpu_vm_it_remove(mapping, &vm->va);
2435 mapping->bo_va = NULL;
2436 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2437
2438 if (valid)
2439 list_add(&mapping->list, &vm->freed);
2440 else
2441 amdgpu_vm_free_mapping(adev, vm, mapping,
2442 bo_va->last_pt_update);
2443
2444 return 0;
2445}
2446
2447/**
2448 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2449 *
2450 * @adev: amdgpu_device pointer
2451 * @vm: VM structure to use
2452 * @saddr: start of the range
2453 * @size: size of the range
2454 *
2455 * Remove all mappings in a range, split them as appropriate.
2456 *
2457 * Returns:
2458 * 0 for success, error for failure.
2459 */
2460int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2461 struct amdgpu_vm *vm,
2462 uint64_t saddr, uint64_t size)
2463{
2464 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2465 LIST_HEAD(removed);
2466 uint64_t eaddr;
2467
2468 eaddr = saddr + size - 1;
2469 saddr /= AMDGPU_GPU_PAGE_SIZE;
2470 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2471
2472 /* Allocate all the needed memory */
2473 before = kzalloc(sizeof(*before), GFP_KERNEL);
2474 if (!before)
2475 return -ENOMEM;
2476 INIT_LIST_HEAD(&before->list);
2477
2478 after = kzalloc(sizeof(*after), GFP_KERNEL);
2479 if (!after) {
2480 kfree(before);
2481 return -ENOMEM;
2482 }
2483 INIT_LIST_HEAD(&after->list);
2484
2485 /* Now gather all removed mappings */
2486 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2487 while (tmp) {
2488 /* Remember mapping split at the start */
2489 if (tmp->start < saddr) {
2490 before->start = tmp->start;
2491 before->last = saddr - 1;
2492 before->offset = tmp->offset;
2493 before->flags = tmp->flags;
2494 before->bo_va = tmp->bo_va;
2495 list_add(&before->list, &tmp->bo_va->invalids);
2496 }
2497
2498 /* Remember mapping split at the end */
2499 if (tmp->last > eaddr) {
2500 after->start = eaddr + 1;
2501 after->last = tmp->last;
2502 after->offset = tmp->offset;
2503 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
2504 after->flags = tmp->flags;
2505 after->bo_va = tmp->bo_va;
2506 list_add(&after->list, &tmp->bo_va->invalids);
2507 }
2508
2509 list_del(&tmp->list);
2510 list_add(&tmp->list, &removed);
2511
2512 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2513 }
2514
2515 /* And free them up */
2516 list_for_each_entry_safe(tmp, next, &removed, list) {
2517 amdgpu_vm_it_remove(tmp, &vm->va);
2518 list_del(&tmp->list);
2519
2520 if (tmp->start < saddr)
2521 tmp->start = saddr;
2522 if (tmp->last > eaddr)
2523 tmp->last = eaddr;
2524
2525 tmp->bo_va = NULL;
2526 list_add(&tmp->list, &vm->freed);
2527 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2528 }
2529
2530 /* Insert partial mapping before the range */
2531 if (!list_empty(&before->list)) {
2532 amdgpu_vm_it_insert(before, &vm->va);
2533 if (before->flags & AMDGPU_PTE_PRT)
2534 amdgpu_vm_prt_get(adev);
2535 } else {
2536 kfree(before);
2537 }
2538
2539 /* Insert partial mapping after the range */
2540 if (!list_empty(&after->list)) {
2541 amdgpu_vm_it_insert(after, &vm->va);
2542 if (after->flags & AMDGPU_PTE_PRT)
2543 amdgpu_vm_prt_get(adev);
2544 } else {
2545 kfree(after);
2546 }
2547
2548 return 0;
2549}
2550
2551/**
2552 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2553 *
2554 * @vm: the requested VM
2555 * @addr: the address
2556 *
2557 * Find a mapping by it's address.
2558 *
2559 * Returns:
2560 * The amdgpu_bo_va_mapping matching for addr or NULL
2561 *
2562 */
2563struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2564 uint64_t addr)
2565{
2566 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2567}
2568
2569/**
2570 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2571 *
2572 * @vm: the requested vm
2573 * @ticket: CS ticket
2574 *
2575 * Trace all mappings of BOs reserved during a command submission.
2576 */
2577void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2578{
2579 struct amdgpu_bo_va_mapping *mapping;
2580
2581 if (!trace_amdgpu_vm_bo_cs_enabled())
2582 return;
2583
2584 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2585 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2586 if (mapping->bo_va && mapping->bo_va->base.bo) {
2587 struct amdgpu_bo *bo;
2588
2589 bo = mapping->bo_va->base.bo;
2590 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2591 ticket)
2592 continue;
2593 }
2594
2595 trace_amdgpu_vm_bo_cs(mapping);
2596 }
2597}
2598
2599/**
2600 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2601 *
2602 * @adev: amdgpu_device pointer
2603 * @bo_va: requested bo_va
2604 *
2605 * Remove @bo_va->bo from the requested vm.
2606 *
2607 * Object have to be reserved!
2608 */
2609void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2610 struct amdgpu_bo_va *bo_va)
2611{
2612 struct amdgpu_bo_va_mapping *mapping, *next;
2613 struct amdgpu_bo *bo = bo_va->base.bo;
2614 struct amdgpu_vm *vm = bo_va->base.vm;
2615 struct amdgpu_vm_bo_base **base;
2616
2617 if (bo) {
2618 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2619 vm->bulk_moveable = false;
2620
2621 for (base = &bo_va->base.bo->vm_bo; *base;
2622 base = &(*base)->next) {
2623 if (*base != &bo_va->base)
2624 continue;
2625
2626 *base = bo_va->base.next;
2627 break;
2628 }
2629 }
2630
2631 spin_lock(&vm->invalidated_lock);
2632 list_del(&bo_va->base.vm_status);
2633 spin_unlock(&vm->invalidated_lock);
2634
2635 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2636 list_del(&mapping->list);
2637 amdgpu_vm_it_remove(mapping, &vm->va);
2638 mapping->bo_va = NULL;
2639 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2640 list_add(&mapping->list, &vm->freed);
2641 }
2642 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2643 list_del(&mapping->list);
2644 amdgpu_vm_it_remove(mapping, &vm->va);
2645 amdgpu_vm_free_mapping(adev, vm, mapping,
2646 bo_va->last_pt_update);
2647 }
2648
2649 dma_fence_put(bo_va->last_pt_update);
2650
2651 if (bo && bo_va->is_xgmi)
2652 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2653
2654 kfree(bo_va);
2655}
2656
2657/**
2658 * amdgpu_vm_evictable - check if we can evict a VM
2659 *
2660 * @bo: A page table of the VM.
2661 *
2662 * Check if it is possible to evict a VM.
2663 */
2664bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2665{
2666 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2667
2668 /* Page tables of a destroyed VM can go away immediately */
2669 if (!bo_base || !bo_base->vm)
2670 return true;
2671
2672 /* Don't evict VM page tables while they are busy */
2673 if (!dma_resv_test_signaled(bo->tbo.base.resv, true))
2674 return false;
2675
2676 /* Try to block ongoing updates */
2677 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2678 return false;
2679
2680 /* Don't evict VM page tables while they are updated */
2681 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2682 amdgpu_vm_eviction_unlock(bo_base->vm);
2683 return false;
2684 }
2685
2686 bo_base->vm->evicting = true;
2687 amdgpu_vm_eviction_unlock(bo_base->vm);
2688 return true;
2689}
2690
2691/**
2692 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2693 *
2694 * @adev: amdgpu_device pointer
2695 * @bo: amdgpu buffer object
2696 * @evicted: is the BO evicted
2697 *
2698 * Mark @bo as invalid.
2699 */
2700void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2701 struct amdgpu_bo *bo, bool evicted)
2702{
2703 struct amdgpu_vm_bo_base *bo_base;
2704
2705 /* shadow bo doesn't have bo base, its validation needs its parent */
2706 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2707 bo = bo->parent;
2708
2709 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2710 struct amdgpu_vm *vm = bo_base->vm;
2711
2712 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2713 amdgpu_vm_bo_evicted(bo_base);
2714 continue;
2715 }
2716
2717 if (bo_base->moved)
2718 continue;
2719 bo_base->moved = true;
2720
2721 if (bo->tbo.type == ttm_bo_type_kernel)
2722 amdgpu_vm_bo_relocated(bo_base);
2723 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2724 amdgpu_vm_bo_moved(bo_base);
2725 else
2726 amdgpu_vm_bo_invalidated(bo_base);
2727 }
2728}
2729
2730/**
2731 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2732 *
2733 * @vm_size: VM size
2734 *
2735 * Returns:
2736 * VM page table as power of two
2737 */
2738static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2739{
2740 /* Total bits covered by PD + PTs */
2741 unsigned bits = ilog2(vm_size) + 18;
2742
2743 /* Make sure the PD is 4K in size up to 8GB address space.
2744 Above that split equal between PD and PTs */
2745 if (vm_size <= 8)
2746 return (bits - 9);
2747 else
2748 return ((bits + 3) / 2);
2749}
2750
2751/**
2752 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2753 *
2754 * @adev: amdgpu_device pointer
2755 * @min_vm_size: the minimum vm size in GB if it's set auto
2756 * @fragment_size_default: Default PTE fragment size
2757 * @max_level: max VMPT level
2758 * @max_bits: max address space size in bits
2759 *
2760 */
2761void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2762 uint32_t fragment_size_default, unsigned max_level,
2763 unsigned max_bits)
2764{
2765 unsigned int max_size = 1 << (max_bits - 30);
2766 unsigned int vm_size;
2767 uint64_t tmp;
2768
2769 /* adjust vm size first */
2770 if (amdgpu_vm_size != -1) {
2771 vm_size = amdgpu_vm_size;
2772 if (vm_size > max_size) {
2773 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2774 amdgpu_vm_size, max_size);
2775 vm_size = max_size;
2776 }
2777 } else {
2778 struct sysinfo si;
2779 unsigned int phys_ram_gb;
2780
2781 /* Optimal VM size depends on the amount of physical
2782 * RAM available. Underlying requirements and
2783 * assumptions:
2784 *
2785 * - Need to map system memory and VRAM from all GPUs
2786 * - VRAM from other GPUs not known here
2787 * - Assume VRAM <= system memory
2788 * - On GFX8 and older, VM space can be segmented for
2789 * different MTYPEs
2790 * - Need to allow room for fragmentation, guard pages etc.
2791 *
2792 * This adds up to a rough guess of system memory x3.
2793 * Round up to power of two to maximize the available
2794 * VM size with the given page table size.
2795 */
2796 si_meminfo(&si);
2797 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2798 (1 << 30) - 1) >> 30;
2799 vm_size = roundup_pow_of_two(
2800 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2801 }
2802
2803 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2804
2805 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2806 if (amdgpu_vm_block_size != -1)
2807 tmp >>= amdgpu_vm_block_size - 9;
2808 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2809 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2810 switch (adev->vm_manager.num_level) {
2811 case 3:
2812 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2813 break;
2814 case 2:
2815 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2816 break;
2817 case 1:
2818 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2819 break;
2820 default:
2821 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2822 }
2823 /* block size depends on vm size and hw setup*/
2824 if (amdgpu_vm_block_size != -1)
2825 adev->vm_manager.block_size =
2826 min((unsigned)amdgpu_vm_block_size, max_bits
2827 - AMDGPU_GPU_PAGE_SHIFT
2828 - 9 * adev->vm_manager.num_level);
2829 else if (adev->vm_manager.num_level > 1)
2830 adev->vm_manager.block_size = 9;
2831 else
2832 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2833
2834 if (amdgpu_vm_fragment_size == -1)
2835 adev->vm_manager.fragment_size = fragment_size_default;
2836 else
2837 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2838
2839 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2840 vm_size, adev->vm_manager.num_level + 1,
2841 adev->vm_manager.block_size,
2842 adev->vm_manager.fragment_size);
2843}
2844
2845/**
2846 * amdgpu_vm_wait_idle - wait for the VM to become idle
2847 *
2848 * @vm: VM object to wait for
2849 * @timeout: timeout to wait for VM to become idle
2850 */
2851long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2852{
2853 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, true,
2854 true, timeout);
2855 if (timeout <= 0)
2856 return timeout;
2857
2858 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2859}
2860
2861/**
2862 * amdgpu_vm_init - initialize a vm instance
2863 *
2864 * @adev: amdgpu_device pointer
2865 * @vm: requested vm
2866 * @pasid: Process address space identifier
2867 *
2868 * Init @vm fields.
2869 *
2870 * Returns:
2871 * 0 for success, error for failure.
2872 */
2873int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
2874{
2875 struct amdgpu_bo *root_bo;
2876 struct amdgpu_bo_vm *root;
2877 int r, i;
2878
2879 vm->va = RB_ROOT_CACHED;
2880 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2881 vm->reserved_vmid[i] = NULL;
2882 INIT_LIST_HEAD(&vm->evicted);
2883 INIT_LIST_HEAD(&vm->relocated);
2884 INIT_LIST_HEAD(&vm->moved);
2885 INIT_LIST_HEAD(&vm->idle);
2886 INIT_LIST_HEAD(&vm->invalidated);
2887 spin_lock_init(&vm->invalidated_lock);
2888 INIT_LIST_HEAD(&vm->freed);
2889 INIT_LIST_HEAD(&vm->done);
2890
2891 /* create scheduler entities for page table updates */
2892 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2893 adev->vm_manager.vm_pte_scheds,
2894 adev->vm_manager.vm_pte_num_scheds, NULL);
2895 if (r)
2896 return r;
2897
2898 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2899 adev->vm_manager.vm_pte_scheds,
2900 adev->vm_manager.vm_pte_num_scheds, NULL);
2901 if (r)
2902 goto error_free_immediate;
2903
2904 vm->pte_support_ats = false;
2905 vm->is_compute_context = false;
2906
2907 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2908 AMDGPU_VM_USE_CPU_FOR_GFX);
2909
2910 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2911 vm->use_cpu_for_update ? "CPU" : "SDMA");
2912 WARN_ONCE((vm->use_cpu_for_update &&
2913 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2914 "CPU update of VM recommended only for large BAR system\n");
2915
2916 if (vm->use_cpu_for_update)
2917 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2918 else
2919 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2920 vm->last_update = NULL;
2921 vm->last_unlocked = dma_fence_get_stub();
2922
2923 mutex_init(&vm->eviction_lock);
2924 vm->evicting = false;
2925
2926 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2927 false, &root);
2928 if (r)
2929 goto error_free_delayed;
2930 root_bo = &root->bo;
2931 r = amdgpu_bo_reserve(root_bo, true);
2932 if (r)
2933 goto error_free_root;
2934
2935 r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1);
2936 if (r)
2937 goto error_unreserve;
2938
2939 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2940
2941 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2942 if (r)
2943 goto error_unreserve;
2944
2945 amdgpu_bo_unreserve(vm->root.bo);
2946
2947 if (pasid) {
2948 unsigned long flags;
2949
2950 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2951 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2952 GFP_ATOMIC);
2953 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2954 if (r < 0)
2955 goto error_free_root;
2956
2957 vm->pasid = pasid;
2958 }
2959
2960 INIT_KFIFO(vm->faults);
2961
2962 return 0;
2963
2964error_unreserve:
2965 amdgpu_bo_unreserve(vm->root.bo);
2966
2967error_free_root:
2968 amdgpu_bo_unref(&root->shadow);
2969 amdgpu_bo_unref(&root_bo);
2970 vm->root.bo = NULL;
2971
2972error_free_delayed:
2973 dma_fence_put(vm->last_unlocked);
2974 drm_sched_entity_destroy(&vm->delayed);
2975
2976error_free_immediate:
2977 drm_sched_entity_destroy(&vm->immediate);
2978
2979 return r;
2980}
2981
2982/**
2983 * amdgpu_vm_check_clean_reserved - check if a VM is clean
2984 *
2985 * @adev: amdgpu_device pointer
2986 * @vm: the VM to check
2987 *
2988 * check all entries of the root PD, if any subsequent PDs are allocated,
2989 * it means there are page table creating and filling, and is no a clean
2990 * VM
2991 *
2992 * Returns:
2993 * 0 if this VM is clean
2994 */
2995static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2996 struct amdgpu_vm *vm)
2997{
2998 enum amdgpu_vm_level root = adev->vm_manager.root_level;
2999 unsigned int entries = amdgpu_vm_num_entries(adev, root);
3000 unsigned int i = 0;
3001
3002 for (i = 0; i < entries; i++) {
3003 if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
3004 return -EINVAL;
3005 }
3006
3007 return 0;
3008}
3009
3010/**
3011 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
3012 *
3013 * @adev: amdgpu_device pointer
3014 * @vm: requested vm
3015 * @pasid: pasid to use
3016 *
3017 * This only works on GFX VMs that don't have any BOs added and no
3018 * page tables allocated yet.
3019 *
3020 * Changes the following VM parameters:
3021 * - use_cpu_for_update
3022 * - pte_supports_ats
3023 * - pasid (old PASID is released, because compute manages its own PASIDs)
3024 *
3025 * Reinitializes the page directory to reflect the changed ATS
3026 * setting.
3027 *
3028 * Returns:
3029 * 0 for success, -errno for errors.
3030 */
3031int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
3032 u32 pasid)
3033{
3034 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3035 int r;
3036
3037 r = amdgpu_bo_reserve(vm->root.bo, true);
3038 if (r)
3039 return r;
3040
3041 /* Sanity checks */
3042 r = amdgpu_vm_check_clean_reserved(adev, vm);
3043 if (r)
3044 goto unreserve_bo;
3045
3046 if (pasid) {
3047 unsigned long flags;
3048
3049 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3050 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3051 GFP_ATOMIC);
3052 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3053
3054 if (r == -ENOSPC)
3055 goto unreserve_bo;
3056 r = 0;
3057 }
3058
3059 /* Check if PD needs to be reinitialized and do it before
3060 * changing any other state, in case it fails.
3061 */
3062 if (pte_support_ats != vm->pte_support_ats) {
3063 vm->pte_support_ats = pte_support_ats;
3064 r = amdgpu_vm_clear_bo(adev, vm,
3065 to_amdgpu_bo_vm(vm->root.bo),
3066 false);
3067 if (r)
3068 goto free_idr;
3069 }
3070
3071 /* Update VM state */
3072 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3073 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3074 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3075 vm->use_cpu_for_update ? "CPU" : "SDMA");
3076 WARN_ONCE((vm->use_cpu_for_update &&
3077 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3078 "CPU update of VM recommended only for large BAR system\n");
3079
3080 if (vm->use_cpu_for_update) {
3081 /* Sync with last SDMA update/clear before switching to CPU */
3082 r = amdgpu_bo_sync_wait(vm->root.bo,
3083 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3084 if (r)
3085 goto free_idr;
3086
3087 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3088 } else {
3089 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3090 }
3091 dma_fence_put(vm->last_update);
3092 vm->last_update = NULL;
3093 vm->is_compute_context = true;
3094
3095 if (vm->pasid) {
3096 unsigned long flags;
3097
3098 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3099 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3100 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3101
3102 /* Free the original amdgpu allocated pasid
3103 * Will be replaced with kfd allocated pasid
3104 */
3105 amdgpu_pasid_free(vm->pasid);
3106 vm->pasid = 0;
3107 }
3108
3109 /* Free the shadow bo for compute VM */
3110 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
3111
3112 if (pasid)
3113 vm->pasid = pasid;
3114
3115 goto unreserve_bo;
3116
3117free_idr:
3118 if (pasid) {
3119 unsigned long flags;
3120
3121 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3122 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3123 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3124 }
3125unreserve_bo:
3126 amdgpu_bo_unreserve(vm->root.bo);
3127 return r;
3128}
3129
3130/**
3131 * amdgpu_vm_release_compute - release a compute vm
3132 * @adev: amdgpu_device pointer
3133 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3134 *
3135 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3136 * pasid from vm. Compute should stop use of vm after this call.
3137 */
3138void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3139{
3140 if (vm->pasid) {
3141 unsigned long flags;
3142
3143 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3144 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3145 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3146 }
3147 vm->pasid = 0;
3148 vm->is_compute_context = false;
3149}
3150
3151/**
3152 * amdgpu_vm_fini - tear down a vm instance
3153 *
3154 * @adev: amdgpu_device pointer
3155 * @vm: requested vm
3156 *
3157 * Tear down @vm.
3158 * Unbind the VM and remove all bos from the vm bo list
3159 */
3160void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3161{
3162 struct amdgpu_bo_va_mapping *mapping, *tmp;
3163 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3164 struct amdgpu_bo *root;
3165 int i;
3166
3167 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3168
3169 root = amdgpu_bo_ref(vm->root.bo);
3170 amdgpu_bo_reserve(root, true);
3171 if (vm->pasid) {
3172 unsigned long flags;
3173
3174 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3175 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3176 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3177 vm->pasid = 0;
3178 }
3179
3180 dma_fence_wait(vm->last_unlocked, false);
3181 dma_fence_put(vm->last_unlocked);
3182
3183 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3184 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3185 amdgpu_vm_prt_fini(adev, vm);
3186 prt_fini_needed = false;
3187 }
3188
3189 list_del(&mapping->list);
3190 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3191 }
3192
3193 amdgpu_vm_free_pts(adev, vm, NULL);
3194 amdgpu_bo_unreserve(root);
3195 amdgpu_bo_unref(&root);
3196 WARN_ON(vm->root.bo);
3197
3198 drm_sched_entity_destroy(&vm->immediate);
3199 drm_sched_entity_destroy(&vm->delayed);
3200
3201 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3202 dev_err(adev->dev, "still active bo inside vm\n");
3203 }
3204 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3205 &vm->va.rb_root, rb) {
3206 /* Don't remove the mapping here, we don't want to trigger a
3207 * rebalance and the tree is about to be destroyed anyway.
3208 */
3209 list_del(&mapping->list);
3210 kfree(mapping);
3211 }
3212
3213 dma_fence_put(vm->last_update);
3214 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3215 amdgpu_vmid_free_reserved(adev, vm, i);
3216}
3217
3218/**
3219 * amdgpu_vm_manager_init - init the VM manager
3220 *
3221 * @adev: amdgpu_device pointer
3222 *
3223 * Initialize the VM manager structures
3224 */
3225void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3226{
3227 unsigned i;
3228
3229 /* Concurrent flushes are only possible starting with Vega10 and
3230 * are broken on Navi10 and Navi14.
3231 */
3232 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
3233 adev->asic_type == CHIP_NAVI10 ||
3234 adev->asic_type == CHIP_NAVI14);
3235 amdgpu_vmid_mgr_init(adev);
3236
3237 adev->vm_manager.fence_context =
3238 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3239 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3240 adev->vm_manager.seqno[i] = 0;
3241
3242 spin_lock_init(&adev->vm_manager.prt_lock);
3243 atomic_set(&adev->vm_manager.num_prt_users, 0);
3244
3245 /* If not overridden by the user, by default, only in large BAR systems
3246 * Compute VM tables will be updated by CPU
3247 */
3248#ifdef CONFIG_X86_64
3249 if (amdgpu_vm_update_mode == -1) {
3250 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3251 adev->vm_manager.vm_update_mode =
3252 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3253 else
3254 adev->vm_manager.vm_update_mode = 0;
3255 } else
3256 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3257#else
3258 adev->vm_manager.vm_update_mode = 0;
3259#endif
3260
3261 idr_init(&adev->vm_manager.pasid_idr);
3262 spin_lock_init(&adev->vm_manager.pasid_lock);
3263}
3264
3265/**
3266 * amdgpu_vm_manager_fini - cleanup VM manager
3267 *
3268 * @adev: amdgpu_device pointer
3269 *
3270 * Cleanup the VM manager and free resources.
3271 */
3272void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3273{
3274 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3275 idr_destroy(&adev->vm_manager.pasid_idr);
3276
3277 amdgpu_vmid_mgr_fini(adev);
3278}
3279
3280/**
3281 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3282 *
3283 * @dev: drm device pointer
3284 * @data: drm_amdgpu_vm
3285 * @filp: drm file pointer
3286 *
3287 * Returns:
3288 * 0 for success, -errno for errors.
3289 */
3290int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3291{
3292 union drm_amdgpu_vm *args = data;
3293 struct amdgpu_device *adev = drm_to_adev(dev);
3294 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3295 long timeout = msecs_to_jiffies(2000);
3296 int r;
3297
3298 switch (args->in.op) {
3299 case AMDGPU_VM_OP_RESERVE_VMID:
3300 /* We only have requirement to reserve vmid from gfxhub */
3301 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3302 AMDGPU_GFXHUB_0);
3303 if (r)
3304 return r;
3305 break;
3306 case AMDGPU_VM_OP_UNRESERVE_VMID:
3307 if (amdgpu_sriov_runtime(adev))
3308 timeout = 8 * timeout;
3309
3310 /* Wait vm idle to make sure the vmid set in SPM_VMID is
3311 * not referenced anymore.
3312 */
3313 r = amdgpu_bo_reserve(fpriv->vm.root.bo, true);
3314 if (r)
3315 return r;
3316
3317 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3318 if (r < 0)
3319 return r;
3320
3321 amdgpu_bo_unreserve(fpriv->vm.root.bo);
3322 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3323 break;
3324 default:
3325 return -EINVAL;
3326 }
3327
3328 return 0;
3329}
3330
3331/**
3332 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3333 *
3334 * @adev: drm device pointer
3335 * @pasid: PASID identifier for VM
3336 * @task_info: task_info to fill.
3337 */
3338void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
3339 struct amdgpu_task_info *task_info)
3340{
3341 struct amdgpu_vm *vm;
3342 unsigned long flags;
3343
3344 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3345
3346 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3347 if (vm)
3348 *task_info = vm->task_info;
3349
3350 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3351}
3352
3353/**
3354 * amdgpu_vm_set_task_info - Sets VMs task info.
3355 *
3356 * @vm: vm for which to set the info
3357 */
3358void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3359{
3360 if (vm->task_info.pid)
3361 return;
3362
3363 vm->task_info.pid = current->pid;
3364 get_task_comm(vm->task_info.task_name, current);
3365
3366 if (current->group_leader->mm != current->mm)
3367 return;
3368
3369 vm->task_info.tgid = current->group_leader->pid;
3370 get_task_comm(vm->task_info.process_name, current->group_leader);
3371}
3372
3373/**
3374 * amdgpu_vm_handle_fault - graceful handling of VM faults.
3375 * @adev: amdgpu device pointer
3376 * @pasid: PASID of the VM
3377 * @addr: Address of the fault
3378 *
3379 * Try to gracefully handle a VM fault. Return true if the fault was handled and
3380 * shouldn't be reported any more.
3381 */
3382bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
3383 uint64_t addr)
3384{
3385 bool is_compute_context = false;
3386 struct amdgpu_bo *root;
3387 unsigned long irqflags;
3388 uint64_t value, flags;
3389 struct amdgpu_vm *vm;
3390 int r;
3391
3392 spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
3393 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3394 if (vm) {
3395 root = amdgpu_bo_ref(vm->root.bo);
3396 is_compute_context = vm->is_compute_context;
3397 } else {
3398 root = NULL;
3399 }
3400 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
3401
3402 if (!root)
3403 return false;
3404
3405 addr /= AMDGPU_GPU_PAGE_SIZE;
3406
3407 if (is_compute_context &&
3408 !svm_range_restore_pages(adev, pasid, addr)) {
3409 amdgpu_bo_unref(&root);
3410 return true;
3411 }
3412
3413 r = amdgpu_bo_reserve(root, true);
3414 if (r)
3415 goto error_unref;
3416
3417 /* Double check that the VM still exists */
3418 spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
3419 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3420 if (vm && vm->root.bo != root)
3421 vm = NULL;
3422 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
3423 if (!vm)
3424 goto error_unlock;
3425
3426 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3427 AMDGPU_PTE_SYSTEM;
3428
3429 if (is_compute_context) {
3430 /* Intentionally setting invalid PTE flag
3431 * combination to force a no-retry-fault
3432 */
3433 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3434 AMDGPU_PTE_TF;
3435 value = 0;
3436 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3437 /* Redirect the access to the dummy page */
3438 value = adev->dummy_page_addr;
3439 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3440 AMDGPU_PTE_WRITEABLE;
3441
3442 } else {
3443 /* Let the hw retry silently on the PTE */
3444 value = 0;
3445 }
3446
3447 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3448 if (r) {
3449 pr_debug("failed %d to reserve fence slot\n", r);
3450 goto error_unlock;
3451 }
3452
3453 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3454 addr, flags, value, NULL, NULL, NULL,
3455 NULL);
3456 if (r)
3457 goto error_unlock;
3458
3459 r = amdgpu_vm_update_pdes(adev, vm, true);
3460
3461error_unlock:
3462 amdgpu_bo_unreserve(root);
3463 if (r < 0)
3464 DRM_ERROR("Can't handle page fault (%d)\n", r);
3465
3466error_unref:
3467 amdgpu_bo_unref(&root);
3468
3469 return false;
3470}
3471
3472#if defined(CONFIG_DEBUG_FS)
3473/**
3474 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
3475 *
3476 * @vm: Requested VM for printing BO info
3477 * @m: debugfs file
3478 *
3479 * Print BO information in debugfs file for the VM
3480 */
3481void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
3482{
3483 struct amdgpu_bo_va *bo_va, *tmp;
3484 u64 total_idle = 0;
3485 u64 total_evicted = 0;
3486 u64 total_relocated = 0;
3487 u64 total_moved = 0;
3488 u64 total_invalidated = 0;
3489 u64 total_done = 0;
3490 unsigned int total_idle_objs = 0;
3491 unsigned int total_evicted_objs = 0;
3492 unsigned int total_relocated_objs = 0;
3493 unsigned int total_moved_objs = 0;
3494 unsigned int total_invalidated_objs = 0;
3495 unsigned int total_done_objs = 0;
3496 unsigned int id = 0;
3497
3498 seq_puts(m, "\tIdle BOs:\n");
3499 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
3500 if (!bo_va->base.bo)
3501 continue;
3502 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3503 }
3504 total_idle_objs = id;
3505 id = 0;
3506
3507 seq_puts(m, "\tEvicted BOs:\n");
3508 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
3509 if (!bo_va->base.bo)
3510 continue;
3511 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3512 }
3513 total_evicted_objs = id;
3514 id = 0;
3515
3516 seq_puts(m, "\tRelocated BOs:\n");
3517 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
3518 if (!bo_va->base.bo)
3519 continue;
3520 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3521 }
3522 total_relocated_objs = id;
3523 id = 0;
3524
3525 seq_puts(m, "\tMoved BOs:\n");
3526 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
3527 if (!bo_va->base.bo)
3528 continue;
3529 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3530 }
3531 total_moved_objs = id;
3532 id = 0;
3533
3534 seq_puts(m, "\tInvalidated BOs:\n");
3535 spin_lock(&vm->invalidated_lock);
3536 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
3537 if (!bo_va->base.bo)
3538 continue;
3539 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3540 }
3541 total_invalidated_objs = id;
3542 id = 0;
3543
3544 seq_puts(m, "\tDone BOs:\n");
3545 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
3546 if (!bo_va->base.bo)
3547 continue;
3548 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3549 }
3550 spin_unlock(&vm->invalidated_lock);
3551 total_done_objs = id;
3552
3553 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
3554 total_idle_objs);
3555 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
3556 total_evicted_objs);
3557 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
3558 total_relocated_objs);
3559 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
3560 total_moved_objs);
3561 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
3562 total_invalidated_objs);
3563 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
3564 total_done_objs);
3565}
3566#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include <drm/ttm/ttm_tt.h>
37#include <drm/drm_exec.h>
38#include "amdgpu.h"
39#include "amdgpu_trace.h"
40#include "amdgpu_amdkfd.h"
41#include "amdgpu_gmc.h"
42#include "amdgpu_xgmi.h"
43#include "amdgpu_dma_buf.h"
44#include "amdgpu_res_cursor.h"
45#include "kfd_svm.h"
46
47/**
48 * DOC: GPUVM
49 *
50 * GPUVM is the MMU functionality provided on the GPU.
51 * GPUVM is similar to the legacy GART on older asics, however
52 * rather than there being a single global GART table
53 * for the entire GPU, there can be multiple GPUVM page tables active
54 * at any given time. The GPUVM page tables can contain a mix
55 * VRAM pages and system pages (both memory and MMIO) and system pages
56 * can be mapped as snooped (cached system pages) or unsnooped
57 * (uncached system pages).
58 *
59 * Each active GPUVM has an ID associated with it and there is a page table
60 * linked with each VMID. When executing a command buffer,
61 * the kernel tells the engine what VMID to use for that command
62 * buffer. VMIDs are allocated dynamically as commands are submitted.
63 * The userspace drivers maintain their own address space and the kernel
64 * sets up their pages tables accordingly when they submit their
65 * command buffers and a VMID is assigned.
66 * The hardware supports up to 16 active GPUVMs at any given time.
67 *
68 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69 * on the ASIC family. GPUVM supports RWX attributes on each page as well
70 * as other features such as encryption and caching attributes.
71 *
72 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
73 * addition to an aperture managed by a page table, VMID 0 also has
74 * several other apertures. There is an aperture for direct access to VRAM
75 * and there is a legacy AGP aperture which just forwards accesses directly
76 * to the matching system physical addresses (or IOVAs when an IOMMU is
77 * present). These apertures provide direct access to these memories without
78 * incurring the overhead of a page table. VMID 0 is used by the kernel
79 * driver for tasks like memory management.
80 *
81 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82 * For user applications, each application can have their own unique GPUVM
83 * address space. The application manages the address space and the kernel
84 * driver manages the GPUVM page tables for each process. If an GPU client
85 * accesses an invalid page, it will generate a GPU page fault, similar to
86 * accessing an invalid page on a CPU.
87 */
88
89#define START(node) ((node)->start)
90#define LAST(node) ((node)->last)
91
92INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 START, LAST, static, amdgpu_vm_it)
94
95#undef START
96#undef LAST
97
98/**
99 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
100 */
101struct amdgpu_prt_cb {
102
103 /**
104 * @adev: amdgpu device
105 */
106 struct amdgpu_device *adev;
107
108 /**
109 * @cb: callback
110 */
111 struct dma_fence_cb cb;
112};
113
114/**
115 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
116 */
117struct amdgpu_vm_tlb_seq_struct {
118 /**
119 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
120 */
121 struct amdgpu_vm *vm;
122
123 /**
124 * @cb: callback
125 */
126 struct dma_fence_cb cb;
127};
128
129/**
130 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
131 *
132 * @adev: amdgpu_device pointer
133 * @vm: amdgpu_vm pointer
134 * @pasid: the pasid the VM is using on this GPU
135 *
136 * Set the pasid this VM is using on this GPU, can also be used to remove the
137 * pasid by passing in zero.
138 *
139 */
140int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
141 u32 pasid)
142{
143 int r;
144
145 if (vm->pasid == pasid)
146 return 0;
147
148 if (vm->pasid) {
149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
150 if (r < 0)
151 return r;
152
153 vm->pasid = 0;
154 }
155
156 if (pasid) {
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
158 GFP_KERNEL));
159 if (r < 0)
160 return r;
161
162 vm->pasid = pasid;
163 }
164
165
166 return 0;
167}
168
169/**
170 * amdgpu_vm_bo_evicted - vm_bo is evicted
171 *
172 * @vm_bo: vm_bo which is evicted
173 *
174 * State for PDs/PTs and per VM BOs which are not at the location they should
175 * be.
176 */
177static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
178{
179 struct amdgpu_vm *vm = vm_bo->vm;
180 struct amdgpu_bo *bo = vm_bo->bo;
181
182 vm_bo->moved = true;
183 spin_lock(&vm_bo->vm->status_lock);
184 if (bo->tbo.type == ttm_bo_type_kernel)
185 list_move(&vm_bo->vm_status, &vm->evicted);
186 else
187 list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 spin_unlock(&vm_bo->vm->status_lock);
189}
190/**
191 * amdgpu_vm_bo_moved - vm_bo is moved
192 *
193 * @vm_bo: vm_bo which is moved
194 *
195 * State for per VM BOs which are moved, but that change is not yet reflected
196 * in the page tables.
197 */
198static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
199{
200 spin_lock(&vm_bo->vm->status_lock);
201 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 spin_unlock(&vm_bo->vm->status_lock);
203}
204
205/**
206 * amdgpu_vm_bo_idle - vm_bo is idle
207 *
208 * @vm_bo: vm_bo which is now idle
209 *
210 * State for PDs/PTs and per VM BOs which have gone through the state machine
211 * and are now idle.
212 */
213static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
214{
215 spin_lock(&vm_bo->vm->status_lock);
216 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 spin_unlock(&vm_bo->vm->status_lock);
218 vm_bo->moved = false;
219}
220
221/**
222 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
223 *
224 * @vm_bo: vm_bo which is now invalidated
225 *
226 * State for normal BOs which are invalidated and that change not yet reflected
227 * in the PTs.
228 */
229static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
230{
231 spin_lock(&vm_bo->vm->status_lock);
232 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 spin_unlock(&vm_bo->vm->status_lock);
234}
235
236/**
237 * amdgpu_vm_bo_evicted_user - vm_bo is evicted
238 *
239 * @vm_bo: vm_bo which is evicted
240 *
241 * State for BOs used by user mode queues which are not at the location they
242 * should be.
243 */
244static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo)
245{
246 vm_bo->moved = true;
247 spin_lock(&vm_bo->vm->status_lock);
248 list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user);
249 spin_unlock(&vm_bo->vm->status_lock);
250}
251
252/**
253 * amdgpu_vm_bo_relocated - vm_bo is reloacted
254 *
255 * @vm_bo: vm_bo which is relocated
256 *
257 * State for PDs/PTs which needs to update their parent PD.
258 * For the root PD, just move to idle state.
259 */
260static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
261{
262 if (vm_bo->bo->parent) {
263 spin_lock(&vm_bo->vm->status_lock);
264 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
265 spin_unlock(&vm_bo->vm->status_lock);
266 } else {
267 amdgpu_vm_bo_idle(vm_bo);
268 }
269}
270
271/**
272 * amdgpu_vm_bo_done - vm_bo is done
273 *
274 * @vm_bo: vm_bo which is now done
275 *
276 * State for normal BOs which are invalidated and that change has been updated
277 * in the PTs.
278 */
279static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
280{
281 spin_lock(&vm_bo->vm->status_lock);
282 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
283 spin_unlock(&vm_bo->vm->status_lock);
284}
285
286/**
287 * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
288 * @vm: the VM which state machine to reset
289 *
290 * Move all vm_bo object in the VM into a state where they will be updated
291 * again during validation.
292 */
293static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
294{
295 struct amdgpu_vm_bo_base *vm_bo, *tmp;
296
297 spin_lock(&vm->status_lock);
298 list_splice_init(&vm->done, &vm->invalidated);
299 list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
300 vm_bo->moved = true;
301 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
302 struct amdgpu_bo *bo = vm_bo->bo;
303
304 vm_bo->moved = true;
305 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
306 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
307 else if (bo->parent)
308 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
309 }
310 spin_unlock(&vm->status_lock);
311}
312
313/**
314 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
315 *
316 * @base: base structure for tracking BO usage in a VM
317 * @vm: vm to which bo is to be added
318 * @bo: amdgpu buffer object
319 *
320 * Initialize a bo_va_base structure and add it to the appropriate lists
321 *
322 */
323void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
324 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
325{
326 base->vm = vm;
327 base->bo = bo;
328 base->next = NULL;
329 INIT_LIST_HEAD(&base->vm_status);
330
331 if (!bo)
332 return;
333 base->next = bo->vm_bo;
334 bo->vm_bo = base;
335
336 if (!amdgpu_vm_is_bo_always_valid(vm, bo))
337 return;
338
339 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
340
341 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
342 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
343 amdgpu_vm_bo_relocated(base);
344 else
345 amdgpu_vm_bo_idle(base);
346
347 if (bo->preferred_domains &
348 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
349 return;
350
351 /*
352 * we checked all the prerequisites, but it looks like this per vm bo
353 * is currently evicted. add the bo to the evicted list to make sure it
354 * is validated on next vm use to avoid fault.
355 * */
356 amdgpu_vm_bo_evicted(base);
357}
358
359/**
360 * amdgpu_vm_lock_pd - lock PD in drm_exec
361 *
362 * @vm: vm providing the BOs
363 * @exec: drm execution context
364 * @num_fences: number of extra fences to reserve
365 *
366 * Lock the VM root PD in the DRM execution context.
367 */
368int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
369 unsigned int num_fences)
370{
371 /* We need at least two fences for the VM PD/PT updates */
372 return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
373 2 + num_fences);
374}
375
376/**
377 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
378 *
379 * @adev: amdgpu device pointer
380 * @vm: vm providing the BOs
381 *
382 * Move all BOs to the end of LRU and remember their positions to put them
383 * together.
384 */
385void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
386 struct amdgpu_vm *vm)
387{
388 spin_lock(&adev->mman.bdev.lru_lock);
389 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
390 spin_unlock(&adev->mman.bdev.lru_lock);
391}
392
393/* Create scheduler entities for page table updates */
394static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm)
396{
397 int r;
398
399 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
400 adev->vm_manager.vm_pte_scheds,
401 adev->vm_manager.vm_pte_num_scheds, NULL);
402 if (r)
403 goto error;
404
405 return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
406 adev->vm_manager.vm_pte_scheds,
407 adev->vm_manager.vm_pte_num_scheds, NULL);
408
409error:
410 drm_sched_entity_destroy(&vm->immediate);
411 return r;
412}
413
414/* Destroy the entities for page table updates again */
415static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
416{
417 drm_sched_entity_destroy(&vm->immediate);
418 drm_sched_entity_destroy(&vm->delayed);
419}
420
421/**
422 * amdgpu_vm_generation - return the page table re-generation counter
423 * @adev: the amdgpu_device
424 * @vm: optional VM to check, might be NULL
425 *
426 * Returns a page table re-generation token to allow checking if submissions
427 * are still valid to use this VM. The VM parameter might be NULL in which case
428 * just the VRAM lost counter will be used.
429 */
430uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
431{
432 uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
433
434 if (!vm)
435 return result;
436
437 result += lower_32_bits(vm->generation);
438 /* Add one if the page tables will be re-generated on next CS */
439 if (drm_sched_entity_error(&vm->delayed))
440 ++result;
441
442 return result;
443}
444
445/**
446 * amdgpu_vm_validate - validate evicted BOs tracked in the VM
447 *
448 * @adev: amdgpu device pointer
449 * @vm: vm providing the BOs
450 * @ticket: optional reservation ticket used to reserve the VM
451 * @validate: callback to do the validation
452 * @param: parameter for the validation callback
453 *
454 * Validate the page table BOs and per-VM BOs on command submission if
455 * necessary. If a ticket is given, also try to validate evicted user queue
456 * BOs. They must already be reserved with the given ticket.
457 *
458 * Returns:
459 * Validation result.
460 */
461int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
462 struct ww_acquire_ctx *ticket,
463 int (*validate)(void *p, struct amdgpu_bo *bo),
464 void *param)
465{
466 uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm);
467 struct amdgpu_vm_bo_base *bo_base;
468 struct amdgpu_bo *bo;
469 int r;
470
471 if (vm->generation != new_vm_generation) {
472 vm->generation = new_vm_generation;
473 amdgpu_vm_bo_reset_state_machine(vm);
474 amdgpu_vm_fini_entities(vm);
475 r = amdgpu_vm_init_entities(adev, vm);
476 if (r)
477 return r;
478 }
479
480 spin_lock(&vm->status_lock);
481 while (!list_empty(&vm->evicted)) {
482 bo_base = list_first_entry(&vm->evicted,
483 struct amdgpu_vm_bo_base,
484 vm_status);
485 spin_unlock(&vm->status_lock);
486
487 bo = bo_base->bo;
488
489 r = validate(param, bo);
490 if (r)
491 return r;
492
493 if (bo->tbo.type != ttm_bo_type_kernel) {
494 amdgpu_vm_bo_moved(bo_base);
495 } else {
496 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
497 amdgpu_vm_bo_relocated(bo_base);
498 }
499 spin_lock(&vm->status_lock);
500 }
501 while (ticket && !list_empty(&vm->evicted_user)) {
502 bo_base = list_first_entry(&vm->evicted_user,
503 struct amdgpu_vm_bo_base,
504 vm_status);
505 spin_unlock(&vm->status_lock);
506
507 bo = bo_base->bo;
508
509 if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) {
510 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
511
512 pr_warn_ratelimited("Evicted user BO is not reserved\n");
513 if (ti) {
514 pr_warn_ratelimited("pid %d\n", ti->pid);
515 amdgpu_vm_put_task_info(ti);
516 }
517
518 return -EINVAL;
519 }
520
521 r = validate(param, bo);
522 if (r)
523 return r;
524
525 amdgpu_vm_bo_invalidated(bo_base);
526
527 spin_lock(&vm->status_lock);
528 }
529 spin_unlock(&vm->status_lock);
530
531 amdgpu_vm_eviction_lock(vm);
532 vm->evicting = false;
533 amdgpu_vm_eviction_unlock(vm);
534
535 return 0;
536}
537
538/**
539 * amdgpu_vm_ready - check VM is ready for updates
540 *
541 * @vm: VM to check
542 *
543 * Check if all VM PDs/PTs are ready for updates
544 *
545 * Returns:
546 * True if VM is not evicting.
547 */
548bool amdgpu_vm_ready(struct amdgpu_vm *vm)
549{
550 bool empty;
551 bool ret;
552
553 amdgpu_vm_eviction_lock(vm);
554 ret = !vm->evicting;
555 amdgpu_vm_eviction_unlock(vm);
556
557 spin_lock(&vm->status_lock);
558 empty = list_empty(&vm->evicted);
559 spin_unlock(&vm->status_lock);
560
561 return ret && empty;
562}
563
564/**
565 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
566 *
567 * @adev: amdgpu_device pointer
568 */
569void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
570{
571 const struct amdgpu_ip_block *ip_block;
572 bool has_compute_vm_bug;
573 struct amdgpu_ring *ring;
574 int i;
575
576 has_compute_vm_bug = false;
577
578 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
579 if (ip_block) {
580 /* Compute has a VM bug for GFX version < 7.
581 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
582 if (ip_block->version->major <= 7)
583 has_compute_vm_bug = true;
584 else if (ip_block->version->major == 8)
585 if (adev->gfx.mec_fw_version < 673)
586 has_compute_vm_bug = true;
587 }
588
589 for (i = 0; i < adev->num_rings; i++) {
590 ring = adev->rings[i];
591 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
592 /* only compute rings */
593 ring->has_compute_vm_bug = has_compute_vm_bug;
594 else
595 ring->has_compute_vm_bug = false;
596 }
597}
598
599/**
600 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
601 *
602 * @ring: ring on which the job will be submitted
603 * @job: job to submit
604 *
605 * Returns:
606 * True if sync is needed.
607 */
608bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
609 struct amdgpu_job *job)
610{
611 struct amdgpu_device *adev = ring->adev;
612 unsigned vmhub = ring->vm_hub;
613 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
614
615 if (job->vmid == 0)
616 return false;
617
618 if (job->vm_needs_flush || ring->has_compute_vm_bug)
619 return true;
620
621 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
622 return true;
623
624 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
625 return true;
626
627 return false;
628}
629
630/**
631 * amdgpu_vm_flush - hardware flush the vm
632 *
633 * @ring: ring to use for flush
634 * @job: related job
635 * @need_pipe_sync: is pipe sync needed
636 *
637 * Emit a VM flush when it is necessary.
638 *
639 * Returns:
640 * 0 on success, errno otherwise.
641 */
642int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
643 bool need_pipe_sync)
644{
645 struct amdgpu_device *adev = ring->adev;
646 unsigned vmhub = ring->vm_hub;
647 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
648 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
649 bool spm_update_needed = job->spm_update_needed;
650 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
651 job->gds_switch_needed;
652 bool vm_flush_needed = job->vm_needs_flush;
653 struct dma_fence *fence = NULL;
654 bool pasid_mapping_needed = false;
655 unsigned int patch;
656 int r;
657
658 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
659 gds_switch_needed = true;
660 vm_flush_needed = true;
661 pasid_mapping_needed = true;
662 spm_update_needed = true;
663 }
664
665 mutex_lock(&id_mgr->lock);
666 if (id->pasid != job->pasid || !id->pasid_mapping ||
667 !dma_fence_is_signaled(id->pasid_mapping))
668 pasid_mapping_needed = true;
669 mutex_unlock(&id_mgr->lock);
670
671 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
672 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
673 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
674 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
675 ring->funcs->emit_wreg;
676
677 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync &&
678 !(job->enforce_isolation && !job->vmid))
679 return 0;
680
681 amdgpu_ring_ib_begin(ring);
682 if (ring->funcs->init_cond_exec)
683 patch = amdgpu_ring_init_cond_exec(ring,
684 ring->cond_exe_gpu_addr);
685
686 if (need_pipe_sync)
687 amdgpu_ring_emit_pipeline_sync(ring);
688
689 if (adev->gfx.enable_cleaner_shader &&
690 ring->funcs->emit_cleaner_shader &&
691 job->enforce_isolation)
692 ring->funcs->emit_cleaner_shader(ring);
693
694 if (vm_flush_needed) {
695 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
696 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
697 }
698
699 if (pasid_mapping_needed)
700 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
701
702 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
703 adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);
704
705 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
706 gds_switch_needed) {
707 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
708 job->gds_size, job->gws_base,
709 job->gws_size, job->oa_base,
710 job->oa_size);
711 }
712
713 if (vm_flush_needed || pasid_mapping_needed) {
714 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
715 if (r)
716 return r;
717 }
718
719 if (vm_flush_needed) {
720 mutex_lock(&id_mgr->lock);
721 dma_fence_put(id->last_flush);
722 id->last_flush = dma_fence_get(fence);
723 id->current_gpu_reset_count =
724 atomic_read(&adev->gpu_reset_counter);
725 mutex_unlock(&id_mgr->lock);
726 }
727
728 if (pasid_mapping_needed) {
729 mutex_lock(&id_mgr->lock);
730 id->pasid = job->pasid;
731 dma_fence_put(id->pasid_mapping);
732 id->pasid_mapping = dma_fence_get(fence);
733 mutex_unlock(&id_mgr->lock);
734 }
735 dma_fence_put(fence);
736
737 amdgpu_ring_patch_cond_exec(ring, patch);
738
739 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
740 if (ring->funcs->emit_switch_buffer) {
741 amdgpu_ring_emit_switch_buffer(ring);
742 amdgpu_ring_emit_switch_buffer(ring);
743 }
744
745 amdgpu_ring_ib_end(ring);
746 return 0;
747}
748
749/**
750 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
751 *
752 * @vm: requested vm
753 * @bo: requested buffer object
754 *
755 * Find @bo inside the requested vm.
756 * Search inside the @bos vm list for the requested vm
757 * Returns the found bo_va or NULL if none is found
758 *
759 * Object has to be reserved!
760 *
761 * Returns:
762 * Found bo_va or NULL.
763 */
764struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
765 struct amdgpu_bo *bo)
766{
767 struct amdgpu_vm_bo_base *base;
768
769 for (base = bo->vm_bo; base; base = base->next) {
770 if (base->vm != vm)
771 continue;
772
773 return container_of(base, struct amdgpu_bo_va, base);
774 }
775 return NULL;
776}
777
778/**
779 * amdgpu_vm_map_gart - Resolve gart mapping of addr
780 *
781 * @pages_addr: optional DMA address to use for lookup
782 * @addr: the unmapped addr
783 *
784 * Look up the physical address of the page that the pte resolves
785 * to.
786 *
787 * Returns:
788 * The pointer for the page table entry.
789 */
790uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
791{
792 uint64_t result;
793
794 /* page table offset */
795 result = pages_addr[addr >> PAGE_SHIFT];
796
797 /* in case cpu page size != gpu page size*/
798 result |= addr & (~PAGE_MASK);
799
800 result &= 0xFFFFFFFFFFFFF000ULL;
801
802 return result;
803}
804
805/**
806 * amdgpu_vm_update_pdes - make sure that all directories are valid
807 *
808 * @adev: amdgpu_device pointer
809 * @vm: requested vm
810 * @immediate: submit immediately to the paging queue
811 *
812 * Makes sure all directories are up to date.
813 *
814 * Returns:
815 * 0 for success, error for failure.
816 */
817int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
818 struct amdgpu_vm *vm, bool immediate)
819{
820 struct amdgpu_vm_update_params params;
821 struct amdgpu_vm_bo_base *entry;
822 bool flush_tlb_needed = false;
823 LIST_HEAD(relocated);
824 int r, idx;
825
826 spin_lock(&vm->status_lock);
827 list_splice_init(&vm->relocated, &relocated);
828 spin_unlock(&vm->status_lock);
829
830 if (list_empty(&relocated))
831 return 0;
832
833 if (!drm_dev_enter(adev_to_drm(adev), &idx))
834 return -ENODEV;
835
836 memset(¶ms, 0, sizeof(params));
837 params.adev = adev;
838 params.vm = vm;
839 params.immediate = immediate;
840
841 r = vm->update_funcs->prepare(¶ms, NULL);
842 if (r)
843 goto error;
844
845 list_for_each_entry(entry, &relocated, vm_status) {
846 /* vm_flush_needed after updating moved PDEs */
847 flush_tlb_needed |= entry->moved;
848
849 r = amdgpu_vm_pde_update(¶ms, entry);
850 if (r)
851 goto error;
852 }
853
854 r = vm->update_funcs->commit(¶ms, &vm->last_update);
855 if (r)
856 goto error;
857
858 if (flush_tlb_needed)
859 atomic64_inc(&vm->tlb_seq);
860
861 while (!list_empty(&relocated)) {
862 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
863 vm_status);
864 amdgpu_vm_bo_idle(entry);
865 }
866
867error:
868 drm_dev_exit(idx);
869 return r;
870}
871
872/**
873 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
874 * @fence: unused
875 * @cb: the callback structure
876 *
877 * Increments the tlb sequence to make sure that future CS execute a VM flush.
878 */
879static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
880 struct dma_fence_cb *cb)
881{
882 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
883
884 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
885 atomic64_inc(&tlb_cb->vm->tlb_seq);
886 kfree(tlb_cb);
887}
888
889/**
890 * amdgpu_vm_tlb_flush - prepare TLB flush
891 *
892 * @params: parameters for update
893 * @fence: input fence to sync TLB flush with
894 * @tlb_cb: the callback structure
895 *
896 * Increments the tlb sequence to make sure that future CS execute a VM flush.
897 */
898static void
899amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params,
900 struct dma_fence **fence,
901 struct amdgpu_vm_tlb_seq_struct *tlb_cb)
902{
903 struct amdgpu_vm *vm = params->vm;
904
905 tlb_cb->vm = vm;
906 if (!fence || !*fence) {
907 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
908 return;
909 }
910
911 if (!dma_fence_add_callback(*fence, &tlb_cb->cb,
912 amdgpu_vm_tlb_seq_cb)) {
913 dma_fence_put(vm->last_tlb_flush);
914 vm->last_tlb_flush = dma_fence_get(*fence);
915 } else {
916 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
917 }
918
919 /* Prepare a TLB flush fence to be attached to PTs */
920 if (!params->unlocked && vm->is_compute_context) {
921 amdgpu_vm_tlb_fence_create(params->adev, vm, fence);
922
923 /* Makes sure no PD/PT is freed before the flush */
924 dma_resv_add_fence(vm->root.bo->tbo.base.resv, *fence,
925 DMA_RESV_USAGE_BOOKKEEP);
926 }
927}
928
929/**
930 * amdgpu_vm_update_range - update a range in the vm page table
931 *
932 * @adev: amdgpu_device pointer to use for commands
933 * @vm: the VM to update the range
934 * @immediate: immediate submission in a page fault
935 * @unlocked: unlocked invalidation during MM callback
936 * @flush_tlb: trigger tlb invalidation after update completed
937 * @allow_override: change MTYPE for local NUMA nodes
938 * @sync: fences we need to sync to
939 * @start: start of mapped range
940 * @last: last mapped entry
941 * @flags: flags for the entries
942 * @offset: offset into nodes and pages_addr
943 * @vram_base: base for vram mappings
944 * @res: ttm_resource to map
945 * @pages_addr: DMA addresses to use for mapping
946 * @fence: optional resulting fence
947 *
948 * Fill in the page table entries between @start and @last.
949 *
950 * Returns:
951 * 0 for success, negative erro code for failure.
952 */
953int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
954 bool immediate, bool unlocked, bool flush_tlb,
955 bool allow_override, struct amdgpu_sync *sync,
956 uint64_t start, uint64_t last, uint64_t flags,
957 uint64_t offset, uint64_t vram_base,
958 struct ttm_resource *res, dma_addr_t *pages_addr,
959 struct dma_fence **fence)
960{
961 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
962 struct amdgpu_vm_update_params params;
963 struct amdgpu_res_cursor cursor;
964 int r, idx;
965
966 if (!drm_dev_enter(adev_to_drm(adev), &idx))
967 return -ENODEV;
968
969 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
970 if (!tlb_cb) {
971 drm_dev_exit(idx);
972 return -ENOMEM;
973 }
974
975 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
976 * heavy-weight flush TLB unconditionally.
977 */
978 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
979 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0);
980
981 /*
982 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
983 */
984 flush_tlb |= amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0);
985
986 memset(¶ms, 0, sizeof(params));
987 params.adev = adev;
988 params.vm = vm;
989 params.immediate = immediate;
990 params.pages_addr = pages_addr;
991 params.unlocked = unlocked;
992 params.needs_flush = flush_tlb;
993 params.allow_override = allow_override;
994 INIT_LIST_HEAD(¶ms.tlb_flush_waitlist);
995
996 amdgpu_vm_eviction_lock(vm);
997 if (vm->evicting) {
998 r = -EBUSY;
999 goto error_free;
1000 }
1001
1002 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1003 struct dma_fence *tmp = dma_fence_get_stub();
1004
1005 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1006 swap(vm->last_unlocked, tmp);
1007 dma_fence_put(tmp);
1008 }
1009
1010 r = vm->update_funcs->prepare(¶ms, sync);
1011 if (r)
1012 goto error_free;
1013
1014 amdgpu_res_first(pages_addr ? NULL : res, offset,
1015 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1016 while (cursor.remaining) {
1017 uint64_t tmp, num_entries, addr;
1018
1019 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1020 if (pages_addr) {
1021 bool contiguous = true;
1022
1023 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1024 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1025 uint64_t count;
1026
1027 contiguous = pages_addr[pfn + 1] ==
1028 pages_addr[pfn] + PAGE_SIZE;
1029
1030 tmp = num_entries /
1031 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1032 for (count = 2; count < tmp; ++count) {
1033 uint64_t idx = pfn + count;
1034
1035 if (contiguous != (pages_addr[idx] ==
1036 pages_addr[idx - 1] + PAGE_SIZE))
1037 break;
1038 }
1039 if (!contiguous)
1040 count--;
1041 num_entries = count *
1042 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1043 }
1044
1045 if (!contiguous) {
1046 addr = cursor.start;
1047 params.pages_addr = pages_addr;
1048 } else {
1049 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1050 params.pages_addr = NULL;
1051 }
1052
1053 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) {
1054 addr = vram_base + cursor.start;
1055 } else {
1056 addr = 0;
1057 }
1058
1059 tmp = start + num_entries;
1060 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
1061 if (r)
1062 goto error_free;
1063
1064 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1065 start = tmp;
1066 }
1067
1068 r = vm->update_funcs->commit(¶ms, fence);
1069 if (r)
1070 goto error_free;
1071
1072 if (params.needs_flush) {
1073 amdgpu_vm_tlb_flush(¶ms, fence, tlb_cb);
1074 tlb_cb = NULL;
1075 }
1076
1077 amdgpu_vm_pt_free_list(adev, ¶ms);
1078
1079error_free:
1080 kfree(tlb_cb);
1081 amdgpu_vm_eviction_unlock(vm);
1082 drm_dev_exit(idx);
1083 return r;
1084}
1085
1086static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1087 struct amdgpu_mem_stats *stats,
1088 unsigned int size)
1089{
1090 struct amdgpu_vm *vm = bo_va->base.vm;
1091 struct amdgpu_bo *bo = bo_va->base.bo;
1092
1093 if (!bo)
1094 return;
1095
1096 /*
1097 * For now ignore BOs which are currently locked and potentially
1098 * changing their location.
1099 */
1100 if (!amdgpu_vm_is_bo_always_valid(vm, bo) &&
1101 !dma_resv_trylock(bo->tbo.base.resv))
1102 return;
1103
1104 amdgpu_bo_get_memory(bo, stats, size);
1105 if (!amdgpu_vm_is_bo_always_valid(vm, bo))
1106 dma_resv_unlock(bo->tbo.base.resv);
1107}
1108
1109void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1110 struct amdgpu_mem_stats *stats,
1111 unsigned int size)
1112{
1113 struct amdgpu_bo_va *bo_va, *tmp;
1114
1115 spin_lock(&vm->status_lock);
1116 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1117 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1118
1119 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1120 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1121
1122 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1123 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1124
1125 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1126 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1127
1128 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1129 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1130
1131 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1132 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1133 spin_unlock(&vm->status_lock);
1134}
1135
1136/**
1137 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1138 *
1139 * @adev: amdgpu_device pointer
1140 * @bo_va: requested BO and VM object
1141 * @clear: if true clear the entries
1142 *
1143 * Fill in the page table entries for @bo_va.
1144 *
1145 * Returns:
1146 * 0 for success, -EINVAL for failure.
1147 */
1148int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1149 bool clear)
1150{
1151 struct amdgpu_bo *bo = bo_va->base.bo;
1152 struct amdgpu_vm *vm = bo_va->base.vm;
1153 struct amdgpu_bo_va_mapping *mapping;
1154 struct dma_fence **last_update;
1155 dma_addr_t *pages_addr = NULL;
1156 struct ttm_resource *mem;
1157 struct amdgpu_sync sync;
1158 bool flush_tlb = clear;
1159 uint64_t vram_base;
1160 uint64_t flags;
1161 bool uncached;
1162 int r;
1163
1164 amdgpu_sync_create(&sync);
1165 if (clear) {
1166 mem = NULL;
1167
1168 /* Implicitly sync to command submissions in the same VM before
1169 * unmapping.
1170 */
1171 r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv,
1172 AMDGPU_SYNC_EQ_OWNER, vm);
1173 if (r)
1174 goto error_free;
1175 if (bo) {
1176 r = amdgpu_sync_kfd(&sync, bo->tbo.base.resv);
1177 if (r)
1178 goto error_free;
1179 }
1180 } else if (!bo) {
1181 mem = NULL;
1182
1183 /* PRT map operations don't need to sync to anything. */
1184
1185 } else {
1186 struct drm_gem_object *obj = &bo->tbo.base;
1187
1188 if (obj->import_attach && bo_va->is_xgmi) {
1189 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1190 struct drm_gem_object *gobj = dma_buf->priv;
1191 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1192
1193 if (abo->tbo.resource &&
1194 abo->tbo.resource->mem_type == TTM_PL_VRAM)
1195 bo = gem_to_amdgpu_bo(gobj);
1196 }
1197 mem = bo->tbo.resource;
1198 if (mem && (mem->mem_type == TTM_PL_TT ||
1199 mem->mem_type == AMDGPU_PL_PREEMPT))
1200 pages_addr = bo->tbo.ttm->dma_address;
1201
1202 /* Implicitly sync to moving fences before mapping anything */
1203 r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv,
1204 AMDGPU_SYNC_EXPLICIT, vm);
1205 if (r)
1206 goto error_free;
1207 }
1208
1209 if (bo) {
1210 struct amdgpu_device *bo_adev;
1211
1212 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1213
1214 if (amdgpu_bo_encrypted(bo))
1215 flags |= AMDGPU_PTE_TMZ;
1216
1217 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1218 vram_base = bo_adev->vm_manager.vram_base_offset;
1219 uncached = (bo->flags & AMDGPU_GEM_CREATE_UNCACHED) != 0;
1220 } else {
1221 flags = 0x0;
1222 vram_base = 0;
1223 uncached = false;
1224 }
1225
1226 if (clear || amdgpu_vm_is_bo_always_valid(vm, bo))
1227 last_update = &vm->last_update;
1228 else
1229 last_update = &bo_va->last_pt_update;
1230
1231 if (!clear && bo_va->base.moved) {
1232 flush_tlb = true;
1233 list_splice_init(&bo_va->valids, &bo_va->invalids);
1234
1235 } else if (bo_va->cleared != clear) {
1236 list_splice_init(&bo_va->valids, &bo_va->invalids);
1237 }
1238
1239 list_for_each_entry(mapping, &bo_va->invalids, list) {
1240 uint64_t update_flags = flags;
1241
1242 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1243 * but in case of something, we filter the flags in first place
1244 */
1245 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1246 update_flags &= ~AMDGPU_PTE_READABLE;
1247 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1248 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1249
1250 /* Apply ASIC specific mapping flags */
1251 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1252
1253 trace_amdgpu_vm_bo_update(mapping);
1254
1255 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1256 !uncached, &sync, mapping->start,
1257 mapping->last, update_flags,
1258 mapping->offset, vram_base, mem,
1259 pages_addr, last_update);
1260 if (r)
1261 goto error_free;
1262 }
1263
1264 /* If the BO is not in its preferred location add it back to
1265 * the evicted list so that it gets validated again on the
1266 * next command submission.
1267 */
1268 if (amdgpu_vm_is_bo_always_valid(vm, bo)) {
1269 if (bo->tbo.resource &&
1270 !(bo->preferred_domains &
1271 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type)))
1272 amdgpu_vm_bo_evicted(&bo_va->base);
1273 else
1274 amdgpu_vm_bo_idle(&bo_va->base);
1275 } else {
1276 amdgpu_vm_bo_done(&bo_va->base);
1277 }
1278
1279 list_splice_init(&bo_va->invalids, &bo_va->valids);
1280 bo_va->cleared = clear;
1281 bo_va->base.moved = false;
1282
1283 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1284 list_for_each_entry(mapping, &bo_va->valids, list)
1285 trace_amdgpu_vm_bo_mapping(mapping);
1286 }
1287
1288error_free:
1289 amdgpu_sync_free(&sync);
1290 return r;
1291}
1292
1293/**
1294 * amdgpu_vm_update_prt_state - update the global PRT state
1295 *
1296 * @adev: amdgpu_device pointer
1297 */
1298static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1299{
1300 unsigned long flags;
1301 bool enable;
1302
1303 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1304 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1305 adev->gmc.gmc_funcs->set_prt(adev, enable);
1306 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1307}
1308
1309/**
1310 * amdgpu_vm_prt_get - add a PRT user
1311 *
1312 * @adev: amdgpu_device pointer
1313 */
1314static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1315{
1316 if (!adev->gmc.gmc_funcs->set_prt)
1317 return;
1318
1319 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1320 amdgpu_vm_update_prt_state(adev);
1321}
1322
1323/**
1324 * amdgpu_vm_prt_put - drop a PRT user
1325 *
1326 * @adev: amdgpu_device pointer
1327 */
1328static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1329{
1330 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1331 amdgpu_vm_update_prt_state(adev);
1332}
1333
1334/**
1335 * amdgpu_vm_prt_cb - callback for updating the PRT status
1336 *
1337 * @fence: fence for the callback
1338 * @_cb: the callback function
1339 */
1340static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1341{
1342 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1343
1344 amdgpu_vm_prt_put(cb->adev);
1345 kfree(cb);
1346}
1347
1348/**
1349 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1350 *
1351 * @adev: amdgpu_device pointer
1352 * @fence: fence for the callback
1353 */
1354static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1355 struct dma_fence *fence)
1356{
1357 struct amdgpu_prt_cb *cb;
1358
1359 if (!adev->gmc.gmc_funcs->set_prt)
1360 return;
1361
1362 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1363 if (!cb) {
1364 /* Last resort when we are OOM */
1365 if (fence)
1366 dma_fence_wait(fence, false);
1367
1368 amdgpu_vm_prt_put(adev);
1369 } else {
1370 cb->adev = adev;
1371 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1372 amdgpu_vm_prt_cb))
1373 amdgpu_vm_prt_cb(fence, &cb->cb);
1374 }
1375}
1376
1377/**
1378 * amdgpu_vm_free_mapping - free a mapping
1379 *
1380 * @adev: amdgpu_device pointer
1381 * @vm: requested vm
1382 * @mapping: mapping to be freed
1383 * @fence: fence of the unmap operation
1384 *
1385 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1386 */
1387static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1388 struct amdgpu_vm *vm,
1389 struct amdgpu_bo_va_mapping *mapping,
1390 struct dma_fence *fence)
1391{
1392 if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev))
1393 amdgpu_vm_add_prt_cb(adev, fence);
1394 kfree(mapping);
1395}
1396
1397/**
1398 * amdgpu_vm_prt_fini - finish all prt mappings
1399 *
1400 * @adev: amdgpu_device pointer
1401 * @vm: requested vm
1402 *
1403 * Register a cleanup callback to disable PRT support after VM dies.
1404 */
1405static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1406{
1407 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1408 struct dma_resv_iter cursor;
1409 struct dma_fence *fence;
1410
1411 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1412 /* Add a callback for each fence in the reservation object */
1413 amdgpu_vm_prt_get(adev);
1414 amdgpu_vm_add_prt_cb(adev, fence);
1415 }
1416}
1417
1418/**
1419 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1420 *
1421 * @adev: amdgpu_device pointer
1422 * @vm: requested vm
1423 * @fence: optional resulting fence (unchanged if no work needed to be done
1424 * or if an error occurred)
1425 *
1426 * Make sure all freed BOs are cleared in the PT.
1427 * PTs have to be reserved and mutex must be locked!
1428 *
1429 * Returns:
1430 * 0 for success.
1431 *
1432 */
1433int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1434 struct amdgpu_vm *vm,
1435 struct dma_fence **fence)
1436{
1437 struct amdgpu_bo_va_mapping *mapping;
1438 struct dma_fence *f = NULL;
1439 struct amdgpu_sync sync;
1440 int r;
1441
1442
1443 /*
1444 * Implicitly sync to command submissions in the same VM before
1445 * unmapping.
1446 */
1447 amdgpu_sync_create(&sync);
1448 r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv,
1449 AMDGPU_SYNC_EQ_OWNER, vm);
1450 if (r)
1451 goto error_free;
1452
1453 while (!list_empty(&vm->freed)) {
1454 mapping = list_first_entry(&vm->freed,
1455 struct amdgpu_bo_va_mapping, list);
1456 list_del(&mapping->list);
1457
1458 r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
1459 &sync, mapping->start, mapping->last,
1460 0, 0, 0, NULL, NULL, &f);
1461 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1462 if (r) {
1463 dma_fence_put(f);
1464 goto error_free;
1465 }
1466 }
1467
1468 if (fence && f) {
1469 dma_fence_put(*fence);
1470 *fence = f;
1471 } else {
1472 dma_fence_put(f);
1473 }
1474
1475error_free:
1476 amdgpu_sync_free(&sync);
1477 return r;
1478
1479}
1480
1481/**
1482 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1483 *
1484 * @adev: amdgpu_device pointer
1485 * @vm: requested vm
1486 * @ticket: optional reservation ticket used to reserve the VM
1487 *
1488 * Make sure all BOs which are moved are updated in the PTs.
1489 *
1490 * Returns:
1491 * 0 for success.
1492 *
1493 * PTs have to be reserved!
1494 */
1495int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1496 struct amdgpu_vm *vm,
1497 struct ww_acquire_ctx *ticket)
1498{
1499 struct amdgpu_bo_va *bo_va;
1500 struct dma_resv *resv;
1501 bool clear, unlock;
1502 int r;
1503
1504 spin_lock(&vm->status_lock);
1505 while (!list_empty(&vm->moved)) {
1506 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1507 base.vm_status);
1508 spin_unlock(&vm->status_lock);
1509
1510 /* Per VM BOs never need to bo cleared in the page tables */
1511 r = amdgpu_vm_bo_update(adev, bo_va, false);
1512 if (r)
1513 return r;
1514 spin_lock(&vm->status_lock);
1515 }
1516
1517 while (!list_empty(&vm->invalidated)) {
1518 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1519 base.vm_status);
1520 resv = bo_va->base.bo->tbo.base.resv;
1521 spin_unlock(&vm->status_lock);
1522
1523 /* Try to reserve the BO to avoid clearing its ptes */
1524 if (!adev->debug_vm && dma_resv_trylock(resv)) {
1525 clear = false;
1526 unlock = true;
1527 /* The caller is already holding the reservation lock */
1528 } else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
1529 clear = false;
1530 unlock = false;
1531 /* Somebody else is using the BO right now */
1532 } else {
1533 clear = true;
1534 unlock = false;
1535 }
1536
1537 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1538
1539 if (unlock)
1540 dma_resv_unlock(resv);
1541 if (r)
1542 return r;
1543
1544 /* Remember evicted DMABuf imports in compute VMs for later
1545 * validation
1546 */
1547 if (vm->is_compute_context &&
1548 bo_va->base.bo->tbo.base.import_attach &&
1549 (!bo_va->base.bo->tbo.resource ||
1550 bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM))
1551 amdgpu_vm_bo_evicted_user(&bo_va->base);
1552
1553 spin_lock(&vm->status_lock);
1554 }
1555 spin_unlock(&vm->status_lock);
1556
1557 return 0;
1558}
1559
1560/**
1561 * amdgpu_vm_flush_compute_tlb - Flush TLB on compute VM
1562 *
1563 * @adev: amdgpu_device pointer
1564 * @vm: requested vm
1565 * @flush_type: flush type
1566 * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush.
1567 *
1568 * Flush TLB if needed for a compute VM.
1569 *
1570 * Returns:
1571 * 0 for success.
1572 */
1573int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
1574 struct amdgpu_vm *vm,
1575 uint32_t flush_type,
1576 uint32_t xcc_mask)
1577{
1578 uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);
1579 bool all_hub = false;
1580 int xcc = 0, r = 0;
1581
1582 WARN_ON_ONCE(!vm->is_compute_context);
1583
1584 /*
1585 * It can be that we race and lose here, but that is extremely unlikely
1586 * and the worst thing which could happen is that we flush the changes
1587 * into the TLB once more which is harmless.
1588 */
1589 if (atomic64_xchg(&vm->kfd_last_flushed_seq, tlb_seq) == tlb_seq)
1590 return 0;
1591
1592 if (adev->family == AMDGPU_FAMILY_AI ||
1593 adev->family == AMDGPU_FAMILY_RV)
1594 all_hub = true;
1595
1596 for_each_inst(xcc, xcc_mask) {
1597 r = amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, flush_type,
1598 all_hub, xcc);
1599 if (r)
1600 break;
1601 }
1602 return r;
1603}
1604
1605/**
1606 * amdgpu_vm_bo_add - add a bo to a specific vm
1607 *
1608 * @adev: amdgpu_device pointer
1609 * @vm: requested vm
1610 * @bo: amdgpu buffer object
1611 *
1612 * Add @bo into the requested vm.
1613 * Add @bo to the list of bos associated with the vm
1614 *
1615 * Returns:
1616 * Newly added bo_va or NULL for failure
1617 *
1618 * Object has to be reserved!
1619 */
1620struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1621 struct amdgpu_vm *vm,
1622 struct amdgpu_bo *bo)
1623{
1624 struct amdgpu_bo_va *bo_va;
1625
1626 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1627 if (bo_va == NULL) {
1628 return NULL;
1629 }
1630 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1631
1632 bo_va->ref_count = 1;
1633 bo_va->last_pt_update = dma_fence_get_stub();
1634 INIT_LIST_HEAD(&bo_va->valids);
1635 INIT_LIST_HEAD(&bo_va->invalids);
1636
1637 if (!bo)
1638 return bo_va;
1639
1640 dma_resv_assert_held(bo->tbo.base.resv);
1641 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1642 bo_va->is_xgmi = true;
1643 /* Power up XGMI if it can be potentially used */
1644 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1645 }
1646
1647 return bo_va;
1648}
1649
1650
1651/**
1652 * amdgpu_vm_bo_insert_map - insert a new mapping
1653 *
1654 * @adev: amdgpu_device pointer
1655 * @bo_va: bo_va to store the address
1656 * @mapping: the mapping to insert
1657 *
1658 * Insert a new mapping into all structures.
1659 */
1660static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1661 struct amdgpu_bo_va *bo_va,
1662 struct amdgpu_bo_va_mapping *mapping)
1663{
1664 struct amdgpu_vm *vm = bo_va->base.vm;
1665 struct amdgpu_bo *bo = bo_va->base.bo;
1666
1667 mapping->bo_va = bo_va;
1668 list_add(&mapping->list, &bo_va->invalids);
1669 amdgpu_vm_it_insert(mapping, &vm->va);
1670
1671 if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev))
1672 amdgpu_vm_prt_get(adev);
1673
1674 if (amdgpu_vm_is_bo_always_valid(vm, bo) && !bo_va->base.moved)
1675 amdgpu_vm_bo_moved(&bo_va->base);
1676
1677 trace_amdgpu_vm_bo_map(bo_va, mapping);
1678}
1679
1680/* Validate operation parameters to prevent potential abuse */
1681static int amdgpu_vm_verify_parameters(struct amdgpu_device *adev,
1682 struct amdgpu_bo *bo,
1683 uint64_t saddr,
1684 uint64_t offset,
1685 uint64_t size)
1686{
1687 uint64_t tmp, lpfn;
1688
1689 if (saddr & AMDGPU_GPU_PAGE_MASK
1690 || offset & AMDGPU_GPU_PAGE_MASK
1691 || size & AMDGPU_GPU_PAGE_MASK)
1692 return -EINVAL;
1693
1694 if (check_add_overflow(saddr, size, &tmp)
1695 || check_add_overflow(offset, size, &tmp)
1696 || size == 0 /* which also leads to end < begin */)
1697 return -EINVAL;
1698
1699 /* make sure object fit at this offset */
1700 if (bo && offset + size > amdgpu_bo_size(bo))
1701 return -EINVAL;
1702
1703 /* Ensure last pfn not exceed max_pfn */
1704 lpfn = (saddr + size - 1) >> AMDGPU_GPU_PAGE_SHIFT;
1705 if (lpfn >= adev->vm_manager.max_pfn)
1706 return -EINVAL;
1707
1708 return 0;
1709}
1710
1711/**
1712 * amdgpu_vm_bo_map - map bo inside a vm
1713 *
1714 * @adev: amdgpu_device pointer
1715 * @bo_va: bo_va to store the address
1716 * @saddr: where to map the BO
1717 * @offset: requested offset in the BO
1718 * @size: BO size in bytes
1719 * @flags: attributes of pages (read/write/valid/etc.)
1720 *
1721 * Add a mapping of the BO at the specefied addr into the VM.
1722 *
1723 * Returns:
1724 * 0 for success, error for failure.
1725 *
1726 * Object has to be reserved and unreserved outside!
1727 */
1728int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1729 struct amdgpu_bo_va *bo_va,
1730 uint64_t saddr, uint64_t offset,
1731 uint64_t size, uint64_t flags)
1732{
1733 struct amdgpu_bo_va_mapping *mapping, *tmp;
1734 struct amdgpu_bo *bo = bo_va->base.bo;
1735 struct amdgpu_vm *vm = bo_va->base.vm;
1736 uint64_t eaddr;
1737 int r;
1738
1739 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1740 if (r)
1741 return r;
1742
1743 saddr /= AMDGPU_GPU_PAGE_SIZE;
1744 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1745
1746 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1747 if (tmp) {
1748 /* bo and tmp overlap, invalid addr */
1749 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1750 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1751 tmp->start, tmp->last + 1);
1752 return -EINVAL;
1753 }
1754
1755 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1756 if (!mapping)
1757 return -ENOMEM;
1758
1759 mapping->start = saddr;
1760 mapping->last = eaddr;
1761 mapping->offset = offset;
1762 mapping->flags = flags;
1763
1764 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1765
1766 return 0;
1767}
1768
1769/**
1770 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1771 *
1772 * @adev: amdgpu_device pointer
1773 * @bo_va: bo_va to store the address
1774 * @saddr: where to map the BO
1775 * @offset: requested offset in the BO
1776 * @size: BO size in bytes
1777 * @flags: attributes of pages (read/write/valid/etc.)
1778 *
1779 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1780 * mappings as we do so.
1781 *
1782 * Returns:
1783 * 0 for success, error for failure.
1784 *
1785 * Object has to be reserved and unreserved outside!
1786 */
1787int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1788 struct amdgpu_bo_va *bo_va,
1789 uint64_t saddr, uint64_t offset,
1790 uint64_t size, uint64_t flags)
1791{
1792 struct amdgpu_bo_va_mapping *mapping;
1793 struct amdgpu_bo *bo = bo_va->base.bo;
1794 uint64_t eaddr;
1795 int r;
1796
1797 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1798 if (r)
1799 return r;
1800
1801 /* Allocate all the needed memory */
1802 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1803 if (!mapping)
1804 return -ENOMEM;
1805
1806 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1807 if (r) {
1808 kfree(mapping);
1809 return r;
1810 }
1811
1812 saddr /= AMDGPU_GPU_PAGE_SIZE;
1813 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1814
1815 mapping->start = saddr;
1816 mapping->last = eaddr;
1817 mapping->offset = offset;
1818 mapping->flags = flags;
1819
1820 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1821
1822 return 0;
1823}
1824
1825/**
1826 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1827 *
1828 * @adev: amdgpu_device pointer
1829 * @bo_va: bo_va to remove the address from
1830 * @saddr: where to the BO is mapped
1831 *
1832 * Remove a mapping of the BO at the specefied addr from the VM.
1833 *
1834 * Returns:
1835 * 0 for success, error for failure.
1836 *
1837 * Object has to be reserved and unreserved outside!
1838 */
1839int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1840 struct amdgpu_bo_va *bo_va,
1841 uint64_t saddr)
1842{
1843 struct amdgpu_bo_va_mapping *mapping;
1844 struct amdgpu_vm *vm = bo_va->base.vm;
1845 bool valid = true;
1846
1847 saddr /= AMDGPU_GPU_PAGE_SIZE;
1848
1849 list_for_each_entry(mapping, &bo_va->valids, list) {
1850 if (mapping->start == saddr)
1851 break;
1852 }
1853
1854 if (&mapping->list == &bo_va->valids) {
1855 valid = false;
1856
1857 list_for_each_entry(mapping, &bo_va->invalids, list) {
1858 if (mapping->start == saddr)
1859 break;
1860 }
1861
1862 if (&mapping->list == &bo_va->invalids)
1863 return -ENOENT;
1864 }
1865
1866 list_del(&mapping->list);
1867 amdgpu_vm_it_remove(mapping, &vm->va);
1868 mapping->bo_va = NULL;
1869 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1870
1871 if (valid)
1872 list_add(&mapping->list, &vm->freed);
1873 else
1874 amdgpu_vm_free_mapping(adev, vm, mapping,
1875 bo_va->last_pt_update);
1876
1877 return 0;
1878}
1879
1880/**
1881 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1882 *
1883 * @adev: amdgpu_device pointer
1884 * @vm: VM structure to use
1885 * @saddr: start of the range
1886 * @size: size of the range
1887 *
1888 * Remove all mappings in a range, split them as appropriate.
1889 *
1890 * Returns:
1891 * 0 for success, error for failure.
1892 */
1893int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1894 struct amdgpu_vm *vm,
1895 uint64_t saddr, uint64_t size)
1896{
1897 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1898 LIST_HEAD(removed);
1899 uint64_t eaddr;
1900 int r;
1901
1902 r = amdgpu_vm_verify_parameters(adev, NULL, saddr, 0, size);
1903 if (r)
1904 return r;
1905
1906 saddr /= AMDGPU_GPU_PAGE_SIZE;
1907 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1908
1909 /* Allocate all the needed memory */
1910 before = kzalloc(sizeof(*before), GFP_KERNEL);
1911 if (!before)
1912 return -ENOMEM;
1913 INIT_LIST_HEAD(&before->list);
1914
1915 after = kzalloc(sizeof(*after), GFP_KERNEL);
1916 if (!after) {
1917 kfree(before);
1918 return -ENOMEM;
1919 }
1920 INIT_LIST_HEAD(&after->list);
1921
1922 /* Now gather all removed mappings */
1923 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1924 while (tmp) {
1925 /* Remember mapping split at the start */
1926 if (tmp->start < saddr) {
1927 before->start = tmp->start;
1928 before->last = saddr - 1;
1929 before->offset = tmp->offset;
1930 before->flags = tmp->flags;
1931 before->bo_va = tmp->bo_va;
1932 list_add(&before->list, &tmp->bo_va->invalids);
1933 }
1934
1935 /* Remember mapping split at the end */
1936 if (tmp->last > eaddr) {
1937 after->start = eaddr + 1;
1938 after->last = tmp->last;
1939 after->offset = tmp->offset;
1940 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1941 after->flags = tmp->flags;
1942 after->bo_va = tmp->bo_va;
1943 list_add(&after->list, &tmp->bo_va->invalids);
1944 }
1945
1946 list_del(&tmp->list);
1947 list_add(&tmp->list, &removed);
1948
1949 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1950 }
1951
1952 /* And free them up */
1953 list_for_each_entry_safe(tmp, next, &removed, list) {
1954 amdgpu_vm_it_remove(tmp, &vm->va);
1955 list_del(&tmp->list);
1956
1957 if (tmp->start < saddr)
1958 tmp->start = saddr;
1959 if (tmp->last > eaddr)
1960 tmp->last = eaddr;
1961
1962 tmp->bo_va = NULL;
1963 list_add(&tmp->list, &vm->freed);
1964 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1965 }
1966
1967 /* Insert partial mapping before the range */
1968 if (!list_empty(&before->list)) {
1969 struct amdgpu_bo *bo = before->bo_va->base.bo;
1970
1971 amdgpu_vm_it_insert(before, &vm->va);
1972 if (before->flags & AMDGPU_PTE_PRT_FLAG(adev))
1973 amdgpu_vm_prt_get(adev);
1974
1975 if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
1976 !before->bo_va->base.moved)
1977 amdgpu_vm_bo_moved(&before->bo_va->base);
1978 } else {
1979 kfree(before);
1980 }
1981
1982 /* Insert partial mapping after the range */
1983 if (!list_empty(&after->list)) {
1984 struct amdgpu_bo *bo = after->bo_va->base.bo;
1985
1986 amdgpu_vm_it_insert(after, &vm->va);
1987 if (after->flags & AMDGPU_PTE_PRT_FLAG(adev))
1988 amdgpu_vm_prt_get(adev);
1989
1990 if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
1991 !after->bo_va->base.moved)
1992 amdgpu_vm_bo_moved(&after->bo_va->base);
1993 } else {
1994 kfree(after);
1995 }
1996
1997 return 0;
1998}
1999
2000/**
2001 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2002 *
2003 * @vm: the requested VM
2004 * @addr: the address
2005 *
2006 * Find a mapping by it's address.
2007 *
2008 * Returns:
2009 * The amdgpu_bo_va_mapping matching for addr or NULL
2010 *
2011 */
2012struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2013 uint64_t addr)
2014{
2015 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2016}
2017
2018/**
2019 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2020 *
2021 * @vm: the requested vm
2022 * @ticket: CS ticket
2023 *
2024 * Trace all mappings of BOs reserved during a command submission.
2025 */
2026void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2027{
2028 struct amdgpu_bo_va_mapping *mapping;
2029
2030 if (!trace_amdgpu_vm_bo_cs_enabled())
2031 return;
2032
2033 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2034 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2035 if (mapping->bo_va && mapping->bo_va->base.bo) {
2036 struct amdgpu_bo *bo;
2037
2038 bo = mapping->bo_va->base.bo;
2039 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2040 ticket)
2041 continue;
2042 }
2043
2044 trace_amdgpu_vm_bo_cs(mapping);
2045 }
2046}
2047
2048/**
2049 * amdgpu_vm_bo_del - remove a bo from a specific vm
2050 *
2051 * @adev: amdgpu_device pointer
2052 * @bo_va: requested bo_va
2053 *
2054 * Remove @bo_va->bo from the requested vm.
2055 *
2056 * Object have to be reserved!
2057 */
2058void amdgpu_vm_bo_del(struct amdgpu_device *adev,
2059 struct amdgpu_bo_va *bo_va)
2060{
2061 struct amdgpu_bo_va_mapping *mapping, *next;
2062 struct amdgpu_bo *bo = bo_va->base.bo;
2063 struct amdgpu_vm *vm = bo_va->base.vm;
2064 struct amdgpu_vm_bo_base **base;
2065
2066 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
2067
2068 if (bo) {
2069 dma_resv_assert_held(bo->tbo.base.resv);
2070 if (amdgpu_vm_is_bo_always_valid(vm, bo))
2071 ttm_bo_set_bulk_move(&bo->tbo, NULL);
2072
2073 for (base = &bo_va->base.bo->vm_bo; *base;
2074 base = &(*base)->next) {
2075 if (*base != &bo_va->base)
2076 continue;
2077
2078 *base = bo_va->base.next;
2079 break;
2080 }
2081 }
2082
2083 spin_lock(&vm->status_lock);
2084 list_del(&bo_va->base.vm_status);
2085 spin_unlock(&vm->status_lock);
2086
2087 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2088 list_del(&mapping->list);
2089 amdgpu_vm_it_remove(mapping, &vm->va);
2090 mapping->bo_va = NULL;
2091 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2092 list_add(&mapping->list, &vm->freed);
2093 }
2094 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2095 list_del(&mapping->list);
2096 amdgpu_vm_it_remove(mapping, &vm->va);
2097 amdgpu_vm_free_mapping(adev, vm, mapping,
2098 bo_va->last_pt_update);
2099 }
2100
2101 dma_fence_put(bo_va->last_pt_update);
2102
2103 if (bo && bo_va->is_xgmi)
2104 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2105
2106 kfree(bo_va);
2107}
2108
2109/**
2110 * amdgpu_vm_evictable - check if we can evict a VM
2111 *
2112 * @bo: A page table of the VM.
2113 *
2114 * Check if it is possible to evict a VM.
2115 */
2116bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2117{
2118 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2119
2120 /* Page tables of a destroyed VM can go away immediately */
2121 if (!bo_base || !bo_base->vm)
2122 return true;
2123
2124 /* Don't evict VM page tables while they are busy */
2125 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
2126 return false;
2127
2128 /* Try to block ongoing updates */
2129 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2130 return false;
2131
2132 /* Don't evict VM page tables while they are updated */
2133 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2134 amdgpu_vm_eviction_unlock(bo_base->vm);
2135 return false;
2136 }
2137
2138 bo_base->vm->evicting = true;
2139 amdgpu_vm_eviction_unlock(bo_base->vm);
2140 return true;
2141}
2142
2143/**
2144 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2145 *
2146 * @adev: amdgpu_device pointer
2147 * @bo: amdgpu buffer object
2148 * @evicted: is the BO evicted
2149 *
2150 * Mark @bo as invalid.
2151 */
2152void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2153 struct amdgpu_bo *bo, bool evicted)
2154{
2155 struct amdgpu_vm_bo_base *bo_base;
2156
2157 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2158 struct amdgpu_vm *vm = bo_base->vm;
2159
2160 if (evicted && amdgpu_vm_is_bo_always_valid(vm, bo)) {
2161 amdgpu_vm_bo_evicted(bo_base);
2162 continue;
2163 }
2164
2165 if (bo_base->moved)
2166 continue;
2167 bo_base->moved = true;
2168
2169 if (bo->tbo.type == ttm_bo_type_kernel)
2170 amdgpu_vm_bo_relocated(bo_base);
2171 else if (amdgpu_vm_is_bo_always_valid(vm, bo))
2172 amdgpu_vm_bo_moved(bo_base);
2173 else
2174 amdgpu_vm_bo_invalidated(bo_base);
2175 }
2176}
2177
2178/**
2179 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2180 *
2181 * @vm_size: VM size
2182 *
2183 * Returns:
2184 * VM page table as power of two
2185 */
2186static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2187{
2188 /* Total bits covered by PD + PTs */
2189 unsigned bits = ilog2(vm_size) + 18;
2190
2191 /* Make sure the PD is 4K in size up to 8GB address space.
2192 Above that split equal between PD and PTs */
2193 if (vm_size <= 8)
2194 return (bits - 9);
2195 else
2196 return ((bits + 3) / 2);
2197}
2198
2199/**
2200 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2201 *
2202 * @adev: amdgpu_device pointer
2203 * @min_vm_size: the minimum vm size in GB if it's set auto
2204 * @fragment_size_default: Default PTE fragment size
2205 * @max_level: max VMPT level
2206 * @max_bits: max address space size in bits
2207 *
2208 */
2209void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2210 uint32_t fragment_size_default, unsigned max_level,
2211 unsigned max_bits)
2212{
2213 unsigned int max_size = 1 << (max_bits - 30);
2214 unsigned int vm_size;
2215 uint64_t tmp;
2216
2217 /* adjust vm size first */
2218 if (amdgpu_vm_size != -1) {
2219 vm_size = amdgpu_vm_size;
2220 if (vm_size > max_size) {
2221 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2222 amdgpu_vm_size, max_size);
2223 vm_size = max_size;
2224 }
2225 } else {
2226 struct sysinfo si;
2227 unsigned int phys_ram_gb;
2228
2229 /* Optimal VM size depends on the amount of physical
2230 * RAM available. Underlying requirements and
2231 * assumptions:
2232 *
2233 * - Need to map system memory and VRAM from all GPUs
2234 * - VRAM from other GPUs not known here
2235 * - Assume VRAM <= system memory
2236 * - On GFX8 and older, VM space can be segmented for
2237 * different MTYPEs
2238 * - Need to allow room for fragmentation, guard pages etc.
2239 *
2240 * This adds up to a rough guess of system memory x3.
2241 * Round up to power of two to maximize the available
2242 * VM size with the given page table size.
2243 */
2244 si_meminfo(&si);
2245 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2246 (1 << 30) - 1) >> 30;
2247 vm_size = roundup_pow_of_two(
2248 clamp(phys_ram_gb * 3, min_vm_size, max_size));
2249 }
2250
2251 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2252
2253 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2254 if (amdgpu_vm_block_size != -1)
2255 tmp >>= amdgpu_vm_block_size - 9;
2256 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2257 adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
2258 switch (adev->vm_manager.num_level) {
2259 case 3:
2260 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2261 break;
2262 case 2:
2263 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2264 break;
2265 case 1:
2266 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2267 break;
2268 default:
2269 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2270 }
2271 /* block size depends on vm size and hw setup*/
2272 if (amdgpu_vm_block_size != -1)
2273 adev->vm_manager.block_size =
2274 min((unsigned)amdgpu_vm_block_size, max_bits
2275 - AMDGPU_GPU_PAGE_SHIFT
2276 - 9 * adev->vm_manager.num_level);
2277 else if (adev->vm_manager.num_level > 1)
2278 adev->vm_manager.block_size = 9;
2279 else
2280 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2281
2282 if (amdgpu_vm_fragment_size == -1)
2283 adev->vm_manager.fragment_size = fragment_size_default;
2284 else
2285 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2286
2287 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2288 vm_size, adev->vm_manager.num_level + 1,
2289 adev->vm_manager.block_size,
2290 adev->vm_manager.fragment_size);
2291}
2292
2293/**
2294 * amdgpu_vm_wait_idle - wait for the VM to become idle
2295 *
2296 * @vm: VM object to wait for
2297 * @timeout: timeout to wait for VM to become idle
2298 */
2299long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2300{
2301 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2302 DMA_RESV_USAGE_BOOKKEEP,
2303 true, timeout);
2304 if (timeout <= 0)
2305 return timeout;
2306
2307 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2308}
2309
2310static void amdgpu_vm_destroy_task_info(struct kref *kref)
2311{
2312 struct amdgpu_task_info *ti = container_of(kref, struct amdgpu_task_info, refcount);
2313
2314 kfree(ti);
2315}
2316
2317static inline struct amdgpu_vm *
2318amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid)
2319{
2320 struct amdgpu_vm *vm;
2321 unsigned long flags;
2322
2323 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2324 vm = xa_load(&adev->vm_manager.pasids, pasid);
2325 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2326
2327 return vm;
2328}
2329
2330/**
2331 * amdgpu_vm_put_task_info - reference down the vm task_info ptr
2332 *
2333 * @task_info: task_info struct under discussion.
2334 *
2335 * frees the vm task_info ptr at the last put
2336 */
2337void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info)
2338{
2339 kref_put(&task_info->refcount, amdgpu_vm_destroy_task_info);
2340}
2341
2342/**
2343 * amdgpu_vm_get_task_info_vm - Extracts task info for a vm.
2344 *
2345 * @vm: VM to get info from
2346 *
2347 * Returns the reference counted task_info structure, which must be
2348 * referenced down with amdgpu_vm_put_task_info.
2349 */
2350struct amdgpu_task_info *
2351amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm)
2352{
2353 struct amdgpu_task_info *ti = NULL;
2354
2355 if (vm) {
2356 ti = vm->task_info;
2357 kref_get(&vm->task_info->refcount);
2358 }
2359
2360 return ti;
2361}
2362
2363/**
2364 * amdgpu_vm_get_task_info_pasid - Extracts task info for a PASID.
2365 *
2366 * @adev: drm device pointer
2367 * @pasid: PASID identifier for VM
2368 *
2369 * Returns the reference counted task_info structure, which must be
2370 * referenced down with amdgpu_vm_put_task_info.
2371 */
2372struct amdgpu_task_info *
2373amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid)
2374{
2375 return amdgpu_vm_get_task_info_vm(
2376 amdgpu_vm_get_vm_from_pasid(adev, pasid));
2377}
2378
2379static int amdgpu_vm_create_task_info(struct amdgpu_vm *vm)
2380{
2381 vm->task_info = kzalloc(sizeof(struct amdgpu_task_info), GFP_KERNEL);
2382 if (!vm->task_info)
2383 return -ENOMEM;
2384
2385 kref_init(&vm->task_info->refcount);
2386 return 0;
2387}
2388
2389/**
2390 * amdgpu_vm_set_task_info - Sets VMs task info.
2391 *
2392 * @vm: vm for which to set the info
2393 */
2394void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2395{
2396 if (!vm->task_info)
2397 return;
2398
2399 if (vm->task_info->pid == current->pid)
2400 return;
2401
2402 vm->task_info->pid = current->pid;
2403 get_task_comm(vm->task_info->task_name, current);
2404
2405 if (current->group_leader->mm != current->mm)
2406 return;
2407
2408 vm->task_info->tgid = current->group_leader->pid;
2409 get_task_comm(vm->task_info->process_name, current->group_leader);
2410}
2411
2412/**
2413 * amdgpu_vm_init - initialize a vm instance
2414 *
2415 * @adev: amdgpu_device pointer
2416 * @vm: requested vm
2417 * @xcp_id: GPU partition selection id
2418 *
2419 * Init @vm fields.
2420 *
2421 * Returns:
2422 * 0 for success, error for failure.
2423 */
2424int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2425 int32_t xcp_id)
2426{
2427 struct amdgpu_bo *root_bo;
2428 struct amdgpu_bo_vm *root;
2429 int r, i;
2430
2431 vm->va = RB_ROOT_CACHED;
2432 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2433 vm->reserved_vmid[i] = NULL;
2434 INIT_LIST_HEAD(&vm->evicted);
2435 INIT_LIST_HEAD(&vm->evicted_user);
2436 INIT_LIST_HEAD(&vm->relocated);
2437 INIT_LIST_HEAD(&vm->moved);
2438 INIT_LIST_HEAD(&vm->idle);
2439 INIT_LIST_HEAD(&vm->invalidated);
2440 spin_lock_init(&vm->status_lock);
2441 INIT_LIST_HEAD(&vm->freed);
2442 INIT_LIST_HEAD(&vm->done);
2443 INIT_LIST_HEAD(&vm->pt_freed);
2444 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2445 INIT_KFIFO(vm->faults);
2446
2447 r = amdgpu_vm_init_entities(adev, vm);
2448 if (r)
2449 return r;
2450
2451 ttm_lru_bulk_move_init(&vm->lru_bulk_move);
2452
2453 vm->is_compute_context = false;
2454
2455 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2456 AMDGPU_VM_USE_CPU_FOR_GFX);
2457
2458 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2459 vm->use_cpu_for_update ? "CPU" : "SDMA");
2460 WARN_ONCE((vm->use_cpu_for_update &&
2461 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2462 "CPU update of VM recommended only for large BAR system\n");
2463
2464 if (vm->use_cpu_for_update)
2465 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2466 else
2467 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2468
2469 vm->last_update = dma_fence_get_stub();
2470 vm->last_unlocked = dma_fence_get_stub();
2471 vm->last_tlb_flush = dma_fence_get_stub();
2472 vm->generation = amdgpu_vm_generation(adev, NULL);
2473
2474 mutex_init(&vm->eviction_lock);
2475 vm->evicting = false;
2476 vm->tlb_fence_context = dma_fence_context_alloc(1);
2477
2478 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2479 false, &root, xcp_id);
2480 if (r)
2481 goto error_free_delayed;
2482
2483 root_bo = amdgpu_bo_ref(&root->bo);
2484 r = amdgpu_bo_reserve(root_bo, true);
2485 if (r) {
2486 amdgpu_bo_unref(&root_bo);
2487 goto error_free_delayed;
2488 }
2489
2490 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2491 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2492 if (r)
2493 goto error_free_root;
2494
2495 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2496 if (r)
2497 goto error_free_root;
2498
2499 r = amdgpu_vm_create_task_info(vm);
2500 if (r)
2501 DRM_DEBUG("Failed to create task info for VM\n");
2502
2503 amdgpu_bo_unreserve(vm->root.bo);
2504 amdgpu_bo_unref(&root_bo);
2505
2506 return 0;
2507
2508error_free_root:
2509 amdgpu_vm_pt_free_root(adev, vm);
2510 amdgpu_bo_unreserve(vm->root.bo);
2511 amdgpu_bo_unref(&root_bo);
2512
2513error_free_delayed:
2514 dma_fence_put(vm->last_tlb_flush);
2515 dma_fence_put(vm->last_unlocked);
2516 ttm_lru_bulk_move_fini(&adev->mman.bdev, &vm->lru_bulk_move);
2517 amdgpu_vm_fini_entities(vm);
2518
2519 return r;
2520}
2521
2522/**
2523 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2524 *
2525 * @adev: amdgpu_device pointer
2526 * @vm: requested vm
2527 *
2528 * This only works on GFX VMs that don't have any BOs added and no
2529 * page tables allocated yet.
2530 *
2531 * Changes the following VM parameters:
2532 * - use_cpu_for_update
2533 * - pte_supports_ats
2534 *
2535 * Reinitializes the page directory to reflect the changed ATS
2536 * setting.
2537 *
2538 * Returns:
2539 * 0 for success, -errno for errors.
2540 */
2541int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2542{
2543 int r;
2544
2545 r = amdgpu_bo_reserve(vm->root.bo, true);
2546 if (r)
2547 return r;
2548
2549 /* Update VM state */
2550 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2551 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2552 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2553 vm->use_cpu_for_update ? "CPU" : "SDMA");
2554 WARN_ONCE((vm->use_cpu_for_update &&
2555 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2556 "CPU update of VM recommended only for large BAR system\n");
2557
2558 if (vm->use_cpu_for_update) {
2559 /* Sync with last SDMA update/clear before switching to CPU */
2560 r = amdgpu_bo_sync_wait(vm->root.bo,
2561 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2562 if (r)
2563 goto unreserve_bo;
2564
2565 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2566 r = amdgpu_vm_pt_map_tables(adev, vm);
2567 if (r)
2568 goto unreserve_bo;
2569
2570 } else {
2571 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2572 }
2573
2574 dma_fence_put(vm->last_update);
2575 vm->last_update = dma_fence_get_stub();
2576 vm->is_compute_context = true;
2577
2578unreserve_bo:
2579 amdgpu_bo_unreserve(vm->root.bo);
2580 return r;
2581}
2582
2583/**
2584 * amdgpu_vm_release_compute - release a compute vm
2585 * @adev: amdgpu_device pointer
2586 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2587 *
2588 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2589 * pasid from vm. Compute should stop use of vm after this call.
2590 */
2591void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2592{
2593 amdgpu_vm_set_pasid(adev, vm, 0);
2594 vm->is_compute_context = false;
2595}
2596
2597/**
2598 * amdgpu_vm_fini - tear down a vm instance
2599 *
2600 * @adev: amdgpu_device pointer
2601 * @vm: requested vm
2602 *
2603 * Tear down @vm.
2604 * Unbind the VM and remove all bos from the vm bo list
2605 */
2606void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2607{
2608 struct amdgpu_bo_va_mapping *mapping, *tmp;
2609 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2610 struct amdgpu_bo *root;
2611 unsigned long flags;
2612 int i;
2613
2614 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2615
2616 flush_work(&vm->pt_free_work);
2617
2618 root = amdgpu_bo_ref(vm->root.bo);
2619 amdgpu_bo_reserve(root, true);
2620 amdgpu_vm_put_task_info(vm->task_info);
2621 amdgpu_vm_set_pasid(adev, vm, 0);
2622 dma_fence_wait(vm->last_unlocked, false);
2623 dma_fence_put(vm->last_unlocked);
2624 dma_fence_wait(vm->last_tlb_flush, false);
2625 /* Make sure that all fence callbacks have completed */
2626 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2627 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2628 dma_fence_put(vm->last_tlb_flush);
2629
2630 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2631 if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev) && prt_fini_needed) {
2632 amdgpu_vm_prt_fini(adev, vm);
2633 prt_fini_needed = false;
2634 }
2635
2636 list_del(&mapping->list);
2637 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2638 }
2639
2640 amdgpu_vm_pt_free_root(adev, vm);
2641 amdgpu_bo_unreserve(root);
2642 amdgpu_bo_unref(&root);
2643 WARN_ON(vm->root.bo);
2644
2645 amdgpu_vm_fini_entities(vm);
2646
2647 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2648 dev_err(adev->dev, "still active bo inside vm\n");
2649 }
2650 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2651 &vm->va.rb_root, rb) {
2652 /* Don't remove the mapping here, we don't want to trigger a
2653 * rebalance and the tree is about to be destroyed anyway.
2654 */
2655 list_del(&mapping->list);
2656 kfree(mapping);
2657 }
2658
2659 dma_fence_put(vm->last_update);
2660
2661 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2662 if (vm->reserved_vmid[i]) {
2663 amdgpu_vmid_free_reserved(adev, i);
2664 vm->reserved_vmid[i] = false;
2665 }
2666 }
2667
2668 ttm_lru_bulk_move_fini(&adev->mman.bdev, &vm->lru_bulk_move);
2669}
2670
2671/**
2672 * amdgpu_vm_manager_init - init the VM manager
2673 *
2674 * @adev: amdgpu_device pointer
2675 *
2676 * Initialize the VM manager structures
2677 */
2678void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2679{
2680 unsigned i;
2681
2682 /* Concurrent flushes are only possible starting with Vega10 and
2683 * are broken on Navi10 and Navi14.
2684 */
2685 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2686 adev->asic_type == CHIP_NAVI10 ||
2687 adev->asic_type == CHIP_NAVI14);
2688 amdgpu_vmid_mgr_init(adev);
2689
2690 adev->vm_manager.fence_context =
2691 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2692 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2693 adev->vm_manager.seqno[i] = 0;
2694
2695 spin_lock_init(&adev->vm_manager.prt_lock);
2696 atomic_set(&adev->vm_manager.num_prt_users, 0);
2697
2698 /* If not overridden by the user, by default, only in large BAR systems
2699 * Compute VM tables will be updated by CPU
2700 */
2701#ifdef CONFIG_X86_64
2702 if (amdgpu_vm_update_mode == -1) {
2703 /* For asic with VF MMIO access protection
2704 * avoid using CPU for VM table updates
2705 */
2706 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2707 !amdgpu_sriov_vf_mmio_access_protection(adev))
2708 adev->vm_manager.vm_update_mode =
2709 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2710 else
2711 adev->vm_manager.vm_update_mode = 0;
2712 } else
2713 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2714#else
2715 adev->vm_manager.vm_update_mode = 0;
2716#endif
2717
2718 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2719}
2720
2721/**
2722 * amdgpu_vm_manager_fini - cleanup VM manager
2723 *
2724 * @adev: amdgpu_device pointer
2725 *
2726 * Cleanup the VM manager and free resources.
2727 */
2728void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2729{
2730 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2731 xa_destroy(&adev->vm_manager.pasids);
2732
2733 amdgpu_vmid_mgr_fini(adev);
2734}
2735
2736/**
2737 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2738 *
2739 * @dev: drm device pointer
2740 * @data: drm_amdgpu_vm
2741 * @filp: drm file pointer
2742 *
2743 * Returns:
2744 * 0 for success, -errno for errors.
2745 */
2746int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2747{
2748 union drm_amdgpu_vm *args = data;
2749 struct amdgpu_device *adev = drm_to_adev(dev);
2750 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2751
2752 /* No valid flags defined yet */
2753 if (args->in.flags)
2754 return -EINVAL;
2755
2756 switch (args->in.op) {
2757 case AMDGPU_VM_OP_RESERVE_VMID:
2758 /* We only have requirement to reserve vmid from gfxhub */
2759 if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2760 amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2761 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2762 }
2763
2764 break;
2765 case AMDGPU_VM_OP_UNRESERVE_VMID:
2766 if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2767 amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2768 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2769 }
2770 break;
2771 default:
2772 return -EINVAL;
2773 }
2774
2775 return 0;
2776}
2777
2778/**
2779 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2780 * @adev: amdgpu device pointer
2781 * @pasid: PASID of the VM
2782 * @ts: Timestamp of the fault
2783 * @vmid: VMID, only used for GFX 9.4.3.
2784 * @node_id: Node_id received in IH cookie. Only applicable for
2785 * GFX 9.4.3.
2786 * @addr: Address of the fault
2787 * @write_fault: true is write fault, false is read fault
2788 *
2789 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2790 * shouldn't be reported any more.
2791 */
2792bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2793 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,
2794 bool write_fault)
2795{
2796 bool is_compute_context = false;
2797 struct amdgpu_bo *root;
2798 unsigned long irqflags;
2799 uint64_t value, flags;
2800 struct amdgpu_vm *vm;
2801 int r;
2802
2803 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2804 vm = xa_load(&adev->vm_manager.pasids, pasid);
2805 if (vm) {
2806 root = amdgpu_bo_ref(vm->root.bo);
2807 is_compute_context = vm->is_compute_context;
2808 } else {
2809 root = NULL;
2810 }
2811 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2812
2813 if (!root)
2814 return false;
2815
2816 addr /= AMDGPU_GPU_PAGE_SIZE;
2817
2818 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2819 node_id, addr, ts, write_fault)) {
2820 amdgpu_bo_unref(&root);
2821 return true;
2822 }
2823
2824 r = amdgpu_bo_reserve(root, true);
2825 if (r)
2826 goto error_unref;
2827
2828 /* Double check that the VM still exists */
2829 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2830 vm = xa_load(&adev->vm_manager.pasids, pasid);
2831 if (vm && vm->root.bo != root)
2832 vm = NULL;
2833 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2834 if (!vm)
2835 goto error_unlock;
2836
2837 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2838 AMDGPU_PTE_SYSTEM;
2839
2840 if (is_compute_context) {
2841 /* Intentionally setting invalid PTE flag
2842 * combination to force a no-retry-fault
2843 */
2844 flags = AMDGPU_VM_NORETRY_FLAGS;
2845 value = 0;
2846 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2847 /* Redirect the access to the dummy page */
2848 value = adev->dummy_page_addr;
2849 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2850 AMDGPU_PTE_WRITEABLE;
2851
2852 } else {
2853 /* Let the hw retry silently on the PTE */
2854 value = 0;
2855 }
2856
2857 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2858 if (r) {
2859 pr_debug("failed %d to reserve fence slot\n", r);
2860 goto error_unlock;
2861 }
2862
2863 r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
2864 NULL, addr, addr, flags, value, 0, NULL, NULL, NULL);
2865 if (r)
2866 goto error_unlock;
2867
2868 r = amdgpu_vm_update_pdes(adev, vm, true);
2869
2870error_unlock:
2871 amdgpu_bo_unreserve(root);
2872 if (r < 0)
2873 DRM_ERROR("Can't handle page fault (%d)\n", r);
2874
2875error_unref:
2876 amdgpu_bo_unref(&root);
2877
2878 return false;
2879}
2880
2881#if defined(CONFIG_DEBUG_FS)
2882/**
2883 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2884 *
2885 * @vm: Requested VM for printing BO info
2886 * @m: debugfs file
2887 *
2888 * Print BO information in debugfs file for the VM
2889 */
2890void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2891{
2892 struct amdgpu_bo_va *bo_va, *tmp;
2893 u64 total_idle = 0;
2894 u64 total_evicted = 0;
2895 u64 total_relocated = 0;
2896 u64 total_moved = 0;
2897 u64 total_invalidated = 0;
2898 u64 total_done = 0;
2899 unsigned int total_idle_objs = 0;
2900 unsigned int total_evicted_objs = 0;
2901 unsigned int total_relocated_objs = 0;
2902 unsigned int total_moved_objs = 0;
2903 unsigned int total_invalidated_objs = 0;
2904 unsigned int total_done_objs = 0;
2905 unsigned int id = 0;
2906
2907 spin_lock(&vm->status_lock);
2908 seq_puts(m, "\tIdle BOs:\n");
2909 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2910 if (!bo_va->base.bo)
2911 continue;
2912 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2913 }
2914 total_idle_objs = id;
2915 id = 0;
2916
2917 seq_puts(m, "\tEvicted BOs:\n");
2918 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2919 if (!bo_va->base.bo)
2920 continue;
2921 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2922 }
2923 total_evicted_objs = id;
2924 id = 0;
2925
2926 seq_puts(m, "\tRelocated BOs:\n");
2927 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2928 if (!bo_va->base.bo)
2929 continue;
2930 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2931 }
2932 total_relocated_objs = id;
2933 id = 0;
2934
2935 seq_puts(m, "\tMoved BOs:\n");
2936 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2937 if (!bo_va->base.bo)
2938 continue;
2939 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2940 }
2941 total_moved_objs = id;
2942 id = 0;
2943
2944 seq_puts(m, "\tInvalidated BOs:\n");
2945 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2946 if (!bo_va->base.bo)
2947 continue;
2948 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2949 }
2950 total_invalidated_objs = id;
2951 id = 0;
2952
2953 seq_puts(m, "\tDone BOs:\n");
2954 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2955 if (!bo_va->base.bo)
2956 continue;
2957 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2958 }
2959 spin_unlock(&vm->status_lock);
2960 total_done_objs = id;
2961
2962 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2963 total_idle_objs);
2964 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2965 total_evicted_objs);
2966 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2967 total_relocated_objs);
2968 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2969 total_moved_objs);
2970 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2971 total_invalidated_objs);
2972 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2973 total_done_objs);
2974}
2975#endif
2976
2977/**
2978 * amdgpu_vm_update_fault_cache - update cached fault into.
2979 * @adev: amdgpu device pointer
2980 * @pasid: PASID of the VM
2981 * @addr: Address of the fault
2982 * @status: GPUVM fault status register
2983 * @vmhub: which vmhub got the fault
2984 *
2985 * Cache the fault info for later use by userspace in debugging.
2986 */
2987void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
2988 unsigned int pasid,
2989 uint64_t addr,
2990 uint32_t status,
2991 unsigned int vmhub)
2992{
2993 struct amdgpu_vm *vm;
2994 unsigned long flags;
2995
2996 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2997
2998 vm = xa_load(&adev->vm_manager.pasids, pasid);
2999 /* Don't update the fault cache if status is 0. In the multiple
3000 * fault case, subsequent faults will return a 0 status which is
3001 * useless for userspace and replaces the useful fault status, so
3002 * only update if status is non-0.
3003 */
3004 if (vm && status) {
3005 vm->fault_info.addr = addr;
3006 vm->fault_info.status = status;
3007 /*
3008 * Update the fault information globally for later usage
3009 * when vm could be stale or freed.
3010 */
3011 adev->vm_manager.fault_info.addr = addr;
3012 adev->vm_manager.fault_info.vmhub = vmhub;
3013 adev->vm_manager.fault_info.status = status;
3014
3015 if (AMDGPU_IS_GFXHUB(vmhub)) {
3016 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;
3017 vm->fault_info.vmhub |=
3018 (vmhub - AMDGPU_GFXHUB_START) << AMDGPU_VMHUB_IDX_SHIFT;
3019 } else if (AMDGPU_IS_MMHUB0(vmhub)) {
3020 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM0;
3021 vm->fault_info.vmhub |=
3022 (vmhub - AMDGPU_MMHUB0_START) << AMDGPU_VMHUB_IDX_SHIFT;
3023 } else if (AMDGPU_IS_MMHUB1(vmhub)) {
3024 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM1;
3025 vm->fault_info.vmhub |=
3026 (vmhub - AMDGPU_MMHUB1_START) << AMDGPU_VMHUB_IDX_SHIFT;
3027 } else {
3028 WARN_ONCE(1, "Invalid vmhub %u\n", vmhub);
3029 }
3030 }
3031 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
3032}
3033
3034/**
3035 * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid
3036 *
3037 * @vm: VM to test against.
3038 * @bo: BO to be tested.
3039 *
3040 * Returns true if the BO shares the dma_resv object with the root PD and is
3041 * always guaranteed to be valid inside the VM.
3042 */
3043bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo)
3044{
3045 return bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv;
3046}