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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
4 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
5 * Copyright (C) 2004 Maciej W. Rozycki
6 */
7#include <linux/delay.h>
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/seq_file.h>
11#include <asm/bootinfo.h>
12#include <asm/cpu.h>
13#include <asm/cpu-features.h>
14#include <asm/idle.h>
15#include <asm/mipsregs.h>
16#include <asm/processor.h>
17#include <asm/prom.h>
18
19unsigned int vced_count, vcei_count;
20
21/*
22 * * No lock; only written during early bootup by CPU 0.
23 * */
24static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain);
25
26int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb)
27{
28 return raw_notifier_chain_register(&proc_cpuinfo_chain, nb);
29}
30
31int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
32{
33 return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
34}
35
36static int show_cpuinfo(struct seq_file *m, void *v)
37{
38 struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
39 unsigned long n = (unsigned long) v - 1;
40 unsigned int version = cpu_data[n].processor_id;
41 unsigned int fp_vers = cpu_data[n].fpu_id;
42 char fmt [64];
43 int i;
44
45#ifdef CONFIG_SMP
46 if (!cpu_online(n))
47 return 0;
48#endif
49
50 /*
51 * For the first processor also print the system type
52 */
53 if (n == 0) {
54 seq_printf(m, "system type\t\t: %s\n", get_system_type());
55 if (mips_get_machine_name())
56 seq_printf(m, "machine\t\t\t: %s\n",
57 mips_get_machine_name());
58 }
59
60 seq_printf(m, "processor\t\t: %ld\n", n);
61 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
62 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
63 seq_printf(m, fmt, __cpu_name[n],
64 (version >> 4) & 0x0f, version & 0x0f,
65 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
66 seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
67 cpu_data[n].udelay_val / (500000/HZ),
68 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
69 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
70 seq_printf(m, "microsecond timers\t: %s\n",
71 cpu_has_counter ? "yes" : "no");
72 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
73 seq_printf(m, "extra interrupt vector\t: %s\n",
74 cpu_has_divec ? "yes" : "no");
75 seq_printf(m, "hardware watchpoint\t: %s",
76 cpu_has_watch ? "yes, " : "no\n");
77 if (cpu_has_watch) {
78 seq_printf(m, "count: %d, address/irw mask: [",
79 cpu_data[n].watch_reg_count);
80 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
81 seq_printf(m, "%s0x%04x", i ? ", " : "" ,
82 cpu_data[n].watch_reg_masks[i]);
83 seq_printf(m, "]\n");
84 }
85
86 seq_printf(m, "isa\t\t\t:");
87 if (cpu_has_mips_1)
88 seq_printf(m, " mips1");
89 if (cpu_has_mips_2)
90 seq_printf(m, "%s", " mips2");
91 if (cpu_has_mips_3)
92 seq_printf(m, "%s", " mips3");
93 if (cpu_has_mips_4)
94 seq_printf(m, "%s", " mips4");
95 if (cpu_has_mips_5)
96 seq_printf(m, "%s", " mips5");
97 if (cpu_has_mips32r1)
98 seq_printf(m, "%s", " mips32r1");
99 if (cpu_has_mips32r2)
100 seq_printf(m, "%s", " mips32r2");
101 if (cpu_has_mips32r5)
102 seq_printf(m, "%s", " mips32r5");
103 if (cpu_has_mips32r6)
104 seq_printf(m, "%s", " mips32r6");
105 if (cpu_has_mips64r1)
106 seq_printf(m, "%s", " mips64r1");
107 if (cpu_has_mips64r2)
108 seq_printf(m, "%s", " mips64r2");
109 if (cpu_has_mips64r5)
110 seq_printf(m, "%s", " mips64r5");
111 if (cpu_has_mips64r6)
112 seq_printf(m, "%s", " mips64r6");
113 seq_printf(m, "\n");
114
115 seq_printf(m, "ASEs implemented\t:");
116 if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
117 if (cpu_has_mips16e2) seq_printf(m, "%s", " mips16e2");
118 if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx");
119 if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d");
120 if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips");
121 if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
122 if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
123 if (cpu_has_dsp3) seq_printf(m, "%s", " dsp3");
124 if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
125 if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
126 if (cpu_has_vz) seq_printf(m, "%s", " vz");
127 if (cpu_has_msa) seq_printf(m, "%s", " msa");
128 if (cpu_has_eva) seq_printf(m, "%s", " eva");
129 if (cpu_has_htw) seq_printf(m, "%s", " htw");
130 if (cpu_has_xpa) seq_printf(m, "%s", " xpa");
131 if (cpu_has_loongson_mmi) seq_printf(m, "%s", " loongson-mmi");
132 if (cpu_has_loongson_cam) seq_printf(m, "%s", " loongson-cam");
133 if (cpu_has_loongson_ext) seq_printf(m, "%s", " loongson-ext");
134 if (cpu_has_loongson_ext2) seq_printf(m, "%s", " loongson-ext2");
135 seq_printf(m, "\n");
136
137 if (cpu_has_mmips) {
138 seq_printf(m, "micromips kernel\t: %s\n",
139 (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no");
140 }
141 seq_printf(m, "shadow register sets\t: %d\n",
142 cpu_data[n].srsets);
143 seq_printf(m, "kscratch registers\t: %d\n",
144 hweight8(cpu_data[n].kscratch_mask));
145 seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
146 seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
147
148#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
149 if (cpu_has_mipsmt)
150 seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
151 else if (cpu_has_vp)
152 seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
153#endif
154
155 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
156 cpu_has_vce ? "%u" : "not available");
157 seq_printf(m, fmt, 'D', vced_count);
158 seq_printf(m, fmt, 'I', vcei_count);
159
160 proc_cpuinfo_notifier_args.m = m;
161 proc_cpuinfo_notifier_args.n = n;
162
163 raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
164 &proc_cpuinfo_notifier_args);
165
166 seq_printf(m, "\n");
167
168 return 0;
169}
170
171static void *c_start(struct seq_file *m, loff_t *pos)
172{
173 unsigned long i = *pos;
174
175 return i < NR_CPUS ? (void *) (i + 1) : NULL;
176}
177
178static void *c_next(struct seq_file *m, void *v, loff_t *pos)
179{
180 ++*pos;
181 return c_start(m, pos);
182}
183
184static void c_stop(struct seq_file *m, void *v)
185{
186}
187
188const struct seq_operations cpuinfo_op = {
189 .start = c_start,
190 .next = c_next,
191 .stop = c_stop,
192 .show = show_cpuinfo,
193};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
4 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
5 * Copyright (C) 2004 Maciej W. Rozycki
6 */
7#include <linux/delay.h>
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/seq_file.h>
11#include <asm/bootinfo.h>
12#include <asm/cpu.h>
13#include <asm/cpu-features.h>
14#include <asm/idle.h>
15#include <asm/mipsregs.h>
16#include <asm/processor.h>
17#include <asm/prom.h>
18
19unsigned int vced_count, vcei_count;
20
21/*
22 * No lock; only written during early bootup by CPU 0.
23 */
24static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain);
25
26int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb)
27{
28 return raw_notifier_chain_register(&proc_cpuinfo_chain, nb);
29}
30
31int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
32{
33 return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
34}
35
36static int show_cpuinfo(struct seq_file *m, void *v)
37{
38 struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
39 unsigned long n = (unsigned long) v - 1;
40 unsigned int version = cpu_data[n].processor_id;
41 unsigned int fp_vers = cpu_data[n].fpu_id;
42 char fmt[64];
43 int i;
44
45#ifdef CONFIG_SMP
46 if (!cpu_online(n))
47 return 0;
48#endif
49
50 /*
51 * For the first processor also print the system type
52 */
53 if (n == 0) {
54 seq_printf(m, "system type\t\t: %s\n", get_system_type());
55 if (mips_get_machine_name())
56 seq_printf(m, "machine\t\t\t: %s\n",
57 mips_get_machine_name());
58 }
59
60 seq_printf(m, "processor\t\t: %ld\n", n);
61 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
62 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
63 seq_printf(m, fmt, __cpu_name[n],
64 (version >> 4) & 0x0f, version & 0x0f,
65 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
66 seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
67 cpu_data[n].udelay_val / (500000/HZ),
68 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
69 seq_printf(m, "wait instruction\t: %s\n", str_yes_no(cpu_wait));
70 seq_printf(m, "microsecond timers\t: %s\n",
71 str_yes_no(cpu_has_counter));
72 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
73 seq_printf(m, "extra interrupt vector\t: %s\n",
74 str_yes_no(cpu_has_divec));
75 seq_printf(m, "hardware watchpoint\t: %s", str_yes_no(cpu_has_watch));
76 if (cpu_has_watch) {
77 seq_printf(m, ", count: %d, address/irw mask: [",
78 cpu_data[n].watch_reg_count);
79 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
80 seq_printf(m, "%s0x%04x", i ? ", " : "",
81 cpu_data[n].watch_reg_masks[i]);
82 seq_puts(m, "]");
83 }
84
85 seq_puts(m, "\nisa\t\t\t:");
86 if (cpu_has_mips_1)
87 seq_puts(m, " mips1");
88 if (cpu_has_mips_2)
89 seq_puts(m, " mips2");
90 if (cpu_has_mips_3)
91 seq_puts(m, " mips3");
92 if (cpu_has_mips_4)
93 seq_puts(m, " mips4");
94 if (cpu_has_mips_5)
95 seq_puts(m, " mips5");
96 if (cpu_has_mips32r1)
97 seq_puts(m, " mips32r1");
98 if (cpu_has_mips32r2)
99 seq_puts(m, " mips32r2");
100 if (cpu_has_mips32r5)
101 seq_puts(m, " mips32r5");
102 if (cpu_has_mips32r6)
103 seq_puts(m, " mips32r6");
104 if (cpu_has_mips64r1)
105 seq_puts(m, " mips64r1");
106 if (cpu_has_mips64r2)
107 seq_puts(m, " mips64r2");
108 if (cpu_has_mips64r5)
109 seq_puts(m, " mips64r5");
110 if (cpu_has_mips64r6)
111 seq_puts(m, " mips64r6");
112 seq_puts(m, "\n");
113
114 seq_puts(m, "ASEs implemented\t:");
115 if (cpu_has_mips16)
116 seq_puts(m, " mips16");
117 if (cpu_has_mips16e2)
118 seq_puts(m, " mips16e2");
119 if (cpu_has_mdmx)
120 seq_puts(m, " mdmx");
121 if (cpu_has_mips3d)
122 seq_puts(m, " mips3d");
123 if (cpu_has_smartmips)
124 seq_puts(m, " smartmips");
125 if (cpu_has_dsp)
126 seq_puts(m, " dsp");
127 if (cpu_has_dsp2)
128 seq_puts(m, " dsp2");
129 if (cpu_has_dsp3)
130 seq_puts(m, " dsp3");
131 if (cpu_has_mipsmt)
132 seq_puts(m, " mt");
133 if (cpu_has_mmips)
134 seq_puts(m, " micromips");
135 if (cpu_has_vz)
136 seq_puts(m, " vz");
137 if (cpu_has_msa)
138 seq_puts(m, " msa");
139 if (cpu_has_eva)
140 seq_puts(m, " eva");
141 if (cpu_has_htw)
142 seq_puts(m, " htw");
143 if (cpu_has_xpa)
144 seq_puts(m, " xpa");
145 if (cpu_has_loongson_mmi)
146 seq_puts(m, " loongson-mmi");
147 if (cpu_has_loongson_cam)
148 seq_puts(m, " loongson-cam");
149 if (cpu_has_loongson_ext)
150 seq_puts(m, " loongson-ext");
151 if (cpu_has_loongson_ext2)
152 seq_puts(m, " loongson-ext2");
153 seq_puts(m, "\n");
154
155 if (cpu_has_mmips) {
156 seq_printf(m, "micromips kernel\t: %s\n",
157 str_yes_no(read_c0_config3() & MIPS_CONF3_ISA_OE));
158 }
159
160 seq_puts(m, "Options implemented\t:");
161 if (cpu_has_tlb)
162 seq_puts(m, " tlb");
163 if (cpu_has_ftlb)
164 seq_puts(m, " ftlb");
165 if (cpu_has_tlbinv)
166 seq_puts(m, " tlbinv");
167 if (cpu_has_segments)
168 seq_puts(m, " segments");
169 if (cpu_has_rixiex)
170 seq_puts(m, " rixiex");
171 if (cpu_has_ldpte)
172 seq_puts(m, " ldpte");
173 if (cpu_has_maar)
174 seq_puts(m, " maar");
175 if (cpu_has_rw_llb)
176 seq_puts(m, " rw_llb");
177 if (cpu_has_4kex)
178 seq_puts(m, " 4kex");
179 if (cpu_has_3k_cache)
180 seq_puts(m, " 3k_cache");
181 if (cpu_has_4k_cache)
182 seq_puts(m, " 4k_cache");
183 if (cpu_has_octeon_cache)
184 seq_puts(m, " octeon_cache");
185 if (raw_cpu_has_fpu)
186 seq_puts(m, " fpu");
187 if (cpu_has_32fpr)
188 seq_puts(m, " 32fpr");
189 if (cpu_has_cache_cdex_p)
190 seq_puts(m, " cache_cdex_p");
191 if (cpu_has_cache_cdex_s)
192 seq_puts(m, " cache_cdex_s");
193 if (cpu_has_prefetch)
194 seq_puts(m, " prefetch");
195 if (cpu_has_mcheck)
196 seq_puts(m, " mcheck");
197 if (cpu_has_ejtag)
198 seq_puts(m, " ejtag");
199 if (cpu_has_llsc)
200 seq_puts(m, " llsc");
201 if (cpu_has_guestctl0ext)
202 seq_puts(m, " guestctl0ext");
203 if (cpu_has_guestctl1)
204 seq_puts(m, " guestctl1");
205 if (cpu_has_guestctl2)
206 seq_puts(m, " guestctl2");
207 if (cpu_has_guestid)
208 seq_puts(m, " guestid");
209 if (cpu_has_drg)
210 seq_puts(m, " drg");
211 if (cpu_has_rixi)
212 seq_puts(m, " rixi");
213 if (cpu_has_lpa)
214 seq_puts(m, " lpa");
215 if (cpu_has_mvh)
216 seq_puts(m, " mvh");
217 if (cpu_has_vtag_icache)
218 seq_puts(m, " vtag_icache");
219 if (cpu_has_dc_aliases)
220 seq_puts(m, " dc_aliases");
221 if (cpu_has_ic_fills_f_dc)
222 seq_puts(m, " ic_fills_f_dc");
223 if (cpu_has_pindexed_dcache)
224 seq_puts(m, " pindexed_dcache");
225 if (cpu_has_userlocal)
226 seq_puts(m, " userlocal");
227 if (cpu_has_nofpuex)
228 seq_puts(m, " nofpuex");
229 if (cpu_has_vint)
230 seq_puts(m, " vint");
231 if (cpu_has_veic)
232 seq_puts(m, " veic");
233 if (cpu_has_inclusive_pcaches)
234 seq_puts(m, " inclusive_pcaches");
235 if (cpu_has_perf_cntr_intr_bit)
236 seq_puts(m, " perf_cntr_intr_bit");
237 if (cpu_has_ufr)
238 seq_puts(m, " ufr");
239 if (cpu_has_fre)
240 seq_puts(m, " fre");
241 if (cpu_has_cdmm)
242 seq_puts(m, " cdmm");
243 if (cpu_has_small_pages)
244 seq_puts(m, " small_pages");
245 if (cpu_has_nan_legacy)
246 seq_puts(m, " nan_legacy");
247 if (cpu_has_nan_2008)
248 seq_puts(m, " nan_2008");
249 if (cpu_has_ebase_wg)
250 seq_puts(m, " ebase_wg");
251 if (cpu_has_badinstr)
252 seq_puts(m, " badinstr");
253 if (cpu_has_badinstrp)
254 seq_puts(m, " badinstrp");
255 if (cpu_has_contextconfig)
256 seq_puts(m, " contextconfig");
257 if (cpu_has_perf)
258 seq_puts(m, " perf");
259 if (cpu_has_mac2008_only)
260 seq_puts(m, " mac2008_only");
261 if (cpu_has_ftlbparex)
262 seq_puts(m, " ftlbparex");
263 if (cpu_has_gsexcex)
264 seq_puts(m, " gsexcex");
265 if (cpu_has_shared_ftlb_ram)
266 seq_puts(m, " shared_ftlb_ram");
267 if (cpu_has_shared_ftlb_entries)
268 seq_puts(m, " shared_ftlb_entries");
269 if (cpu_has_mipsmt_pertccounters)
270 seq_puts(m, " mipsmt_pertccounters");
271 if (cpu_has_mmid)
272 seq_puts(m, " mmid");
273 if (cpu_has_mm_sysad)
274 seq_puts(m, " mm_sysad");
275 if (cpu_has_mm_full)
276 seq_puts(m, " mm_full");
277 seq_puts(m, "\n");
278
279 seq_printf(m, "shadow register sets\t: %d\n",
280 cpu_data[n].srsets);
281 seq_printf(m, "kscratch registers\t: %d\n",
282 hweight8(cpu_data[n].kscratch_mask));
283 seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
284 seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
285
286#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
287 if (cpu_has_mipsmt)
288 seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
289 else if (cpu_has_vp)
290 seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
291#endif
292
293 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
294 cpu_has_vce ? "%u" : "not available");
295 seq_printf(m, fmt, 'D', vced_count);
296 seq_printf(m, fmt, 'I', vcei_count);
297
298 proc_cpuinfo_notifier_args.m = m;
299 proc_cpuinfo_notifier_args.n = n;
300
301 raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
302 &proc_cpuinfo_notifier_args);
303
304 seq_puts(m, "\n");
305
306 return 0;
307}
308
309static void *c_start(struct seq_file *m, loff_t *pos)
310{
311 unsigned long i = *pos;
312
313 return i < nr_cpu_ids ? (void *) (i + 1) : NULL;
314}
315
316static void *c_next(struct seq_file *m, void *v, loff_t *pos)
317{
318 ++*pos;
319 return c_start(m, pos);
320}
321
322static void c_stop(struct seq_file *m, void *v)
323{
324}
325
326const struct seq_operations cpuinfo_op = {
327 .start = c_start,
328 .next = c_next,
329 .stop = c_stop,
330 .show = show_cpuinfo,
331};