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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
4 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
5 * Takashi Iwai <tiwai@suse.de>
6 *
7 * Most of the driver code comes from Zach Brown(zab@redhat.com)
8 * Alan Cox OSS Driver
9 * Rewritted from card-es1938.c source.
10 *
11 * TODO:
12 * Perhaps Synth
13 *
14 * Notes from Zach Brown about the driver code
15 *
16 * Hardware Description
17 *
18 * A working Maestro setup contains the Maestro chip wired to a
19 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
20 * Wavecache. The APUs can be though of as virtual audio routing
21 * channels. They can take data from a number of sources and perform
22 * basic encodings of the data. The wavecache is a storehouse for
23 * PCM data. Typically it deals with PCI and interracts with the
24 * APUs. The ASSP is a wacky DSP like device that ESS is loth
25 * to release docs on. Thankfully it isn't required on the Maestro
26 * until you start doing insane things like FM emulation and surround
27 * encoding. The codecs are almost always AC-97 compliant codecs,
28 * but it appears that early Maestros may have had PT101 (an ESS
29 * part?) wired to them. The only real difference in the Maestro
30 * families is external goop like docking capability, memory for
31 * the ASSP, and initialization differences.
32 *
33 * Driver Operation
34 *
35 * We only drive the APU/Wavecache as typical DACs and drive the
36 * mixers in the codecs. There are 64 APUs. We assign 6 to each
37 * /dev/dsp? device. 2 channels for output, and 4 channels for
38 * input.
39 *
40 * Each APU can do a number of things, but we only really use
41 * 3 basic functions. For playback we use them to convert PCM
42 * data fetched over PCI by the wavecahche into analog data that
43 * is handed to the codec. One APU for mono, and a pair for stereo.
44 * When in stereo, the combination of smarts in the APU and Wavecache
45 * decide which wavecache gets the left or right channel.
46 *
47 * For record we still use the old overly mono system. For each in
48 * coming channel the data comes in from the codec, through a 'input'
49 * APU, through another rate converter APU, and then into memory via
50 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
51 * software. The pass between the 2 APUs is supposedly what requires us
52 * to have a 512 byte buffer sitting around in wavecache/memory.
53 *
54 * The wavecache makes our life even more fun. First off, it can
55 * only address the first 28 bits of PCI address space, making it
56 * useless on quite a few architectures. Secondly, its insane.
57 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
58 * But that doesn't really work. You can only use 1 region. So all our
59 * allocations have to be in 4meg of each other. Booo. Hiss.
60 * So we have a module parameter, dsps_order, that is the order of
61 * the number of dsps to provide. All their buffer space is allocated
62 * on open time. The sonicvibes OSS routines we inherited really want
63 * power of 2 buffers, so we have all those next to each other, then
64 * 512 byte regions for the recording wavecaches. This ends up
65 * wasting quite a bit of memory. The only fixes I can see would be
66 * getting a kernel allocator that could work in zones, or figuring out
67 * just how to coerce the WP into doing what we want.
68 *
69 * The indirection of the various registers means we have to spinlock
70 * nearly all register accesses. We have the main register indirection
71 * like the wave cache, maestro registers, etc. Then we have beasts
72 * like the APU interface that is indirect registers gotten at through
73 * the main maestro indirection. Ouch. We spinlock around the actual
74 * ports on a per card basis. This means spinlock activity at each IO
75 * operation, but the only IO operation clusters are in non critical
76 * paths and it makes the code far easier to follow. Interrupts are
77 * blocked while holding the locks because the int handler has to
78 * get at some of them :(. The mixer interface doesn't, however.
79 * We also have an OSS state lock that is thrown around in a few
80 * places.
81 */
82
83#include <linux/io.h>
84#include <linux/delay.h>
85#include <linux/interrupt.h>
86#include <linux/init.h>
87#include <linux/pci.h>
88#include <linux/dma-mapping.h>
89#include <linux/slab.h>
90#include <linux/gameport.h>
91#include <linux/module.h>
92#include <linux/mutex.h>
93#include <linux/input.h>
94
95#include <sound/core.h>
96#include <sound/pcm.h>
97#include <sound/mpu401.h>
98#include <sound/ac97_codec.h>
99#include <sound/initval.h>
100
101#ifdef CONFIG_SND_ES1968_RADIO
102#include <media/drv-intf/tea575x.h>
103#endif
104
105#define CARD_NAME "ESS Maestro1/2"
106#define DRIVER_NAME "ES1968"
107
108MODULE_DESCRIPTION("ESS Maestro");
109MODULE_LICENSE("GPL");
110
111#if IS_REACHABLE(CONFIG_GAMEPORT)
112#define SUPPORT_JOYSTICK 1
113#endif
114
115static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
116static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
117static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
118static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
119static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
120static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
121static int clock[SNDRV_CARDS];
122static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
123static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
124#ifdef SUPPORT_JOYSTICK
125static bool joystick[SNDRV_CARDS];
126#endif
127static int radio_nr[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
128
129module_param_array(index, int, NULL, 0444);
130MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
131module_param_array(id, charp, NULL, 0444);
132MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
133module_param_array(enable, bool, NULL, 0444);
134MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
135module_param_array(total_bufsize, int, NULL, 0444);
136MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
137module_param_array(pcm_substreams_p, int, NULL, 0444);
138MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
139module_param_array(pcm_substreams_c, int, NULL, 0444);
140MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
141module_param_array(clock, int, NULL, 0444);
142MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
143module_param_array(use_pm, int, NULL, 0444);
144MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
145module_param_array(enable_mpu, int, NULL, 0444);
146MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
147#ifdef SUPPORT_JOYSTICK
148module_param_array(joystick, bool, NULL, 0444);
149MODULE_PARM_DESC(joystick, "Enable joystick.");
150#endif
151module_param_array(radio_nr, int, NULL, 0444);
152MODULE_PARM_DESC(radio_nr, "Radio device numbers");
153
154
155
156#define NR_APUS 64
157#define NR_APU_REGS 16
158
159/* NEC Versas ? */
160#define NEC_VERSA_SUBID1 0x80581033
161#define NEC_VERSA_SUBID2 0x803c1033
162
163/* Mode Flags */
164#define ESS_FMT_STEREO 0x01
165#define ESS_FMT_16BIT 0x02
166
167#define DAC_RUNNING 1
168#define ADC_RUNNING 2
169
170/* Values for the ESM_LEGACY_AUDIO_CONTROL */
171
172#define ESS_DISABLE_AUDIO 0x8000
173#define ESS_ENABLE_SERIAL_IRQ 0x4000
174#define IO_ADRESS_ALIAS 0x0020
175#define MPU401_IRQ_ENABLE 0x0010
176#define MPU401_IO_ENABLE 0x0008
177#define GAME_IO_ENABLE 0x0004
178#define FM_IO_ENABLE 0x0002
179#define SB_IO_ENABLE 0x0001
180
181/* Values for the ESM_CONFIG_A */
182
183#define PIC_SNOOP1 0x4000
184#define PIC_SNOOP2 0x2000
185#define SAFEGUARD 0x0800
186#define DMA_CLEAR 0x0700
187#define DMA_DDMA 0x0000
188#define DMA_TDMA 0x0100
189#define DMA_PCPCI 0x0200
190#define POST_WRITE 0x0080
191#define PCI_TIMING 0x0040
192#define SWAP_LR 0x0020
193#define SUBTR_DECODE 0x0002
194
195/* Values for the ESM_CONFIG_B */
196
197#define SPDIF_CONFB 0x0100
198#define HWV_CONFB 0x0080
199#define DEBOUNCE 0x0040
200#define GPIO_CONFB 0x0020
201#define CHI_CONFB 0x0010
202#define IDMA_CONFB 0x0008 /*undoc */
203#define MIDI_FIX 0x0004 /*undoc */
204#define IRQ_TO_ISA 0x0001 /*undoc */
205
206/* Values for Ring Bus Control B */
207#define RINGB_2CODEC_ID_MASK 0x0003
208#define RINGB_DIS_VALIDATION 0x0008
209#define RINGB_EN_SPDIF 0x0010
210#define RINGB_EN_2CODEC 0x0020
211#define RINGB_SING_BIT_DUAL 0x0040
212
213/* ****Port Addresses**** */
214
215/* Write & Read */
216#define ESM_INDEX 0x02
217#define ESM_DATA 0x00
218
219/* AC97 + RingBus */
220#define ESM_AC97_INDEX 0x30
221#define ESM_AC97_DATA 0x32
222#define ESM_RING_BUS_DEST 0x34
223#define ESM_RING_BUS_CONTR_A 0x36
224#define ESM_RING_BUS_CONTR_B 0x38
225#define ESM_RING_BUS_SDO 0x3A
226
227/* WaveCache*/
228#define WC_INDEX 0x10
229#define WC_DATA 0x12
230#define WC_CONTROL 0x14
231
232/* ASSP*/
233#define ASSP_INDEX 0x80
234#define ASSP_MEMORY 0x82
235#define ASSP_DATA 0x84
236#define ASSP_CONTROL_A 0xA2
237#define ASSP_CONTROL_B 0xA4
238#define ASSP_CONTROL_C 0xA6
239#define ASSP_HOSTW_INDEX 0xA8
240#define ASSP_HOSTW_DATA 0xAA
241#define ASSP_HOSTW_IRQ 0xAC
242/* Midi */
243#define ESM_MPU401_PORT 0x98
244/* Others */
245#define ESM_PORT_HOST_IRQ 0x18
246
247#define IDR0_DATA_PORT 0x00
248#define IDR1_CRAM_POINTER 0x01
249#define IDR2_CRAM_DATA 0x02
250#define IDR3_WAVE_DATA 0x03
251#define IDR4_WAVE_PTR_LOW 0x04
252#define IDR5_WAVE_PTR_HI 0x05
253#define IDR6_TIMER_CTRL 0x06
254#define IDR7_WAVE_ROMRAM 0x07
255
256#define WRITEABLE_MAP 0xEFFFFF
257#define READABLE_MAP 0x64003F
258
259/* PCI Register */
260
261#define ESM_LEGACY_AUDIO_CONTROL 0x40
262#define ESM_ACPI_COMMAND 0x54
263#define ESM_CONFIG_A 0x50
264#define ESM_CONFIG_B 0x52
265#define ESM_DDMA 0x60
266
267/* Bob Bits */
268#define ESM_BOB_ENABLE 0x0001
269#define ESM_BOB_START 0x0001
270
271/* Host IRQ Control Bits */
272#define ESM_RESET_MAESTRO 0x8000
273#define ESM_RESET_DIRECTSOUND 0x4000
274#define ESM_HIRQ_ClkRun 0x0100
275#define ESM_HIRQ_HW_VOLUME 0x0040
276#define ESM_HIRQ_HARPO 0x0030 /* What's that? */
277#define ESM_HIRQ_ASSP 0x0010
278#define ESM_HIRQ_DSIE 0x0004
279#define ESM_HIRQ_MPU401 0x0002
280#define ESM_HIRQ_SB 0x0001
281
282/* Host IRQ Status Bits */
283#define ESM_MPU401_IRQ 0x02
284#define ESM_SB_IRQ 0x01
285#define ESM_SOUND_IRQ 0x04
286#define ESM_ASSP_IRQ 0x10
287#define ESM_HWVOL_IRQ 0x40
288
289#define ESS_SYSCLK 50000000
290#define ESM_BOB_FREQ 200
291#define ESM_BOB_FREQ_MAX 800
292
293#define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
294#define ESM_FREQ_ESM2 (50000000L / 1024L)
295
296/* APU Modes: reg 0x00, bit 4-7 */
297#define ESM_APU_MODE_SHIFT 4
298#define ESM_APU_MODE_MASK (0xf << 4)
299#define ESM_APU_OFF 0x00
300#define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
301#define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
302#define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
303#define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
304#define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
305#define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
306#define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
307#define ESM_APU_CORRELATOR 0x08 /* Correlator */
308#define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
309#define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
310#define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
311#define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
312#define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
313#define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
314#define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
315
316/* reg 0x00 */
317#define ESM_APU_FILTER_Q_SHIFT 0
318#define ESM_APU_FILTER_Q_MASK (3 << 0)
319/* APU Filtey Q Control */
320#define ESM_APU_FILTER_LESSQ 0x00
321#define ESM_APU_FILTER_MOREQ 0x03
322
323#define ESM_APU_FILTER_TYPE_SHIFT 2
324#define ESM_APU_FILTER_TYPE_MASK (3 << 2)
325#define ESM_APU_ENV_TYPE_SHIFT 8
326#define ESM_APU_ENV_TYPE_MASK (3 << 8)
327#define ESM_APU_ENV_STATE_SHIFT 10
328#define ESM_APU_ENV_STATE_MASK (3 << 10)
329#define ESM_APU_END_CURVE (1 << 12)
330#define ESM_APU_INT_ON_LOOP (1 << 13)
331#define ESM_APU_DMA_ENABLE (1 << 14)
332
333/* reg 0x02 */
334#define ESM_APU_SUBMIX_GROUP_SHIRT 0
335#define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
336#define ESM_APU_SUBMIX_MODE (1 << 3)
337#define ESM_APU_6dB (1 << 4)
338#define ESM_APU_DUAL_EFFECT (1 << 5)
339#define ESM_APU_EFFECT_CHANNELS_SHIFT 6
340#define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
341
342/* reg 0x03 */
343#define ESM_APU_STEP_SIZE_MASK 0x0fff
344
345/* reg 0x04 */
346#define ESM_APU_PHASE_SHIFT 0
347#define ESM_APU_PHASE_MASK (0xff << 0)
348#define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
349#define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
350
351/* reg 0x05 - wave start offset */
352/* reg 0x06 - wave end offset */
353/* reg 0x07 - wave loop length */
354
355/* reg 0x08 */
356#define ESM_APU_EFFECT_GAIN_SHIFT 0
357#define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
358#define ESM_APU_TREMOLO_DEPTH_SHIFT 8
359#define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
360#define ESM_APU_TREMOLO_RATE_SHIFT 12
361#define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
362
363/* reg 0x09 */
364/* bit 0-7 amplitude dest? */
365#define ESM_APU_AMPLITUDE_NOW_SHIFT 8
366#define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
367
368/* reg 0x0a */
369#define ESM_APU_POLAR_PAN_SHIFT 0
370#define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
371/* Polar Pan Control */
372#define ESM_APU_PAN_CENTER_CIRCLE 0x00
373#define ESM_APU_PAN_MIDDLE_RADIUS 0x01
374#define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
375
376#define ESM_APU_FILTER_TUNING_SHIFT 8
377#define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
378
379/* reg 0x0b */
380#define ESM_APU_DATA_SRC_A_SHIFT 0
381#define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
382#define ESM_APU_INV_POL_A (1 << 7)
383#define ESM_APU_DATA_SRC_B_SHIFT 8
384#define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
385#define ESM_APU_INV_POL_B (1 << 15)
386
387#define ESM_APU_VIBRATO_RATE_SHIFT 0
388#define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
389#define ESM_APU_VIBRATO_DEPTH_SHIFT 4
390#define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
391#define ESM_APU_VIBRATO_PHASE_SHIFT 8
392#define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
393
394/* reg 0x0c */
395#define ESM_APU_RADIUS_SELECT (1 << 6)
396
397/* APU Filter Control */
398#define ESM_APU_FILTER_2POLE_LOPASS 0x00
399#define ESM_APU_FILTER_2POLE_BANDPASS 0x01
400#define ESM_APU_FILTER_2POLE_HIPASS 0x02
401#define ESM_APU_FILTER_1POLE_LOPASS 0x03
402#define ESM_APU_FILTER_1POLE_HIPASS 0x04
403#define ESM_APU_FILTER_OFF 0x05
404
405/* APU ATFP Type */
406#define ESM_APU_ATFP_AMPLITUDE 0x00
407#define ESM_APU_ATFP_TREMELO 0x01
408#define ESM_APU_ATFP_FILTER 0x02
409#define ESM_APU_ATFP_PAN 0x03
410
411/* APU ATFP Flags */
412#define ESM_APU_ATFP_FLG_OFF 0x00
413#define ESM_APU_ATFP_FLG_WAIT 0x01
414#define ESM_APU_ATFP_FLG_DONE 0x02
415#define ESM_APU_ATFP_FLG_INPROCESS 0x03
416
417
418/* capture mixing buffer size */
419#define ESM_MEM_ALIGN 0x1000
420#define ESM_MIXBUF_SIZE 0x400
421
422#define ESM_MODE_PLAY 0
423#define ESM_MODE_CAPTURE 1
424
425
426/* APU use in the driver */
427enum snd_enum_apu_type {
428 ESM_APU_PCM_PLAY,
429 ESM_APU_PCM_CAPTURE,
430 ESM_APU_PCM_RATECONV,
431 ESM_APU_FREE
432};
433
434/* chip type */
435enum {
436 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
437};
438
439/* DMA Hack! */
440struct esm_memory {
441 struct snd_dma_buffer buf;
442 int empty; /* status */
443 struct list_head list;
444};
445
446/* Playback Channel */
447struct esschan {
448 int running;
449
450 u8 apu[4];
451 u8 apu_mode[4];
452
453 /* playback/capture pcm buffer */
454 struct esm_memory *memory;
455 /* capture mixer buffer */
456 struct esm_memory *mixbuf;
457
458 unsigned int hwptr; /* current hw pointer in bytes */
459 unsigned int count; /* sample counter in bytes */
460 unsigned int dma_size; /* total buffer size in bytes */
461 unsigned int frag_size; /* period size in bytes */
462 unsigned int wav_shift;
463 u16 base[4]; /* offset for ptr */
464
465 /* stereo/16bit flag */
466 unsigned char fmt;
467 int mode; /* playback / capture */
468
469 int bob_freq; /* required timer frequency */
470
471 struct snd_pcm_substream *substream;
472
473 /* linked list */
474 struct list_head list;
475
476#ifdef CONFIG_PM_SLEEP
477 u16 wc_map[4];
478#endif
479};
480
481struct es1968 {
482 /* Module Config */
483 int total_bufsize; /* in bytes */
484
485 int playback_streams, capture_streams;
486
487 unsigned int clock; /* clock */
488 /* for clock measurement */
489 unsigned int in_measurement: 1;
490 unsigned int measure_apu;
491 unsigned int measure_lastpos;
492 unsigned int measure_count;
493
494 /* buffer */
495 struct snd_dma_buffer dma;
496
497 /* Resources... */
498 int irq;
499 unsigned long io_port;
500 int type;
501 struct pci_dev *pci;
502 struct snd_card *card;
503 struct snd_pcm *pcm;
504 int do_pm; /* power-management enabled */
505
506 /* DMA memory block */
507 struct list_head buf_list;
508
509 /* ALSA Stuff */
510 struct snd_ac97 *ac97;
511 struct snd_rawmidi *rmidi;
512
513 spinlock_t reg_lock;
514 unsigned int in_suspend;
515
516 /* Maestro Stuff */
517 u16 maestro_map[32];
518 int bobclient; /* active timer instancs */
519 int bob_freq; /* timer frequency */
520 struct mutex memory_mutex; /* memory lock */
521
522 /* APU states */
523 unsigned char apu[NR_APUS];
524
525 /* active substreams */
526 struct list_head substream_list;
527 spinlock_t substream_lock;
528
529#ifdef CONFIG_PM_SLEEP
530 u16 apu_map[NR_APUS][NR_APU_REGS];
531#endif
532
533#ifdef SUPPORT_JOYSTICK
534 struct gameport *gameport;
535#endif
536
537#ifdef CONFIG_SND_ES1968_INPUT
538 struct input_dev *input_dev;
539 char phys[64]; /* physical device path */
540#else
541 struct snd_kcontrol *master_switch; /* for h/w volume control */
542 struct snd_kcontrol *master_volume;
543#endif
544 struct work_struct hwvol_work;
545
546#ifdef CONFIG_SND_ES1968_RADIO
547 struct v4l2_device v4l2_dev;
548 struct snd_tea575x tea;
549 unsigned int tea575x_tuner;
550#endif
551};
552
553static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
554
555static const struct pci_device_id snd_es1968_ids[] = {
556 /* Maestro 1 */
557 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
558 /* Maestro 2 */
559 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
560 /* Maestro 2E */
561 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
562 { 0, }
563};
564
565MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
566
567/* *********************
568 * Low Level Funcs! *
569 *********************/
570
571/* no spinlock */
572static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
573{
574 outw(reg, chip->io_port + ESM_INDEX);
575 outw(data, chip->io_port + ESM_DATA);
576 chip->maestro_map[reg] = data;
577}
578
579static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
580{
581 unsigned long flags;
582 spin_lock_irqsave(&chip->reg_lock, flags);
583 __maestro_write(chip, reg, data);
584 spin_unlock_irqrestore(&chip->reg_lock, flags);
585}
586
587/* no spinlock */
588static u16 __maestro_read(struct es1968 *chip, u16 reg)
589{
590 if (READABLE_MAP & (1 << reg)) {
591 outw(reg, chip->io_port + ESM_INDEX);
592 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
593 }
594 return chip->maestro_map[reg];
595}
596
597static inline u16 maestro_read(struct es1968 *chip, u16 reg)
598{
599 unsigned long flags;
600 u16 result;
601 spin_lock_irqsave(&chip->reg_lock, flags);
602 result = __maestro_read(chip, reg);
603 spin_unlock_irqrestore(&chip->reg_lock, flags);
604 return result;
605}
606
607/* Wait for the codec bus to be free */
608static int snd_es1968_ac97_wait(struct es1968 *chip)
609{
610 int timeout = 100000;
611
612 while (timeout-- > 0) {
613 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
614 return 0;
615 cond_resched();
616 }
617 dev_dbg(chip->card->dev, "ac97 timeout\n");
618 return 1; /* timeout */
619}
620
621static int snd_es1968_ac97_wait_poll(struct es1968 *chip)
622{
623 int timeout = 100000;
624
625 while (timeout-- > 0) {
626 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
627 return 0;
628 }
629 dev_dbg(chip->card->dev, "ac97 timeout\n");
630 return 1; /* timeout */
631}
632
633static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
634{
635 struct es1968 *chip = ac97->private_data;
636
637 snd_es1968_ac97_wait(chip);
638
639 /* Write the bus */
640 outw(val, chip->io_port + ESM_AC97_DATA);
641 /*msleep(1);*/
642 outb(reg, chip->io_port + ESM_AC97_INDEX);
643 /*msleep(1);*/
644}
645
646static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
647{
648 u16 data = 0;
649 struct es1968 *chip = ac97->private_data;
650
651 snd_es1968_ac97_wait(chip);
652
653 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
654 /*msleep(1);*/
655
656 if (!snd_es1968_ac97_wait_poll(chip)) {
657 data = inw(chip->io_port + ESM_AC97_DATA);
658 /*msleep(1);*/
659 }
660
661 return data;
662}
663
664/* no spinlock */
665static void apu_index_set(struct es1968 *chip, u16 index)
666{
667 int i;
668 __maestro_write(chip, IDR1_CRAM_POINTER, index);
669 for (i = 0; i < 1000; i++)
670 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
671 return;
672 dev_dbg(chip->card->dev, "APU register select failed. (Timeout)\n");
673}
674
675/* no spinlock */
676static void apu_data_set(struct es1968 *chip, u16 data)
677{
678 int i;
679 for (i = 0; i < 1000; i++) {
680 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
681 return;
682 __maestro_write(chip, IDR0_DATA_PORT, data);
683 }
684 dev_dbg(chip->card->dev, "APU register set probably failed (Timeout)!\n");
685}
686
687/* no spinlock */
688static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
689{
690 if (snd_BUG_ON(channel >= NR_APUS))
691 return;
692#ifdef CONFIG_PM_SLEEP
693 chip->apu_map[channel][reg] = data;
694#endif
695 reg |= (channel << 4);
696 apu_index_set(chip, reg);
697 apu_data_set(chip, data);
698}
699
700static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
701{
702 unsigned long flags;
703 spin_lock_irqsave(&chip->reg_lock, flags);
704 __apu_set_register(chip, channel, reg, data);
705 spin_unlock_irqrestore(&chip->reg_lock, flags);
706}
707
708static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
709{
710 if (snd_BUG_ON(channel >= NR_APUS))
711 return 0;
712 reg |= (channel << 4);
713 apu_index_set(chip, reg);
714 return __maestro_read(chip, IDR0_DATA_PORT);
715}
716
717static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
718{
719 unsigned long flags;
720 u16 v;
721 spin_lock_irqsave(&chip->reg_lock, flags);
722 v = __apu_get_register(chip, channel, reg);
723 spin_unlock_irqrestore(&chip->reg_lock, flags);
724 return v;
725}
726
727#if 0 /* ASSP is not supported */
728
729static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
730{
731 unsigned long flags;
732
733 spin_lock_irqsave(&chip->reg_lock, flags);
734 outl(reg, chip->io_port + ASSP_INDEX);
735 outl(value, chip->io_port + ASSP_DATA);
736 spin_unlock_irqrestore(&chip->reg_lock, flags);
737}
738
739static u32 assp_get_register(struct es1968 *chip, u32 reg)
740{
741 unsigned long flags;
742 u32 value;
743
744 spin_lock_irqsave(&chip->reg_lock, flags);
745 outl(reg, chip->io_port + ASSP_INDEX);
746 value = inl(chip->io_port + ASSP_DATA);
747 spin_unlock_irqrestore(&chip->reg_lock, flags);
748
749 return value;
750}
751
752#endif
753
754static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
755{
756 unsigned long flags;
757
758 spin_lock_irqsave(&chip->reg_lock, flags);
759 outw(reg, chip->io_port + WC_INDEX);
760 outw(value, chip->io_port + WC_DATA);
761 spin_unlock_irqrestore(&chip->reg_lock, flags);
762}
763
764static u16 wave_get_register(struct es1968 *chip, u16 reg)
765{
766 unsigned long flags;
767 u16 value;
768
769 spin_lock_irqsave(&chip->reg_lock, flags);
770 outw(reg, chip->io_port + WC_INDEX);
771 value = inw(chip->io_port + WC_DATA);
772 spin_unlock_irqrestore(&chip->reg_lock, flags);
773
774 return value;
775}
776
777/* *******************
778 * Bob the Timer! *
779 *******************/
780
781static void snd_es1968_bob_stop(struct es1968 *chip)
782{
783 u16 reg;
784
785 reg = __maestro_read(chip, 0x11);
786 reg &= ~ESM_BOB_ENABLE;
787 __maestro_write(chip, 0x11, reg);
788 reg = __maestro_read(chip, 0x17);
789 reg &= ~ESM_BOB_START;
790 __maestro_write(chip, 0x17, reg);
791}
792
793static void snd_es1968_bob_start(struct es1968 *chip)
794{
795 int prescale;
796 int divide;
797
798 /* compute ideal interrupt frequency for buffer size & play rate */
799 /* first, find best prescaler value to match freq */
800 for (prescale = 5; prescale < 12; prescale++)
801 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
802 break;
803
804 /* next, back off prescaler whilst getting divider into optimum range */
805 divide = 1;
806 while ((prescale > 5) && (divide < 32)) {
807 prescale--;
808 divide <<= 1;
809 }
810 divide >>= 1;
811
812 /* now fine-tune the divider for best match */
813 for (; divide < 31; divide++)
814 if (chip->bob_freq >
815 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
816
817 /* divide = 0 is illegal, but don't let prescale = 4! */
818 if (divide == 0) {
819 divide++;
820 if (prescale > 5)
821 prescale--;
822 } else if (divide > 1)
823 divide--;
824
825 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
826
827 /* Now set IDR 11/17 */
828 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
829 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
830}
831
832/* call with substream spinlock */
833static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
834{
835 chip->bobclient++;
836 if (chip->bobclient == 1) {
837 chip->bob_freq = freq;
838 snd_es1968_bob_start(chip);
839 } else if (chip->bob_freq < freq) {
840 snd_es1968_bob_stop(chip);
841 chip->bob_freq = freq;
842 snd_es1968_bob_start(chip);
843 }
844}
845
846/* call with substream spinlock */
847static void snd_es1968_bob_dec(struct es1968 *chip)
848{
849 chip->bobclient--;
850 if (chip->bobclient <= 0)
851 snd_es1968_bob_stop(chip);
852 else if (chip->bob_freq > ESM_BOB_FREQ) {
853 /* check reduction of timer frequency */
854 int max_freq = ESM_BOB_FREQ;
855 struct esschan *es;
856 list_for_each_entry(es, &chip->substream_list, list) {
857 if (max_freq < es->bob_freq)
858 max_freq = es->bob_freq;
859 }
860 if (max_freq != chip->bob_freq) {
861 snd_es1968_bob_stop(chip);
862 chip->bob_freq = max_freq;
863 snd_es1968_bob_start(chip);
864 }
865 }
866}
867
868static int
869snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
870 struct snd_pcm_runtime *runtime)
871{
872 /* we acquire 4 interrupts per period for precise control.. */
873 int freq = runtime->rate * 4;
874 if (es->fmt & ESS_FMT_STEREO)
875 freq <<= 1;
876 if (es->fmt & ESS_FMT_16BIT)
877 freq <<= 1;
878 freq /= es->frag_size;
879 if (freq < ESM_BOB_FREQ)
880 freq = ESM_BOB_FREQ;
881 else if (freq > ESM_BOB_FREQ_MAX)
882 freq = ESM_BOB_FREQ_MAX;
883 return freq;
884}
885
886
887/*************
888 * PCM Part *
889 *************/
890
891static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
892{
893 u32 rate = (freq << 16) / chip->clock;
894#if 0 /* XXX: do we need this? */
895 if (rate > 0x10000)
896 rate = 0x10000;
897#endif
898 return rate;
899}
900
901/* get current pointer */
902static inline unsigned int
903snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
904{
905 unsigned int offset;
906
907 offset = apu_get_register(chip, es->apu[0], 5);
908
909 offset -= es->base[0];
910
911 return (offset & 0xFFFE); /* hardware is in words */
912}
913
914static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
915{
916 apu_set_register(chip, apu, 2,
917 (apu_get_register(chip, apu, 2) & 0x00FF) |
918 ((freq & 0xff) << 8) | 0x10);
919 apu_set_register(chip, apu, 3, freq >> 8);
920}
921
922/* spin lock held */
923static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
924{
925 /* set the APU mode */
926 __apu_set_register(esm, apu, 0,
927 (__apu_get_register(esm, apu, 0) & 0xff0f) |
928 (mode << 4));
929}
930
931static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
932{
933 spin_lock(&chip->reg_lock);
934 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
935 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
936 if (es->mode == ESM_MODE_CAPTURE) {
937 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
938 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
939 }
940 if (es->fmt & ESS_FMT_STEREO) {
941 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
942 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
943 if (es->mode == ESM_MODE_CAPTURE) {
944 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
945 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
946 }
947 }
948 spin_unlock(&chip->reg_lock);
949}
950
951static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
952{
953 spin_lock(&chip->reg_lock);
954 snd_es1968_trigger_apu(chip, es->apu[0], 0);
955 snd_es1968_trigger_apu(chip, es->apu[1], 0);
956 if (es->mode == ESM_MODE_CAPTURE) {
957 snd_es1968_trigger_apu(chip, es->apu[2], 0);
958 snd_es1968_trigger_apu(chip, es->apu[3], 0);
959 }
960 spin_unlock(&chip->reg_lock);
961}
962
963/* set the wavecache control reg */
964static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
965 int channel, u32 addr, int capture)
966{
967 u32 tmpval = (addr - 0x10) & 0xFFF8;
968
969 if (! capture) {
970 if (!(es->fmt & ESS_FMT_16BIT))
971 tmpval |= 4; /* 8bit */
972 if (es->fmt & ESS_FMT_STEREO)
973 tmpval |= 2; /* stereo */
974 }
975
976 /* set the wavecache control reg */
977 wave_set_register(chip, es->apu[channel] << 3, tmpval);
978
979#ifdef CONFIG_PM_SLEEP
980 es->wc_map[channel] = tmpval;
981#endif
982}
983
984
985static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
986 struct snd_pcm_runtime *runtime)
987{
988 u32 pa;
989 int high_apu = 0;
990 int channel, apu;
991 int i, size;
992 unsigned long flags;
993 u32 freq;
994
995 size = es->dma_size >> es->wav_shift;
996
997 if (es->fmt & ESS_FMT_STEREO)
998 high_apu++;
999
1000 for (channel = 0; channel <= high_apu; channel++) {
1001 apu = es->apu[channel];
1002
1003 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
1004
1005 /* Offset to PCMBAR */
1006 pa = es->memory->buf.addr;
1007 pa -= chip->dma.addr;
1008 pa >>= 1; /* words */
1009
1010 pa |= 0x00400000; /* System RAM (Bit 22) */
1011
1012 if (es->fmt & ESS_FMT_STEREO) {
1013 /* Enable stereo */
1014 if (channel)
1015 pa |= 0x00800000; /* (Bit 23) */
1016 if (es->fmt & ESS_FMT_16BIT)
1017 pa >>= 1;
1018 }
1019
1020 /* base offset of dma calcs when reading the pointer
1021 on this left one */
1022 es->base[channel] = pa & 0xFFFF;
1023
1024 for (i = 0; i < 16; i++)
1025 apu_set_register(chip, apu, i, 0x0000);
1026
1027 /* Load the buffer into the wave engine */
1028 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1029 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1030 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1031 /* setting loop == sample len */
1032 apu_set_register(chip, apu, 7, size);
1033
1034 /* clear effects/env.. */
1035 apu_set_register(chip, apu, 8, 0x0000);
1036 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1037 apu_set_register(chip, apu, 9, 0xD000);
1038
1039 /* clear routing stuff */
1040 apu_set_register(chip, apu, 11, 0x0000);
1041 /* dma on, no envelopes, filter to all 1s) */
1042 apu_set_register(chip, apu, 0, 0x400F);
1043
1044 if (es->fmt & ESS_FMT_16BIT)
1045 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1046 else
1047 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1048
1049 if (es->fmt & ESS_FMT_STEREO) {
1050 /* set panning: left or right */
1051 /* Check: different panning. On my Canyon 3D Chipset the
1052 Channels are swapped. I don't know, about the output
1053 to the SPDif Link. Perhaps you have to change this
1054 and not the APU Regs 4-5. */
1055 apu_set_register(chip, apu, 10,
1056 0x8F00 | (channel ? 0 : 0x10));
1057 es->apu_mode[channel] += 1; /* stereo */
1058 } else
1059 apu_set_register(chip, apu, 10, 0x8F08);
1060 }
1061
1062 spin_lock_irqsave(&chip->reg_lock, flags);
1063 /* clear WP interrupts */
1064 outw(1, chip->io_port + 0x04);
1065 /* enable WP ints */
1066 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1067 spin_unlock_irqrestore(&chip->reg_lock, flags);
1068
1069 freq = runtime->rate;
1070 /* set frequency */
1071 if (freq > 48000)
1072 freq = 48000;
1073 if (freq < 4000)
1074 freq = 4000;
1075
1076 /* hmmm.. */
1077 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1078 freq >>= 1;
1079
1080 freq = snd_es1968_compute_rate(chip, freq);
1081
1082 /* Load the frequency, turn on 6dB */
1083 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1084 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1085}
1086
1087
1088static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1089 unsigned int pa, unsigned int bsize,
1090 int mode, int route)
1091{
1092 int i, apu = es->apu[channel];
1093
1094 es->apu_mode[channel] = mode;
1095
1096 /* set the wavecache control reg */
1097 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1098
1099 /* Offset to PCMBAR */
1100 pa -= chip->dma.addr;
1101 pa >>= 1; /* words */
1102
1103 /* base offset of dma calcs when reading the pointer
1104 on this left one */
1105 es->base[channel] = pa & 0xFFFF;
1106 pa |= 0x00400000; /* bit 22 -> System RAM */
1107
1108 /* Begin loading the APU */
1109 for (i = 0; i < 16; i++)
1110 apu_set_register(chip, apu, i, 0x0000);
1111
1112 /* need to enable subgroups.. and we should probably
1113 have different groups for different /dev/dsps.. */
1114 apu_set_register(chip, apu, 2, 0x8);
1115
1116 /* Load the buffer into the wave engine */
1117 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1118 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1119 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1120 apu_set_register(chip, apu, 7, bsize);
1121 /* clear effects/env.. */
1122 apu_set_register(chip, apu, 8, 0x00F0);
1123 /* amplitude now? sure. why not. */
1124 apu_set_register(chip, apu, 9, 0x0000);
1125 /* set filter tune, radius, polar pan */
1126 apu_set_register(chip, apu, 10, 0x8F08);
1127 /* route input */
1128 apu_set_register(chip, apu, 11, route);
1129 /* dma on, no envelopes, filter to all 1s) */
1130 apu_set_register(chip, apu, 0, 0x400F);
1131}
1132
1133static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1134 struct snd_pcm_runtime *runtime)
1135{
1136 int size;
1137 u32 freq;
1138 unsigned long flags;
1139
1140 size = es->dma_size >> es->wav_shift;
1141
1142 /* APU assignments:
1143 0 = mono/left SRC
1144 1 = right SRC
1145 2 = mono/left Input Mixer
1146 3 = right Input Mixer
1147 */
1148 /* data seems to flow from the codec, through an apu into
1149 the 'mixbuf' bit of page, then through the SRC apu
1150 and out to the real 'buffer'. ok. sure. */
1151
1152 /* input mixer (left/mono) */
1153 /* parallel in crap, see maestro reg 0xC [8-11] */
1154 init_capture_apu(chip, es, 2,
1155 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1156 ESM_APU_INPUTMIXER, 0x14);
1157 /* SRC (left/mono); get input from inputing apu */
1158 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1159 ESM_APU_SRCONVERTOR, es->apu[2]);
1160 if (es->fmt & ESS_FMT_STEREO) {
1161 /* input mixer (right) */
1162 init_capture_apu(chip, es, 3,
1163 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1164 ESM_MIXBUF_SIZE/4, /* in words */
1165 ESM_APU_INPUTMIXER, 0x15);
1166 /* SRC (right) */
1167 init_capture_apu(chip, es, 1,
1168 es->memory->buf.addr + size*2, size,
1169 ESM_APU_SRCONVERTOR, es->apu[3]);
1170 }
1171
1172 freq = runtime->rate;
1173 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1174 if (freq > 47999)
1175 freq = 47999;
1176 if (freq < 4000)
1177 freq = 4000;
1178
1179 freq = snd_es1968_compute_rate(chip, freq);
1180
1181 /* Load the frequency, turn on 6dB */
1182 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1183 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1184
1185 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1186 freq = 0x10000;
1187 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1188 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1189
1190 spin_lock_irqsave(&chip->reg_lock, flags);
1191 /* clear WP interrupts */
1192 outw(1, chip->io_port + 0x04);
1193 /* enable WP ints */
1194 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1195 spin_unlock_irqrestore(&chip->reg_lock, flags);
1196}
1197
1198/*******************
1199 * ALSA Interface *
1200 *******************/
1201
1202static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1203{
1204 struct es1968 *chip = snd_pcm_substream_chip(substream);
1205 struct snd_pcm_runtime *runtime = substream->runtime;
1206 struct esschan *es = runtime->private_data;
1207
1208 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1209 es->frag_size = snd_pcm_lib_period_bytes(substream);
1210
1211 es->wav_shift = 1; /* maestro handles always 16bit */
1212 es->fmt = 0;
1213 if (snd_pcm_format_width(runtime->format) == 16)
1214 es->fmt |= ESS_FMT_16BIT;
1215 if (runtime->channels > 1) {
1216 es->fmt |= ESS_FMT_STEREO;
1217 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1218 es->wav_shift++;
1219 }
1220 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1221
1222 switch (es->mode) {
1223 case ESM_MODE_PLAY:
1224 snd_es1968_playback_setup(chip, es, runtime);
1225 break;
1226 case ESM_MODE_CAPTURE:
1227 snd_es1968_capture_setup(chip, es, runtime);
1228 break;
1229 }
1230
1231 return 0;
1232}
1233
1234static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1235{
1236 struct es1968 *chip = snd_pcm_substream_chip(substream);
1237 struct esschan *es = substream->runtime->private_data;
1238
1239 spin_lock(&chip->substream_lock);
1240 switch (cmd) {
1241 case SNDRV_PCM_TRIGGER_START:
1242 case SNDRV_PCM_TRIGGER_RESUME:
1243 if (es->running)
1244 break;
1245 snd_es1968_bob_inc(chip, es->bob_freq);
1246 es->count = 0;
1247 es->hwptr = 0;
1248 snd_es1968_pcm_start(chip, es);
1249 es->running = 1;
1250 break;
1251 case SNDRV_PCM_TRIGGER_STOP:
1252 case SNDRV_PCM_TRIGGER_SUSPEND:
1253 if (! es->running)
1254 break;
1255 snd_es1968_pcm_stop(chip, es);
1256 es->running = 0;
1257 snd_es1968_bob_dec(chip);
1258 break;
1259 }
1260 spin_unlock(&chip->substream_lock);
1261 return 0;
1262}
1263
1264static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1265{
1266 struct es1968 *chip = snd_pcm_substream_chip(substream);
1267 struct esschan *es = substream->runtime->private_data;
1268 unsigned int ptr;
1269
1270 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1271
1272 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1273}
1274
1275static const struct snd_pcm_hardware snd_es1968_playback = {
1276 .info = (SNDRV_PCM_INFO_MMAP |
1277 SNDRV_PCM_INFO_MMAP_VALID |
1278 SNDRV_PCM_INFO_INTERLEAVED |
1279 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1280 /*SNDRV_PCM_INFO_PAUSE |*/
1281 SNDRV_PCM_INFO_RESUME),
1282 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1283 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1284 .rate_min = 4000,
1285 .rate_max = 48000,
1286 .channels_min = 1,
1287 .channels_max = 2,
1288 .buffer_bytes_max = 65536,
1289 .period_bytes_min = 256,
1290 .period_bytes_max = 65536,
1291 .periods_min = 1,
1292 .periods_max = 1024,
1293 .fifo_size = 0,
1294};
1295
1296static const struct snd_pcm_hardware snd_es1968_capture = {
1297 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1298 SNDRV_PCM_INFO_MMAP |
1299 SNDRV_PCM_INFO_MMAP_VALID |
1300 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1301 /*SNDRV_PCM_INFO_PAUSE |*/
1302 SNDRV_PCM_INFO_RESUME),
1303 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1304 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1305 .rate_min = 4000,
1306 .rate_max = 48000,
1307 .channels_min = 1,
1308 .channels_max = 2,
1309 .buffer_bytes_max = 65536,
1310 .period_bytes_min = 256,
1311 .period_bytes_max = 65536,
1312 .periods_min = 1,
1313 .periods_max = 1024,
1314 .fifo_size = 0,
1315};
1316
1317/* *************************
1318 * DMA memory management *
1319 *************************/
1320
1321/* Because the Maestro can only take addresses relative to the PCM base address
1322 register :( */
1323
1324static int calc_available_memory_size(struct es1968 *chip)
1325{
1326 int max_size = 0;
1327 struct esm_memory *buf;
1328
1329 mutex_lock(&chip->memory_mutex);
1330 list_for_each_entry(buf, &chip->buf_list, list) {
1331 if (buf->empty && buf->buf.bytes > max_size)
1332 max_size = buf->buf.bytes;
1333 }
1334 mutex_unlock(&chip->memory_mutex);
1335 if (max_size >= 128*1024)
1336 max_size = 127*1024;
1337 return max_size;
1338}
1339
1340/* allocate a new memory chunk with the specified size */
1341static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1342{
1343 struct esm_memory *buf;
1344
1345 size = ALIGN(size, ESM_MEM_ALIGN);
1346 mutex_lock(&chip->memory_mutex);
1347 list_for_each_entry(buf, &chip->buf_list, list) {
1348 if (buf->empty && buf->buf.bytes >= size)
1349 goto __found;
1350 }
1351 mutex_unlock(&chip->memory_mutex);
1352 return NULL;
1353
1354__found:
1355 if (buf->buf.bytes > size) {
1356 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1357 if (chunk == NULL) {
1358 mutex_unlock(&chip->memory_mutex);
1359 return NULL;
1360 }
1361 chunk->buf = buf->buf;
1362 chunk->buf.bytes -= size;
1363 chunk->buf.area += size;
1364 chunk->buf.addr += size;
1365 chunk->empty = 1;
1366 buf->buf.bytes = size;
1367 list_add(&chunk->list, &buf->list);
1368 }
1369 buf->empty = 0;
1370 mutex_unlock(&chip->memory_mutex);
1371 return buf;
1372}
1373
1374/* free a memory chunk */
1375static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1376{
1377 struct esm_memory *chunk;
1378
1379 mutex_lock(&chip->memory_mutex);
1380 buf->empty = 1;
1381 if (buf->list.prev != &chip->buf_list) {
1382 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1383 if (chunk->empty) {
1384 chunk->buf.bytes += buf->buf.bytes;
1385 list_del(&buf->list);
1386 kfree(buf);
1387 buf = chunk;
1388 }
1389 }
1390 if (buf->list.next != &chip->buf_list) {
1391 chunk = list_entry(buf->list.next, struct esm_memory, list);
1392 if (chunk->empty) {
1393 buf->buf.bytes += chunk->buf.bytes;
1394 list_del(&chunk->list);
1395 kfree(chunk);
1396 }
1397 }
1398 mutex_unlock(&chip->memory_mutex);
1399}
1400
1401static void snd_es1968_free_dmabuf(struct es1968 *chip)
1402{
1403 struct list_head *p;
1404
1405 if (! chip->dma.area)
1406 return;
1407 snd_dma_free_pages(&chip->dma);
1408 while ((p = chip->buf_list.next) != &chip->buf_list) {
1409 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1410 list_del(p);
1411 kfree(chunk);
1412 }
1413}
1414
1415static int
1416snd_es1968_init_dmabuf(struct es1968 *chip)
1417{
1418 int err;
1419 struct esm_memory *chunk;
1420
1421 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1422 &chip->pci->dev,
1423 chip->total_bufsize, &chip->dma);
1424 if (err < 0 || ! chip->dma.area) {
1425 dev_err(chip->card->dev,
1426 "can't allocate dma pages for size %d\n",
1427 chip->total_bufsize);
1428 return -ENOMEM;
1429 }
1430 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1431 snd_dma_free_pages(&chip->dma);
1432 dev_err(chip->card->dev, "DMA buffer beyond 256MB.\n");
1433 return -ENOMEM;
1434 }
1435
1436 INIT_LIST_HEAD(&chip->buf_list);
1437 /* allocate an empty chunk */
1438 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1439 if (chunk == NULL) {
1440 snd_es1968_free_dmabuf(chip);
1441 return -ENOMEM;
1442 }
1443 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1444 chunk->buf = chip->dma;
1445 chunk->buf.area += ESM_MEM_ALIGN;
1446 chunk->buf.addr += ESM_MEM_ALIGN;
1447 chunk->buf.bytes -= ESM_MEM_ALIGN;
1448 chunk->empty = 1;
1449 list_add(&chunk->list, &chip->buf_list);
1450
1451 return 0;
1452}
1453
1454/* setup the dma_areas */
1455/* buffer is extracted from the pre-allocated memory chunk */
1456static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1457 struct snd_pcm_hw_params *hw_params)
1458{
1459 struct es1968 *chip = snd_pcm_substream_chip(substream);
1460 struct snd_pcm_runtime *runtime = substream->runtime;
1461 struct esschan *chan = runtime->private_data;
1462 int size = params_buffer_bytes(hw_params);
1463
1464 if (chan->memory) {
1465 if (chan->memory->buf.bytes >= size) {
1466 runtime->dma_bytes = size;
1467 return 0;
1468 }
1469 snd_es1968_free_memory(chip, chan->memory);
1470 }
1471 chan->memory = snd_es1968_new_memory(chip, size);
1472 if (chan->memory == NULL) {
1473 dev_dbg(chip->card->dev,
1474 "cannot allocate dma buffer: size = %d\n", size);
1475 return -ENOMEM;
1476 }
1477 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1478 return 1; /* area was changed */
1479}
1480
1481/* remove dma areas if allocated */
1482static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1483{
1484 struct es1968 *chip = snd_pcm_substream_chip(substream);
1485 struct snd_pcm_runtime *runtime = substream->runtime;
1486 struct esschan *chan;
1487
1488 if (runtime->private_data == NULL)
1489 return 0;
1490 chan = runtime->private_data;
1491 if (chan->memory) {
1492 snd_es1968_free_memory(chip, chan->memory);
1493 chan->memory = NULL;
1494 }
1495 return 0;
1496}
1497
1498
1499/*
1500 * allocate APU pair
1501 */
1502static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1503{
1504 int apu;
1505
1506 for (apu = 0; apu < NR_APUS; apu += 2) {
1507 if (chip->apu[apu] == ESM_APU_FREE &&
1508 chip->apu[apu + 1] == ESM_APU_FREE) {
1509 chip->apu[apu] = chip->apu[apu + 1] = type;
1510 return apu;
1511 }
1512 }
1513 return -EBUSY;
1514}
1515
1516/*
1517 * release APU pair
1518 */
1519static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1520{
1521 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1522}
1523
1524
1525/******************
1526 * PCM open/close *
1527 ******************/
1528
1529static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1530{
1531 struct es1968 *chip = snd_pcm_substream_chip(substream);
1532 struct snd_pcm_runtime *runtime = substream->runtime;
1533 struct esschan *es;
1534 int apu1;
1535
1536 /* search 2 APUs */
1537 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1538 if (apu1 < 0)
1539 return apu1;
1540
1541 es = kzalloc(sizeof(*es), GFP_KERNEL);
1542 if (!es) {
1543 snd_es1968_free_apu_pair(chip, apu1);
1544 return -ENOMEM;
1545 }
1546
1547 es->apu[0] = apu1;
1548 es->apu[1] = apu1 + 1;
1549 es->apu_mode[0] = 0;
1550 es->apu_mode[1] = 0;
1551 es->running = 0;
1552 es->substream = substream;
1553 es->mode = ESM_MODE_PLAY;
1554
1555 runtime->private_data = es;
1556 runtime->hw = snd_es1968_playback;
1557 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1558 calc_available_memory_size(chip);
1559
1560 spin_lock_irq(&chip->substream_lock);
1561 list_add(&es->list, &chip->substream_list);
1562 spin_unlock_irq(&chip->substream_lock);
1563
1564 return 0;
1565}
1566
1567static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1568{
1569 struct snd_pcm_runtime *runtime = substream->runtime;
1570 struct es1968 *chip = snd_pcm_substream_chip(substream);
1571 struct esschan *es;
1572 int apu1, apu2;
1573
1574 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1575 if (apu1 < 0)
1576 return apu1;
1577 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1578 if (apu2 < 0) {
1579 snd_es1968_free_apu_pair(chip, apu1);
1580 return apu2;
1581 }
1582
1583 es = kzalloc(sizeof(*es), GFP_KERNEL);
1584 if (!es) {
1585 snd_es1968_free_apu_pair(chip, apu1);
1586 snd_es1968_free_apu_pair(chip, apu2);
1587 return -ENOMEM;
1588 }
1589
1590 es->apu[0] = apu1;
1591 es->apu[1] = apu1 + 1;
1592 es->apu[2] = apu2;
1593 es->apu[3] = apu2 + 1;
1594 es->apu_mode[0] = 0;
1595 es->apu_mode[1] = 0;
1596 es->apu_mode[2] = 0;
1597 es->apu_mode[3] = 0;
1598 es->running = 0;
1599 es->substream = substream;
1600 es->mode = ESM_MODE_CAPTURE;
1601
1602 /* get mixbuffer */
1603 es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE);
1604 if (!es->mixbuf) {
1605 snd_es1968_free_apu_pair(chip, apu1);
1606 snd_es1968_free_apu_pair(chip, apu2);
1607 kfree(es);
1608 return -ENOMEM;
1609 }
1610 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1611
1612 runtime->private_data = es;
1613 runtime->hw = snd_es1968_capture;
1614 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1615 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1616 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
1617
1618 spin_lock_irq(&chip->substream_lock);
1619 list_add(&es->list, &chip->substream_list);
1620 spin_unlock_irq(&chip->substream_lock);
1621
1622 return 0;
1623}
1624
1625static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1626{
1627 struct es1968 *chip = snd_pcm_substream_chip(substream);
1628 struct esschan *es;
1629
1630 if (substream->runtime->private_data == NULL)
1631 return 0;
1632 es = substream->runtime->private_data;
1633 spin_lock_irq(&chip->substream_lock);
1634 list_del(&es->list);
1635 spin_unlock_irq(&chip->substream_lock);
1636 snd_es1968_free_apu_pair(chip, es->apu[0]);
1637 kfree(es);
1638
1639 return 0;
1640}
1641
1642static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1643{
1644 struct es1968 *chip = snd_pcm_substream_chip(substream);
1645 struct esschan *es;
1646
1647 if (substream->runtime->private_data == NULL)
1648 return 0;
1649 es = substream->runtime->private_data;
1650 spin_lock_irq(&chip->substream_lock);
1651 list_del(&es->list);
1652 spin_unlock_irq(&chip->substream_lock);
1653 snd_es1968_free_memory(chip, es->mixbuf);
1654 snd_es1968_free_apu_pair(chip, es->apu[0]);
1655 snd_es1968_free_apu_pair(chip, es->apu[2]);
1656 kfree(es);
1657
1658 return 0;
1659}
1660
1661static const struct snd_pcm_ops snd_es1968_playback_ops = {
1662 .open = snd_es1968_playback_open,
1663 .close = snd_es1968_playback_close,
1664 .hw_params = snd_es1968_hw_params,
1665 .hw_free = snd_es1968_hw_free,
1666 .prepare = snd_es1968_pcm_prepare,
1667 .trigger = snd_es1968_pcm_trigger,
1668 .pointer = snd_es1968_pcm_pointer,
1669};
1670
1671static const struct snd_pcm_ops snd_es1968_capture_ops = {
1672 .open = snd_es1968_capture_open,
1673 .close = snd_es1968_capture_close,
1674 .hw_params = snd_es1968_hw_params,
1675 .hw_free = snd_es1968_hw_free,
1676 .prepare = snd_es1968_pcm_prepare,
1677 .trigger = snd_es1968_pcm_trigger,
1678 .pointer = snd_es1968_pcm_pointer,
1679};
1680
1681
1682/*
1683 * measure clock
1684 */
1685#define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1686
1687static void es1968_measure_clock(struct es1968 *chip)
1688{
1689 int i, apu;
1690 unsigned int pa, offset, t;
1691 struct esm_memory *memory;
1692 ktime_t start_time, stop_time;
1693 ktime_t diff;
1694
1695 if (chip->clock == 0)
1696 chip->clock = 48000; /* default clock value */
1697
1698 /* search 2 APUs (although one apu is enough) */
1699 apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1700 if (apu < 0) {
1701 dev_err(chip->card->dev, "Hmm, cannot find empty APU pair!?\n");
1702 return;
1703 }
1704 memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE);
1705 if (!memory) {
1706 dev_warn(chip->card->dev,
1707 "cannot allocate dma buffer - using default clock %d\n",
1708 chip->clock);
1709 snd_es1968_free_apu_pair(chip, apu);
1710 return;
1711 }
1712
1713 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1714
1715 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1716
1717 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1718 pa |= 0x00400000; /* System RAM (Bit 22) */
1719
1720 /* initialize apu */
1721 for (i = 0; i < 16; i++)
1722 apu_set_register(chip, apu, i, 0x0000);
1723
1724 apu_set_register(chip, apu, 0, 0x400f);
1725 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1726 apu_set_register(chip, apu, 5, pa & 0xffff);
1727 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1728 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1729 apu_set_register(chip, apu, 8, 0x0000);
1730 apu_set_register(chip, apu, 9, 0xD000);
1731 apu_set_register(chip, apu, 10, 0x8F08);
1732 apu_set_register(chip, apu, 11, 0x0000);
1733 spin_lock_irq(&chip->reg_lock);
1734 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1735 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1736 spin_unlock_irq(&chip->reg_lock);
1737
1738 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1739
1740 chip->in_measurement = 1;
1741 chip->measure_apu = apu;
1742 spin_lock_irq(&chip->reg_lock);
1743 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1744 __apu_set_register(chip, apu, 5, pa & 0xffff);
1745 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1746 start_time = ktime_get();
1747 spin_unlock_irq(&chip->reg_lock);
1748 msleep(50);
1749 spin_lock_irq(&chip->reg_lock);
1750 offset = __apu_get_register(chip, apu, 5);
1751 stop_time = ktime_get();
1752 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1753 snd_es1968_bob_dec(chip);
1754 chip->in_measurement = 0;
1755 spin_unlock_irq(&chip->reg_lock);
1756
1757 /* check the current position */
1758 offset -= (pa & 0xffff);
1759 offset &= 0xfffe;
1760 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1761
1762 diff = ktime_sub(stop_time, start_time);
1763 t = ktime_to_us(diff);
1764 if (t == 0) {
1765 dev_err(chip->card->dev, "?? calculation error..\n");
1766 } else {
1767 offset *= 1000;
1768 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1769 if (offset < 47500 || offset > 48500) {
1770 if (offset >= 40000 && offset <= 50000)
1771 chip->clock = (chip->clock * offset) / 48000;
1772 }
1773 dev_info(chip->card->dev, "clocking to %d\n", chip->clock);
1774 }
1775 snd_es1968_free_memory(chip, memory);
1776 snd_es1968_free_apu_pair(chip, apu);
1777}
1778
1779
1780/*
1781 */
1782
1783static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1784{
1785 struct es1968 *esm = pcm->private_data;
1786 snd_es1968_free_dmabuf(esm);
1787 esm->pcm = NULL;
1788}
1789
1790static int
1791snd_es1968_pcm(struct es1968 *chip, int device)
1792{
1793 struct snd_pcm *pcm;
1794 int err;
1795
1796 /* get DMA buffer */
1797 err = snd_es1968_init_dmabuf(chip);
1798 if (err < 0)
1799 return err;
1800
1801 /* set PCMBAR */
1802 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1803 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1804 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1805 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1806
1807 err = snd_pcm_new(chip->card, "ESS Maestro", device,
1808 chip->playback_streams,
1809 chip->capture_streams, &pcm);
1810 if (err < 0)
1811 return err;
1812
1813 pcm->private_data = chip;
1814 pcm->private_free = snd_es1968_pcm_free;
1815
1816 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1817 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1818
1819 pcm->info_flags = 0;
1820
1821 strcpy(pcm->name, "ESS Maestro");
1822
1823 chip->pcm = pcm;
1824
1825 return 0;
1826}
1827/*
1828 * suppress jitter on some maestros when playing stereo
1829 */
1830static void snd_es1968_suppress_jitter(struct es1968 *chip, struct esschan *es)
1831{
1832 unsigned int cp1;
1833 unsigned int cp2;
1834 unsigned int diff;
1835
1836 cp1 = __apu_get_register(chip, 0, 5);
1837 cp2 = __apu_get_register(chip, 1, 5);
1838 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1839
1840 if (diff > 1)
1841 __maestro_write(chip, IDR0_DATA_PORT, cp1);
1842}
1843
1844/*
1845 * update pointer
1846 */
1847static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1848{
1849 unsigned int hwptr;
1850 unsigned int diff;
1851 struct snd_pcm_substream *subs = es->substream;
1852
1853 if (subs == NULL || !es->running)
1854 return;
1855
1856 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1857 hwptr %= es->dma_size;
1858
1859 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1860
1861 es->hwptr = hwptr;
1862 es->count += diff;
1863
1864 if (es->count > es->frag_size) {
1865 spin_unlock(&chip->substream_lock);
1866 snd_pcm_period_elapsed(subs);
1867 spin_lock(&chip->substream_lock);
1868 es->count %= es->frag_size;
1869 }
1870}
1871
1872/* The hardware volume works by incrementing / decrementing 2 counters
1873 (without wrap around) in response to volume button presses and then
1874 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1875 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1876static void es1968_update_hw_volume(struct work_struct *work)
1877{
1878 struct es1968 *chip = container_of(work, struct es1968, hwvol_work);
1879 int x, val;
1880
1881 /* Figure out which volume control button was pushed,
1882 based on differences from the default register
1883 values. */
1884 x = inb(chip->io_port + 0x1c) & 0xee;
1885 /* Reset the volume control registers. */
1886 outb(0x88, chip->io_port + 0x1c);
1887 outb(0x88, chip->io_port + 0x1d);
1888 outb(0x88, chip->io_port + 0x1e);
1889 outb(0x88, chip->io_port + 0x1f);
1890
1891 if (chip->in_suspend)
1892 return;
1893
1894#ifndef CONFIG_SND_ES1968_INPUT
1895 if (! chip->master_switch || ! chip->master_volume)
1896 return;
1897
1898 val = snd_ac97_read(chip->ac97, AC97_MASTER);
1899 switch (x) {
1900 case 0x88:
1901 /* mute */
1902 val ^= 0x8000;
1903 break;
1904 case 0xaa:
1905 /* volume up */
1906 if ((val & 0x7f) > 0)
1907 val--;
1908 if ((val & 0x7f00) > 0)
1909 val -= 0x0100;
1910 break;
1911 case 0x66:
1912 /* volume down */
1913 if ((val & 0x7f) < 0x1f)
1914 val++;
1915 if ((val & 0x7f00) < 0x1f00)
1916 val += 0x0100;
1917 break;
1918 }
1919 if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1920 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1921 &chip->master_volume->id);
1922#else
1923 if (!chip->input_dev)
1924 return;
1925
1926 val = 0;
1927 switch (x) {
1928 case 0x88:
1929 /* The counters have not changed, yet we've received a HV
1930 interrupt. According to tests run by various people this
1931 happens when pressing the mute button. */
1932 val = KEY_MUTE;
1933 break;
1934 case 0xaa:
1935 /* counters increased by 1 -> volume up */
1936 val = KEY_VOLUMEUP;
1937 break;
1938 case 0x66:
1939 /* counters decreased by 1 -> volume down */
1940 val = KEY_VOLUMEDOWN;
1941 break;
1942 }
1943
1944 if (val) {
1945 input_report_key(chip->input_dev, val, 1);
1946 input_sync(chip->input_dev);
1947 input_report_key(chip->input_dev, val, 0);
1948 input_sync(chip->input_dev);
1949 }
1950#endif
1951}
1952
1953/*
1954 * interrupt handler
1955 */
1956static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1957{
1958 struct es1968 *chip = dev_id;
1959 u32 event;
1960
1961 event = inb(chip->io_port + 0x1A);
1962 if (!event)
1963 return IRQ_NONE;
1964
1965 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1966
1967 if (event & ESM_HWVOL_IRQ)
1968 schedule_work(&chip->hwvol_work);
1969
1970 /* else ack 'em all, i imagine */
1971 outb(0xFF, chip->io_port + 0x1A);
1972
1973 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1974 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1975 }
1976
1977 if (event & ESM_SOUND_IRQ) {
1978 struct esschan *es;
1979 spin_lock(&chip->substream_lock);
1980 list_for_each_entry(es, &chip->substream_list, list) {
1981 if (es->running) {
1982 snd_es1968_update_pcm(chip, es);
1983 if (es->fmt & ESS_FMT_STEREO)
1984 snd_es1968_suppress_jitter(chip, es);
1985 }
1986 }
1987 spin_unlock(&chip->substream_lock);
1988 if (chip->in_measurement) {
1989 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
1990 if (curp < chip->measure_lastpos)
1991 chip->measure_count++;
1992 chip->measure_lastpos = curp;
1993 }
1994 }
1995
1996 return IRQ_HANDLED;
1997}
1998
1999/*
2000 * Mixer stuff
2001 */
2002
2003static int
2004snd_es1968_mixer(struct es1968 *chip)
2005{
2006 struct snd_ac97_bus *pbus;
2007 struct snd_ac97_template ac97;
2008#ifndef CONFIG_SND_ES1968_INPUT
2009 struct snd_ctl_elem_id elem_id;
2010#endif
2011 int err;
2012 static const struct snd_ac97_bus_ops ops = {
2013 .write = snd_es1968_ac97_write,
2014 .read = snd_es1968_ac97_read,
2015 };
2016
2017 err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus);
2018 if (err < 0)
2019 return err;
2020 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
2021
2022 memset(&ac97, 0, sizeof(ac97));
2023 ac97.private_data = chip;
2024 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97);
2025 if (err < 0)
2026 return err;
2027
2028#ifndef CONFIG_SND_ES1968_INPUT
2029 /* attach master switch / volumes for h/w volume control */
2030 memset(&elem_id, 0, sizeof(elem_id));
2031 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2032 strcpy(elem_id.name, "Master Playback Switch");
2033 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2034 memset(&elem_id, 0, sizeof(elem_id));
2035 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2036 strcpy(elem_id.name, "Master Playback Volume");
2037 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2038#endif
2039
2040 return 0;
2041}
2042
2043/*
2044 * reset ac97 codec
2045 */
2046
2047static void snd_es1968_ac97_reset(struct es1968 *chip)
2048{
2049 unsigned long ioaddr = chip->io_port;
2050
2051 unsigned short save_ringbus_a;
2052 unsigned short save_68;
2053 unsigned short w;
2054 unsigned int vend;
2055
2056 /* save configuration */
2057 save_ringbus_a = inw(ioaddr + 0x36);
2058
2059 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2060 /* set command/status address i/o to 1st codec */
2061 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2062 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2063
2064 /* disable ac link */
2065 outw(0x0000, ioaddr + 0x36);
2066 save_68 = inw(ioaddr + 0x68);
2067 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2068 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2069 if (w & 1)
2070 save_68 |= 0x10;
2071 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2072 outw(0x0001, ioaddr + 0x68); /* gpio write */
2073 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2074 udelay(20);
2075 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2076 msleep(20);
2077
2078 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2079 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2080 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2081 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2082
2083 /* now the second codec */
2084 /* disable ac link */
2085 outw(0x0000, ioaddr + 0x36);
2086 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2087 save_68 = inw(ioaddr + 0x68);
2088 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2089 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2090 udelay(20);
2091 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2092 msleep(500);
2093 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2094 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2095 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2096
2097#if 0 /* the loop here needs to be much better if we want it.. */
2098 dev_info(chip->card->dev, "trying software reset\n");
2099 /* try and do a software reset */
2100 outb(0x80 | 0x7c, ioaddr + 0x30);
2101 for (w = 0;; w++) {
2102 if ((inw(ioaddr + 0x30) & 1) == 0) {
2103 if (inb(ioaddr + 0x32) != 0)
2104 break;
2105
2106 outb(0x80 | 0x7d, ioaddr + 0x30);
2107 if (((inw(ioaddr + 0x30) & 1) == 0)
2108 && (inb(ioaddr + 0x32) != 0))
2109 break;
2110 outb(0x80 | 0x7f, ioaddr + 0x30);
2111 if (((inw(ioaddr + 0x30) & 1) == 0)
2112 && (inb(ioaddr + 0x32) != 0))
2113 break;
2114 }
2115
2116 if (w > 10000) {
2117 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2118 msleep(500); /* oh my.. */
2119 outb(inb(ioaddr + 0x37) & ~0x08,
2120 ioaddr + 0x37);
2121 udelay(1);
2122 outw(0x80, ioaddr + 0x30);
2123 for (w = 0; w < 10000; w++) {
2124 if ((inw(ioaddr + 0x30) & 1) == 0)
2125 break;
2126 }
2127 }
2128 }
2129#endif
2130 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2131 /* turn on external amp? */
2132 outw(0xf9ff, ioaddr + 0x64);
2133 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2134 outw(0x0209, ioaddr + 0x60);
2135 }
2136
2137 /* restore.. */
2138 outw(save_ringbus_a, ioaddr + 0x36);
2139
2140 /* Turn on the 978 docking chip.
2141 First frob the "master output enable" bit,
2142 then set most of the playback volume control registers to max. */
2143 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2144 outb(0xff, ioaddr+0xc3);
2145 outb(0xff, ioaddr+0xc4);
2146 outb(0xff, ioaddr+0xc6);
2147 outb(0xff, ioaddr+0xc8);
2148 outb(0x3f, ioaddr+0xcf);
2149 outb(0x3f, ioaddr+0xd0);
2150}
2151
2152static void snd_es1968_reset(struct es1968 *chip)
2153{
2154 /* Reset */
2155 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2156 chip->io_port + ESM_PORT_HOST_IRQ);
2157 udelay(10);
2158 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2159 udelay(10);
2160}
2161
2162/*
2163 * initialize maestro chip
2164 */
2165static void snd_es1968_chip_init(struct es1968 *chip)
2166{
2167 struct pci_dev *pci = chip->pci;
2168 int i;
2169 unsigned long iobase = chip->io_port;
2170 u16 w;
2171 u32 n;
2172
2173 /* We used to muck around with pci config space that
2174 * we had no business messing with. We don't know enough
2175 * about the machine to know which DMA mode is appropriate,
2176 * etc. We were guessing wrong on some machines and making
2177 * them unhappy. We now trust in the BIOS to do things right,
2178 * which almost certainly means a new host of problems will
2179 * arise with broken BIOS implementations. screw 'em.
2180 * We're already intolerant of machines that don't assign
2181 * IRQs.
2182 */
2183
2184 /* Config Reg A */
2185 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2186
2187 w &= ~DMA_CLEAR; /* Clear DMA bits */
2188 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2189 w &= ~SAFEGUARD; /* Safeguard off */
2190 w |= POST_WRITE; /* Posted write */
2191 w |= PCI_TIMING; /* PCI timing on */
2192 /* XXX huh? claims to be reserved.. */
2193 w &= ~SWAP_LR; /* swap left/right
2194 seems to only have effect on SB
2195 Emulation */
2196 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2197
2198 pci_write_config_word(pci, ESM_CONFIG_A, w);
2199
2200 /* Config Reg B */
2201
2202 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2203
2204 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2205 /* XXX how do we know which to use? */
2206 w &= ~(1 << 14); /* External clock */
2207
2208 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2209 w |= HWV_CONFB; /* HWV on */
2210 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2211 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2212 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2213 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2214 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2215 w &= ~(1 << 1); /* reserved, always write 0 */
2216 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2217
2218 pci_write_config_word(pci, ESM_CONFIG_B, w);
2219
2220 /* DDMA off */
2221
2222 pci_read_config_word(pci, ESM_DDMA, &w);
2223 w &= ~(1 << 0);
2224 pci_write_config_word(pci, ESM_DDMA, w);
2225
2226 /*
2227 * Legacy mode
2228 */
2229
2230 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2231
2232 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
2233 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2234 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2235
2236 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2237
2238 /* Set up 978 docking control chip. */
2239 pci_read_config_word(pci, 0x58, &w);
2240 w|=1<<2; /* Enable 978. */
2241 w|=1<<3; /* Turn on 978 hardware volume control. */
2242 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2243 pci_write_config_word(pci, 0x58, w);
2244
2245 /* Sound Reset */
2246
2247 snd_es1968_reset(chip);
2248
2249 /*
2250 * Ring Bus Setup
2251 */
2252
2253 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2254 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2255 udelay(20);
2256 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2257 udelay(20);
2258
2259 /*
2260 * Reset the CODEC
2261 */
2262
2263 snd_es1968_ac97_reset(chip);
2264
2265 /* Ring Bus Control B */
2266
2267 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2268 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2269 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2270 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2271
2272 /* Set hardware volume control registers to midpoints.
2273 We can tell which button was pushed based on how they change. */
2274 outb(0x88, iobase+0x1c);
2275 outb(0x88, iobase+0x1d);
2276 outb(0x88, iobase+0x1e);
2277 outb(0x88, iobase+0x1f);
2278
2279 /* it appears some maestros (dell 7500) only work if these are set,
2280 regardless of whether we use the assp or not. */
2281
2282 outb(0, iobase + ASSP_CONTROL_B);
2283 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2284 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2285
2286 /*
2287 * set up wavecache
2288 */
2289 for (i = 0; i < 16; i++) {
2290 /* Write 0 into the buffer area 0x1E0->1EF */
2291 outw(0x01E0 + i, iobase + WC_INDEX);
2292 outw(0x0000, iobase + WC_DATA);
2293
2294 /* The 1.10 test program seem to write 0 into the buffer area
2295 * 0x1D0-0x1DF too.*/
2296 outw(0x01D0 + i, iobase + WC_INDEX);
2297 outw(0x0000, iobase + WC_DATA);
2298 }
2299 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2300 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2301 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2302 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2303 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2304 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2305 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2306 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2307
2308
2309 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2310 /* Now back to the DirectSound stuff */
2311 /* audio serial configuration.. ? */
2312 maestro_write(chip, 0x08, 0xB004);
2313 maestro_write(chip, 0x09, 0x001B);
2314 maestro_write(chip, 0x0A, 0x8000);
2315 maestro_write(chip, 0x0B, 0x3F37);
2316 maestro_write(chip, 0x0C, 0x0098);
2317
2318 /* parallel in, has something to do with recording :) */
2319 maestro_write(chip, 0x0C,
2320 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2321 /* parallel out */
2322 maestro_write(chip, 0x0C,
2323 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2324
2325 maestro_write(chip, 0x0D, 0x7632);
2326
2327 /* Wave cache control on - test off, sg off,
2328 enable, enable extra chans 1Mb */
2329
2330 w = inw(iobase + WC_CONTROL);
2331
2332 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2333 w |= 0xA000; /* reserved... I don't know */
2334 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2335 Seems to crash the Computer if enabled... */
2336 w |= 0x0100; /* Wave Cache Operation Enabled */
2337 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2338 w &= ~0x0060; /* Clear Wavtable Size */
2339 w |= 0x0020; /* Wavetable Size : 1MB */
2340 /* Bit 4 is reserved */
2341 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2342 /* Bit 1 is reserved */
2343 w &= ~0x0001; /* Test Mode off */
2344
2345 outw(w, iobase + WC_CONTROL);
2346
2347 /* Now clear the APU control ram */
2348 for (i = 0; i < NR_APUS; i++) {
2349 for (w = 0; w < NR_APU_REGS; w++)
2350 apu_set_register(chip, i, w, 0);
2351
2352 }
2353}
2354
2355/* Enable IRQ's */
2356static void snd_es1968_start_irq(struct es1968 *chip)
2357{
2358 unsigned short w;
2359 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2360 if (chip->rmidi)
2361 w |= ESM_HIRQ_MPU401;
2362 outb(w, chip->io_port + 0x1A);
2363 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2364}
2365
2366#ifdef CONFIG_PM_SLEEP
2367/*
2368 * PM support
2369 */
2370static int es1968_suspend(struct device *dev)
2371{
2372 struct snd_card *card = dev_get_drvdata(dev);
2373 struct es1968 *chip = card->private_data;
2374
2375 if (! chip->do_pm)
2376 return 0;
2377
2378 chip->in_suspend = 1;
2379 cancel_work_sync(&chip->hwvol_work);
2380 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2381 snd_ac97_suspend(chip->ac97);
2382 snd_es1968_bob_stop(chip);
2383 return 0;
2384}
2385
2386static int es1968_resume(struct device *dev)
2387{
2388 struct snd_card *card = dev_get_drvdata(dev);
2389 struct es1968 *chip = card->private_data;
2390 struct esschan *es;
2391
2392 if (! chip->do_pm)
2393 return 0;
2394
2395 snd_es1968_chip_init(chip);
2396
2397 /* need to restore the base pointers.. */
2398 if (chip->dma.addr) {
2399 /* set PCMBAR */
2400 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2401 }
2402
2403 snd_es1968_start_irq(chip);
2404
2405 /* restore ac97 state */
2406 snd_ac97_resume(chip->ac97);
2407
2408 list_for_each_entry(es, &chip->substream_list, list) {
2409 switch (es->mode) {
2410 case ESM_MODE_PLAY:
2411 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2412 break;
2413 case ESM_MODE_CAPTURE:
2414 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2415 break;
2416 }
2417 }
2418
2419 /* start timer again */
2420 if (chip->bobclient)
2421 snd_es1968_bob_start(chip);
2422
2423 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2424 chip->in_suspend = 0;
2425 return 0;
2426}
2427
2428static SIMPLE_DEV_PM_OPS(es1968_pm, es1968_suspend, es1968_resume);
2429#define ES1968_PM_OPS &es1968_pm
2430#else
2431#define ES1968_PM_OPS NULL
2432#endif /* CONFIG_PM_SLEEP */
2433
2434#ifdef SUPPORT_JOYSTICK
2435#define JOYSTICK_ADDR 0x200
2436static int snd_es1968_create_gameport(struct es1968 *chip, int dev)
2437{
2438 struct gameport *gp;
2439 struct resource *r;
2440 u16 val;
2441
2442 if (!joystick[dev])
2443 return -ENODEV;
2444
2445 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2446 if (!r)
2447 return -EBUSY;
2448
2449 chip->gameport = gp = gameport_allocate_port();
2450 if (!gp) {
2451 dev_err(chip->card->dev,
2452 "cannot allocate memory for gameport\n");
2453 release_and_free_resource(r);
2454 return -ENOMEM;
2455 }
2456
2457 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2458 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2459
2460 gameport_set_name(gp, "ES1968 Gameport");
2461 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2462 gameport_set_dev_parent(gp, &chip->pci->dev);
2463 gp->io = JOYSTICK_ADDR;
2464 gameport_set_port_data(gp, r);
2465
2466 gameport_register_port(gp);
2467
2468 return 0;
2469}
2470
2471static void snd_es1968_free_gameport(struct es1968 *chip)
2472{
2473 if (chip->gameport) {
2474 struct resource *r = gameport_get_port_data(chip->gameport);
2475
2476 gameport_unregister_port(chip->gameport);
2477 chip->gameport = NULL;
2478
2479 release_and_free_resource(r);
2480 }
2481}
2482#else
2483static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2484static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2485#endif
2486
2487#ifdef CONFIG_SND_ES1968_INPUT
2488static int snd_es1968_input_register(struct es1968 *chip)
2489{
2490 struct input_dev *input_dev;
2491 int err;
2492
2493 input_dev = input_allocate_device();
2494 if (!input_dev)
2495 return -ENOMEM;
2496
2497 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2498 pci_name(chip->pci));
2499
2500 input_dev->name = chip->card->driver;
2501 input_dev->phys = chip->phys;
2502 input_dev->id.bustype = BUS_PCI;
2503 input_dev->id.vendor = chip->pci->vendor;
2504 input_dev->id.product = chip->pci->device;
2505 input_dev->dev.parent = &chip->pci->dev;
2506
2507 __set_bit(EV_KEY, input_dev->evbit);
2508 __set_bit(KEY_MUTE, input_dev->keybit);
2509 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2510 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2511
2512 err = input_register_device(input_dev);
2513 if (err) {
2514 input_free_device(input_dev);
2515 return err;
2516 }
2517
2518 chip->input_dev = input_dev;
2519 return 0;
2520}
2521#endif /* CONFIG_SND_ES1968_INPUT */
2522
2523#ifdef CONFIG_SND_ES1968_RADIO
2524#define GPIO_DATA 0x60
2525#define IO_MASK 4 /* mask register offset from GPIO_DATA
2526 bits 1=unmask write to given bit */
2527#define IO_DIR 8 /* direction register offset from GPIO_DATA
2528 bits 0/1=read/write direction */
2529
2530/* GPIO to TEA575x maps */
2531struct snd_es1968_tea575x_gpio {
2532 u8 data, clk, wren, most;
2533 char *name;
2534};
2535
2536static const struct snd_es1968_tea575x_gpio snd_es1968_tea575x_gpios[] = {
2537 { .data = 6, .clk = 7, .wren = 8, .most = 9, .name = "SF64-PCE2" },
2538 { .data = 7, .clk = 8, .wren = 6, .most = 10, .name = "M56VAP" },
2539};
2540
2541#define get_tea575x_gpio(chip) \
2542 (&snd_es1968_tea575x_gpios[(chip)->tea575x_tuner])
2543
2544
2545static void snd_es1968_tea575x_set_pins(struct snd_tea575x *tea, u8 pins)
2546{
2547 struct es1968 *chip = tea->private_data;
2548 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2549 u16 val = 0;
2550
2551 val |= (pins & TEA575X_DATA) ? (1 << gpio.data) : 0;
2552 val |= (pins & TEA575X_CLK) ? (1 << gpio.clk) : 0;
2553 val |= (pins & TEA575X_WREN) ? (1 << gpio.wren) : 0;
2554
2555 outw(val, chip->io_port + GPIO_DATA);
2556}
2557
2558static u8 snd_es1968_tea575x_get_pins(struct snd_tea575x *tea)
2559{
2560 struct es1968 *chip = tea->private_data;
2561 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2562 u16 val = inw(chip->io_port + GPIO_DATA);
2563 u8 ret = 0;
2564
2565 if (val & (1 << gpio.data))
2566 ret |= TEA575X_DATA;
2567 if (val & (1 << gpio.most))
2568 ret |= TEA575X_MOST;
2569
2570 return ret;
2571}
2572
2573static void snd_es1968_tea575x_set_direction(struct snd_tea575x *tea, bool output)
2574{
2575 struct es1968 *chip = tea->private_data;
2576 unsigned long io = chip->io_port + GPIO_DATA;
2577 u16 odir = inw(io + IO_DIR);
2578 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2579
2580 if (output) {
2581 outw(~((1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren)),
2582 io + IO_MASK);
2583 outw(odir | (1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren),
2584 io + IO_DIR);
2585 } else {
2586 outw(~((1 << gpio.clk) | (1 << gpio.wren) | (1 << gpio.data) | (1 << gpio.most)),
2587 io + IO_MASK);
2588 outw((odir & ~((1 << gpio.data) | (1 << gpio.most)))
2589 | (1 << gpio.clk) | (1 << gpio.wren), io + IO_DIR);
2590 }
2591}
2592
2593static const struct snd_tea575x_ops snd_es1968_tea_ops = {
2594 .set_pins = snd_es1968_tea575x_set_pins,
2595 .get_pins = snd_es1968_tea575x_get_pins,
2596 .set_direction = snd_es1968_tea575x_set_direction,
2597};
2598#endif
2599
2600static int snd_es1968_free(struct es1968 *chip)
2601{
2602 cancel_work_sync(&chip->hwvol_work);
2603#ifdef CONFIG_SND_ES1968_INPUT
2604 if (chip->input_dev)
2605 input_unregister_device(chip->input_dev);
2606#endif
2607
2608 if (chip->io_port) {
2609 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2610 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2611 }
2612
2613#ifdef CONFIG_SND_ES1968_RADIO
2614 snd_tea575x_exit(&chip->tea);
2615 v4l2_device_unregister(&chip->v4l2_dev);
2616#endif
2617
2618 if (chip->irq >= 0)
2619 free_irq(chip->irq, chip);
2620 snd_es1968_free_gameport(chip);
2621 pci_release_regions(chip->pci);
2622 pci_disable_device(chip->pci);
2623 kfree(chip);
2624 return 0;
2625}
2626
2627static int snd_es1968_dev_free(struct snd_device *device)
2628{
2629 struct es1968 *chip = device->device_data;
2630 return snd_es1968_free(chip);
2631}
2632
2633struct ess_device_list {
2634 unsigned short type; /* chip type */
2635 unsigned short vendor; /* subsystem vendor id */
2636};
2637
2638static const struct ess_device_list pm_allowlist[] = {
2639 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2640 { TYPE_MAESTRO2E, 0x1028 },
2641 { TYPE_MAESTRO2E, 0x103c },
2642 { TYPE_MAESTRO2E, 0x1179 },
2643 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2644 { TYPE_MAESTRO2E, 0x1558 },
2645 { TYPE_MAESTRO2E, 0x125d }, /* a PCI card, e.g. Terratec DMX */
2646 { TYPE_MAESTRO2, 0x125d }, /* a PCI card, e.g. SF64-PCE2 */
2647};
2648
2649static const struct ess_device_list mpu_denylist[] = {
2650 { TYPE_MAESTRO2, 0x125d },
2651};
2652
2653static int snd_es1968_create(struct snd_card *card,
2654 struct pci_dev *pci,
2655 int total_bufsize,
2656 int play_streams,
2657 int capt_streams,
2658 int chip_type,
2659 int do_pm,
2660 int radio_nr,
2661 struct es1968 **chip_ret)
2662{
2663 static const struct snd_device_ops ops = {
2664 .dev_free = snd_es1968_dev_free,
2665 };
2666 struct es1968 *chip;
2667 int i, err;
2668
2669 *chip_ret = NULL;
2670
2671 /* enable PCI device */
2672 err = pci_enable_device(pci);
2673 if (err < 0)
2674 return err;
2675 /* check, if we can restrict PCI DMA transfers to 28 bits */
2676 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28))) {
2677 dev_err(card->dev,
2678 "architecture does not support 28bit PCI busmaster DMA\n");
2679 pci_disable_device(pci);
2680 return -ENXIO;
2681 }
2682
2683 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2684 if (! chip) {
2685 pci_disable_device(pci);
2686 return -ENOMEM;
2687 }
2688
2689 /* Set Vars */
2690 chip->type = chip_type;
2691 spin_lock_init(&chip->reg_lock);
2692 spin_lock_init(&chip->substream_lock);
2693 INIT_LIST_HEAD(&chip->buf_list);
2694 INIT_LIST_HEAD(&chip->substream_list);
2695 mutex_init(&chip->memory_mutex);
2696 INIT_WORK(&chip->hwvol_work, es1968_update_hw_volume);
2697 chip->card = card;
2698 chip->pci = pci;
2699 chip->irq = -1;
2700 chip->total_bufsize = total_bufsize; /* in bytes */
2701 chip->playback_streams = play_streams;
2702 chip->capture_streams = capt_streams;
2703
2704 err = pci_request_regions(pci, "ESS Maestro");
2705 if (err < 0) {
2706 kfree(chip);
2707 pci_disable_device(pci);
2708 return err;
2709 }
2710 chip->io_port = pci_resource_start(pci, 0);
2711 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2712 KBUILD_MODNAME, chip)) {
2713 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2714 snd_es1968_free(chip);
2715 return -EBUSY;
2716 }
2717 chip->irq = pci->irq;
2718 card->sync_irq = chip->irq;
2719
2720 /* Clear Maestro_map */
2721 for (i = 0; i < 32; i++)
2722 chip->maestro_map[i] = 0;
2723
2724 /* Clear Apu Map */
2725 for (i = 0; i < NR_APUS; i++)
2726 chip->apu[i] = ESM_APU_FREE;
2727
2728 /* just to be sure */
2729 pci_set_master(pci);
2730
2731 if (do_pm > 1) {
2732 /* disable power-management if not on the allowlist */
2733 unsigned short vend;
2734 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2735 for (i = 0; i < (int)ARRAY_SIZE(pm_allowlist); i++) {
2736 if (chip->type == pm_allowlist[i].type &&
2737 vend == pm_allowlist[i].vendor) {
2738 do_pm = 1;
2739 break;
2740 }
2741 }
2742 if (do_pm > 1) {
2743 /* not matched; disabling pm */
2744 dev_info(card->dev, "not attempting power management.\n");
2745 do_pm = 0;
2746 }
2747 }
2748 chip->do_pm = do_pm;
2749
2750 snd_es1968_chip_init(chip);
2751
2752 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2753 if (err < 0) {
2754 snd_es1968_free(chip);
2755 return err;
2756 }
2757
2758#ifdef CONFIG_SND_ES1968_RADIO
2759 /* don't play with GPIOs on laptops */
2760 if (chip->pci->subsystem_vendor != 0x125d)
2761 goto no_radio;
2762 err = v4l2_device_register(&pci->dev, &chip->v4l2_dev);
2763 if (err < 0) {
2764 snd_es1968_free(chip);
2765 return err;
2766 }
2767 chip->tea.v4l2_dev = &chip->v4l2_dev;
2768 chip->tea.private_data = chip;
2769 chip->tea.radio_nr = radio_nr;
2770 chip->tea.ops = &snd_es1968_tea_ops;
2771 sprintf(chip->tea.bus_info, "PCI:%s", pci_name(pci));
2772 for (i = 0; i < ARRAY_SIZE(snd_es1968_tea575x_gpios); i++) {
2773 chip->tea575x_tuner = i;
2774 if (!snd_tea575x_init(&chip->tea, THIS_MODULE)) {
2775 dev_info(card->dev, "detected TEA575x radio type %s\n",
2776 get_tea575x_gpio(chip)->name);
2777 strscpy(chip->tea.card, get_tea575x_gpio(chip)->name,
2778 sizeof(chip->tea.card));
2779 break;
2780 }
2781 }
2782no_radio:
2783#endif
2784
2785 *chip_ret = chip;
2786
2787 return 0;
2788}
2789
2790
2791/*
2792 */
2793static int snd_es1968_probe(struct pci_dev *pci,
2794 const struct pci_device_id *pci_id)
2795{
2796 static int dev;
2797 struct snd_card *card;
2798 struct es1968 *chip;
2799 unsigned int i;
2800 int err;
2801
2802 if (dev >= SNDRV_CARDS)
2803 return -ENODEV;
2804 if (!enable[dev]) {
2805 dev++;
2806 return -ENOENT;
2807 }
2808
2809 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2810 0, &card);
2811 if (err < 0)
2812 return err;
2813
2814 if (total_bufsize[dev] < 128)
2815 total_bufsize[dev] = 128;
2816 if (total_bufsize[dev] > 4096)
2817 total_bufsize[dev] = 4096;
2818 err = snd_es1968_create(card, pci,
2819 total_bufsize[dev] * 1024, /* in bytes */
2820 pcm_substreams_p[dev],
2821 pcm_substreams_c[dev],
2822 pci_id->driver_data,
2823 use_pm[dev],
2824 radio_nr[dev],
2825 &chip);
2826 if (err < 0) {
2827 snd_card_free(card);
2828 return err;
2829 }
2830 card->private_data = chip;
2831
2832 switch (chip->type) {
2833 case TYPE_MAESTRO2E:
2834 strcpy(card->driver, "ES1978");
2835 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2836 break;
2837 case TYPE_MAESTRO2:
2838 strcpy(card->driver, "ES1968");
2839 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2840 break;
2841 case TYPE_MAESTRO:
2842 strcpy(card->driver, "ESM1");
2843 strcpy(card->shortname, "ESS Maestro 1");
2844 break;
2845 }
2846
2847 err = snd_es1968_pcm(chip, 0);
2848 if (err < 0) {
2849 snd_card_free(card);
2850 return err;
2851 }
2852
2853 err = snd_es1968_mixer(chip);
2854 if (err < 0) {
2855 snd_card_free(card);
2856 return err;
2857 }
2858
2859 if (enable_mpu[dev] == 2) {
2860 /* check the deny list */
2861 unsigned short vend;
2862 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2863 for (i = 0; i < ARRAY_SIZE(mpu_denylist); i++) {
2864 if (chip->type == mpu_denylist[i].type &&
2865 vend == mpu_denylist[i].vendor) {
2866 enable_mpu[dev] = 0;
2867 break;
2868 }
2869 }
2870 }
2871 if (enable_mpu[dev]) {
2872 err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2873 chip->io_port + ESM_MPU401_PORT,
2874 MPU401_INFO_INTEGRATED |
2875 MPU401_INFO_IRQ_HOOK,
2876 -1, &chip->rmidi);
2877 if (err < 0)
2878 dev_warn(card->dev, "skipping MPU-401 MIDI support..\n");
2879 }
2880
2881 snd_es1968_create_gameport(chip, dev);
2882
2883#ifdef CONFIG_SND_ES1968_INPUT
2884 err = snd_es1968_input_register(chip);
2885 if (err)
2886 dev_warn(card->dev,
2887 "Input device registration failed with error %i", err);
2888#endif
2889
2890 snd_es1968_start_irq(chip);
2891
2892 chip->clock = clock[dev];
2893 if (! chip->clock)
2894 es1968_measure_clock(chip);
2895
2896 sprintf(card->longname, "%s at 0x%lx, irq %i",
2897 card->shortname, chip->io_port, chip->irq);
2898
2899 err = snd_card_register(card);
2900 if (err < 0) {
2901 snd_card_free(card);
2902 return err;
2903 }
2904 pci_set_drvdata(pci, card);
2905 dev++;
2906 return 0;
2907}
2908
2909static void snd_es1968_remove(struct pci_dev *pci)
2910{
2911 snd_card_free(pci_get_drvdata(pci));
2912}
2913
2914static struct pci_driver es1968_driver = {
2915 .name = KBUILD_MODNAME,
2916 .id_table = snd_es1968_ids,
2917 .probe = snd_es1968_probe,
2918 .remove = snd_es1968_remove,
2919 .driver = {
2920 .pm = ES1968_PM_OPS,
2921 },
2922};
2923
2924module_pci_driver(es1968_driver);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
4 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
5 * Takashi Iwai <tiwai@suse.de>
6 *
7 * Most of the driver code comes from Zach Brown(zab@redhat.com)
8 * Alan Cox OSS Driver
9 * Rewritted from card-es1938.c source.
10 *
11 * TODO:
12 * Perhaps Synth
13 *
14 * Notes from Zach Brown about the driver code
15 *
16 * Hardware Description
17 *
18 * A working Maestro setup contains the Maestro chip wired to a
19 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
20 * Wavecache. The APUs can be though of as virtual audio routing
21 * channels. They can take data from a number of sources and perform
22 * basic encodings of the data. The wavecache is a storehouse for
23 * PCM data. Typically it deals with PCI and interracts with the
24 * APUs. The ASSP is a wacky DSP like device that ESS is loth
25 * to release docs on. Thankfully it isn't required on the Maestro
26 * until you start doing insane things like FM emulation and surround
27 * encoding. The codecs are almost always AC-97 compliant codecs,
28 * but it appears that early Maestros may have had PT101 (an ESS
29 * part?) wired to them. The only real difference in the Maestro
30 * families is external goop like docking capability, memory for
31 * the ASSP, and initialization differences.
32 *
33 * Driver Operation
34 *
35 * We only drive the APU/Wavecache as typical DACs and drive the
36 * mixers in the codecs. There are 64 APUs. We assign 6 to each
37 * /dev/dsp? device. 2 channels for output, and 4 channels for
38 * input.
39 *
40 * Each APU can do a number of things, but we only really use
41 * 3 basic functions. For playback we use them to convert PCM
42 * data fetched over PCI by the wavecahche into analog data that
43 * is handed to the codec. One APU for mono, and a pair for stereo.
44 * When in stereo, the combination of smarts in the APU and Wavecache
45 * decide which wavecache gets the left or right channel.
46 *
47 * For record we still use the old overly mono system. For each in
48 * coming channel the data comes in from the codec, through a 'input'
49 * APU, through another rate converter APU, and then into memory via
50 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
51 * software. The pass between the 2 APUs is supposedly what requires us
52 * to have a 512 byte buffer sitting around in wavecache/memory.
53 *
54 * The wavecache makes our life even more fun. First off, it can
55 * only address the first 28 bits of PCI address space, making it
56 * useless on quite a few architectures. Secondly, its insane.
57 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
58 * But that doesn't really work. You can only use 1 region. So all our
59 * allocations have to be in 4meg of each other. Booo. Hiss.
60 * So we have a module parameter, dsps_order, that is the order of
61 * the number of dsps to provide. All their buffer space is allocated
62 * on open time. The sonicvibes OSS routines we inherited really want
63 * power of 2 buffers, so we have all those next to each other, then
64 * 512 byte regions for the recording wavecaches. This ends up
65 * wasting quite a bit of memory. The only fixes I can see would be
66 * getting a kernel allocator that could work in zones, or figuring out
67 * just how to coerce the WP into doing what we want.
68 *
69 * The indirection of the various registers means we have to spinlock
70 * nearly all register accesses. We have the main register indirection
71 * like the wave cache, maestro registers, etc. Then we have beasts
72 * like the APU interface that is indirect registers gotten at through
73 * the main maestro indirection. Ouch. We spinlock around the actual
74 * ports on a per card basis. This means spinlock activity at each IO
75 * operation, but the only IO operation clusters are in non critical
76 * paths and it makes the code far easier to follow. Interrupts are
77 * blocked while holding the locks because the int handler has to
78 * get at some of them :(. The mixer interface doesn't, however.
79 * We also have an OSS state lock that is thrown around in a few
80 * places.
81 */
82
83#include <linux/io.h>
84#include <linux/delay.h>
85#include <linux/interrupt.h>
86#include <linux/init.h>
87#include <linux/pci.h>
88#include <linux/dma-mapping.h>
89#include <linux/slab.h>
90#include <linux/gameport.h>
91#include <linux/module.h>
92#include <linux/mutex.h>
93#include <linux/input.h>
94
95#include <sound/core.h>
96#include <sound/pcm.h>
97#include <sound/mpu401.h>
98#include <sound/ac97_codec.h>
99#include <sound/initval.h>
100
101#ifdef CONFIG_SND_ES1968_RADIO
102#include <media/drv-intf/tea575x.h>
103#endif
104
105#define CARD_NAME "ESS Maestro1/2"
106#define DRIVER_NAME "ES1968"
107
108MODULE_DESCRIPTION("ESS Maestro");
109MODULE_LICENSE("GPL");
110MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
111 "{ESS,Maestro 2},"
112 "{ESS,Maestro 1},"
113 "{TerraTec,DMX}}");
114
115#if IS_REACHABLE(CONFIG_GAMEPORT)
116#define SUPPORT_JOYSTICK 1
117#endif
118
119static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
120static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
121static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
122static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
123static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
124static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
125static int clock[SNDRV_CARDS];
126static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
127static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
128#ifdef SUPPORT_JOYSTICK
129static bool joystick[SNDRV_CARDS];
130#endif
131static int radio_nr[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
132
133module_param_array(index, int, NULL, 0444);
134MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
135module_param_array(id, charp, NULL, 0444);
136MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
137module_param_array(enable, bool, NULL, 0444);
138MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
139module_param_array(total_bufsize, int, NULL, 0444);
140MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
141module_param_array(pcm_substreams_p, int, NULL, 0444);
142MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
143module_param_array(pcm_substreams_c, int, NULL, 0444);
144MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
145module_param_array(clock, int, NULL, 0444);
146MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
147module_param_array(use_pm, int, NULL, 0444);
148MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
149module_param_array(enable_mpu, int, NULL, 0444);
150MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
151#ifdef SUPPORT_JOYSTICK
152module_param_array(joystick, bool, NULL, 0444);
153MODULE_PARM_DESC(joystick, "Enable joystick.");
154#endif
155module_param_array(radio_nr, int, NULL, 0444);
156MODULE_PARM_DESC(radio_nr, "Radio device numbers");
157
158
159
160#define NR_APUS 64
161#define NR_APU_REGS 16
162
163/* NEC Versas ? */
164#define NEC_VERSA_SUBID1 0x80581033
165#define NEC_VERSA_SUBID2 0x803c1033
166
167/* Mode Flags */
168#define ESS_FMT_STEREO 0x01
169#define ESS_FMT_16BIT 0x02
170
171#define DAC_RUNNING 1
172#define ADC_RUNNING 2
173
174/* Values for the ESM_LEGACY_AUDIO_CONTROL */
175
176#define ESS_DISABLE_AUDIO 0x8000
177#define ESS_ENABLE_SERIAL_IRQ 0x4000
178#define IO_ADRESS_ALIAS 0x0020
179#define MPU401_IRQ_ENABLE 0x0010
180#define MPU401_IO_ENABLE 0x0008
181#define GAME_IO_ENABLE 0x0004
182#define FM_IO_ENABLE 0x0002
183#define SB_IO_ENABLE 0x0001
184
185/* Values for the ESM_CONFIG_A */
186
187#define PIC_SNOOP1 0x4000
188#define PIC_SNOOP2 0x2000
189#define SAFEGUARD 0x0800
190#define DMA_CLEAR 0x0700
191#define DMA_DDMA 0x0000
192#define DMA_TDMA 0x0100
193#define DMA_PCPCI 0x0200
194#define POST_WRITE 0x0080
195#define PCI_TIMING 0x0040
196#define SWAP_LR 0x0020
197#define SUBTR_DECODE 0x0002
198
199/* Values for the ESM_CONFIG_B */
200
201#define SPDIF_CONFB 0x0100
202#define HWV_CONFB 0x0080
203#define DEBOUNCE 0x0040
204#define GPIO_CONFB 0x0020
205#define CHI_CONFB 0x0010
206#define IDMA_CONFB 0x0008 /*undoc */
207#define MIDI_FIX 0x0004 /*undoc */
208#define IRQ_TO_ISA 0x0001 /*undoc */
209
210/* Values for Ring Bus Control B */
211#define RINGB_2CODEC_ID_MASK 0x0003
212#define RINGB_DIS_VALIDATION 0x0008
213#define RINGB_EN_SPDIF 0x0010
214#define RINGB_EN_2CODEC 0x0020
215#define RINGB_SING_BIT_DUAL 0x0040
216
217/* ****Port Addresses**** */
218
219/* Write & Read */
220#define ESM_INDEX 0x02
221#define ESM_DATA 0x00
222
223/* AC97 + RingBus */
224#define ESM_AC97_INDEX 0x30
225#define ESM_AC97_DATA 0x32
226#define ESM_RING_BUS_DEST 0x34
227#define ESM_RING_BUS_CONTR_A 0x36
228#define ESM_RING_BUS_CONTR_B 0x38
229#define ESM_RING_BUS_SDO 0x3A
230
231/* WaveCache*/
232#define WC_INDEX 0x10
233#define WC_DATA 0x12
234#define WC_CONTROL 0x14
235
236/* ASSP*/
237#define ASSP_INDEX 0x80
238#define ASSP_MEMORY 0x82
239#define ASSP_DATA 0x84
240#define ASSP_CONTROL_A 0xA2
241#define ASSP_CONTROL_B 0xA4
242#define ASSP_CONTROL_C 0xA6
243#define ASSP_HOSTW_INDEX 0xA8
244#define ASSP_HOSTW_DATA 0xAA
245#define ASSP_HOSTW_IRQ 0xAC
246/* Midi */
247#define ESM_MPU401_PORT 0x98
248/* Others */
249#define ESM_PORT_HOST_IRQ 0x18
250
251#define IDR0_DATA_PORT 0x00
252#define IDR1_CRAM_POINTER 0x01
253#define IDR2_CRAM_DATA 0x02
254#define IDR3_WAVE_DATA 0x03
255#define IDR4_WAVE_PTR_LOW 0x04
256#define IDR5_WAVE_PTR_HI 0x05
257#define IDR6_TIMER_CTRL 0x06
258#define IDR7_WAVE_ROMRAM 0x07
259
260#define WRITEABLE_MAP 0xEFFFFF
261#define READABLE_MAP 0x64003F
262
263/* PCI Register */
264
265#define ESM_LEGACY_AUDIO_CONTROL 0x40
266#define ESM_ACPI_COMMAND 0x54
267#define ESM_CONFIG_A 0x50
268#define ESM_CONFIG_B 0x52
269#define ESM_DDMA 0x60
270
271/* Bob Bits */
272#define ESM_BOB_ENABLE 0x0001
273#define ESM_BOB_START 0x0001
274
275/* Host IRQ Control Bits */
276#define ESM_RESET_MAESTRO 0x8000
277#define ESM_RESET_DIRECTSOUND 0x4000
278#define ESM_HIRQ_ClkRun 0x0100
279#define ESM_HIRQ_HW_VOLUME 0x0040
280#define ESM_HIRQ_HARPO 0x0030 /* What's that? */
281#define ESM_HIRQ_ASSP 0x0010
282#define ESM_HIRQ_DSIE 0x0004
283#define ESM_HIRQ_MPU401 0x0002
284#define ESM_HIRQ_SB 0x0001
285
286/* Host IRQ Status Bits */
287#define ESM_MPU401_IRQ 0x02
288#define ESM_SB_IRQ 0x01
289#define ESM_SOUND_IRQ 0x04
290#define ESM_ASSP_IRQ 0x10
291#define ESM_HWVOL_IRQ 0x40
292
293#define ESS_SYSCLK 50000000
294#define ESM_BOB_FREQ 200
295#define ESM_BOB_FREQ_MAX 800
296
297#define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
298#define ESM_FREQ_ESM2 (50000000L / 1024L)
299
300/* APU Modes: reg 0x00, bit 4-7 */
301#define ESM_APU_MODE_SHIFT 4
302#define ESM_APU_MODE_MASK (0xf << 4)
303#define ESM_APU_OFF 0x00
304#define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
305#define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
306#define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
307#define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
308#define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
309#define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
310#define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
311#define ESM_APU_CORRELATOR 0x08 /* Correlator */
312#define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
313#define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
314#define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
315#define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
316#define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
317#define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
318#define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
319
320/* reg 0x00 */
321#define ESM_APU_FILTER_Q_SHIFT 0
322#define ESM_APU_FILTER_Q_MASK (3 << 0)
323/* APU Filtey Q Control */
324#define ESM_APU_FILTER_LESSQ 0x00
325#define ESM_APU_FILTER_MOREQ 0x03
326
327#define ESM_APU_FILTER_TYPE_SHIFT 2
328#define ESM_APU_FILTER_TYPE_MASK (3 << 2)
329#define ESM_APU_ENV_TYPE_SHIFT 8
330#define ESM_APU_ENV_TYPE_MASK (3 << 8)
331#define ESM_APU_ENV_STATE_SHIFT 10
332#define ESM_APU_ENV_STATE_MASK (3 << 10)
333#define ESM_APU_END_CURVE (1 << 12)
334#define ESM_APU_INT_ON_LOOP (1 << 13)
335#define ESM_APU_DMA_ENABLE (1 << 14)
336
337/* reg 0x02 */
338#define ESM_APU_SUBMIX_GROUP_SHIRT 0
339#define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
340#define ESM_APU_SUBMIX_MODE (1 << 3)
341#define ESM_APU_6dB (1 << 4)
342#define ESM_APU_DUAL_EFFECT (1 << 5)
343#define ESM_APU_EFFECT_CHANNELS_SHIFT 6
344#define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
345
346/* reg 0x03 */
347#define ESM_APU_STEP_SIZE_MASK 0x0fff
348
349/* reg 0x04 */
350#define ESM_APU_PHASE_SHIFT 0
351#define ESM_APU_PHASE_MASK (0xff << 0)
352#define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
353#define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
354
355/* reg 0x05 - wave start offset */
356/* reg 0x06 - wave end offset */
357/* reg 0x07 - wave loop length */
358
359/* reg 0x08 */
360#define ESM_APU_EFFECT_GAIN_SHIFT 0
361#define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
362#define ESM_APU_TREMOLO_DEPTH_SHIFT 8
363#define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
364#define ESM_APU_TREMOLO_RATE_SHIFT 12
365#define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
366
367/* reg 0x09 */
368/* bit 0-7 amplitude dest? */
369#define ESM_APU_AMPLITUDE_NOW_SHIFT 8
370#define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
371
372/* reg 0x0a */
373#define ESM_APU_POLAR_PAN_SHIFT 0
374#define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
375/* Polar Pan Control */
376#define ESM_APU_PAN_CENTER_CIRCLE 0x00
377#define ESM_APU_PAN_MIDDLE_RADIUS 0x01
378#define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
379
380#define ESM_APU_FILTER_TUNING_SHIFT 8
381#define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
382
383/* reg 0x0b */
384#define ESM_APU_DATA_SRC_A_SHIFT 0
385#define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
386#define ESM_APU_INV_POL_A (1 << 7)
387#define ESM_APU_DATA_SRC_B_SHIFT 8
388#define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
389#define ESM_APU_INV_POL_B (1 << 15)
390
391#define ESM_APU_VIBRATO_RATE_SHIFT 0
392#define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
393#define ESM_APU_VIBRATO_DEPTH_SHIFT 4
394#define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
395#define ESM_APU_VIBRATO_PHASE_SHIFT 8
396#define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
397
398/* reg 0x0c */
399#define ESM_APU_RADIUS_SELECT (1 << 6)
400
401/* APU Filter Control */
402#define ESM_APU_FILTER_2POLE_LOPASS 0x00
403#define ESM_APU_FILTER_2POLE_BANDPASS 0x01
404#define ESM_APU_FILTER_2POLE_HIPASS 0x02
405#define ESM_APU_FILTER_1POLE_LOPASS 0x03
406#define ESM_APU_FILTER_1POLE_HIPASS 0x04
407#define ESM_APU_FILTER_OFF 0x05
408
409/* APU ATFP Type */
410#define ESM_APU_ATFP_AMPLITUDE 0x00
411#define ESM_APU_ATFP_TREMELO 0x01
412#define ESM_APU_ATFP_FILTER 0x02
413#define ESM_APU_ATFP_PAN 0x03
414
415/* APU ATFP Flags */
416#define ESM_APU_ATFP_FLG_OFF 0x00
417#define ESM_APU_ATFP_FLG_WAIT 0x01
418#define ESM_APU_ATFP_FLG_DONE 0x02
419#define ESM_APU_ATFP_FLG_INPROCESS 0x03
420
421
422/* capture mixing buffer size */
423#define ESM_MEM_ALIGN 0x1000
424#define ESM_MIXBUF_SIZE 0x400
425
426#define ESM_MODE_PLAY 0
427#define ESM_MODE_CAPTURE 1
428
429
430/* APU use in the driver */
431enum snd_enum_apu_type {
432 ESM_APU_PCM_PLAY,
433 ESM_APU_PCM_CAPTURE,
434 ESM_APU_PCM_RATECONV,
435 ESM_APU_FREE
436};
437
438/* chip type */
439enum {
440 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
441};
442
443/* DMA Hack! */
444struct esm_memory {
445 struct snd_dma_buffer buf;
446 int empty; /* status */
447 struct list_head list;
448};
449
450/* Playback Channel */
451struct esschan {
452 int running;
453
454 u8 apu[4];
455 u8 apu_mode[4];
456
457 /* playback/capture pcm buffer */
458 struct esm_memory *memory;
459 /* capture mixer buffer */
460 struct esm_memory *mixbuf;
461
462 unsigned int hwptr; /* current hw pointer in bytes */
463 unsigned int count; /* sample counter in bytes */
464 unsigned int dma_size; /* total buffer size in bytes */
465 unsigned int frag_size; /* period size in bytes */
466 unsigned int wav_shift;
467 u16 base[4]; /* offset for ptr */
468
469 /* stereo/16bit flag */
470 unsigned char fmt;
471 int mode; /* playback / capture */
472
473 int bob_freq; /* required timer frequency */
474
475 struct snd_pcm_substream *substream;
476
477 /* linked list */
478 struct list_head list;
479
480#ifdef CONFIG_PM_SLEEP
481 u16 wc_map[4];
482#endif
483};
484
485struct es1968 {
486 /* Module Config */
487 int total_bufsize; /* in bytes */
488
489 int playback_streams, capture_streams;
490
491 unsigned int clock; /* clock */
492 /* for clock measurement */
493 unsigned int in_measurement: 1;
494 unsigned int measure_apu;
495 unsigned int measure_lastpos;
496 unsigned int measure_count;
497
498 /* buffer */
499 struct snd_dma_buffer dma;
500
501 /* Resources... */
502 int irq;
503 unsigned long io_port;
504 int type;
505 struct pci_dev *pci;
506 struct snd_card *card;
507 struct snd_pcm *pcm;
508 int do_pm; /* power-management enabled */
509
510 /* DMA memory block */
511 struct list_head buf_list;
512
513 /* ALSA Stuff */
514 struct snd_ac97 *ac97;
515 struct snd_rawmidi *rmidi;
516
517 spinlock_t reg_lock;
518 unsigned int in_suspend;
519
520 /* Maestro Stuff */
521 u16 maestro_map[32];
522 int bobclient; /* active timer instancs */
523 int bob_freq; /* timer frequency */
524 struct mutex memory_mutex; /* memory lock */
525
526 /* APU states */
527 unsigned char apu[NR_APUS];
528
529 /* active substreams */
530 struct list_head substream_list;
531 spinlock_t substream_lock;
532
533#ifdef CONFIG_PM_SLEEP
534 u16 apu_map[NR_APUS][NR_APU_REGS];
535#endif
536
537#ifdef SUPPORT_JOYSTICK
538 struct gameport *gameport;
539#endif
540
541#ifdef CONFIG_SND_ES1968_INPUT
542 struct input_dev *input_dev;
543 char phys[64]; /* physical device path */
544#else
545 struct snd_kcontrol *master_switch; /* for h/w volume control */
546 struct snd_kcontrol *master_volume;
547#endif
548 struct work_struct hwvol_work;
549
550#ifdef CONFIG_SND_ES1968_RADIO
551 struct v4l2_device v4l2_dev;
552 struct snd_tea575x tea;
553 unsigned int tea575x_tuner;
554#endif
555};
556
557static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
558
559static const struct pci_device_id snd_es1968_ids[] = {
560 /* Maestro 1 */
561 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
562 /* Maestro 2 */
563 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
564 /* Maestro 2E */
565 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
566 { 0, }
567};
568
569MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
570
571/* *********************
572 * Low Level Funcs! *
573 *********************/
574
575/* no spinlock */
576static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
577{
578 outw(reg, chip->io_port + ESM_INDEX);
579 outw(data, chip->io_port + ESM_DATA);
580 chip->maestro_map[reg] = data;
581}
582
583static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
584{
585 unsigned long flags;
586 spin_lock_irqsave(&chip->reg_lock, flags);
587 __maestro_write(chip, reg, data);
588 spin_unlock_irqrestore(&chip->reg_lock, flags);
589}
590
591/* no spinlock */
592static u16 __maestro_read(struct es1968 *chip, u16 reg)
593{
594 if (READABLE_MAP & (1 << reg)) {
595 outw(reg, chip->io_port + ESM_INDEX);
596 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
597 }
598 return chip->maestro_map[reg];
599}
600
601static inline u16 maestro_read(struct es1968 *chip, u16 reg)
602{
603 unsigned long flags;
604 u16 result;
605 spin_lock_irqsave(&chip->reg_lock, flags);
606 result = __maestro_read(chip, reg);
607 spin_unlock_irqrestore(&chip->reg_lock, flags);
608 return result;
609}
610
611/* Wait for the codec bus to be free */
612static int snd_es1968_ac97_wait(struct es1968 *chip)
613{
614 int timeout = 100000;
615
616 while (timeout-- > 0) {
617 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
618 return 0;
619 cond_resched();
620 }
621 dev_dbg(chip->card->dev, "ac97 timeout\n");
622 return 1; /* timeout */
623}
624
625static int snd_es1968_ac97_wait_poll(struct es1968 *chip)
626{
627 int timeout = 100000;
628
629 while (timeout-- > 0) {
630 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
631 return 0;
632 }
633 dev_dbg(chip->card->dev, "ac97 timeout\n");
634 return 1; /* timeout */
635}
636
637static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
638{
639 struct es1968 *chip = ac97->private_data;
640
641 snd_es1968_ac97_wait(chip);
642
643 /* Write the bus */
644 outw(val, chip->io_port + ESM_AC97_DATA);
645 /*msleep(1);*/
646 outb(reg, chip->io_port + ESM_AC97_INDEX);
647 /*msleep(1);*/
648}
649
650static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
651{
652 u16 data = 0;
653 struct es1968 *chip = ac97->private_data;
654
655 snd_es1968_ac97_wait(chip);
656
657 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
658 /*msleep(1);*/
659
660 if (!snd_es1968_ac97_wait_poll(chip)) {
661 data = inw(chip->io_port + ESM_AC97_DATA);
662 /*msleep(1);*/
663 }
664
665 return data;
666}
667
668/* no spinlock */
669static void apu_index_set(struct es1968 *chip, u16 index)
670{
671 int i;
672 __maestro_write(chip, IDR1_CRAM_POINTER, index);
673 for (i = 0; i < 1000; i++)
674 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
675 return;
676 dev_dbg(chip->card->dev, "APU register select failed. (Timeout)\n");
677}
678
679/* no spinlock */
680static void apu_data_set(struct es1968 *chip, u16 data)
681{
682 int i;
683 for (i = 0; i < 1000; i++) {
684 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
685 return;
686 __maestro_write(chip, IDR0_DATA_PORT, data);
687 }
688 dev_dbg(chip->card->dev, "APU register set probably failed (Timeout)!\n");
689}
690
691/* no spinlock */
692static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
693{
694 if (snd_BUG_ON(channel >= NR_APUS))
695 return;
696#ifdef CONFIG_PM_SLEEP
697 chip->apu_map[channel][reg] = data;
698#endif
699 reg |= (channel << 4);
700 apu_index_set(chip, reg);
701 apu_data_set(chip, data);
702}
703
704static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
705{
706 unsigned long flags;
707 spin_lock_irqsave(&chip->reg_lock, flags);
708 __apu_set_register(chip, channel, reg, data);
709 spin_unlock_irqrestore(&chip->reg_lock, flags);
710}
711
712static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
713{
714 if (snd_BUG_ON(channel >= NR_APUS))
715 return 0;
716 reg |= (channel << 4);
717 apu_index_set(chip, reg);
718 return __maestro_read(chip, IDR0_DATA_PORT);
719}
720
721static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
722{
723 unsigned long flags;
724 u16 v;
725 spin_lock_irqsave(&chip->reg_lock, flags);
726 v = __apu_get_register(chip, channel, reg);
727 spin_unlock_irqrestore(&chip->reg_lock, flags);
728 return v;
729}
730
731#if 0 /* ASSP is not supported */
732
733static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
734{
735 unsigned long flags;
736
737 spin_lock_irqsave(&chip->reg_lock, flags);
738 outl(reg, chip->io_port + ASSP_INDEX);
739 outl(value, chip->io_port + ASSP_DATA);
740 spin_unlock_irqrestore(&chip->reg_lock, flags);
741}
742
743static u32 assp_get_register(struct es1968 *chip, u32 reg)
744{
745 unsigned long flags;
746 u32 value;
747
748 spin_lock_irqsave(&chip->reg_lock, flags);
749 outl(reg, chip->io_port + ASSP_INDEX);
750 value = inl(chip->io_port + ASSP_DATA);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
752
753 return value;
754}
755
756#endif
757
758static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
759{
760 unsigned long flags;
761
762 spin_lock_irqsave(&chip->reg_lock, flags);
763 outw(reg, chip->io_port + WC_INDEX);
764 outw(value, chip->io_port + WC_DATA);
765 spin_unlock_irqrestore(&chip->reg_lock, flags);
766}
767
768static u16 wave_get_register(struct es1968 *chip, u16 reg)
769{
770 unsigned long flags;
771 u16 value;
772
773 spin_lock_irqsave(&chip->reg_lock, flags);
774 outw(reg, chip->io_port + WC_INDEX);
775 value = inw(chip->io_port + WC_DATA);
776 spin_unlock_irqrestore(&chip->reg_lock, flags);
777
778 return value;
779}
780
781/* *******************
782 * Bob the Timer! *
783 *******************/
784
785static void snd_es1968_bob_stop(struct es1968 *chip)
786{
787 u16 reg;
788
789 reg = __maestro_read(chip, 0x11);
790 reg &= ~ESM_BOB_ENABLE;
791 __maestro_write(chip, 0x11, reg);
792 reg = __maestro_read(chip, 0x17);
793 reg &= ~ESM_BOB_START;
794 __maestro_write(chip, 0x17, reg);
795}
796
797static void snd_es1968_bob_start(struct es1968 *chip)
798{
799 int prescale;
800 int divide;
801
802 /* compute ideal interrupt frequency for buffer size & play rate */
803 /* first, find best prescaler value to match freq */
804 for (prescale = 5; prescale < 12; prescale++)
805 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
806 break;
807
808 /* next, back off prescaler whilst getting divider into optimum range */
809 divide = 1;
810 while ((prescale > 5) && (divide < 32)) {
811 prescale--;
812 divide <<= 1;
813 }
814 divide >>= 1;
815
816 /* now fine-tune the divider for best match */
817 for (; divide < 31; divide++)
818 if (chip->bob_freq >
819 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
820
821 /* divide = 0 is illegal, but don't let prescale = 4! */
822 if (divide == 0) {
823 divide++;
824 if (prescale > 5)
825 prescale--;
826 } else if (divide > 1)
827 divide--;
828
829 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
830
831 /* Now set IDR 11/17 */
832 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
833 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
834}
835
836/* call with substream spinlock */
837static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
838{
839 chip->bobclient++;
840 if (chip->bobclient == 1) {
841 chip->bob_freq = freq;
842 snd_es1968_bob_start(chip);
843 } else if (chip->bob_freq < freq) {
844 snd_es1968_bob_stop(chip);
845 chip->bob_freq = freq;
846 snd_es1968_bob_start(chip);
847 }
848}
849
850/* call with substream spinlock */
851static void snd_es1968_bob_dec(struct es1968 *chip)
852{
853 chip->bobclient--;
854 if (chip->bobclient <= 0)
855 snd_es1968_bob_stop(chip);
856 else if (chip->bob_freq > ESM_BOB_FREQ) {
857 /* check reduction of timer frequency */
858 int max_freq = ESM_BOB_FREQ;
859 struct esschan *es;
860 list_for_each_entry(es, &chip->substream_list, list) {
861 if (max_freq < es->bob_freq)
862 max_freq = es->bob_freq;
863 }
864 if (max_freq != chip->bob_freq) {
865 snd_es1968_bob_stop(chip);
866 chip->bob_freq = max_freq;
867 snd_es1968_bob_start(chip);
868 }
869 }
870}
871
872static int
873snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
874 struct snd_pcm_runtime *runtime)
875{
876 /* we acquire 4 interrupts per period for precise control.. */
877 int freq = runtime->rate * 4;
878 if (es->fmt & ESS_FMT_STEREO)
879 freq <<= 1;
880 if (es->fmt & ESS_FMT_16BIT)
881 freq <<= 1;
882 freq /= es->frag_size;
883 if (freq < ESM_BOB_FREQ)
884 freq = ESM_BOB_FREQ;
885 else if (freq > ESM_BOB_FREQ_MAX)
886 freq = ESM_BOB_FREQ_MAX;
887 return freq;
888}
889
890
891/*************
892 * PCM Part *
893 *************/
894
895static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
896{
897 u32 rate = (freq << 16) / chip->clock;
898#if 0 /* XXX: do we need this? */
899 if (rate > 0x10000)
900 rate = 0x10000;
901#endif
902 return rate;
903}
904
905/* get current pointer */
906static inline unsigned int
907snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
908{
909 unsigned int offset;
910
911 offset = apu_get_register(chip, es->apu[0], 5);
912
913 offset -= es->base[0];
914
915 return (offset & 0xFFFE); /* hardware is in words */
916}
917
918static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
919{
920 apu_set_register(chip, apu, 2,
921 (apu_get_register(chip, apu, 2) & 0x00FF) |
922 ((freq & 0xff) << 8) | 0x10);
923 apu_set_register(chip, apu, 3, freq >> 8);
924}
925
926/* spin lock held */
927static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
928{
929 /* set the APU mode */
930 __apu_set_register(esm, apu, 0,
931 (__apu_get_register(esm, apu, 0) & 0xff0f) |
932 (mode << 4));
933}
934
935static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
936{
937 spin_lock(&chip->reg_lock);
938 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
939 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
940 if (es->mode == ESM_MODE_CAPTURE) {
941 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
942 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
943 }
944 if (es->fmt & ESS_FMT_STEREO) {
945 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
946 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
947 if (es->mode == ESM_MODE_CAPTURE) {
948 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
949 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
950 }
951 }
952 spin_unlock(&chip->reg_lock);
953}
954
955static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
956{
957 spin_lock(&chip->reg_lock);
958 snd_es1968_trigger_apu(chip, es->apu[0], 0);
959 snd_es1968_trigger_apu(chip, es->apu[1], 0);
960 if (es->mode == ESM_MODE_CAPTURE) {
961 snd_es1968_trigger_apu(chip, es->apu[2], 0);
962 snd_es1968_trigger_apu(chip, es->apu[3], 0);
963 }
964 spin_unlock(&chip->reg_lock);
965}
966
967/* set the wavecache control reg */
968static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
969 int channel, u32 addr, int capture)
970{
971 u32 tmpval = (addr - 0x10) & 0xFFF8;
972
973 if (! capture) {
974 if (!(es->fmt & ESS_FMT_16BIT))
975 tmpval |= 4; /* 8bit */
976 if (es->fmt & ESS_FMT_STEREO)
977 tmpval |= 2; /* stereo */
978 }
979
980 /* set the wavecache control reg */
981 wave_set_register(chip, es->apu[channel] << 3, tmpval);
982
983#ifdef CONFIG_PM_SLEEP
984 es->wc_map[channel] = tmpval;
985#endif
986}
987
988
989static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
990 struct snd_pcm_runtime *runtime)
991{
992 u32 pa;
993 int high_apu = 0;
994 int channel, apu;
995 int i, size;
996 unsigned long flags;
997 u32 freq;
998
999 size = es->dma_size >> es->wav_shift;
1000
1001 if (es->fmt & ESS_FMT_STEREO)
1002 high_apu++;
1003
1004 for (channel = 0; channel <= high_apu; channel++) {
1005 apu = es->apu[channel];
1006
1007 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
1008
1009 /* Offset to PCMBAR */
1010 pa = es->memory->buf.addr;
1011 pa -= chip->dma.addr;
1012 pa >>= 1; /* words */
1013
1014 pa |= 0x00400000; /* System RAM (Bit 22) */
1015
1016 if (es->fmt & ESS_FMT_STEREO) {
1017 /* Enable stereo */
1018 if (channel)
1019 pa |= 0x00800000; /* (Bit 23) */
1020 if (es->fmt & ESS_FMT_16BIT)
1021 pa >>= 1;
1022 }
1023
1024 /* base offset of dma calcs when reading the pointer
1025 on this left one */
1026 es->base[channel] = pa & 0xFFFF;
1027
1028 for (i = 0; i < 16; i++)
1029 apu_set_register(chip, apu, i, 0x0000);
1030
1031 /* Load the buffer into the wave engine */
1032 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1033 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1034 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1035 /* setting loop == sample len */
1036 apu_set_register(chip, apu, 7, size);
1037
1038 /* clear effects/env.. */
1039 apu_set_register(chip, apu, 8, 0x0000);
1040 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1041 apu_set_register(chip, apu, 9, 0xD000);
1042
1043 /* clear routing stuff */
1044 apu_set_register(chip, apu, 11, 0x0000);
1045 /* dma on, no envelopes, filter to all 1s) */
1046 apu_set_register(chip, apu, 0, 0x400F);
1047
1048 if (es->fmt & ESS_FMT_16BIT)
1049 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1050 else
1051 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1052
1053 if (es->fmt & ESS_FMT_STEREO) {
1054 /* set panning: left or right */
1055 /* Check: different panning. On my Canyon 3D Chipset the
1056 Channels are swapped. I don't know, about the output
1057 to the SPDif Link. Perhaps you have to change this
1058 and not the APU Regs 4-5. */
1059 apu_set_register(chip, apu, 10,
1060 0x8F00 | (channel ? 0 : 0x10));
1061 es->apu_mode[channel] += 1; /* stereo */
1062 } else
1063 apu_set_register(chip, apu, 10, 0x8F08);
1064 }
1065
1066 spin_lock_irqsave(&chip->reg_lock, flags);
1067 /* clear WP interrupts */
1068 outw(1, chip->io_port + 0x04);
1069 /* enable WP ints */
1070 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1071 spin_unlock_irqrestore(&chip->reg_lock, flags);
1072
1073 freq = runtime->rate;
1074 /* set frequency */
1075 if (freq > 48000)
1076 freq = 48000;
1077 if (freq < 4000)
1078 freq = 4000;
1079
1080 /* hmmm.. */
1081 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1082 freq >>= 1;
1083
1084 freq = snd_es1968_compute_rate(chip, freq);
1085
1086 /* Load the frequency, turn on 6dB */
1087 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1088 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1089}
1090
1091
1092static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1093 unsigned int pa, unsigned int bsize,
1094 int mode, int route)
1095{
1096 int i, apu = es->apu[channel];
1097
1098 es->apu_mode[channel] = mode;
1099
1100 /* set the wavecache control reg */
1101 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1102
1103 /* Offset to PCMBAR */
1104 pa -= chip->dma.addr;
1105 pa >>= 1; /* words */
1106
1107 /* base offset of dma calcs when reading the pointer
1108 on this left one */
1109 es->base[channel] = pa & 0xFFFF;
1110 pa |= 0x00400000; /* bit 22 -> System RAM */
1111
1112 /* Begin loading the APU */
1113 for (i = 0; i < 16; i++)
1114 apu_set_register(chip, apu, i, 0x0000);
1115
1116 /* need to enable subgroups.. and we should probably
1117 have different groups for different /dev/dsps.. */
1118 apu_set_register(chip, apu, 2, 0x8);
1119
1120 /* Load the buffer into the wave engine */
1121 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1122 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1123 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1124 apu_set_register(chip, apu, 7, bsize);
1125 /* clear effects/env.. */
1126 apu_set_register(chip, apu, 8, 0x00F0);
1127 /* amplitude now? sure. why not. */
1128 apu_set_register(chip, apu, 9, 0x0000);
1129 /* set filter tune, radius, polar pan */
1130 apu_set_register(chip, apu, 10, 0x8F08);
1131 /* route input */
1132 apu_set_register(chip, apu, 11, route);
1133 /* dma on, no envelopes, filter to all 1s) */
1134 apu_set_register(chip, apu, 0, 0x400F);
1135}
1136
1137static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1138 struct snd_pcm_runtime *runtime)
1139{
1140 int size;
1141 u32 freq;
1142 unsigned long flags;
1143
1144 size = es->dma_size >> es->wav_shift;
1145
1146 /* APU assignments:
1147 0 = mono/left SRC
1148 1 = right SRC
1149 2 = mono/left Input Mixer
1150 3 = right Input Mixer
1151 */
1152 /* data seems to flow from the codec, through an apu into
1153 the 'mixbuf' bit of page, then through the SRC apu
1154 and out to the real 'buffer'. ok. sure. */
1155
1156 /* input mixer (left/mono) */
1157 /* parallel in crap, see maestro reg 0xC [8-11] */
1158 init_capture_apu(chip, es, 2,
1159 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1160 ESM_APU_INPUTMIXER, 0x14);
1161 /* SRC (left/mono); get input from inputing apu */
1162 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1163 ESM_APU_SRCONVERTOR, es->apu[2]);
1164 if (es->fmt & ESS_FMT_STEREO) {
1165 /* input mixer (right) */
1166 init_capture_apu(chip, es, 3,
1167 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1168 ESM_MIXBUF_SIZE/4, /* in words */
1169 ESM_APU_INPUTMIXER, 0x15);
1170 /* SRC (right) */
1171 init_capture_apu(chip, es, 1,
1172 es->memory->buf.addr + size*2, size,
1173 ESM_APU_SRCONVERTOR, es->apu[3]);
1174 }
1175
1176 freq = runtime->rate;
1177 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1178 if (freq > 47999)
1179 freq = 47999;
1180 if (freq < 4000)
1181 freq = 4000;
1182
1183 freq = snd_es1968_compute_rate(chip, freq);
1184
1185 /* Load the frequency, turn on 6dB */
1186 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1187 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1188
1189 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1190 freq = 0x10000;
1191 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1192 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1193
1194 spin_lock_irqsave(&chip->reg_lock, flags);
1195 /* clear WP interrupts */
1196 outw(1, chip->io_port + 0x04);
1197 /* enable WP ints */
1198 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1199 spin_unlock_irqrestore(&chip->reg_lock, flags);
1200}
1201
1202/*******************
1203 * ALSA Interface *
1204 *******************/
1205
1206static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1207{
1208 struct es1968 *chip = snd_pcm_substream_chip(substream);
1209 struct snd_pcm_runtime *runtime = substream->runtime;
1210 struct esschan *es = runtime->private_data;
1211
1212 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1213 es->frag_size = snd_pcm_lib_period_bytes(substream);
1214
1215 es->wav_shift = 1; /* maestro handles always 16bit */
1216 es->fmt = 0;
1217 if (snd_pcm_format_width(runtime->format) == 16)
1218 es->fmt |= ESS_FMT_16BIT;
1219 if (runtime->channels > 1) {
1220 es->fmt |= ESS_FMT_STEREO;
1221 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1222 es->wav_shift++;
1223 }
1224 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1225
1226 switch (es->mode) {
1227 case ESM_MODE_PLAY:
1228 snd_es1968_playback_setup(chip, es, runtime);
1229 break;
1230 case ESM_MODE_CAPTURE:
1231 snd_es1968_capture_setup(chip, es, runtime);
1232 break;
1233 }
1234
1235 return 0;
1236}
1237
1238static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1239{
1240 struct es1968 *chip = snd_pcm_substream_chip(substream);
1241 struct esschan *es = substream->runtime->private_data;
1242
1243 spin_lock(&chip->substream_lock);
1244 switch (cmd) {
1245 case SNDRV_PCM_TRIGGER_START:
1246 case SNDRV_PCM_TRIGGER_RESUME:
1247 if (es->running)
1248 break;
1249 snd_es1968_bob_inc(chip, es->bob_freq);
1250 es->count = 0;
1251 es->hwptr = 0;
1252 snd_es1968_pcm_start(chip, es);
1253 es->running = 1;
1254 break;
1255 case SNDRV_PCM_TRIGGER_STOP:
1256 case SNDRV_PCM_TRIGGER_SUSPEND:
1257 if (! es->running)
1258 break;
1259 snd_es1968_pcm_stop(chip, es);
1260 es->running = 0;
1261 snd_es1968_bob_dec(chip);
1262 break;
1263 }
1264 spin_unlock(&chip->substream_lock);
1265 return 0;
1266}
1267
1268static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1269{
1270 struct es1968 *chip = snd_pcm_substream_chip(substream);
1271 struct esschan *es = substream->runtime->private_data;
1272 unsigned int ptr;
1273
1274 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1275
1276 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1277}
1278
1279static const struct snd_pcm_hardware snd_es1968_playback = {
1280 .info = (SNDRV_PCM_INFO_MMAP |
1281 SNDRV_PCM_INFO_MMAP_VALID |
1282 SNDRV_PCM_INFO_INTERLEAVED |
1283 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1284 /*SNDRV_PCM_INFO_PAUSE |*/
1285 SNDRV_PCM_INFO_RESUME),
1286 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1287 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1288 .rate_min = 4000,
1289 .rate_max = 48000,
1290 .channels_min = 1,
1291 .channels_max = 2,
1292 .buffer_bytes_max = 65536,
1293 .period_bytes_min = 256,
1294 .period_bytes_max = 65536,
1295 .periods_min = 1,
1296 .periods_max = 1024,
1297 .fifo_size = 0,
1298};
1299
1300static const struct snd_pcm_hardware snd_es1968_capture = {
1301 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1302 SNDRV_PCM_INFO_MMAP |
1303 SNDRV_PCM_INFO_MMAP_VALID |
1304 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1305 /*SNDRV_PCM_INFO_PAUSE |*/
1306 SNDRV_PCM_INFO_RESUME),
1307 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1308 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1309 .rate_min = 4000,
1310 .rate_max = 48000,
1311 .channels_min = 1,
1312 .channels_max = 2,
1313 .buffer_bytes_max = 65536,
1314 .period_bytes_min = 256,
1315 .period_bytes_max = 65536,
1316 .periods_min = 1,
1317 .periods_max = 1024,
1318 .fifo_size = 0,
1319};
1320
1321/* *************************
1322 * DMA memory management *
1323 *************************/
1324
1325/* Because the Maestro can only take addresses relative to the PCM base address
1326 register :( */
1327
1328static int calc_available_memory_size(struct es1968 *chip)
1329{
1330 int max_size = 0;
1331 struct esm_memory *buf;
1332
1333 mutex_lock(&chip->memory_mutex);
1334 list_for_each_entry(buf, &chip->buf_list, list) {
1335 if (buf->empty && buf->buf.bytes > max_size)
1336 max_size = buf->buf.bytes;
1337 }
1338 mutex_unlock(&chip->memory_mutex);
1339 if (max_size >= 128*1024)
1340 max_size = 127*1024;
1341 return max_size;
1342}
1343
1344/* allocate a new memory chunk with the specified size */
1345static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1346{
1347 struct esm_memory *buf;
1348
1349 size = ALIGN(size, ESM_MEM_ALIGN);
1350 mutex_lock(&chip->memory_mutex);
1351 list_for_each_entry(buf, &chip->buf_list, list) {
1352 if (buf->empty && buf->buf.bytes >= size)
1353 goto __found;
1354 }
1355 mutex_unlock(&chip->memory_mutex);
1356 return NULL;
1357
1358__found:
1359 if (buf->buf.bytes > size) {
1360 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1361 if (chunk == NULL) {
1362 mutex_unlock(&chip->memory_mutex);
1363 return NULL;
1364 }
1365 chunk->buf = buf->buf;
1366 chunk->buf.bytes -= size;
1367 chunk->buf.area += size;
1368 chunk->buf.addr += size;
1369 chunk->empty = 1;
1370 buf->buf.bytes = size;
1371 list_add(&chunk->list, &buf->list);
1372 }
1373 buf->empty = 0;
1374 mutex_unlock(&chip->memory_mutex);
1375 return buf;
1376}
1377
1378/* free a memory chunk */
1379static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1380{
1381 struct esm_memory *chunk;
1382
1383 mutex_lock(&chip->memory_mutex);
1384 buf->empty = 1;
1385 if (buf->list.prev != &chip->buf_list) {
1386 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1387 if (chunk->empty) {
1388 chunk->buf.bytes += buf->buf.bytes;
1389 list_del(&buf->list);
1390 kfree(buf);
1391 buf = chunk;
1392 }
1393 }
1394 if (buf->list.next != &chip->buf_list) {
1395 chunk = list_entry(buf->list.next, struct esm_memory, list);
1396 if (chunk->empty) {
1397 buf->buf.bytes += chunk->buf.bytes;
1398 list_del(&chunk->list);
1399 kfree(chunk);
1400 }
1401 }
1402 mutex_unlock(&chip->memory_mutex);
1403}
1404
1405static void snd_es1968_free_dmabuf(struct es1968 *chip)
1406{
1407 struct list_head *p;
1408
1409 if (! chip->dma.area)
1410 return;
1411 snd_dma_free_pages(&chip->dma);
1412 while ((p = chip->buf_list.next) != &chip->buf_list) {
1413 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1414 list_del(p);
1415 kfree(chunk);
1416 }
1417}
1418
1419static int
1420snd_es1968_init_dmabuf(struct es1968 *chip)
1421{
1422 int err;
1423 struct esm_memory *chunk;
1424
1425 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1426 &chip->pci->dev,
1427 chip->total_bufsize, &chip->dma);
1428 if (err < 0 || ! chip->dma.area) {
1429 dev_err(chip->card->dev,
1430 "can't allocate dma pages for size %d\n",
1431 chip->total_bufsize);
1432 return -ENOMEM;
1433 }
1434 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1435 snd_dma_free_pages(&chip->dma);
1436 dev_err(chip->card->dev, "DMA buffer beyond 256MB.\n");
1437 return -ENOMEM;
1438 }
1439
1440 INIT_LIST_HEAD(&chip->buf_list);
1441 /* allocate an empty chunk */
1442 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1443 if (chunk == NULL) {
1444 snd_es1968_free_dmabuf(chip);
1445 return -ENOMEM;
1446 }
1447 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1448 chunk->buf = chip->dma;
1449 chunk->buf.area += ESM_MEM_ALIGN;
1450 chunk->buf.addr += ESM_MEM_ALIGN;
1451 chunk->buf.bytes -= ESM_MEM_ALIGN;
1452 chunk->empty = 1;
1453 list_add(&chunk->list, &chip->buf_list);
1454
1455 return 0;
1456}
1457
1458/* setup the dma_areas */
1459/* buffer is extracted from the pre-allocated memory chunk */
1460static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1461 struct snd_pcm_hw_params *hw_params)
1462{
1463 struct es1968 *chip = snd_pcm_substream_chip(substream);
1464 struct snd_pcm_runtime *runtime = substream->runtime;
1465 struct esschan *chan = runtime->private_data;
1466 int size = params_buffer_bytes(hw_params);
1467
1468 if (chan->memory) {
1469 if (chan->memory->buf.bytes >= size) {
1470 runtime->dma_bytes = size;
1471 return 0;
1472 }
1473 snd_es1968_free_memory(chip, chan->memory);
1474 }
1475 chan->memory = snd_es1968_new_memory(chip, size);
1476 if (chan->memory == NULL) {
1477 dev_dbg(chip->card->dev,
1478 "cannot allocate dma buffer: size = %d\n", size);
1479 return -ENOMEM;
1480 }
1481 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1482 return 1; /* area was changed */
1483}
1484
1485/* remove dma areas if allocated */
1486static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1487{
1488 struct es1968 *chip = snd_pcm_substream_chip(substream);
1489 struct snd_pcm_runtime *runtime = substream->runtime;
1490 struct esschan *chan;
1491
1492 if (runtime->private_data == NULL)
1493 return 0;
1494 chan = runtime->private_data;
1495 if (chan->memory) {
1496 snd_es1968_free_memory(chip, chan->memory);
1497 chan->memory = NULL;
1498 }
1499 return 0;
1500}
1501
1502
1503/*
1504 * allocate APU pair
1505 */
1506static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1507{
1508 int apu;
1509
1510 for (apu = 0; apu < NR_APUS; apu += 2) {
1511 if (chip->apu[apu] == ESM_APU_FREE &&
1512 chip->apu[apu + 1] == ESM_APU_FREE) {
1513 chip->apu[apu] = chip->apu[apu + 1] = type;
1514 return apu;
1515 }
1516 }
1517 return -EBUSY;
1518}
1519
1520/*
1521 * release APU pair
1522 */
1523static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1524{
1525 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1526}
1527
1528
1529/******************
1530 * PCM open/close *
1531 ******************/
1532
1533static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1534{
1535 struct es1968 *chip = snd_pcm_substream_chip(substream);
1536 struct snd_pcm_runtime *runtime = substream->runtime;
1537 struct esschan *es;
1538 int apu1;
1539
1540 /* search 2 APUs */
1541 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1542 if (apu1 < 0)
1543 return apu1;
1544
1545 es = kzalloc(sizeof(*es), GFP_KERNEL);
1546 if (!es) {
1547 snd_es1968_free_apu_pair(chip, apu1);
1548 return -ENOMEM;
1549 }
1550
1551 es->apu[0] = apu1;
1552 es->apu[1] = apu1 + 1;
1553 es->apu_mode[0] = 0;
1554 es->apu_mode[1] = 0;
1555 es->running = 0;
1556 es->substream = substream;
1557 es->mode = ESM_MODE_PLAY;
1558
1559 runtime->private_data = es;
1560 runtime->hw = snd_es1968_playback;
1561 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1562 calc_available_memory_size(chip);
1563
1564 spin_lock_irq(&chip->substream_lock);
1565 list_add(&es->list, &chip->substream_list);
1566 spin_unlock_irq(&chip->substream_lock);
1567
1568 return 0;
1569}
1570
1571static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1572{
1573 struct snd_pcm_runtime *runtime = substream->runtime;
1574 struct es1968 *chip = snd_pcm_substream_chip(substream);
1575 struct esschan *es;
1576 int apu1, apu2;
1577
1578 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1579 if (apu1 < 0)
1580 return apu1;
1581 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1582 if (apu2 < 0) {
1583 snd_es1968_free_apu_pair(chip, apu1);
1584 return apu2;
1585 }
1586
1587 es = kzalloc(sizeof(*es), GFP_KERNEL);
1588 if (!es) {
1589 snd_es1968_free_apu_pair(chip, apu1);
1590 snd_es1968_free_apu_pair(chip, apu2);
1591 return -ENOMEM;
1592 }
1593
1594 es->apu[0] = apu1;
1595 es->apu[1] = apu1 + 1;
1596 es->apu[2] = apu2;
1597 es->apu[3] = apu2 + 1;
1598 es->apu_mode[0] = 0;
1599 es->apu_mode[1] = 0;
1600 es->apu_mode[2] = 0;
1601 es->apu_mode[3] = 0;
1602 es->running = 0;
1603 es->substream = substream;
1604 es->mode = ESM_MODE_CAPTURE;
1605
1606 /* get mixbuffer */
1607 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1608 snd_es1968_free_apu_pair(chip, apu1);
1609 snd_es1968_free_apu_pair(chip, apu2);
1610 kfree(es);
1611 return -ENOMEM;
1612 }
1613 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1614
1615 runtime->private_data = es;
1616 runtime->hw = snd_es1968_capture;
1617 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1618 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1619 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
1620
1621 spin_lock_irq(&chip->substream_lock);
1622 list_add(&es->list, &chip->substream_list);
1623 spin_unlock_irq(&chip->substream_lock);
1624
1625 return 0;
1626}
1627
1628static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1629{
1630 struct es1968 *chip = snd_pcm_substream_chip(substream);
1631 struct esschan *es;
1632
1633 if (substream->runtime->private_data == NULL)
1634 return 0;
1635 es = substream->runtime->private_data;
1636 spin_lock_irq(&chip->substream_lock);
1637 list_del(&es->list);
1638 spin_unlock_irq(&chip->substream_lock);
1639 snd_es1968_free_apu_pair(chip, es->apu[0]);
1640 kfree(es);
1641
1642 return 0;
1643}
1644
1645static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1646{
1647 struct es1968 *chip = snd_pcm_substream_chip(substream);
1648 struct esschan *es;
1649
1650 if (substream->runtime->private_data == NULL)
1651 return 0;
1652 es = substream->runtime->private_data;
1653 spin_lock_irq(&chip->substream_lock);
1654 list_del(&es->list);
1655 spin_unlock_irq(&chip->substream_lock);
1656 snd_es1968_free_memory(chip, es->mixbuf);
1657 snd_es1968_free_apu_pair(chip, es->apu[0]);
1658 snd_es1968_free_apu_pair(chip, es->apu[2]);
1659 kfree(es);
1660
1661 return 0;
1662}
1663
1664static const struct snd_pcm_ops snd_es1968_playback_ops = {
1665 .open = snd_es1968_playback_open,
1666 .close = snd_es1968_playback_close,
1667 .hw_params = snd_es1968_hw_params,
1668 .hw_free = snd_es1968_hw_free,
1669 .prepare = snd_es1968_pcm_prepare,
1670 .trigger = snd_es1968_pcm_trigger,
1671 .pointer = snd_es1968_pcm_pointer,
1672};
1673
1674static const struct snd_pcm_ops snd_es1968_capture_ops = {
1675 .open = snd_es1968_capture_open,
1676 .close = snd_es1968_capture_close,
1677 .hw_params = snd_es1968_hw_params,
1678 .hw_free = snd_es1968_hw_free,
1679 .prepare = snd_es1968_pcm_prepare,
1680 .trigger = snd_es1968_pcm_trigger,
1681 .pointer = snd_es1968_pcm_pointer,
1682};
1683
1684
1685/*
1686 * measure clock
1687 */
1688#define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1689
1690static void es1968_measure_clock(struct es1968 *chip)
1691{
1692 int i, apu;
1693 unsigned int pa, offset, t;
1694 struct esm_memory *memory;
1695 ktime_t start_time, stop_time;
1696 ktime_t diff;
1697
1698 if (chip->clock == 0)
1699 chip->clock = 48000; /* default clock value */
1700
1701 /* search 2 APUs (although one apu is enough) */
1702 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1703 dev_err(chip->card->dev, "Hmm, cannot find empty APU pair!?\n");
1704 return;
1705 }
1706 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1707 dev_warn(chip->card->dev,
1708 "cannot allocate dma buffer - using default clock %d\n",
1709 chip->clock);
1710 snd_es1968_free_apu_pair(chip, apu);
1711 return;
1712 }
1713
1714 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1715
1716 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1717
1718 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1719 pa |= 0x00400000; /* System RAM (Bit 22) */
1720
1721 /* initialize apu */
1722 for (i = 0; i < 16; i++)
1723 apu_set_register(chip, apu, i, 0x0000);
1724
1725 apu_set_register(chip, apu, 0, 0x400f);
1726 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1727 apu_set_register(chip, apu, 5, pa & 0xffff);
1728 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1729 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1730 apu_set_register(chip, apu, 8, 0x0000);
1731 apu_set_register(chip, apu, 9, 0xD000);
1732 apu_set_register(chip, apu, 10, 0x8F08);
1733 apu_set_register(chip, apu, 11, 0x0000);
1734 spin_lock_irq(&chip->reg_lock);
1735 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1736 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1737 spin_unlock_irq(&chip->reg_lock);
1738
1739 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1740
1741 chip->in_measurement = 1;
1742 chip->measure_apu = apu;
1743 spin_lock_irq(&chip->reg_lock);
1744 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1745 __apu_set_register(chip, apu, 5, pa & 0xffff);
1746 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1747 start_time = ktime_get();
1748 spin_unlock_irq(&chip->reg_lock);
1749 msleep(50);
1750 spin_lock_irq(&chip->reg_lock);
1751 offset = __apu_get_register(chip, apu, 5);
1752 stop_time = ktime_get();
1753 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1754 snd_es1968_bob_dec(chip);
1755 chip->in_measurement = 0;
1756 spin_unlock_irq(&chip->reg_lock);
1757
1758 /* check the current position */
1759 offset -= (pa & 0xffff);
1760 offset &= 0xfffe;
1761 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1762
1763 diff = ktime_sub(stop_time, start_time);
1764 t = ktime_to_us(diff);
1765 if (t == 0) {
1766 dev_err(chip->card->dev, "?? calculation error..\n");
1767 } else {
1768 offset *= 1000;
1769 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1770 if (offset < 47500 || offset > 48500) {
1771 if (offset >= 40000 && offset <= 50000)
1772 chip->clock = (chip->clock * offset) / 48000;
1773 }
1774 dev_info(chip->card->dev, "clocking to %d\n", chip->clock);
1775 }
1776 snd_es1968_free_memory(chip, memory);
1777 snd_es1968_free_apu_pair(chip, apu);
1778}
1779
1780
1781/*
1782 */
1783
1784static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1785{
1786 struct es1968 *esm = pcm->private_data;
1787 snd_es1968_free_dmabuf(esm);
1788 esm->pcm = NULL;
1789}
1790
1791static int
1792snd_es1968_pcm(struct es1968 *chip, int device)
1793{
1794 struct snd_pcm *pcm;
1795 int err;
1796
1797 /* get DMA buffer */
1798 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1799 return err;
1800
1801 /* set PCMBAR */
1802 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1803 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1804 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1805 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1806
1807 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1808 chip->playback_streams,
1809 chip->capture_streams, &pcm)) < 0)
1810 return err;
1811
1812 pcm->private_data = chip;
1813 pcm->private_free = snd_es1968_pcm_free;
1814
1815 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1816 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1817
1818 pcm->info_flags = 0;
1819
1820 strcpy(pcm->name, "ESS Maestro");
1821
1822 chip->pcm = pcm;
1823
1824 return 0;
1825}
1826/*
1827 * suppress jitter on some maestros when playing stereo
1828 */
1829static void snd_es1968_suppress_jitter(struct es1968 *chip, struct esschan *es)
1830{
1831 unsigned int cp1;
1832 unsigned int cp2;
1833 unsigned int diff;
1834
1835 cp1 = __apu_get_register(chip, 0, 5);
1836 cp2 = __apu_get_register(chip, 1, 5);
1837 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1838
1839 if (diff > 1)
1840 __maestro_write(chip, IDR0_DATA_PORT, cp1);
1841}
1842
1843/*
1844 * update pointer
1845 */
1846static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1847{
1848 unsigned int hwptr;
1849 unsigned int diff;
1850 struct snd_pcm_substream *subs = es->substream;
1851
1852 if (subs == NULL || !es->running)
1853 return;
1854
1855 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1856 hwptr %= es->dma_size;
1857
1858 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1859
1860 es->hwptr = hwptr;
1861 es->count += diff;
1862
1863 if (es->count > es->frag_size) {
1864 spin_unlock(&chip->substream_lock);
1865 snd_pcm_period_elapsed(subs);
1866 spin_lock(&chip->substream_lock);
1867 es->count %= es->frag_size;
1868 }
1869}
1870
1871/* The hardware volume works by incrementing / decrementing 2 counters
1872 (without wrap around) in response to volume button presses and then
1873 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1874 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1875static void es1968_update_hw_volume(struct work_struct *work)
1876{
1877 struct es1968 *chip = container_of(work, struct es1968, hwvol_work);
1878 int x, val;
1879
1880 /* Figure out which volume control button was pushed,
1881 based on differences from the default register
1882 values. */
1883 x = inb(chip->io_port + 0x1c) & 0xee;
1884 /* Reset the volume control registers. */
1885 outb(0x88, chip->io_port + 0x1c);
1886 outb(0x88, chip->io_port + 0x1d);
1887 outb(0x88, chip->io_port + 0x1e);
1888 outb(0x88, chip->io_port + 0x1f);
1889
1890 if (chip->in_suspend)
1891 return;
1892
1893#ifndef CONFIG_SND_ES1968_INPUT
1894 if (! chip->master_switch || ! chip->master_volume)
1895 return;
1896
1897 val = snd_ac97_read(chip->ac97, AC97_MASTER);
1898 switch (x) {
1899 case 0x88:
1900 /* mute */
1901 val ^= 0x8000;
1902 break;
1903 case 0xaa:
1904 /* volume up */
1905 if ((val & 0x7f) > 0)
1906 val--;
1907 if ((val & 0x7f00) > 0)
1908 val -= 0x0100;
1909 break;
1910 case 0x66:
1911 /* volume down */
1912 if ((val & 0x7f) < 0x1f)
1913 val++;
1914 if ((val & 0x7f00) < 0x1f00)
1915 val += 0x0100;
1916 break;
1917 }
1918 if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1919 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1920 &chip->master_volume->id);
1921#else
1922 if (!chip->input_dev)
1923 return;
1924
1925 val = 0;
1926 switch (x) {
1927 case 0x88:
1928 /* The counters have not changed, yet we've received a HV
1929 interrupt. According to tests run by various people this
1930 happens when pressing the mute button. */
1931 val = KEY_MUTE;
1932 break;
1933 case 0xaa:
1934 /* counters increased by 1 -> volume up */
1935 val = KEY_VOLUMEUP;
1936 break;
1937 case 0x66:
1938 /* counters decreased by 1 -> volume down */
1939 val = KEY_VOLUMEDOWN;
1940 break;
1941 }
1942
1943 if (val) {
1944 input_report_key(chip->input_dev, val, 1);
1945 input_sync(chip->input_dev);
1946 input_report_key(chip->input_dev, val, 0);
1947 input_sync(chip->input_dev);
1948 }
1949#endif
1950}
1951
1952/*
1953 * interrupt handler
1954 */
1955static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1956{
1957 struct es1968 *chip = dev_id;
1958 u32 event;
1959
1960 if (!(event = inb(chip->io_port + 0x1A)))
1961 return IRQ_NONE;
1962
1963 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1964
1965 if (event & ESM_HWVOL_IRQ)
1966 schedule_work(&chip->hwvol_work);
1967
1968 /* else ack 'em all, i imagine */
1969 outb(0xFF, chip->io_port + 0x1A);
1970
1971 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1972 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1973 }
1974
1975 if (event & ESM_SOUND_IRQ) {
1976 struct esschan *es;
1977 spin_lock(&chip->substream_lock);
1978 list_for_each_entry(es, &chip->substream_list, list) {
1979 if (es->running) {
1980 snd_es1968_update_pcm(chip, es);
1981 if (es->fmt & ESS_FMT_STEREO)
1982 snd_es1968_suppress_jitter(chip, es);
1983 }
1984 }
1985 spin_unlock(&chip->substream_lock);
1986 if (chip->in_measurement) {
1987 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
1988 if (curp < chip->measure_lastpos)
1989 chip->measure_count++;
1990 chip->measure_lastpos = curp;
1991 }
1992 }
1993
1994 return IRQ_HANDLED;
1995}
1996
1997/*
1998 * Mixer stuff
1999 */
2000
2001static int
2002snd_es1968_mixer(struct es1968 *chip)
2003{
2004 struct snd_ac97_bus *pbus;
2005 struct snd_ac97_template ac97;
2006#ifndef CONFIG_SND_ES1968_INPUT
2007 struct snd_ctl_elem_id elem_id;
2008#endif
2009 int err;
2010 static const struct snd_ac97_bus_ops ops = {
2011 .write = snd_es1968_ac97_write,
2012 .read = snd_es1968_ac97_read,
2013 };
2014
2015 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2016 return err;
2017 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
2018
2019 memset(&ac97, 0, sizeof(ac97));
2020 ac97.private_data = chip;
2021 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2022 return err;
2023
2024#ifndef CONFIG_SND_ES1968_INPUT
2025 /* attach master switch / volumes for h/w volume control */
2026 memset(&elem_id, 0, sizeof(elem_id));
2027 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2028 strcpy(elem_id.name, "Master Playback Switch");
2029 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2030 memset(&elem_id, 0, sizeof(elem_id));
2031 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2032 strcpy(elem_id.name, "Master Playback Volume");
2033 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2034#endif
2035
2036 return 0;
2037}
2038
2039/*
2040 * reset ac97 codec
2041 */
2042
2043static void snd_es1968_ac97_reset(struct es1968 *chip)
2044{
2045 unsigned long ioaddr = chip->io_port;
2046
2047 unsigned short save_ringbus_a;
2048 unsigned short save_68;
2049 unsigned short w;
2050 unsigned int vend;
2051
2052 /* save configuration */
2053 save_ringbus_a = inw(ioaddr + 0x36);
2054
2055 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2056 /* set command/status address i/o to 1st codec */
2057 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2058 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2059
2060 /* disable ac link */
2061 outw(0x0000, ioaddr + 0x36);
2062 save_68 = inw(ioaddr + 0x68);
2063 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2064 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2065 if (w & 1)
2066 save_68 |= 0x10;
2067 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2068 outw(0x0001, ioaddr + 0x68); /* gpio write */
2069 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2070 udelay(20);
2071 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2072 msleep(20);
2073
2074 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2075 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2076 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2077 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2078
2079 /* now the second codec */
2080 /* disable ac link */
2081 outw(0x0000, ioaddr + 0x36);
2082 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2083 save_68 = inw(ioaddr + 0x68);
2084 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2085 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2086 udelay(20);
2087 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2088 msleep(500);
2089 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2090 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2091 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2092
2093#if 0 /* the loop here needs to be much better if we want it.. */
2094 dev_info(chip->card->dev, "trying software reset\n");
2095 /* try and do a software reset */
2096 outb(0x80 | 0x7c, ioaddr + 0x30);
2097 for (w = 0;; w++) {
2098 if ((inw(ioaddr + 0x30) & 1) == 0) {
2099 if (inb(ioaddr + 0x32) != 0)
2100 break;
2101
2102 outb(0x80 | 0x7d, ioaddr + 0x30);
2103 if (((inw(ioaddr + 0x30) & 1) == 0)
2104 && (inb(ioaddr + 0x32) != 0))
2105 break;
2106 outb(0x80 | 0x7f, ioaddr + 0x30);
2107 if (((inw(ioaddr + 0x30) & 1) == 0)
2108 && (inb(ioaddr + 0x32) != 0))
2109 break;
2110 }
2111
2112 if (w > 10000) {
2113 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2114 msleep(500); /* oh my.. */
2115 outb(inb(ioaddr + 0x37) & ~0x08,
2116 ioaddr + 0x37);
2117 udelay(1);
2118 outw(0x80, ioaddr + 0x30);
2119 for (w = 0; w < 10000; w++) {
2120 if ((inw(ioaddr + 0x30) & 1) == 0)
2121 break;
2122 }
2123 }
2124 }
2125#endif
2126 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2127 /* turn on external amp? */
2128 outw(0xf9ff, ioaddr + 0x64);
2129 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2130 outw(0x0209, ioaddr + 0x60);
2131 }
2132
2133 /* restore.. */
2134 outw(save_ringbus_a, ioaddr + 0x36);
2135
2136 /* Turn on the 978 docking chip.
2137 First frob the "master output enable" bit,
2138 then set most of the playback volume control registers to max. */
2139 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2140 outb(0xff, ioaddr+0xc3);
2141 outb(0xff, ioaddr+0xc4);
2142 outb(0xff, ioaddr+0xc6);
2143 outb(0xff, ioaddr+0xc8);
2144 outb(0x3f, ioaddr+0xcf);
2145 outb(0x3f, ioaddr+0xd0);
2146}
2147
2148static void snd_es1968_reset(struct es1968 *chip)
2149{
2150 /* Reset */
2151 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2152 chip->io_port + ESM_PORT_HOST_IRQ);
2153 udelay(10);
2154 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2155 udelay(10);
2156}
2157
2158/*
2159 * initialize maestro chip
2160 */
2161static void snd_es1968_chip_init(struct es1968 *chip)
2162{
2163 struct pci_dev *pci = chip->pci;
2164 int i;
2165 unsigned long iobase = chip->io_port;
2166 u16 w;
2167 u32 n;
2168
2169 /* We used to muck around with pci config space that
2170 * we had no business messing with. We don't know enough
2171 * about the machine to know which DMA mode is appropriate,
2172 * etc. We were guessing wrong on some machines and making
2173 * them unhappy. We now trust in the BIOS to do things right,
2174 * which almost certainly means a new host of problems will
2175 * arise with broken BIOS implementations. screw 'em.
2176 * We're already intolerant of machines that don't assign
2177 * IRQs.
2178 */
2179
2180 /* Config Reg A */
2181 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2182
2183 w &= ~DMA_CLEAR; /* Clear DMA bits */
2184 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2185 w &= ~SAFEGUARD; /* Safeguard off */
2186 w |= POST_WRITE; /* Posted write */
2187 w |= PCI_TIMING; /* PCI timing on */
2188 /* XXX huh? claims to be reserved.. */
2189 w &= ~SWAP_LR; /* swap left/right
2190 seems to only have effect on SB
2191 Emulation */
2192 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2193
2194 pci_write_config_word(pci, ESM_CONFIG_A, w);
2195
2196 /* Config Reg B */
2197
2198 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2199
2200 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2201 /* XXX how do we know which to use? */
2202 w &= ~(1 << 14); /* External clock */
2203
2204 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2205 w |= HWV_CONFB; /* HWV on */
2206 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2207 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2208 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2209 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2210 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2211 w &= ~(1 << 1); /* reserved, always write 0 */
2212 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2213
2214 pci_write_config_word(pci, ESM_CONFIG_B, w);
2215
2216 /* DDMA off */
2217
2218 pci_read_config_word(pci, ESM_DDMA, &w);
2219 w &= ~(1 << 0);
2220 pci_write_config_word(pci, ESM_DDMA, w);
2221
2222 /*
2223 * Legacy mode
2224 */
2225
2226 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2227
2228 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
2229 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2230 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2231
2232 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2233
2234 /* Set up 978 docking control chip. */
2235 pci_read_config_word(pci, 0x58, &w);
2236 w|=1<<2; /* Enable 978. */
2237 w|=1<<3; /* Turn on 978 hardware volume control. */
2238 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2239 pci_write_config_word(pci, 0x58, w);
2240
2241 /* Sound Reset */
2242
2243 snd_es1968_reset(chip);
2244
2245 /*
2246 * Ring Bus Setup
2247 */
2248
2249 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2250 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2251 udelay(20);
2252 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2253 udelay(20);
2254
2255 /*
2256 * Reset the CODEC
2257 */
2258
2259 snd_es1968_ac97_reset(chip);
2260
2261 /* Ring Bus Control B */
2262
2263 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2264 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2265 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2266 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2267
2268 /* Set hardware volume control registers to midpoints.
2269 We can tell which button was pushed based on how they change. */
2270 outb(0x88, iobase+0x1c);
2271 outb(0x88, iobase+0x1d);
2272 outb(0x88, iobase+0x1e);
2273 outb(0x88, iobase+0x1f);
2274
2275 /* it appears some maestros (dell 7500) only work if these are set,
2276 regardless of whether we use the assp or not. */
2277
2278 outb(0, iobase + ASSP_CONTROL_B);
2279 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2280 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2281
2282 /*
2283 * set up wavecache
2284 */
2285 for (i = 0; i < 16; i++) {
2286 /* Write 0 into the buffer area 0x1E0->1EF */
2287 outw(0x01E0 + i, iobase + WC_INDEX);
2288 outw(0x0000, iobase + WC_DATA);
2289
2290 /* The 1.10 test program seem to write 0 into the buffer area
2291 * 0x1D0-0x1DF too.*/
2292 outw(0x01D0 + i, iobase + WC_INDEX);
2293 outw(0x0000, iobase + WC_DATA);
2294 }
2295 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2296 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2297 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2298 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2299 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2300 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2301 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2302 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2303
2304
2305 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2306 /* Now back to the DirectSound stuff */
2307 /* audio serial configuration.. ? */
2308 maestro_write(chip, 0x08, 0xB004);
2309 maestro_write(chip, 0x09, 0x001B);
2310 maestro_write(chip, 0x0A, 0x8000);
2311 maestro_write(chip, 0x0B, 0x3F37);
2312 maestro_write(chip, 0x0C, 0x0098);
2313
2314 /* parallel in, has something to do with recording :) */
2315 maestro_write(chip, 0x0C,
2316 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2317 /* parallel out */
2318 maestro_write(chip, 0x0C,
2319 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2320
2321 maestro_write(chip, 0x0D, 0x7632);
2322
2323 /* Wave cache control on - test off, sg off,
2324 enable, enable extra chans 1Mb */
2325
2326 w = inw(iobase + WC_CONTROL);
2327
2328 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2329 w |= 0xA000; /* reserved... I don't know */
2330 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2331 Seems to crash the Computer if enabled... */
2332 w |= 0x0100; /* Wave Cache Operation Enabled */
2333 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2334 w &= ~0x0060; /* Clear Wavtable Size */
2335 w |= 0x0020; /* Wavetable Size : 1MB */
2336 /* Bit 4 is reserved */
2337 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2338 /* Bit 1 is reserved */
2339 w &= ~0x0001; /* Test Mode off */
2340
2341 outw(w, iobase + WC_CONTROL);
2342
2343 /* Now clear the APU control ram */
2344 for (i = 0; i < NR_APUS; i++) {
2345 for (w = 0; w < NR_APU_REGS; w++)
2346 apu_set_register(chip, i, w, 0);
2347
2348 }
2349}
2350
2351/* Enable IRQ's */
2352static void snd_es1968_start_irq(struct es1968 *chip)
2353{
2354 unsigned short w;
2355 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2356 if (chip->rmidi)
2357 w |= ESM_HIRQ_MPU401;
2358 outb(w, chip->io_port + 0x1A);
2359 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2360}
2361
2362#ifdef CONFIG_PM_SLEEP
2363/*
2364 * PM support
2365 */
2366static int es1968_suspend(struct device *dev)
2367{
2368 struct snd_card *card = dev_get_drvdata(dev);
2369 struct es1968 *chip = card->private_data;
2370
2371 if (! chip->do_pm)
2372 return 0;
2373
2374 chip->in_suspend = 1;
2375 cancel_work_sync(&chip->hwvol_work);
2376 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2377 snd_ac97_suspend(chip->ac97);
2378 snd_es1968_bob_stop(chip);
2379 return 0;
2380}
2381
2382static int es1968_resume(struct device *dev)
2383{
2384 struct snd_card *card = dev_get_drvdata(dev);
2385 struct es1968 *chip = card->private_data;
2386 struct esschan *es;
2387
2388 if (! chip->do_pm)
2389 return 0;
2390
2391 snd_es1968_chip_init(chip);
2392
2393 /* need to restore the base pointers.. */
2394 if (chip->dma.addr) {
2395 /* set PCMBAR */
2396 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2397 }
2398
2399 snd_es1968_start_irq(chip);
2400
2401 /* restore ac97 state */
2402 snd_ac97_resume(chip->ac97);
2403
2404 list_for_each_entry(es, &chip->substream_list, list) {
2405 switch (es->mode) {
2406 case ESM_MODE_PLAY:
2407 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2408 break;
2409 case ESM_MODE_CAPTURE:
2410 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2411 break;
2412 }
2413 }
2414
2415 /* start timer again */
2416 if (chip->bobclient)
2417 snd_es1968_bob_start(chip);
2418
2419 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2420 chip->in_suspend = 0;
2421 return 0;
2422}
2423
2424static SIMPLE_DEV_PM_OPS(es1968_pm, es1968_suspend, es1968_resume);
2425#define ES1968_PM_OPS &es1968_pm
2426#else
2427#define ES1968_PM_OPS NULL
2428#endif /* CONFIG_PM_SLEEP */
2429
2430#ifdef SUPPORT_JOYSTICK
2431#define JOYSTICK_ADDR 0x200
2432static int snd_es1968_create_gameport(struct es1968 *chip, int dev)
2433{
2434 struct gameport *gp;
2435 struct resource *r;
2436 u16 val;
2437
2438 if (!joystick[dev])
2439 return -ENODEV;
2440
2441 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2442 if (!r)
2443 return -EBUSY;
2444
2445 chip->gameport = gp = gameport_allocate_port();
2446 if (!gp) {
2447 dev_err(chip->card->dev,
2448 "cannot allocate memory for gameport\n");
2449 release_and_free_resource(r);
2450 return -ENOMEM;
2451 }
2452
2453 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2454 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2455
2456 gameport_set_name(gp, "ES1968 Gameport");
2457 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2458 gameport_set_dev_parent(gp, &chip->pci->dev);
2459 gp->io = JOYSTICK_ADDR;
2460 gameport_set_port_data(gp, r);
2461
2462 gameport_register_port(gp);
2463
2464 return 0;
2465}
2466
2467static void snd_es1968_free_gameport(struct es1968 *chip)
2468{
2469 if (chip->gameport) {
2470 struct resource *r = gameport_get_port_data(chip->gameport);
2471
2472 gameport_unregister_port(chip->gameport);
2473 chip->gameport = NULL;
2474
2475 release_and_free_resource(r);
2476 }
2477}
2478#else
2479static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2480static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2481#endif
2482
2483#ifdef CONFIG_SND_ES1968_INPUT
2484static int snd_es1968_input_register(struct es1968 *chip)
2485{
2486 struct input_dev *input_dev;
2487 int err;
2488
2489 input_dev = input_allocate_device();
2490 if (!input_dev)
2491 return -ENOMEM;
2492
2493 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2494 pci_name(chip->pci));
2495
2496 input_dev->name = chip->card->driver;
2497 input_dev->phys = chip->phys;
2498 input_dev->id.bustype = BUS_PCI;
2499 input_dev->id.vendor = chip->pci->vendor;
2500 input_dev->id.product = chip->pci->device;
2501 input_dev->dev.parent = &chip->pci->dev;
2502
2503 __set_bit(EV_KEY, input_dev->evbit);
2504 __set_bit(KEY_MUTE, input_dev->keybit);
2505 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2506 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2507
2508 err = input_register_device(input_dev);
2509 if (err) {
2510 input_free_device(input_dev);
2511 return err;
2512 }
2513
2514 chip->input_dev = input_dev;
2515 return 0;
2516}
2517#endif /* CONFIG_SND_ES1968_INPUT */
2518
2519#ifdef CONFIG_SND_ES1968_RADIO
2520#define GPIO_DATA 0x60
2521#define IO_MASK 4 /* mask register offset from GPIO_DATA
2522 bits 1=unmask write to given bit */
2523#define IO_DIR 8 /* direction register offset from GPIO_DATA
2524 bits 0/1=read/write direction */
2525
2526/* GPIO to TEA575x maps */
2527struct snd_es1968_tea575x_gpio {
2528 u8 data, clk, wren, most;
2529 char *name;
2530};
2531
2532static const struct snd_es1968_tea575x_gpio snd_es1968_tea575x_gpios[] = {
2533 { .data = 6, .clk = 7, .wren = 8, .most = 9, .name = "SF64-PCE2" },
2534 { .data = 7, .clk = 8, .wren = 6, .most = 10, .name = "M56VAP" },
2535};
2536
2537#define get_tea575x_gpio(chip) \
2538 (&snd_es1968_tea575x_gpios[(chip)->tea575x_tuner])
2539
2540
2541static void snd_es1968_tea575x_set_pins(struct snd_tea575x *tea, u8 pins)
2542{
2543 struct es1968 *chip = tea->private_data;
2544 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2545 u16 val = 0;
2546
2547 val |= (pins & TEA575X_DATA) ? (1 << gpio.data) : 0;
2548 val |= (pins & TEA575X_CLK) ? (1 << gpio.clk) : 0;
2549 val |= (pins & TEA575X_WREN) ? (1 << gpio.wren) : 0;
2550
2551 outw(val, chip->io_port + GPIO_DATA);
2552}
2553
2554static u8 snd_es1968_tea575x_get_pins(struct snd_tea575x *tea)
2555{
2556 struct es1968 *chip = tea->private_data;
2557 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2558 u16 val = inw(chip->io_port + GPIO_DATA);
2559 u8 ret = 0;
2560
2561 if (val & (1 << gpio.data))
2562 ret |= TEA575X_DATA;
2563 if (val & (1 << gpio.most))
2564 ret |= TEA575X_MOST;
2565
2566 return ret;
2567}
2568
2569static void snd_es1968_tea575x_set_direction(struct snd_tea575x *tea, bool output)
2570{
2571 struct es1968 *chip = tea->private_data;
2572 unsigned long io = chip->io_port + GPIO_DATA;
2573 u16 odir = inw(io + IO_DIR);
2574 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2575
2576 if (output) {
2577 outw(~((1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren)),
2578 io + IO_MASK);
2579 outw(odir | (1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren),
2580 io + IO_DIR);
2581 } else {
2582 outw(~((1 << gpio.clk) | (1 << gpio.wren) | (1 << gpio.data) | (1 << gpio.most)),
2583 io + IO_MASK);
2584 outw((odir & ~((1 << gpio.data) | (1 << gpio.most)))
2585 | (1 << gpio.clk) | (1 << gpio.wren), io + IO_DIR);
2586 }
2587}
2588
2589static const struct snd_tea575x_ops snd_es1968_tea_ops = {
2590 .set_pins = snd_es1968_tea575x_set_pins,
2591 .get_pins = snd_es1968_tea575x_get_pins,
2592 .set_direction = snd_es1968_tea575x_set_direction,
2593};
2594#endif
2595
2596static int snd_es1968_free(struct es1968 *chip)
2597{
2598 cancel_work_sync(&chip->hwvol_work);
2599#ifdef CONFIG_SND_ES1968_INPUT
2600 if (chip->input_dev)
2601 input_unregister_device(chip->input_dev);
2602#endif
2603
2604 if (chip->io_port) {
2605 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2606 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2607 }
2608
2609#ifdef CONFIG_SND_ES1968_RADIO
2610 snd_tea575x_exit(&chip->tea);
2611 v4l2_device_unregister(&chip->v4l2_dev);
2612#endif
2613
2614 if (chip->irq >= 0)
2615 free_irq(chip->irq, chip);
2616 snd_es1968_free_gameport(chip);
2617 pci_release_regions(chip->pci);
2618 pci_disable_device(chip->pci);
2619 kfree(chip);
2620 return 0;
2621}
2622
2623static int snd_es1968_dev_free(struct snd_device *device)
2624{
2625 struct es1968 *chip = device->device_data;
2626 return snd_es1968_free(chip);
2627}
2628
2629struct ess_device_list {
2630 unsigned short type; /* chip type */
2631 unsigned short vendor; /* subsystem vendor id */
2632};
2633
2634static const struct ess_device_list pm_allowlist[] = {
2635 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2636 { TYPE_MAESTRO2E, 0x1028 },
2637 { TYPE_MAESTRO2E, 0x103c },
2638 { TYPE_MAESTRO2E, 0x1179 },
2639 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2640 { TYPE_MAESTRO2E, 0x1558 },
2641 { TYPE_MAESTRO2E, 0x125d }, /* a PCI card, e.g. Terratec DMX */
2642 { TYPE_MAESTRO2, 0x125d }, /* a PCI card, e.g. SF64-PCE2 */
2643};
2644
2645static const struct ess_device_list mpu_denylist[] = {
2646 { TYPE_MAESTRO2, 0x125d },
2647};
2648
2649static int snd_es1968_create(struct snd_card *card,
2650 struct pci_dev *pci,
2651 int total_bufsize,
2652 int play_streams,
2653 int capt_streams,
2654 int chip_type,
2655 int do_pm,
2656 int radio_nr,
2657 struct es1968 **chip_ret)
2658{
2659 static const struct snd_device_ops ops = {
2660 .dev_free = snd_es1968_dev_free,
2661 };
2662 struct es1968 *chip;
2663 int i, err;
2664
2665 *chip_ret = NULL;
2666
2667 /* enable PCI device */
2668 if ((err = pci_enable_device(pci)) < 0)
2669 return err;
2670 /* check, if we can restrict PCI DMA transfers to 28 bits */
2671 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
2672 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
2673 dev_err(card->dev,
2674 "architecture does not support 28bit PCI busmaster DMA\n");
2675 pci_disable_device(pci);
2676 return -ENXIO;
2677 }
2678
2679 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2680 if (! chip) {
2681 pci_disable_device(pci);
2682 return -ENOMEM;
2683 }
2684
2685 /* Set Vars */
2686 chip->type = chip_type;
2687 spin_lock_init(&chip->reg_lock);
2688 spin_lock_init(&chip->substream_lock);
2689 INIT_LIST_HEAD(&chip->buf_list);
2690 INIT_LIST_HEAD(&chip->substream_list);
2691 mutex_init(&chip->memory_mutex);
2692 INIT_WORK(&chip->hwvol_work, es1968_update_hw_volume);
2693 chip->card = card;
2694 chip->pci = pci;
2695 chip->irq = -1;
2696 chip->total_bufsize = total_bufsize; /* in bytes */
2697 chip->playback_streams = play_streams;
2698 chip->capture_streams = capt_streams;
2699
2700 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2701 kfree(chip);
2702 pci_disable_device(pci);
2703 return err;
2704 }
2705 chip->io_port = pci_resource_start(pci, 0);
2706 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2707 KBUILD_MODNAME, chip)) {
2708 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2709 snd_es1968_free(chip);
2710 return -EBUSY;
2711 }
2712 chip->irq = pci->irq;
2713 card->sync_irq = chip->irq;
2714
2715 /* Clear Maestro_map */
2716 for (i = 0; i < 32; i++)
2717 chip->maestro_map[i] = 0;
2718
2719 /* Clear Apu Map */
2720 for (i = 0; i < NR_APUS; i++)
2721 chip->apu[i] = ESM_APU_FREE;
2722
2723 /* just to be sure */
2724 pci_set_master(pci);
2725
2726 if (do_pm > 1) {
2727 /* disable power-management if not on the allowlist */
2728 unsigned short vend;
2729 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2730 for (i = 0; i < (int)ARRAY_SIZE(pm_allowlist); i++) {
2731 if (chip->type == pm_allowlist[i].type &&
2732 vend == pm_allowlist[i].vendor) {
2733 do_pm = 1;
2734 break;
2735 }
2736 }
2737 if (do_pm > 1) {
2738 /* not matched; disabling pm */
2739 dev_info(card->dev, "not attempting power management.\n");
2740 do_pm = 0;
2741 }
2742 }
2743 chip->do_pm = do_pm;
2744
2745 snd_es1968_chip_init(chip);
2746
2747 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2748 snd_es1968_free(chip);
2749 return err;
2750 }
2751
2752#ifdef CONFIG_SND_ES1968_RADIO
2753 /* don't play with GPIOs on laptops */
2754 if (chip->pci->subsystem_vendor != 0x125d)
2755 goto no_radio;
2756 err = v4l2_device_register(&pci->dev, &chip->v4l2_dev);
2757 if (err < 0) {
2758 snd_es1968_free(chip);
2759 return err;
2760 }
2761 chip->tea.v4l2_dev = &chip->v4l2_dev;
2762 chip->tea.private_data = chip;
2763 chip->tea.radio_nr = radio_nr;
2764 chip->tea.ops = &snd_es1968_tea_ops;
2765 sprintf(chip->tea.bus_info, "PCI:%s", pci_name(pci));
2766 for (i = 0; i < ARRAY_SIZE(snd_es1968_tea575x_gpios); i++) {
2767 chip->tea575x_tuner = i;
2768 if (!snd_tea575x_init(&chip->tea, THIS_MODULE)) {
2769 dev_info(card->dev, "detected TEA575x radio type %s\n",
2770 get_tea575x_gpio(chip)->name);
2771 strlcpy(chip->tea.card, get_tea575x_gpio(chip)->name,
2772 sizeof(chip->tea.card));
2773 break;
2774 }
2775 }
2776no_radio:
2777#endif
2778
2779 *chip_ret = chip;
2780
2781 return 0;
2782}
2783
2784
2785/*
2786 */
2787static int snd_es1968_probe(struct pci_dev *pci,
2788 const struct pci_device_id *pci_id)
2789{
2790 static int dev;
2791 struct snd_card *card;
2792 struct es1968 *chip;
2793 unsigned int i;
2794 int err;
2795
2796 if (dev >= SNDRV_CARDS)
2797 return -ENODEV;
2798 if (!enable[dev]) {
2799 dev++;
2800 return -ENOENT;
2801 }
2802
2803 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2804 0, &card);
2805 if (err < 0)
2806 return err;
2807
2808 if (total_bufsize[dev] < 128)
2809 total_bufsize[dev] = 128;
2810 if (total_bufsize[dev] > 4096)
2811 total_bufsize[dev] = 4096;
2812 if ((err = snd_es1968_create(card, pci,
2813 total_bufsize[dev] * 1024, /* in bytes */
2814 pcm_substreams_p[dev],
2815 pcm_substreams_c[dev],
2816 pci_id->driver_data,
2817 use_pm[dev],
2818 radio_nr[dev],
2819 &chip)) < 0) {
2820 snd_card_free(card);
2821 return err;
2822 }
2823 card->private_data = chip;
2824
2825 switch (chip->type) {
2826 case TYPE_MAESTRO2E:
2827 strcpy(card->driver, "ES1978");
2828 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2829 break;
2830 case TYPE_MAESTRO2:
2831 strcpy(card->driver, "ES1968");
2832 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2833 break;
2834 case TYPE_MAESTRO:
2835 strcpy(card->driver, "ESM1");
2836 strcpy(card->shortname, "ESS Maestro 1");
2837 break;
2838 }
2839
2840 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2841 snd_card_free(card);
2842 return err;
2843 }
2844
2845 if ((err = snd_es1968_mixer(chip)) < 0) {
2846 snd_card_free(card);
2847 return err;
2848 }
2849
2850 if (enable_mpu[dev] == 2) {
2851 /* check the deny list */
2852 unsigned short vend;
2853 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2854 for (i = 0; i < ARRAY_SIZE(mpu_denylist); i++) {
2855 if (chip->type == mpu_denylist[i].type &&
2856 vend == mpu_denylist[i].vendor) {
2857 enable_mpu[dev] = 0;
2858 break;
2859 }
2860 }
2861 }
2862 if (enable_mpu[dev]) {
2863 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2864 chip->io_port + ESM_MPU401_PORT,
2865 MPU401_INFO_INTEGRATED |
2866 MPU401_INFO_IRQ_HOOK,
2867 -1, &chip->rmidi)) < 0) {
2868 dev_warn(card->dev, "skipping MPU-401 MIDI support..\n");
2869 }
2870 }
2871
2872 snd_es1968_create_gameport(chip, dev);
2873
2874#ifdef CONFIG_SND_ES1968_INPUT
2875 err = snd_es1968_input_register(chip);
2876 if (err)
2877 dev_warn(card->dev,
2878 "Input device registration failed with error %i", err);
2879#endif
2880
2881 snd_es1968_start_irq(chip);
2882
2883 chip->clock = clock[dev];
2884 if (! chip->clock)
2885 es1968_measure_clock(chip);
2886
2887 sprintf(card->longname, "%s at 0x%lx, irq %i",
2888 card->shortname, chip->io_port, chip->irq);
2889
2890 if ((err = snd_card_register(card)) < 0) {
2891 snd_card_free(card);
2892 return err;
2893 }
2894 pci_set_drvdata(pci, card);
2895 dev++;
2896 return 0;
2897}
2898
2899static void snd_es1968_remove(struct pci_dev *pci)
2900{
2901 snd_card_free(pci_get_drvdata(pci));
2902}
2903
2904static struct pci_driver es1968_driver = {
2905 .name = KBUILD_MODNAME,
2906 .id_table = snd_es1968_ids,
2907 .probe = snd_es1968_probe,
2908 .remove = snd_es1968_remove,
2909 .driver = {
2910 .pm = ES1968_PM_OPS,
2911 },
2912};
2913
2914module_pci_driver(es1968_driver);