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1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/console.h>
26#include <linux/vga_switcheroo.h>
27
28#include <drm/drm_drv.h>
29#include <drm/i915_pciids.h>
30
31#include "display/intel_fbdev.h"
32
33#include "i915_drv.h"
34#include "i915_perf.h"
35#include "i915_globals.h"
36#include "i915_selftest.h"
37
38#define PLATFORM(x) .platform = (x)
39#define GEN(x) \
40 .graphics_ver = (x), \
41 .media_ver = (x), \
42 .display.ver = (x)
43
44#define I845_PIPE_OFFSETS \
45 .pipe_offsets = { \
46 [TRANSCODER_A] = PIPE_A_OFFSET, \
47 }, \
48 .trans_offsets = { \
49 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
50 }
51
52#define I9XX_PIPE_OFFSETS \
53 .pipe_offsets = { \
54 [TRANSCODER_A] = PIPE_A_OFFSET, \
55 [TRANSCODER_B] = PIPE_B_OFFSET, \
56 }, \
57 .trans_offsets = { \
58 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
59 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
60 }
61
62#define IVB_PIPE_OFFSETS \
63 .pipe_offsets = { \
64 [TRANSCODER_A] = PIPE_A_OFFSET, \
65 [TRANSCODER_B] = PIPE_B_OFFSET, \
66 [TRANSCODER_C] = PIPE_C_OFFSET, \
67 }, \
68 .trans_offsets = { \
69 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
70 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
71 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
72 }
73
74#define HSW_PIPE_OFFSETS \
75 .pipe_offsets = { \
76 [TRANSCODER_A] = PIPE_A_OFFSET, \
77 [TRANSCODER_B] = PIPE_B_OFFSET, \
78 [TRANSCODER_C] = PIPE_C_OFFSET, \
79 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
80 }, \
81 .trans_offsets = { \
82 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
83 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
84 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
85 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
86 }
87
88#define CHV_PIPE_OFFSETS \
89 .pipe_offsets = { \
90 [TRANSCODER_A] = PIPE_A_OFFSET, \
91 [TRANSCODER_B] = PIPE_B_OFFSET, \
92 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
93 }, \
94 .trans_offsets = { \
95 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
96 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
97 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
98 }
99
100#define I845_CURSOR_OFFSETS \
101 .cursor_offsets = { \
102 [PIPE_A] = CURSOR_A_OFFSET, \
103 }
104
105#define I9XX_CURSOR_OFFSETS \
106 .cursor_offsets = { \
107 [PIPE_A] = CURSOR_A_OFFSET, \
108 [PIPE_B] = CURSOR_B_OFFSET, \
109 }
110
111#define CHV_CURSOR_OFFSETS \
112 .cursor_offsets = { \
113 [PIPE_A] = CURSOR_A_OFFSET, \
114 [PIPE_B] = CURSOR_B_OFFSET, \
115 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
116 }
117
118#define IVB_CURSOR_OFFSETS \
119 .cursor_offsets = { \
120 [PIPE_A] = CURSOR_A_OFFSET, \
121 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
122 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
123 }
124
125#define TGL_CURSOR_OFFSETS \
126 .cursor_offsets = { \
127 [PIPE_A] = CURSOR_A_OFFSET, \
128 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
129 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
130 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
131 }
132
133#define I9XX_COLORS \
134 .color = { .gamma_lut_size = 256 }
135#define I965_COLORS \
136 .color = { .gamma_lut_size = 129, \
137 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
138 }
139#define ILK_COLORS \
140 .color = { .gamma_lut_size = 1024 }
141#define IVB_COLORS \
142 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
143#define CHV_COLORS \
144 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
145 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
146 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
147 }
148#define GLK_COLORS \
149 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
150 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
151 DRM_COLOR_LUT_EQUAL_CHANNELS, \
152 }
153
154/* Keep in gen based order, and chronological order within a gen */
155
156#define GEN_DEFAULT_PAGE_SIZES \
157 .page_sizes = I915_GTT_PAGE_SIZE_4K
158
159#define GEN_DEFAULT_REGIONS \
160 .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
161
162#define I830_FEATURES \
163 GEN(2), \
164 .is_mobile = 1, \
165 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
166 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
167 .display.has_overlay = 1, \
168 .display.cursor_needs_physical = 1, \
169 .display.overlay_needs_physical = 1, \
170 .display.has_gmch = 1, \
171 .gpu_reset_clobbers_display = true, \
172 .hws_needs_physical = 1, \
173 .unfenced_needs_alignment = 1, \
174 .platform_engine_mask = BIT(RCS0), \
175 .has_snoop = true, \
176 .has_coherent_ggtt = false, \
177 .dma_mask_size = 32, \
178 I9XX_PIPE_OFFSETS, \
179 I9XX_CURSOR_OFFSETS, \
180 I9XX_COLORS, \
181 GEN_DEFAULT_PAGE_SIZES, \
182 GEN_DEFAULT_REGIONS
183
184#define I845_FEATURES \
185 GEN(2), \
186 .pipe_mask = BIT(PIPE_A), \
187 .cpu_transcoder_mask = BIT(TRANSCODER_A), \
188 .display.has_overlay = 1, \
189 .display.overlay_needs_physical = 1, \
190 .display.has_gmch = 1, \
191 .gpu_reset_clobbers_display = true, \
192 .hws_needs_physical = 1, \
193 .unfenced_needs_alignment = 1, \
194 .platform_engine_mask = BIT(RCS0), \
195 .has_snoop = true, \
196 .has_coherent_ggtt = false, \
197 .dma_mask_size = 32, \
198 I845_PIPE_OFFSETS, \
199 I845_CURSOR_OFFSETS, \
200 I9XX_COLORS, \
201 GEN_DEFAULT_PAGE_SIZES, \
202 GEN_DEFAULT_REGIONS
203
204static const struct intel_device_info i830_info = {
205 I830_FEATURES,
206 PLATFORM(INTEL_I830),
207};
208
209static const struct intel_device_info i845g_info = {
210 I845_FEATURES,
211 PLATFORM(INTEL_I845G),
212};
213
214static const struct intel_device_info i85x_info = {
215 I830_FEATURES,
216 PLATFORM(INTEL_I85X),
217 .display.has_fbc = 1,
218};
219
220static const struct intel_device_info i865g_info = {
221 I845_FEATURES,
222 PLATFORM(INTEL_I865G),
223 .display.has_fbc = 1,
224};
225
226#define GEN3_FEATURES \
227 GEN(3), \
228 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
229 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
230 .display.has_gmch = 1, \
231 .gpu_reset_clobbers_display = true, \
232 .platform_engine_mask = BIT(RCS0), \
233 .has_snoop = true, \
234 .has_coherent_ggtt = true, \
235 .dma_mask_size = 32, \
236 I9XX_PIPE_OFFSETS, \
237 I9XX_CURSOR_OFFSETS, \
238 I9XX_COLORS, \
239 GEN_DEFAULT_PAGE_SIZES, \
240 GEN_DEFAULT_REGIONS
241
242static const struct intel_device_info i915g_info = {
243 GEN3_FEATURES,
244 PLATFORM(INTEL_I915G),
245 .has_coherent_ggtt = false,
246 .display.cursor_needs_physical = 1,
247 .display.has_overlay = 1,
248 .display.overlay_needs_physical = 1,
249 .hws_needs_physical = 1,
250 .unfenced_needs_alignment = 1,
251};
252
253static const struct intel_device_info i915gm_info = {
254 GEN3_FEATURES,
255 PLATFORM(INTEL_I915GM),
256 .is_mobile = 1,
257 .display.cursor_needs_physical = 1,
258 .display.has_overlay = 1,
259 .display.overlay_needs_physical = 1,
260 .display.supports_tv = 1,
261 .display.has_fbc = 1,
262 .hws_needs_physical = 1,
263 .unfenced_needs_alignment = 1,
264};
265
266static const struct intel_device_info i945g_info = {
267 GEN3_FEATURES,
268 PLATFORM(INTEL_I945G),
269 .display.has_hotplug = 1,
270 .display.cursor_needs_physical = 1,
271 .display.has_overlay = 1,
272 .display.overlay_needs_physical = 1,
273 .hws_needs_physical = 1,
274 .unfenced_needs_alignment = 1,
275};
276
277static const struct intel_device_info i945gm_info = {
278 GEN3_FEATURES,
279 PLATFORM(INTEL_I945GM),
280 .is_mobile = 1,
281 .display.has_hotplug = 1,
282 .display.cursor_needs_physical = 1,
283 .display.has_overlay = 1,
284 .display.overlay_needs_physical = 1,
285 .display.supports_tv = 1,
286 .display.has_fbc = 1,
287 .hws_needs_physical = 1,
288 .unfenced_needs_alignment = 1,
289};
290
291static const struct intel_device_info g33_info = {
292 GEN3_FEATURES,
293 PLATFORM(INTEL_G33),
294 .display.has_hotplug = 1,
295 .display.has_overlay = 1,
296 .dma_mask_size = 36,
297};
298
299static const struct intel_device_info pnv_g_info = {
300 GEN3_FEATURES,
301 PLATFORM(INTEL_PINEVIEW),
302 .display.has_hotplug = 1,
303 .display.has_overlay = 1,
304 .dma_mask_size = 36,
305};
306
307static const struct intel_device_info pnv_m_info = {
308 GEN3_FEATURES,
309 PLATFORM(INTEL_PINEVIEW),
310 .is_mobile = 1,
311 .display.has_hotplug = 1,
312 .display.has_overlay = 1,
313 .dma_mask_size = 36,
314};
315
316#define GEN4_FEATURES \
317 GEN(4), \
318 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
319 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
320 .display.has_hotplug = 1, \
321 .display.has_gmch = 1, \
322 .gpu_reset_clobbers_display = true, \
323 .platform_engine_mask = BIT(RCS0), \
324 .has_snoop = true, \
325 .has_coherent_ggtt = true, \
326 .dma_mask_size = 36, \
327 I9XX_PIPE_OFFSETS, \
328 I9XX_CURSOR_OFFSETS, \
329 I965_COLORS, \
330 GEN_DEFAULT_PAGE_SIZES, \
331 GEN_DEFAULT_REGIONS
332
333static const struct intel_device_info i965g_info = {
334 GEN4_FEATURES,
335 PLATFORM(INTEL_I965G),
336 .display.has_overlay = 1,
337 .hws_needs_physical = 1,
338 .has_snoop = false,
339};
340
341static const struct intel_device_info i965gm_info = {
342 GEN4_FEATURES,
343 PLATFORM(INTEL_I965GM),
344 .is_mobile = 1,
345 .display.has_fbc = 1,
346 .display.has_overlay = 1,
347 .display.supports_tv = 1,
348 .hws_needs_physical = 1,
349 .has_snoop = false,
350};
351
352static const struct intel_device_info g45_info = {
353 GEN4_FEATURES,
354 PLATFORM(INTEL_G45),
355 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
356 .gpu_reset_clobbers_display = false,
357};
358
359static const struct intel_device_info gm45_info = {
360 GEN4_FEATURES,
361 PLATFORM(INTEL_GM45),
362 .is_mobile = 1,
363 .display.has_fbc = 1,
364 .display.supports_tv = 1,
365 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
366 .gpu_reset_clobbers_display = false,
367};
368
369#define GEN5_FEATURES \
370 GEN(5), \
371 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
372 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
373 .display.has_hotplug = 1, \
374 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
375 .has_snoop = true, \
376 .has_coherent_ggtt = true, \
377 /* ilk does support rc6, but we do not implement [power] contexts */ \
378 .has_rc6 = 0, \
379 .dma_mask_size = 36, \
380 I9XX_PIPE_OFFSETS, \
381 I9XX_CURSOR_OFFSETS, \
382 ILK_COLORS, \
383 GEN_DEFAULT_PAGE_SIZES, \
384 GEN_DEFAULT_REGIONS
385
386static const struct intel_device_info ilk_d_info = {
387 GEN5_FEATURES,
388 PLATFORM(INTEL_IRONLAKE),
389};
390
391static const struct intel_device_info ilk_m_info = {
392 GEN5_FEATURES,
393 PLATFORM(INTEL_IRONLAKE),
394 .is_mobile = 1,
395 .has_rps = true,
396 .display.has_fbc = 1,
397};
398
399#define GEN6_FEATURES \
400 GEN(6), \
401 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
402 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
403 .display.has_hotplug = 1, \
404 .display.has_fbc = 1, \
405 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
406 .has_coherent_ggtt = true, \
407 .has_llc = 1, \
408 .has_rc6 = 1, \
409 .has_rc6p = 1, \
410 .has_rps = true, \
411 .dma_mask_size = 40, \
412 .ppgtt_type = INTEL_PPGTT_ALIASING, \
413 .ppgtt_size = 31, \
414 I9XX_PIPE_OFFSETS, \
415 I9XX_CURSOR_OFFSETS, \
416 ILK_COLORS, \
417 GEN_DEFAULT_PAGE_SIZES, \
418 GEN_DEFAULT_REGIONS
419
420#define SNB_D_PLATFORM \
421 GEN6_FEATURES, \
422 PLATFORM(INTEL_SANDYBRIDGE)
423
424static const struct intel_device_info snb_d_gt1_info = {
425 SNB_D_PLATFORM,
426 .gt = 1,
427};
428
429static const struct intel_device_info snb_d_gt2_info = {
430 SNB_D_PLATFORM,
431 .gt = 2,
432};
433
434#define SNB_M_PLATFORM \
435 GEN6_FEATURES, \
436 PLATFORM(INTEL_SANDYBRIDGE), \
437 .is_mobile = 1
438
439
440static const struct intel_device_info snb_m_gt1_info = {
441 SNB_M_PLATFORM,
442 .gt = 1,
443};
444
445static const struct intel_device_info snb_m_gt2_info = {
446 SNB_M_PLATFORM,
447 .gt = 2,
448};
449
450#define GEN7_FEATURES \
451 GEN(7), \
452 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
453 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
454 .display.has_hotplug = 1, \
455 .display.has_fbc = 1, \
456 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
457 .has_coherent_ggtt = true, \
458 .has_llc = 1, \
459 .has_rc6 = 1, \
460 .has_rc6p = 1, \
461 .has_reset_engine = true, \
462 .has_rps = true, \
463 .dma_mask_size = 40, \
464 .ppgtt_type = INTEL_PPGTT_ALIASING, \
465 .ppgtt_size = 31, \
466 IVB_PIPE_OFFSETS, \
467 IVB_CURSOR_OFFSETS, \
468 IVB_COLORS, \
469 GEN_DEFAULT_PAGE_SIZES, \
470 GEN_DEFAULT_REGIONS
471
472#define IVB_D_PLATFORM \
473 GEN7_FEATURES, \
474 PLATFORM(INTEL_IVYBRIDGE), \
475 .has_l3_dpf = 1
476
477static const struct intel_device_info ivb_d_gt1_info = {
478 IVB_D_PLATFORM,
479 .gt = 1,
480};
481
482static const struct intel_device_info ivb_d_gt2_info = {
483 IVB_D_PLATFORM,
484 .gt = 2,
485};
486
487#define IVB_M_PLATFORM \
488 GEN7_FEATURES, \
489 PLATFORM(INTEL_IVYBRIDGE), \
490 .is_mobile = 1, \
491 .has_l3_dpf = 1
492
493static const struct intel_device_info ivb_m_gt1_info = {
494 IVB_M_PLATFORM,
495 .gt = 1,
496};
497
498static const struct intel_device_info ivb_m_gt2_info = {
499 IVB_M_PLATFORM,
500 .gt = 2,
501};
502
503static const struct intel_device_info ivb_q_info = {
504 GEN7_FEATURES,
505 PLATFORM(INTEL_IVYBRIDGE),
506 .gt = 2,
507 .pipe_mask = 0, /* legal, last one wins */
508 .cpu_transcoder_mask = 0,
509 .has_l3_dpf = 1,
510};
511
512static const struct intel_device_info vlv_info = {
513 PLATFORM(INTEL_VALLEYVIEW),
514 GEN(7),
515 .is_lp = 1,
516 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
517 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
518 .has_runtime_pm = 1,
519 .has_rc6 = 1,
520 .has_reset_engine = true,
521 .has_rps = true,
522 .display.has_gmch = 1,
523 .display.has_hotplug = 1,
524 .dma_mask_size = 40,
525 .ppgtt_type = INTEL_PPGTT_ALIASING,
526 .ppgtt_size = 31,
527 .has_snoop = true,
528 .has_coherent_ggtt = false,
529 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
530 .display_mmio_offset = VLV_DISPLAY_BASE,
531 I9XX_PIPE_OFFSETS,
532 I9XX_CURSOR_OFFSETS,
533 I965_COLORS,
534 GEN_DEFAULT_PAGE_SIZES,
535 GEN_DEFAULT_REGIONS,
536};
537
538#define G75_FEATURES \
539 GEN7_FEATURES, \
540 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
541 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
542 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
543 .display.has_ddi = 1, \
544 .display.has_fpga_dbg = 1, \
545 .display.has_psr = 1, \
546 .display.has_psr_hw_tracking = 1, \
547 .display.has_dp_mst = 1, \
548 .has_rc6p = 0 /* RC6p removed-by HSW */, \
549 HSW_PIPE_OFFSETS, \
550 .has_runtime_pm = 1
551
552#define HSW_PLATFORM \
553 G75_FEATURES, \
554 PLATFORM(INTEL_HASWELL), \
555 .has_l3_dpf = 1
556
557static const struct intel_device_info hsw_gt1_info = {
558 HSW_PLATFORM,
559 .gt = 1,
560};
561
562static const struct intel_device_info hsw_gt2_info = {
563 HSW_PLATFORM,
564 .gt = 2,
565};
566
567static const struct intel_device_info hsw_gt3_info = {
568 HSW_PLATFORM,
569 .gt = 3,
570};
571
572#define GEN8_FEATURES \
573 G75_FEATURES, \
574 GEN(8), \
575 .has_logical_ring_contexts = 1, \
576 .dma_mask_size = 39, \
577 .ppgtt_type = INTEL_PPGTT_FULL, \
578 .ppgtt_size = 48, \
579 .has_64bit_reloc = 1
580
581#define BDW_PLATFORM \
582 GEN8_FEATURES, \
583 PLATFORM(INTEL_BROADWELL)
584
585static const struct intel_device_info bdw_gt1_info = {
586 BDW_PLATFORM,
587 .gt = 1,
588};
589
590static const struct intel_device_info bdw_gt2_info = {
591 BDW_PLATFORM,
592 .gt = 2,
593};
594
595static const struct intel_device_info bdw_rsvd_info = {
596 BDW_PLATFORM,
597 .gt = 3,
598 /* According to the device ID those devices are GT3, they were
599 * previously treated as not GT3, keep it like that.
600 */
601};
602
603static const struct intel_device_info bdw_gt3_info = {
604 BDW_PLATFORM,
605 .gt = 3,
606 .platform_engine_mask =
607 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
608};
609
610static const struct intel_device_info chv_info = {
611 PLATFORM(INTEL_CHERRYVIEW),
612 GEN(8),
613 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
614 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
615 .display.has_hotplug = 1,
616 .is_lp = 1,
617 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
618 .has_64bit_reloc = 1,
619 .has_runtime_pm = 1,
620 .has_rc6 = 1,
621 .has_rps = true,
622 .has_logical_ring_contexts = 1,
623 .display.has_gmch = 1,
624 .dma_mask_size = 39,
625 .ppgtt_type = INTEL_PPGTT_FULL,
626 .ppgtt_size = 32,
627 .has_reset_engine = 1,
628 .has_snoop = true,
629 .has_coherent_ggtt = false,
630 .display_mmio_offset = VLV_DISPLAY_BASE,
631 CHV_PIPE_OFFSETS,
632 CHV_CURSOR_OFFSETS,
633 CHV_COLORS,
634 GEN_DEFAULT_PAGE_SIZES,
635 GEN_DEFAULT_REGIONS,
636};
637
638#define GEN9_DEFAULT_PAGE_SIZES \
639 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
640 I915_GTT_PAGE_SIZE_64K
641
642#define GEN9_FEATURES \
643 GEN8_FEATURES, \
644 GEN(9), \
645 GEN9_DEFAULT_PAGE_SIZES, \
646 .display.has_dmc = 1, \
647 .has_gt_uc = 1, \
648 .display.has_hdcp = 1, \
649 .display.has_ipc = 1, \
650 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
651 .dbuf.slice_mask = BIT(DBUF_S1)
652
653#define SKL_PLATFORM \
654 GEN9_FEATURES, \
655 PLATFORM(INTEL_SKYLAKE)
656
657static const struct intel_device_info skl_gt1_info = {
658 SKL_PLATFORM,
659 .gt = 1,
660};
661
662static const struct intel_device_info skl_gt2_info = {
663 SKL_PLATFORM,
664 .gt = 2,
665};
666
667#define SKL_GT3_PLUS_PLATFORM \
668 SKL_PLATFORM, \
669 .platform_engine_mask = \
670 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
671
672
673static const struct intel_device_info skl_gt3_info = {
674 SKL_GT3_PLUS_PLATFORM,
675 .gt = 3,
676};
677
678static const struct intel_device_info skl_gt4_info = {
679 SKL_GT3_PLUS_PLATFORM,
680 .gt = 4,
681};
682
683#define GEN9_LP_FEATURES \
684 GEN(9), \
685 .is_lp = 1, \
686 .dbuf.slice_mask = BIT(DBUF_S1), \
687 .display.has_hotplug = 1, \
688 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
689 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
690 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
691 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
692 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
693 .has_64bit_reloc = 1, \
694 .display.has_ddi = 1, \
695 .display.has_fpga_dbg = 1, \
696 .display.has_fbc = 1, \
697 .display.has_hdcp = 1, \
698 .display.has_psr = 1, \
699 .display.has_psr_hw_tracking = 1, \
700 .has_runtime_pm = 1, \
701 .display.has_dmc = 1, \
702 .has_rc6 = 1, \
703 .has_rps = true, \
704 .display.has_dp_mst = 1, \
705 .has_logical_ring_contexts = 1, \
706 .has_gt_uc = 1, \
707 .dma_mask_size = 39, \
708 .ppgtt_type = INTEL_PPGTT_FULL, \
709 .ppgtt_size = 48, \
710 .has_reset_engine = 1, \
711 .has_snoop = true, \
712 .has_coherent_ggtt = false, \
713 .display.has_ipc = 1, \
714 HSW_PIPE_OFFSETS, \
715 IVB_CURSOR_OFFSETS, \
716 IVB_COLORS, \
717 GEN9_DEFAULT_PAGE_SIZES, \
718 GEN_DEFAULT_REGIONS
719
720static const struct intel_device_info bxt_info = {
721 GEN9_LP_FEATURES,
722 PLATFORM(INTEL_BROXTON),
723 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
724};
725
726static const struct intel_device_info glk_info = {
727 GEN9_LP_FEATURES,
728 PLATFORM(INTEL_GEMINILAKE),
729 .display.ver = 10,
730 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
731 GLK_COLORS,
732};
733
734#define KBL_PLATFORM \
735 GEN9_FEATURES, \
736 PLATFORM(INTEL_KABYLAKE)
737
738static const struct intel_device_info kbl_gt1_info = {
739 KBL_PLATFORM,
740 .gt = 1,
741};
742
743static const struct intel_device_info kbl_gt2_info = {
744 KBL_PLATFORM,
745 .gt = 2,
746};
747
748static const struct intel_device_info kbl_gt3_info = {
749 KBL_PLATFORM,
750 .gt = 3,
751 .platform_engine_mask =
752 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
753};
754
755#define CFL_PLATFORM \
756 GEN9_FEATURES, \
757 PLATFORM(INTEL_COFFEELAKE)
758
759static const struct intel_device_info cfl_gt1_info = {
760 CFL_PLATFORM,
761 .gt = 1,
762};
763
764static const struct intel_device_info cfl_gt2_info = {
765 CFL_PLATFORM,
766 .gt = 2,
767};
768
769static const struct intel_device_info cfl_gt3_info = {
770 CFL_PLATFORM,
771 .gt = 3,
772 .platform_engine_mask =
773 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
774};
775
776#define CML_PLATFORM \
777 GEN9_FEATURES, \
778 PLATFORM(INTEL_COMETLAKE)
779
780static const struct intel_device_info cml_gt1_info = {
781 CML_PLATFORM,
782 .gt = 1,
783};
784
785static const struct intel_device_info cml_gt2_info = {
786 CML_PLATFORM,
787 .gt = 2,
788};
789
790#define GEN10_FEATURES \
791 GEN9_FEATURES, \
792 GEN(10), \
793 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
794 .display.has_dsc = 1, \
795 .has_coherent_ggtt = false, \
796 GLK_COLORS
797
798static const struct intel_device_info cnl_info = {
799 GEN10_FEATURES,
800 PLATFORM(INTEL_CANNONLAKE),
801 .gt = 2,
802};
803
804#define GEN11_DEFAULT_PAGE_SIZES \
805 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
806 I915_GTT_PAGE_SIZE_64K | \
807 I915_GTT_PAGE_SIZE_2M
808
809#define GEN11_FEATURES \
810 GEN10_FEATURES, \
811 GEN11_DEFAULT_PAGE_SIZES, \
812 .abox_mask = BIT(0), \
813 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
814 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
815 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
816 .pipe_offsets = { \
817 [TRANSCODER_A] = PIPE_A_OFFSET, \
818 [TRANSCODER_B] = PIPE_B_OFFSET, \
819 [TRANSCODER_C] = PIPE_C_OFFSET, \
820 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
821 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
822 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
823 }, \
824 .trans_offsets = { \
825 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
826 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
827 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
828 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
829 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
830 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
831 }, \
832 GEN(11), \
833 .dbuf.size = 2048, \
834 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
835 .has_logical_ring_elsq = 1, \
836 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
837
838static const struct intel_device_info icl_info = {
839 GEN11_FEATURES,
840 PLATFORM(INTEL_ICELAKE),
841 .platform_engine_mask =
842 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
843};
844
845static const struct intel_device_info ehl_info = {
846 GEN11_FEATURES,
847 PLATFORM(INTEL_ELKHARTLAKE),
848 .require_force_probe = 1,
849 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
850 .ppgtt_size = 36,
851};
852
853static const struct intel_device_info jsl_info = {
854 GEN11_FEATURES,
855 PLATFORM(INTEL_JASPERLAKE),
856 .require_force_probe = 1,
857 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
858 .ppgtt_size = 36,
859};
860
861#define GEN12_FEATURES \
862 GEN11_FEATURES, \
863 GEN(12), \
864 .abox_mask = GENMASK(2, 1), \
865 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
866 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
867 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
868 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
869 .pipe_offsets = { \
870 [TRANSCODER_A] = PIPE_A_OFFSET, \
871 [TRANSCODER_B] = PIPE_B_OFFSET, \
872 [TRANSCODER_C] = PIPE_C_OFFSET, \
873 [TRANSCODER_D] = PIPE_D_OFFSET, \
874 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
875 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
876 }, \
877 .trans_offsets = { \
878 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
879 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
880 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
881 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
882 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
883 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
884 }, \
885 TGL_CURSOR_OFFSETS, \
886 .has_global_mocs = 1, \
887 .display.has_dsb = 1
888
889static const struct intel_device_info tgl_info = {
890 GEN12_FEATURES,
891 PLATFORM(INTEL_TIGERLAKE),
892 .display.has_modular_fia = 1,
893 .platform_engine_mask =
894 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
895};
896
897static const struct intel_device_info rkl_info = {
898 GEN12_FEATURES,
899 PLATFORM(INTEL_ROCKETLAKE),
900 .abox_mask = BIT(0),
901 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
902 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
903 BIT(TRANSCODER_C),
904 .display.has_hti = 1,
905 .display.has_psr_hw_tracking = 0,
906 .platform_engine_mask =
907 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
908};
909
910#define DGFX_FEATURES \
911 .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
912 .has_master_unit_irq = 1, \
913 .has_llc = 0, \
914 .has_snoop = 1, \
915 .is_dgfx = 1
916
917static const struct intel_device_info dg1_info __maybe_unused = {
918 GEN12_FEATURES,
919 DGFX_FEATURES,
920 PLATFORM(INTEL_DG1),
921 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
922 .require_force_probe = 1,
923 .platform_engine_mask =
924 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
925 BIT(VCS0) | BIT(VCS2),
926 /* Wa_16011227922 */
927 .ppgtt_size = 47,
928};
929
930static const struct intel_device_info adl_s_info = {
931 GEN12_FEATURES,
932 PLATFORM(INTEL_ALDERLAKE_S),
933 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
934 .require_force_probe = 1,
935 .display.has_hti = 1,
936 .display.has_psr_hw_tracking = 0,
937 .platform_engine_mask =
938 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
939 .dma_mask_size = 46,
940};
941
942#define XE_LPD_FEATURES \
943 .display.ver = 13, \
944 .display.has_psr_hw_tracking = 0, \
945 .abox_mask = GENMASK(1, 0), \
946 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
947 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
948 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
949 .dbuf.size = 4096, \
950 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
951
952static const struct intel_device_info adl_p_info = {
953 GEN12_FEATURES,
954 XE_LPD_FEATURES,
955 PLATFORM(INTEL_ALDERLAKE_P),
956 .has_cdclk_crawl = 1,
957 .require_force_probe = 1,
958 .display.has_modular_fia = 1,
959 .platform_engine_mask =
960 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
961 .ppgtt_size = 48,
962 .dma_mask_size = 39,
963};
964
965#undef GEN
966#undef PLATFORM
967
968/*
969 * Make sure any device matches here are from most specific to most
970 * general. For example, since the Quanta match is based on the subsystem
971 * and subvendor IDs, we need it to come before the more general IVB
972 * PCI ID matches, otherwise we'll use the wrong info struct above.
973 */
974static const struct pci_device_id pciidlist[] = {
975 INTEL_I830_IDS(&i830_info),
976 INTEL_I845G_IDS(&i845g_info),
977 INTEL_I85X_IDS(&i85x_info),
978 INTEL_I865G_IDS(&i865g_info),
979 INTEL_I915G_IDS(&i915g_info),
980 INTEL_I915GM_IDS(&i915gm_info),
981 INTEL_I945G_IDS(&i945g_info),
982 INTEL_I945GM_IDS(&i945gm_info),
983 INTEL_I965G_IDS(&i965g_info),
984 INTEL_G33_IDS(&g33_info),
985 INTEL_I965GM_IDS(&i965gm_info),
986 INTEL_GM45_IDS(&gm45_info),
987 INTEL_G45_IDS(&g45_info),
988 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
989 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
990 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
991 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
992 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
993 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
994 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
995 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
996 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
997 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
998 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
999 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1000 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1001 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1002 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1003 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1004 INTEL_VLV_IDS(&vlv_info),
1005 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1006 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1007 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1008 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1009 INTEL_CHV_IDS(&chv_info),
1010 INTEL_SKL_GT1_IDS(&skl_gt1_info),
1011 INTEL_SKL_GT2_IDS(&skl_gt2_info),
1012 INTEL_SKL_GT3_IDS(&skl_gt3_info),
1013 INTEL_SKL_GT4_IDS(&skl_gt4_info),
1014 INTEL_BXT_IDS(&bxt_info),
1015 INTEL_GLK_IDS(&glk_info),
1016 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1017 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1018 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1019 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1020 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1021 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1022 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1023 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1024 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1025 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1026 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1027 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1028 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1029 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1030 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1031 INTEL_CML_GT1_IDS(&cml_gt1_info),
1032 INTEL_CML_GT2_IDS(&cml_gt2_info),
1033 INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1034 INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1035 INTEL_CNL_IDS(&cnl_info),
1036 INTEL_ICL_11_IDS(&icl_info),
1037 INTEL_EHL_IDS(&ehl_info),
1038 INTEL_JSL_IDS(&jsl_info),
1039 INTEL_TGL_12_IDS(&tgl_info),
1040 INTEL_RKL_IDS(&rkl_info),
1041 INTEL_ADLS_IDS(&adl_s_info),
1042 INTEL_ADLP_IDS(&adl_p_info),
1043 {0, 0, 0}
1044};
1045MODULE_DEVICE_TABLE(pci, pciidlist);
1046
1047static void i915_pci_remove(struct pci_dev *pdev)
1048{
1049 struct drm_i915_private *i915;
1050
1051 i915 = pci_get_drvdata(pdev);
1052 if (!i915) /* driver load aborted, nothing to cleanup */
1053 return;
1054
1055 i915_driver_remove(i915);
1056 pci_set_drvdata(pdev, NULL);
1057}
1058
1059/* is device_id present in comma separated list of ids */
1060static bool force_probe(u16 device_id, const char *devices)
1061{
1062 char *s, *p, *tok;
1063 bool ret;
1064
1065 if (!devices || !*devices)
1066 return false;
1067
1068 /* match everything */
1069 if (strcmp(devices, "*") == 0)
1070 return true;
1071
1072 s = kstrdup(devices, GFP_KERNEL);
1073 if (!s)
1074 return false;
1075
1076 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1077 u16 val;
1078
1079 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1080 ret = true;
1081 break;
1082 }
1083 }
1084
1085 kfree(s);
1086
1087 return ret;
1088}
1089
1090static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1091{
1092 struct intel_device_info *intel_info =
1093 (struct intel_device_info *) ent->driver_data;
1094 int err;
1095
1096 if (intel_info->require_force_probe &&
1097 !force_probe(pdev->device, i915_modparams.force_probe)) {
1098 dev_info(&pdev->dev,
1099 "Your graphics device %04x is not properly supported by the driver in this\n"
1100 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1101 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1102 "or (recommended) check for kernel updates.\n",
1103 pdev->device, pdev->device, pdev->device);
1104 return -ENODEV;
1105 }
1106
1107 /* Only bind to function 0 of the device. Early generations
1108 * used function 1 as a placeholder for multi-head. This causes
1109 * us confusion instead, especially on the systems where both
1110 * functions have the same PCI-ID!
1111 */
1112 if (PCI_FUNC(pdev->devfn))
1113 return -ENODEV;
1114
1115 /*
1116 * apple-gmux is needed on dual GPU MacBook Pro
1117 * to probe the panel if we're the inactive GPU.
1118 */
1119 if (vga_switcheroo_client_probe_defer(pdev))
1120 return -EPROBE_DEFER;
1121
1122 err = i915_driver_probe(pdev, ent);
1123 if (err)
1124 return err;
1125
1126 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1127 i915_pci_remove(pdev);
1128 return -ENODEV;
1129 }
1130
1131 err = i915_live_selftests(pdev);
1132 if (err) {
1133 i915_pci_remove(pdev);
1134 return err > 0 ? -ENOTTY : err;
1135 }
1136
1137 err = i915_perf_selftests(pdev);
1138 if (err) {
1139 i915_pci_remove(pdev);
1140 return err > 0 ? -ENOTTY : err;
1141 }
1142
1143 return 0;
1144}
1145
1146static void i915_pci_shutdown(struct pci_dev *pdev)
1147{
1148 struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1149
1150 i915_driver_shutdown(i915);
1151}
1152
1153static struct pci_driver i915_pci_driver = {
1154 .name = DRIVER_NAME,
1155 .id_table = pciidlist,
1156 .probe = i915_pci_probe,
1157 .remove = i915_pci_remove,
1158 .shutdown = i915_pci_shutdown,
1159 .driver.pm = &i915_pm_ops,
1160};
1161
1162static int __init i915_init(void)
1163{
1164 bool use_kms = true;
1165 int err;
1166
1167 err = i915_globals_init();
1168 if (err)
1169 return err;
1170
1171 err = i915_mock_selftests();
1172 if (err)
1173 return err > 0 ? 0 : err;
1174
1175 /*
1176 * Enable KMS by default, unless explicitly overriden by
1177 * either the i915.modeset prarameter or by the
1178 * vga_text_mode_force boot option.
1179 */
1180
1181 if (i915_modparams.modeset == 0)
1182 use_kms = false;
1183
1184 if (vgacon_text_force() && i915_modparams.modeset == -1)
1185 use_kms = false;
1186
1187 if (!use_kms) {
1188 /* Silently fail loading to not upset userspace. */
1189 DRM_DEBUG_DRIVER("KMS disabled.\n");
1190 return 0;
1191 }
1192
1193 i915_pmu_init();
1194
1195 err = pci_register_driver(&i915_pci_driver);
1196 if (err) {
1197 i915_pmu_exit();
1198 i915_globals_exit();
1199 return err;
1200 }
1201
1202 i915_perf_sysctl_register();
1203 return 0;
1204}
1205
1206static void __exit i915_exit(void)
1207{
1208 if (!i915_pci_driver.driver.owner)
1209 return;
1210
1211 i915_perf_sysctl_unregister();
1212 pci_unregister_driver(&i915_pci_driver);
1213 i915_globals_exit();
1214 i915_pmu_exit();
1215}
1216
1217module_init(i915_init);
1218module_exit(i915_exit);
1219
1220MODULE_AUTHOR("Tungsten Graphics, Inc.");
1221MODULE_AUTHOR("Intel Corporation");
1222
1223MODULE_DESCRIPTION(DRIVER_DESC);
1224MODULE_LICENSE("GPL and additional rights");
1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/console.h>
26#include <linux/vga_switcheroo.h>
27
28#include <drm/drm_drv.h>
29#include <drm/i915_pciids.h>
30
31#include "display/intel_fbdev.h"
32
33#include "i915_drv.h"
34#include "i915_perf.h"
35#include "i915_globals.h"
36#include "i915_selftest.h"
37
38#define PLATFORM(x) .platform = (x)
39#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
40
41#define I845_PIPE_OFFSETS \
42 .pipe_offsets = { \
43 [TRANSCODER_A] = PIPE_A_OFFSET, \
44 }, \
45 .trans_offsets = { \
46 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
47 }
48
49#define I9XX_PIPE_OFFSETS \
50 .pipe_offsets = { \
51 [TRANSCODER_A] = PIPE_A_OFFSET, \
52 [TRANSCODER_B] = PIPE_B_OFFSET, \
53 }, \
54 .trans_offsets = { \
55 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
56 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
57 }
58
59#define IVB_PIPE_OFFSETS \
60 .pipe_offsets = { \
61 [TRANSCODER_A] = PIPE_A_OFFSET, \
62 [TRANSCODER_B] = PIPE_B_OFFSET, \
63 [TRANSCODER_C] = PIPE_C_OFFSET, \
64 }, \
65 .trans_offsets = { \
66 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
67 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
68 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
69 }
70
71#define HSW_PIPE_OFFSETS \
72 .pipe_offsets = { \
73 [TRANSCODER_A] = PIPE_A_OFFSET, \
74 [TRANSCODER_B] = PIPE_B_OFFSET, \
75 [TRANSCODER_C] = PIPE_C_OFFSET, \
76 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
77 }, \
78 .trans_offsets = { \
79 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
80 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
81 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
82 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
83 }
84
85#define CHV_PIPE_OFFSETS \
86 .pipe_offsets = { \
87 [TRANSCODER_A] = PIPE_A_OFFSET, \
88 [TRANSCODER_B] = PIPE_B_OFFSET, \
89 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
90 }, \
91 .trans_offsets = { \
92 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
93 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
94 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
95 }
96
97#define I845_CURSOR_OFFSETS \
98 .cursor_offsets = { \
99 [PIPE_A] = CURSOR_A_OFFSET, \
100 }
101
102#define I9XX_CURSOR_OFFSETS \
103 .cursor_offsets = { \
104 [PIPE_A] = CURSOR_A_OFFSET, \
105 [PIPE_B] = CURSOR_B_OFFSET, \
106 }
107
108#define CHV_CURSOR_OFFSETS \
109 .cursor_offsets = { \
110 [PIPE_A] = CURSOR_A_OFFSET, \
111 [PIPE_B] = CURSOR_B_OFFSET, \
112 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
113 }
114
115#define IVB_CURSOR_OFFSETS \
116 .cursor_offsets = { \
117 [PIPE_A] = CURSOR_A_OFFSET, \
118 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
119 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
120 }
121
122#define TGL_CURSOR_OFFSETS \
123 .cursor_offsets = { \
124 [PIPE_A] = CURSOR_A_OFFSET, \
125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
126 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
127 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
128 }
129
130#define I9XX_COLORS \
131 .color = { .gamma_lut_size = 256 }
132#define I965_COLORS \
133 .color = { .gamma_lut_size = 129, \
134 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
135 }
136#define ILK_COLORS \
137 .color = { .gamma_lut_size = 1024 }
138#define IVB_COLORS \
139 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
140#define CHV_COLORS \
141 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
142 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
143 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
144 }
145#define GLK_COLORS \
146 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
147 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
148 DRM_COLOR_LUT_EQUAL_CHANNELS, \
149 }
150
151/* Keep in gen based order, and chronological order within a gen */
152
153#define GEN_DEFAULT_PAGE_SIZES \
154 .page_sizes = I915_GTT_PAGE_SIZE_4K
155
156#define GEN_DEFAULT_REGIONS \
157 .memory_regions = REGION_SMEM | REGION_STOLEN
158
159#define I830_FEATURES \
160 GEN(2), \
161 .is_mobile = 1, \
162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
163 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
164 .display.has_overlay = 1, \
165 .display.cursor_needs_physical = 1, \
166 .display.overlay_needs_physical = 1, \
167 .display.has_gmch = 1, \
168 .gpu_reset_clobbers_display = true, \
169 .hws_needs_physical = 1, \
170 .unfenced_needs_alignment = 1, \
171 .platform_engine_mask = BIT(RCS0), \
172 .has_snoop = true, \
173 .has_coherent_ggtt = false, \
174 .dma_mask_size = 32, \
175 I9XX_PIPE_OFFSETS, \
176 I9XX_CURSOR_OFFSETS, \
177 I9XX_COLORS, \
178 GEN_DEFAULT_PAGE_SIZES, \
179 GEN_DEFAULT_REGIONS
180
181#define I845_FEATURES \
182 GEN(2), \
183 .pipe_mask = BIT(PIPE_A), \
184 .cpu_transcoder_mask = BIT(TRANSCODER_A), \
185 .display.has_overlay = 1, \
186 .display.overlay_needs_physical = 1, \
187 .display.has_gmch = 1, \
188 .gpu_reset_clobbers_display = true, \
189 .hws_needs_physical = 1, \
190 .unfenced_needs_alignment = 1, \
191 .platform_engine_mask = BIT(RCS0), \
192 .has_snoop = true, \
193 .has_coherent_ggtt = false, \
194 .dma_mask_size = 32, \
195 I845_PIPE_OFFSETS, \
196 I845_CURSOR_OFFSETS, \
197 I9XX_COLORS, \
198 GEN_DEFAULT_PAGE_SIZES, \
199 GEN_DEFAULT_REGIONS
200
201static const struct intel_device_info i830_info = {
202 I830_FEATURES,
203 PLATFORM(INTEL_I830),
204};
205
206static const struct intel_device_info i845g_info = {
207 I845_FEATURES,
208 PLATFORM(INTEL_I845G),
209};
210
211static const struct intel_device_info i85x_info = {
212 I830_FEATURES,
213 PLATFORM(INTEL_I85X),
214 .display.has_fbc = 1,
215};
216
217static const struct intel_device_info i865g_info = {
218 I845_FEATURES,
219 PLATFORM(INTEL_I865G),
220 .display.has_fbc = 1,
221};
222
223#define GEN3_FEATURES \
224 GEN(3), \
225 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
226 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
227 .display.has_gmch = 1, \
228 .gpu_reset_clobbers_display = true, \
229 .platform_engine_mask = BIT(RCS0), \
230 .has_snoop = true, \
231 .has_coherent_ggtt = true, \
232 .dma_mask_size = 32, \
233 I9XX_PIPE_OFFSETS, \
234 I9XX_CURSOR_OFFSETS, \
235 I9XX_COLORS, \
236 GEN_DEFAULT_PAGE_SIZES, \
237 GEN_DEFAULT_REGIONS
238
239static const struct intel_device_info i915g_info = {
240 GEN3_FEATURES,
241 PLATFORM(INTEL_I915G),
242 .has_coherent_ggtt = false,
243 .display.cursor_needs_physical = 1,
244 .display.has_overlay = 1,
245 .display.overlay_needs_physical = 1,
246 .hws_needs_physical = 1,
247 .unfenced_needs_alignment = 1,
248};
249
250static const struct intel_device_info i915gm_info = {
251 GEN3_FEATURES,
252 PLATFORM(INTEL_I915GM),
253 .is_mobile = 1,
254 .display.cursor_needs_physical = 1,
255 .display.has_overlay = 1,
256 .display.overlay_needs_physical = 1,
257 .display.supports_tv = 1,
258 .display.has_fbc = 1,
259 .hws_needs_physical = 1,
260 .unfenced_needs_alignment = 1,
261};
262
263static const struct intel_device_info i945g_info = {
264 GEN3_FEATURES,
265 PLATFORM(INTEL_I945G),
266 .display.has_hotplug = 1,
267 .display.cursor_needs_physical = 1,
268 .display.has_overlay = 1,
269 .display.overlay_needs_physical = 1,
270 .hws_needs_physical = 1,
271 .unfenced_needs_alignment = 1,
272};
273
274static const struct intel_device_info i945gm_info = {
275 GEN3_FEATURES,
276 PLATFORM(INTEL_I945GM),
277 .is_mobile = 1,
278 .display.has_hotplug = 1,
279 .display.cursor_needs_physical = 1,
280 .display.has_overlay = 1,
281 .display.overlay_needs_physical = 1,
282 .display.supports_tv = 1,
283 .display.has_fbc = 1,
284 .hws_needs_physical = 1,
285 .unfenced_needs_alignment = 1,
286};
287
288static const struct intel_device_info g33_info = {
289 GEN3_FEATURES,
290 PLATFORM(INTEL_G33),
291 .display.has_hotplug = 1,
292 .display.has_overlay = 1,
293 .dma_mask_size = 36,
294};
295
296static const struct intel_device_info pnv_g_info = {
297 GEN3_FEATURES,
298 PLATFORM(INTEL_PINEVIEW),
299 .display.has_hotplug = 1,
300 .display.has_overlay = 1,
301 .dma_mask_size = 36,
302};
303
304static const struct intel_device_info pnv_m_info = {
305 GEN3_FEATURES,
306 PLATFORM(INTEL_PINEVIEW),
307 .is_mobile = 1,
308 .display.has_hotplug = 1,
309 .display.has_overlay = 1,
310 .dma_mask_size = 36,
311};
312
313#define GEN4_FEATURES \
314 GEN(4), \
315 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
316 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
317 .display.has_hotplug = 1, \
318 .display.has_gmch = 1, \
319 .gpu_reset_clobbers_display = true, \
320 .platform_engine_mask = BIT(RCS0), \
321 .has_snoop = true, \
322 .has_coherent_ggtt = true, \
323 .dma_mask_size = 36, \
324 I9XX_PIPE_OFFSETS, \
325 I9XX_CURSOR_OFFSETS, \
326 I965_COLORS, \
327 GEN_DEFAULT_PAGE_SIZES, \
328 GEN_DEFAULT_REGIONS
329
330static const struct intel_device_info i965g_info = {
331 GEN4_FEATURES,
332 PLATFORM(INTEL_I965G),
333 .display.has_overlay = 1,
334 .hws_needs_physical = 1,
335 .has_snoop = false,
336};
337
338static const struct intel_device_info i965gm_info = {
339 GEN4_FEATURES,
340 PLATFORM(INTEL_I965GM),
341 .is_mobile = 1,
342 .display.has_fbc = 1,
343 .display.has_overlay = 1,
344 .display.supports_tv = 1,
345 .hws_needs_physical = 1,
346 .has_snoop = false,
347};
348
349static const struct intel_device_info g45_info = {
350 GEN4_FEATURES,
351 PLATFORM(INTEL_G45),
352 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
353 .gpu_reset_clobbers_display = false,
354};
355
356static const struct intel_device_info gm45_info = {
357 GEN4_FEATURES,
358 PLATFORM(INTEL_GM45),
359 .is_mobile = 1,
360 .display.has_fbc = 1,
361 .display.supports_tv = 1,
362 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
363 .gpu_reset_clobbers_display = false,
364};
365
366#define GEN5_FEATURES \
367 GEN(5), \
368 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
369 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
370 .display.has_hotplug = 1, \
371 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
372 .has_snoop = true, \
373 .has_coherent_ggtt = true, \
374 /* ilk does support rc6, but we do not implement [power] contexts */ \
375 .has_rc6 = 0, \
376 .dma_mask_size = 36, \
377 I9XX_PIPE_OFFSETS, \
378 I9XX_CURSOR_OFFSETS, \
379 ILK_COLORS, \
380 GEN_DEFAULT_PAGE_SIZES, \
381 GEN_DEFAULT_REGIONS
382
383static const struct intel_device_info ilk_d_info = {
384 GEN5_FEATURES,
385 PLATFORM(INTEL_IRONLAKE),
386};
387
388static const struct intel_device_info ilk_m_info = {
389 GEN5_FEATURES,
390 PLATFORM(INTEL_IRONLAKE),
391 .is_mobile = 1,
392 .display.has_fbc = 1,
393};
394
395#define GEN6_FEATURES \
396 GEN(6), \
397 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
398 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
399 .display.has_hotplug = 1, \
400 .display.has_fbc = 1, \
401 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
402 .has_coherent_ggtt = true, \
403 .has_llc = 1, \
404 .has_rc6 = 1, \
405 .has_rc6p = 1, \
406 .has_rps = true, \
407 .dma_mask_size = 40, \
408 .ppgtt_type = INTEL_PPGTT_ALIASING, \
409 .ppgtt_size = 31, \
410 I9XX_PIPE_OFFSETS, \
411 I9XX_CURSOR_OFFSETS, \
412 ILK_COLORS, \
413 GEN_DEFAULT_PAGE_SIZES, \
414 GEN_DEFAULT_REGIONS
415
416#define SNB_D_PLATFORM \
417 GEN6_FEATURES, \
418 PLATFORM(INTEL_SANDYBRIDGE)
419
420static const struct intel_device_info snb_d_gt1_info = {
421 SNB_D_PLATFORM,
422 .gt = 1,
423};
424
425static const struct intel_device_info snb_d_gt2_info = {
426 SNB_D_PLATFORM,
427 .gt = 2,
428};
429
430#define SNB_M_PLATFORM \
431 GEN6_FEATURES, \
432 PLATFORM(INTEL_SANDYBRIDGE), \
433 .is_mobile = 1
434
435
436static const struct intel_device_info snb_m_gt1_info = {
437 SNB_M_PLATFORM,
438 .gt = 1,
439};
440
441static const struct intel_device_info snb_m_gt2_info = {
442 SNB_M_PLATFORM,
443 .gt = 2,
444};
445
446#define GEN7_FEATURES \
447 GEN(7), \
448 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
449 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
450 .display.has_hotplug = 1, \
451 .display.has_fbc = 1, \
452 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
453 .has_coherent_ggtt = true, \
454 .has_llc = 1, \
455 .has_rc6 = 1, \
456 .has_rc6p = 1, \
457 .has_rps = true, \
458 .dma_mask_size = 40, \
459 .ppgtt_type = INTEL_PPGTT_ALIASING, \
460 .ppgtt_size = 31, \
461 IVB_PIPE_OFFSETS, \
462 IVB_CURSOR_OFFSETS, \
463 IVB_COLORS, \
464 GEN_DEFAULT_PAGE_SIZES, \
465 GEN_DEFAULT_REGIONS
466
467#define IVB_D_PLATFORM \
468 GEN7_FEATURES, \
469 PLATFORM(INTEL_IVYBRIDGE), \
470 .has_l3_dpf = 1
471
472static const struct intel_device_info ivb_d_gt1_info = {
473 IVB_D_PLATFORM,
474 .gt = 1,
475};
476
477static const struct intel_device_info ivb_d_gt2_info = {
478 IVB_D_PLATFORM,
479 .gt = 2,
480};
481
482#define IVB_M_PLATFORM \
483 GEN7_FEATURES, \
484 PLATFORM(INTEL_IVYBRIDGE), \
485 .is_mobile = 1, \
486 .has_l3_dpf = 1
487
488static const struct intel_device_info ivb_m_gt1_info = {
489 IVB_M_PLATFORM,
490 .gt = 1,
491};
492
493static const struct intel_device_info ivb_m_gt2_info = {
494 IVB_M_PLATFORM,
495 .gt = 2,
496};
497
498static const struct intel_device_info ivb_q_info = {
499 GEN7_FEATURES,
500 PLATFORM(INTEL_IVYBRIDGE),
501 .gt = 2,
502 .pipe_mask = 0, /* legal, last one wins */
503 .cpu_transcoder_mask = 0,
504 .has_l3_dpf = 1,
505};
506
507static const struct intel_device_info vlv_info = {
508 PLATFORM(INTEL_VALLEYVIEW),
509 GEN(7),
510 .is_lp = 1,
511 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
512 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
513 .has_runtime_pm = 1,
514 .has_rc6 = 1,
515 .has_rps = true,
516 .display.has_gmch = 1,
517 .display.has_hotplug = 1,
518 .dma_mask_size = 40,
519 .ppgtt_type = INTEL_PPGTT_ALIASING,
520 .ppgtt_size = 31,
521 .has_snoop = true,
522 .has_coherent_ggtt = false,
523 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
524 .display_mmio_offset = VLV_DISPLAY_BASE,
525 I9XX_PIPE_OFFSETS,
526 I9XX_CURSOR_OFFSETS,
527 I965_COLORS,
528 GEN_DEFAULT_PAGE_SIZES,
529 GEN_DEFAULT_REGIONS,
530};
531
532#define G75_FEATURES \
533 GEN7_FEATURES, \
534 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
535 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
536 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
537 .display.has_ddi = 1, \
538 .has_fpga_dbg = 1, \
539 .display.has_psr = 1, \
540 .display.has_psr_hw_tracking = 1, \
541 .display.has_dp_mst = 1, \
542 .has_rc6p = 0 /* RC6p removed-by HSW */, \
543 HSW_PIPE_OFFSETS, \
544 .has_runtime_pm = 1
545
546#define HSW_PLATFORM \
547 G75_FEATURES, \
548 PLATFORM(INTEL_HASWELL), \
549 .has_l3_dpf = 1
550
551static const struct intel_device_info hsw_gt1_info = {
552 HSW_PLATFORM,
553 .gt = 1,
554};
555
556static const struct intel_device_info hsw_gt2_info = {
557 HSW_PLATFORM,
558 .gt = 2,
559};
560
561static const struct intel_device_info hsw_gt3_info = {
562 HSW_PLATFORM,
563 .gt = 3,
564};
565
566#define GEN8_FEATURES \
567 G75_FEATURES, \
568 GEN(8), \
569 .has_logical_ring_contexts = 1, \
570 .dma_mask_size = 39, \
571 .ppgtt_type = INTEL_PPGTT_FULL, \
572 .ppgtt_size = 48, \
573 .has_64bit_reloc = 1, \
574 .has_reset_engine = 1
575
576#define BDW_PLATFORM \
577 GEN8_FEATURES, \
578 PLATFORM(INTEL_BROADWELL)
579
580static const struct intel_device_info bdw_gt1_info = {
581 BDW_PLATFORM,
582 .gt = 1,
583};
584
585static const struct intel_device_info bdw_gt2_info = {
586 BDW_PLATFORM,
587 .gt = 2,
588};
589
590static const struct intel_device_info bdw_rsvd_info = {
591 BDW_PLATFORM,
592 .gt = 3,
593 /* According to the device ID those devices are GT3, they were
594 * previously treated as not GT3, keep it like that.
595 */
596};
597
598static const struct intel_device_info bdw_gt3_info = {
599 BDW_PLATFORM,
600 .gt = 3,
601 .platform_engine_mask =
602 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
603};
604
605static const struct intel_device_info chv_info = {
606 PLATFORM(INTEL_CHERRYVIEW),
607 GEN(8),
608 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
609 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
610 .display.has_hotplug = 1,
611 .is_lp = 1,
612 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
613 .has_64bit_reloc = 1,
614 .has_runtime_pm = 1,
615 .has_rc6 = 1,
616 .has_rps = true,
617 .has_logical_ring_contexts = 1,
618 .display.has_gmch = 1,
619 .dma_mask_size = 39,
620 .ppgtt_type = INTEL_PPGTT_FULL,
621 .ppgtt_size = 32,
622 .has_reset_engine = 1,
623 .has_snoop = true,
624 .has_coherent_ggtt = false,
625 .display_mmio_offset = VLV_DISPLAY_BASE,
626 CHV_PIPE_OFFSETS,
627 CHV_CURSOR_OFFSETS,
628 CHV_COLORS,
629 GEN_DEFAULT_PAGE_SIZES,
630 GEN_DEFAULT_REGIONS,
631};
632
633#define GEN9_DEFAULT_PAGE_SIZES \
634 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
635 I915_GTT_PAGE_SIZE_64K
636
637#define GEN9_FEATURES \
638 GEN8_FEATURES, \
639 GEN(9), \
640 GEN9_DEFAULT_PAGE_SIZES, \
641 .has_logical_ring_preemption = 1, \
642 .display.has_csr = 1, \
643 .has_gt_uc = 1, \
644 .display.has_hdcp = 1, \
645 .display.has_ipc = 1, \
646 .ddb_size = 896, \
647 .num_supported_dbuf_slices = 1
648
649#define SKL_PLATFORM \
650 GEN9_FEATURES, \
651 PLATFORM(INTEL_SKYLAKE)
652
653static const struct intel_device_info skl_gt1_info = {
654 SKL_PLATFORM,
655 .gt = 1,
656};
657
658static const struct intel_device_info skl_gt2_info = {
659 SKL_PLATFORM,
660 .gt = 2,
661};
662
663#define SKL_GT3_PLUS_PLATFORM \
664 SKL_PLATFORM, \
665 .platform_engine_mask = \
666 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
667
668
669static const struct intel_device_info skl_gt3_info = {
670 SKL_GT3_PLUS_PLATFORM,
671 .gt = 3,
672};
673
674static const struct intel_device_info skl_gt4_info = {
675 SKL_GT3_PLUS_PLATFORM,
676 .gt = 4,
677};
678
679#define GEN9_LP_FEATURES \
680 GEN(9), \
681 .is_lp = 1, \
682 .num_supported_dbuf_slices = 1, \
683 .display.has_hotplug = 1, \
684 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
685 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
686 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
687 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
688 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
689 .has_64bit_reloc = 1, \
690 .display.has_ddi = 1, \
691 .has_fpga_dbg = 1, \
692 .display.has_fbc = 1, \
693 .display.has_hdcp = 1, \
694 .display.has_psr = 1, \
695 .display.has_psr_hw_tracking = 1, \
696 .has_runtime_pm = 1, \
697 .display.has_csr = 1, \
698 .has_rc6 = 1, \
699 .has_rps = true, \
700 .display.has_dp_mst = 1, \
701 .has_logical_ring_contexts = 1, \
702 .has_logical_ring_preemption = 1, \
703 .has_gt_uc = 1, \
704 .dma_mask_size = 39, \
705 .ppgtt_type = INTEL_PPGTT_FULL, \
706 .ppgtt_size = 48, \
707 .has_reset_engine = 1, \
708 .has_snoop = true, \
709 .has_coherent_ggtt = false, \
710 .display.has_ipc = 1, \
711 HSW_PIPE_OFFSETS, \
712 IVB_CURSOR_OFFSETS, \
713 IVB_COLORS, \
714 GEN9_DEFAULT_PAGE_SIZES, \
715 GEN_DEFAULT_REGIONS
716
717static const struct intel_device_info bxt_info = {
718 GEN9_LP_FEATURES,
719 PLATFORM(INTEL_BROXTON),
720 .ddb_size = 512,
721};
722
723static const struct intel_device_info glk_info = {
724 GEN9_LP_FEATURES,
725 PLATFORM(INTEL_GEMINILAKE),
726 .ddb_size = 1024,
727 GLK_COLORS,
728};
729
730#define KBL_PLATFORM \
731 GEN9_FEATURES, \
732 PLATFORM(INTEL_KABYLAKE)
733
734static const struct intel_device_info kbl_gt1_info = {
735 KBL_PLATFORM,
736 .gt = 1,
737};
738
739static const struct intel_device_info kbl_gt2_info = {
740 KBL_PLATFORM,
741 .gt = 2,
742};
743
744static const struct intel_device_info kbl_gt3_info = {
745 KBL_PLATFORM,
746 .gt = 3,
747 .platform_engine_mask =
748 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
749};
750
751#define CFL_PLATFORM \
752 GEN9_FEATURES, \
753 PLATFORM(INTEL_COFFEELAKE)
754
755static const struct intel_device_info cfl_gt1_info = {
756 CFL_PLATFORM,
757 .gt = 1,
758};
759
760static const struct intel_device_info cfl_gt2_info = {
761 CFL_PLATFORM,
762 .gt = 2,
763};
764
765static const struct intel_device_info cfl_gt3_info = {
766 CFL_PLATFORM,
767 .gt = 3,
768 .platform_engine_mask =
769 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
770};
771
772#define CML_PLATFORM \
773 GEN9_FEATURES, \
774 PLATFORM(INTEL_COMETLAKE)
775
776static const struct intel_device_info cml_gt1_info = {
777 CML_PLATFORM,
778 .gt = 1,
779};
780
781static const struct intel_device_info cml_gt2_info = {
782 CML_PLATFORM,
783 .gt = 2,
784};
785
786#define GEN10_FEATURES \
787 GEN9_FEATURES, \
788 GEN(10), \
789 .ddb_size = 1024, \
790 .display.has_dsc = 1, \
791 .has_coherent_ggtt = false, \
792 GLK_COLORS
793
794static const struct intel_device_info cnl_info = {
795 GEN10_FEATURES,
796 PLATFORM(INTEL_CANNONLAKE),
797 .gt = 2,
798};
799
800#define GEN11_DEFAULT_PAGE_SIZES \
801 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
802 I915_GTT_PAGE_SIZE_64K | \
803 I915_GTT_PAGE_SIZE_2M
804
805#define GEN11_FEATURES \
806 GEN10_FEATURES, \
807 GEN11_DEFAULT_PAGE_SIZES, \
808 .abox_mask = BIT(0), \
809 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
810 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
811 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
812 .pipe_offsets = { \
813 [TRANSCODER_A] = PIPE_A_OFFSET, \
814 [TRANSCODER_B] = PIPE_B_OFFSET, \
815 [TRANSCODER_C] = PIPE_C_OFFSET, \
816 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
817 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
818 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
819 }, \
820 .trans_offsets = { \
821 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
822 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
823 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
824 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
825 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
826 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
827 }, \
828 GEN(11), \
829 .ddb_size = 2048, \
830 .num_supported_dbuf_slices = 2, \
831 .has_logical_ring_elsq = 1, \
832 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
833
834static const struct intel_device_info icl_info = {
835 GEN11_FEATURES,
836 PLATFORM(INTEL_ICELAKE),
837 .platform_engine_mask =
838 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
839};
840
841static const struct intel_device_info ehl_info = {
842 GEN11_FEATURES,
843 PLATFORM(INTEL_ELKHARTLAKE),
844 .require_force_probe = 1,
845 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
846 .ppgtt_size = 36,
847};
848
849#define GEN12_FEATURES \
850 GEN11_FEATURES, \
851 GEN(12), \
852 .abox_mask = GENMASK(2, 1), \
853 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
854 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
855 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
856 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
857 .pipe_offsets = { \
858 [TRANSCODER_A] = PIPE_A_OFFSET, \
859 [TRANSCODER_B] = PIPE_B_OFFSET, \
860 [TRANSCODER_C] = PIPE_C_OFFSET, \
861 [TRANSCODER_D] = PIPE_D_OFFSET, \
862 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
863 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
864 }, \
865 .trans_offsets = { \
866 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
867 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
868 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
869 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
870 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
871 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
872 }, \
873 TGL_CURSOR_OFFSETS, \
874 .has_global_mocs = 1, \
875 .display.has_dsb = 1
876
877static const struct intel_device_info tgl_info = {
878 GEN12_FEATURES,
879 PLATFORM(INTEL_TIGERLAKE),
880 .display.has_modular_fia = 1,
881 .platform_engine_mask =
882 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
883};
884
885static const struct intel_device_info rkl_info = {
886 GEN12_FEATURES,
887 PLATFORM(INTEL_ROCKETLAKE),
888 .abox_mask = BIT(0),
889 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
890 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
891 BIT(TRANSCODER_C),
892 .require_force_probe = 1,
893 .display.has_psr_hw_tracking = 0,
894 .platform_engine_mask =
895 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
896};
897
898#define GEN12_DGFX_FEATURES \
899 GEN12_FEATURES, \
900 .memory_regions = REGION_SMEM | REGION_LMEM, \
901 .has_master_unit_irq = 1, \
902 .is_dgfx = 1
903
904static const struct intel_device_info dg1_info __maybe_unused = {
905 GEN12_DGFX_FEATURES,
906 PLATFORM(INTEL_DG1),
907 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
908 .require_force_probe = 1,
909 .platform_engine_mask =
910 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
911 BIT(VCS0) | BIT(VCS2),
912};
913
914#undef GEN
915#undef PLATFORM
916
917/*
918 * Make sure any device matches here are from most specific to most
919 * general. For example, since the Quanta match is based on the subsystem
920 * and subvendor IDs, we need it to come before the more general IVB
921 * PCI ID matches, otherwise we'll use the wrong info struct above.
922 */
923static const struct pci_device_id pciidlist[] = {
924 INTEL_I830_IDS(&i830_info),
925 INTEL_I845G_IDS(&i845g_info),
926 INTEL_I85X_IDS(&i85x_info),
927 INTEL_I865G_IDS(&i865g_info),
928 INTEL_I915G_IDS(&i915g_info),
929 INTEL_I915GM_IDS(&i915gm_info),
930 INTEL_I945G_IDS(&i945g_info),
931 INTEL_I945GM_IDS(&i945gm_info),
932 INTEL_I965G_IDS(&i965g_info),
933 INTEL_G33_IDS(&g33_info),
934 INTEL_I965GM_IDS(&i965gm_info),
935 INTEL_GM45_IDS(&gm45_info),
936 INTEL_G45_IDS(&g45_info),
937 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
938 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
939 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
940 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
941 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
942 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
943 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
944 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
945 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
946 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
947 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
948 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
949 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
950 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
951 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
952 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
953 INTEL_VLV_IDS(&vlv_info),
954 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
955 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
956 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
957 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
958 INTEL_CHV_IDS(&chv_info),
959 INTEL_SKL_GT1_IDS(&skl_gt1_info),
960 INTEL_SKL_GT2_IDS(&skl_gt2_info),
961 INTEL_SKL_GT3_IDS(&skl_gt3_info),
962 INTEL_SKL_GT4_IDS(&skl_gt4_info),
963 INTEL_BXT_IDS(&bxt_info),
964 INTEL_GLK_IDS(&glk_info),
965 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
966 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
967 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
968 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
969 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
970 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
971 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
972 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
973 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
974 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
975 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
976 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
977 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
978 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
979 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
980 INTEL_CML_GT1_IDS(&cml_gt1_info),
981 INTEL_CML_GT2_IDS(&cml_gt2_info),
982 INTEL_CML_U_GT1_IDS(&cml_gt1_info),
983 INTEL_CML_U_GT2_IDS(&cml_gt2_info),
984 INTEL_CNL_IDS(&cnl_info),
985 INTEL_ICL_11_IDS(&icl_info),
986 INTEL_EHL_IDS(&ehl_info),
987 INTEL_TGL_12_IDS(&tgl_info),
988 INTEL_RKL_IDS(&rkl_info),
989 {0, 0, 0}
990};
991MODULE_DEVICE_TABLE(pci, pciidlist);
992
993static void i915_pci_remove(struct pci_dev *pdev)
994{
995 struct drm_i915_private *i915;
996
997 i915 = pci_get_drvdata(pdev);
998 if (!i915) /* driver load aborted, nothing to cleanup */
999 return;
1000
1001 i915_driver_remove(i915);
1002 pci_set_drvdata(pdev, NULL);
1003}
1004
1005/* is device_id present in comma separated list of ids */
1006static bool force_probe(u16 device_id, const char *devices)
1007{
1008 char *s, *p, *tok;
1009 bool ret;
1010
1011 if (!devices || !*devices)
1012 return false;
1013
1014 /* match everything */
1015 if (strcmp(devices, "*") == 0)
1016 return true;
1017
1018 s = kstrdup(devices, GFP_KERNEL);
1019 if (!s)
1020 return false;
1021
1022 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1023 u16 val;
1024
1025 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1026 ret = true;
1027 break;
1028 }
1029 }
1030
1031 kfree(s);
1032
1033 return ret;
1034}
1035
1036static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1037{
1038 struct intel_device_info *intel_info =
1039 (struct intel_device_info *) ent->driver_data;
1040 int err;
1041
1042 if (intel_info->require_force_probe &&
1043 !force_probe(pdev->device, i915_modparams.force_probe)) {
1044 dev_info(&pdev->dev,
1045 "Your graphics device %04x is not properly supported by the driver in this\n"
1046 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1047 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1048 "or (recommended) check for kernel updates.\n",
1049 pdev->device, pdev->device, pdev->device);
1050 return -ENODEV;
1051 }
1052
1053 /* Only bind to function 0 of the device. Early generations
1054 * used function 1 as a placeholder for multi-head. This causes
1055 * us confusion instead, especially on the systems where both
1056 * functions have the same PCI-ID!
1057 */
1058 if (PCI_FUNC(pdev->devfn))
1059 return -ENODEV;
1060
1061 /*
1062 * apple-gmux is needed on dual GPU MacBook Pro
1063 * to probe the panel if we're the inactive GPU.
1064 */
1065 if (vga_switcheroo_client_probe_defer(pdev))
1066 return -EPROBE_DEFER;
1067
1068 err = i915_driver_probe(pdev, ent);
1069 if (err)
1070 return err;
1071
1072 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1073 i915_pci_remove(pdev);
1074 return -ENODEV;
1075 }
1076
1077 err = i915_live_selftests(pdev);
1078 if (err) {
1079 i915_pci_remove(pdev);
1080 return err > 0 ? -ENOTTY : err;
1081 }
1082
1083 err = i915_perf_selftests(pdev);
1084 if (err) {
1085 i915_pci_remove(pdev);
1086 return err > 0 ? -ENOTTY : err;
1087 }
1088
1089 return 0;
1090}
1091
1092static struct pci_driver i915_pci_driver = {
1093 .name = DRIVER_NAME,
1094 .id_table = pciidlist,
1095 .probe = i915_pci_probe,
1096 .remove = i915_pci_remove,
1097 .driver.pm = &i915_pm_ops,
1098};
1099
1100static int __init i915_init(void)
1101{
1102 bool use_kms = true;
1103 int err;
1104
1105 err = i915_globals_init();
1106 if (err)
1107 return err;
1108
1109 err = i915_mock_selftests();
1110 if (err)
1111 return err > 0 ? 0 : err;
1112
1113 /*
1114 * Enable KMS by default, unless explicitly overriden by
1115 * either the i915.modeset prarameter or by the
1116 * vga_text_mode_force boot option.
1117 */
1118
1119 if (i915_modparams.modeset == 0)
1120 use_kms = false;
1121
1122 if (vgacon_text_force() && i915_modparams.modeset == -1)
1123 use_kms = false;
1124
1125 if (!use_kms) {
1126 /* Silently fail loading to not upset userspace. */
1127 DRM_DEBUG_DRIVER("KMS disabled.\n");
1128 return 0;
1129 }
1130
1131 err = pci_register_driver(&i915_pci_driver);
1132 if (err)
1133 return err;
1134
1135 i915_perf_sysctl_register();
1136 return 0;
1137}
1138
1139static void __exit i915_exit(void)
1140{
1141 if (!i915_pci_driver.driver.owner)
1142 return;
1143
1144 i915_perf_sysctl_unregister();
1145 pci_unregister_driver(&i915_pci_driver);
1146 i915_globals_exit();
1147}
1148
1149module_init(i915_init);
1150module_exit(i915_exit);
1151
1152MODULE_AUTHOR("Tungsten Graphics, Inc.");
1153MODULE_AUTHOR("Intel Corporation");
1154
1155MODULE_DESCRIPTION(DRIVER_DESC);
1156MODULE_LICENSE("GPL and additional rights");