Loading...
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "intel_lrc_reg.h"
8#include "intel_sseu.h"
9
10void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
11 u8 max_subslices, u8 max_eus_per_subslice)
12{
13 sseu->max_slices = max_slices;
14 sseu->max_subslices = max_subslices;
15 sseu->max_eus_per_subslice = max_eus_per_subslice;
16
17 sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
18 GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
19 sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
20 GEM_BUG_ON(sseu->eu_stride > GEN_MAX_EU_STRIDE);
21}
22
23unsigned int
24intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
25{
26 unsigned int i, total = 0;
27
28 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
29 total += hweight8(sseu->subslice_mask[i]);
30
31 return total;
32}
33
34u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
35{
36 int i, offset = slice * sseu->ss_stride;
37 u32 mask = 0;
38
39 GEM_BUG_ON(slice >= sseu->max_slices);
40
41 for (i = 0; i < sseu->ss_stride; i++)
42 mask |= (u32)sseu->subslice_mask[offset + i] <<
43 i * BITS_PER_BYTE;
44
45 return mask;
46}
47
48void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
49 u32 ss_mask)
50{
51 int offset = slice * sseu->ss_stride;
52
53 memcpy(&sseu->subslice_mask[offset], &ss_mask, sseu->ss_stride);
54}
55
56unsigned int
57intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
58{
59 return hweight32(intel_sseu_get_subslices(sseu, slice));
60}
61
62static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
63 int subslice)
64{
65 int slice_stride = sseu->max_subslices * sseu->eu_stride;
66
67 return slice * slice_stride + subslice * sseu->eu_stride;
68}
69
70static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
71 int subslice)
72{
73 int i, offset = sseu_eu_idx(sseu, slice, subslice);
74 u16 eu_mask = 0;
75
76 for (i = 0; i < sseu->eu_stride; i++)
77 eu_mask |=
78 ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE);
79
80 return eu_mask;
81}
82
83static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
84 u16 eu_mask)
85{
86 int i, offset = sseu_eu_idx(sseu, slice, subslice);
87
88 for (i = 0; i < sseu->eu_stride; i++)
89 sseu->eu_mask[offset + i] =
90 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
91}
92
93static u16 compute_eu_total(const struct sseu_dev_info *sseu)
94{
95 u16 i, total = 0;
96
97 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
98 total += hweight8(sseu->eu_mask[i]);
99
100 return total;
101}
102
103static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
104 u8 s_en, u32 ss_en, u16 eu_en)
105{
106 int s, ss;
107
108 /* ss_en represents entire subslice mask across all slices */
109 GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
110 sizeof(ss_en) * BITS_PER_BYTE);
111
112 for (s = 0; s < sseu->max_slices; s++) {
113 if ((s_en & BIT(s)) == 0)
114 continue;
115
116 sseu->slice_mask |= BIT(s);
117
118 intel_sseu_set_subslices(sseu, s, ss_en);
119
120 for (ss = 0; ss < sseu->max_subslices; ss++)
121 if (intel_sseu_has_subslice(sseu, s, ss))
122 sseu_set_eus(sseu, s, ss, eu_en);
123 }
124 sseu->eu_per_subslice = hweight16(eu_en);
125 sseu->eu_total = compute_eu_total(sseu);
126}
127
128static void gen12_sseu_info_init(struct intel_gt *gt)
129{
130 struct sseu_dev_info *sseu = >->info.sseu;
131 struct intel_uncore *uncore = gt->uncore;
132 u32 dss_en;
133 u16 eu_en = 0;
134 u8 eu_en_fuse;
135 u8 s_en;
136 int eu;
137
138 /*
139 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
140 * Instead of splitting these, provide userspace with an array
141 * of DSS to more closely represent the hardware resource.
142 */
143 intel_sseu_set_info(sseu, 1, 6, 16);
144
145 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
146 GEN11_GT_S_ENA_MASK;
147
148 dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE);
149
150 /* one bit per pair of EUs */
151 eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
152 GEN11_EU_DIS_MASK);
153 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
154 if (eu_en_fuse & BIT(eu))
155 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
156
157 gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
158
159 /* TGL only supports slice-level power gating */
160 sseu->has_slice_pg = 1;
161}
162
163static void gen11_sseu_info_init(struct intel_gt *gt)
164{
165 struct sseu_dev_info *sseu = >->info.sseu;
166 struct intel_uncore *uncore = gt->uncore;
167 u32 ss_en;
168 u8 eu_en;
169 u8 s_en;
170
171 if (IS_JSL_EHL(gt->i915))
172 intel_sseu_set_info(sseu, 1, 4, 8);
173 else
174 intel_sseu_set_info(sseu, 1, 8, 8);
175
176 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
177 GEN11_GT_S_ENA_MASK;
178 ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
179
180 eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
181 GEN11_EU_DIS_MASK);
182
183 gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
184
185 /* ICL has no power gating restrictions. */
186 sseu->has_slice_pg = 1;
187 sseu->has_subslice_pg = 1;
188 sseu->has_eu_pg = 1;
189}
190
191static void gen10_sseu_info_init(struct intel_gt *gt)
192{
193 struct intel_uncore *uncore = gt->uncore;
194 struct sseu_dev_info *sseu = >->info.sseu;
195 const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
196 const int eu_mask = 0xff;
197 u32 subslice_mask, eu_en;
198 int s, ss;
199
200 intel_sseu_set_info(sseu, 6, 4, 8);
201
202 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
203 GEN10_F2_S_ENA_SHIFT;
204
205 /* Slice0 */
206 eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
207 for (ss = 0; ss < sseu->max_subslices; ss++)
208 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
209 /* Slice1 */
210 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
211 eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
212 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
213 /* Slice2 */
214 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
215 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
216 /* Slice3 */
217 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
218 eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
219 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
220 /* Slice4 */
221 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
222 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
223 /* Slice5 */
224 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
225 eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
226 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
227
228 subslice_mask = (1 << 4) - 1;
229 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
230 GEN10_F2_SS_DIS_SHIFT);
231
232 for (s = 0; s < sseu->max_slices; s++) {
233 u32 subslice_mask_with_eus = subslice_mask;
234
235 for (ss = 0; ss < sseu->max_subslices; ss++) {
236 if (sseu_get_eus(sseu, s, ss) == 0)
237 subslice_mask_with_eus &= ~BIT(ss);
238 }
239
240 /*
241 * Slice0 can have up to 3 subslices, but there are only 2 in
242 * slice1/2.
243 */
244 intel_sseu_set_subslices(sseu, s, s == 0 ?
245 subslice_mask_with_eus :
246 subslice_mask_with_eus & 0x3);
247 }
248
249 sseu->eu_total = compute_eu_total(sseu);
250
251 /*
252 * CNL is expected to always have a uniform distribution
253 * of EU across subslices with the exception that any one
254 * EU in any one subslice may be fused off for die
255 * recovery.
256 */
257 sseu->eu_per_subslice =
258 intel_sseu_subslice_total(sseu) ?
259 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :
260 0;
261
262 /* No restrictions on Power Gating */
263 sseu->has_slice_pg = 1;
264 sseu->has_subslice_pg = 1;
265 sseu->has_eu_pg = 1;
266}
267
268static void cherryview_sseu_info_init(struct intel_gt *gt)
269{
270 struct sseu_dev_info *sseu = >->info.sseu;
271 u32 fuse;
272 u8 subslice_mask = 0;
273
274 fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
275
276 sseu->slice_mask = BIT(0);
277 intel_sseu_set_info(sseu, 1, 2, 8);
278
279 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
280 u8 disabled_mask =
281 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
282 CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
283 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
284 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
285
286 subslice_mask |= BIT(0);
287 sseu_set_eus(sseu, 0, 0, ~disabled_mask);
288 }
289
290 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
291 u8 disabled_mask =
292 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
293 CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
294 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
295 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
296
297 subslice_mask |= BIT(1);
298 sseu_set_eus(sseu, 0, 1, ~disabled_mask);
299 }
300
301 intel_sseu_set_subslices(sseu, 0, subslice_mask);
302
303 sseu->eu_total = compute_eu_total(sseu);
304
305 /*
306 * CHV expected to always have a uniform distribution of EU
307 * across subslices.
308 */
309 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
310 sseu->eu_total /
311 intel_sseu_subslice_total(sseu) :
312 0;
313 /*
314 * CHV supports subslice power gating on devices with more than
315 * one subslice, and supports EU power gating on devices with
316 * more than one EU pair per subslice.
317 */
318 sseu->has_slice_pg = 0;
319 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1;
320 sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
321}
322
323static void gen9_sseu_info_init(struct intel_gt *gt)
324{
325 struct drm_i915_private *i915 = gt->i915;
326 struct intel_device_info *info = mkwrite_device_info(i915);
327 struct sseu_dev_info *sseu = >->info.sseu;
328 struct intel_uncore *uncore = gt->uncore;
329 u32 fuse2, eu_disable, subslice_mask;
330 const u8 eu_mask = 0xff;
331 int s, ss;
332
333 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
334 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
335
336 /* BXT has a single slice and at most 3 subslices. */
337 intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3,
338 IS_GEN9_LP(i915) ? 3 : 4, 8);
339
340 /*
341 * The subslice disable field is global, i.e. it applies
342 * to each of the enabled slices.
343 */
344 subslice_mask = (1 << sseu->max_subslices) - 1;
345 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
346 GEN9_F2_SS_DIS_SHIFT);
347
348 /*
349 * Iterate through enabled slices and subslices to
350 * count the total enabled EU.
351 */
352 for (s = 0; s < sseu->max_slices; s++) {
353 if (!(sseu->slice_mask & BIT(s)))
354 /* skip disabled slice */
355 continue;
356
357 intel_sseu_set_subslices(sseu, s, subslice_mask);
358
359 eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
360 for (ss = 0; ss < sseu->max_subslices; ss++) {
361 int eu_per_ss;
362 u8 eu_disabled_mask;
363
364 if (!intel_sseu_has_subslice(sseu, s, ss))
365 /* skip disabled subslice */
366 continue;
367
368 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
369
370 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
371
372 eu_per_ss = sseu->max_eus_per_subslice -
373 hweight8(eu_disabled_mask);
374
375 /*
376 * Record which subslice(s) has(have) 7 EUs. we
377 * can tune the hash used to spread work among
378 * subslices if they are unbalanced.
379 */
380 if (eu_per_ss == 7)
381 sseu->subslice_7eu[s] |= BIT(ss);
382 }
383 }
384
385 sseu->eu_total = compute_eu_total(sseu);
386
387 /*
388 * SKL is expected to always have a uniform distribution
389 * of EU across subslices with the exception that any one
390 * EU in any one subslice may be fused off for die
391 * recovery. BXT is expected to be perfectly uniform in EU
392 * distribution.
393 */
394 sseu->eu_per_subslice =
395 intel_sseu_subslice_total(sseu) ?
396 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :
397 0;
398
399 /*
400 * SKL+ supports slice power gating on devices with more than
401 * one slice, and supports EU power gating on devices with
402 * more than one EU pair per subslice. BXT+ supports subslice
403 * power gating on devices with more than one subslice, and
404 * supports EU power gating on devices with more than one EU
405 * pair per subslice.
406 */
407 sseu->has_slice_pg =
408 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1;
409 sseu->has_subslice_pg =
410 IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1;
411 sseu->has_eu_pg = sseu->eu_per_subslice > 2;
412
413 if (IS_GEN9_LP(i915)) {
414#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
415 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
416
417 sseu->min_eu_in_pool = 0;
418 if (info->has_pooled_eu) {
419 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
420 sseu->min_eu_in_pool = 3;
421 else if (IS_SS_DISABLED(1))
422 sseu->min_eu_in_pool = 6;
423 else
424 sseu->min_eu_in_pool = 9;
425 }
426#undef IS_SS_DISABLED
427 }
428}
429
430static void bdw_sseu_info_init(struct intel_gt *gt)
431{
432 struct sseu_dev_info *sseu = >->info.sseu;
433 struct intel_uncore *uncore = gt->uncore;
434 int s, ss;
435 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
436 u32 eu_disable0, eu_disable1, eu_disable2;
437
438 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
439 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
440 intel_sseu_set_info(sseu, 3, 3, 8);
441
442 /*
443 * The subslice disable field is global, i.e. it applies
444 * to each of the enabled slices.
445 */
446 subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
447 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
448 GEN8_F2_SS_DIS_SHIFT);
449 eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
450 eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
451 eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
452 eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
453 eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
454 ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
455 (32 - GEN8_EU_DIS0_S1_SHIFT));
456 eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
457 ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
458 (32 - GEN8_EU_DIS1_S2_SHIFT));
459
460 /*
461 * Iterate through enabled slices and subslices to
462 * count the total enabled EU.
463 */
464 for (s = 0; s < sseu->max_slices; s++) {
465 if (!(sseu->slice_mask & BIT(s)))
466 /* skip disabled slice */
467 continue;
468
469 intel_sseu_set_subslices(sseu, s, subslice_mask);
470
471 for (ss = 0; ss < sseu->max_subslices; ss++) {
472 u8 eu_disabled_mask;
473 u32 n_disabled;
474
475 if (!intel_sseu_has_subslice(sseu, s, ss))
476 /* skip disabled subslice */
477 continue;
478
479 eu_disabled_mask =
480 eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
481
482 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
483
484 n_disabled = hweight8(eu_disabled_mask);
485
486 /*
487 * Record which subslices have 7 EUs.
488 */
489 if (sseu->max_eus_per_subslice - n_disabled == 7)
490 sseu->subslice_7eu[s] |= 1 << ss;
491 }
492 }
493
494 sseu->eu_total = compute_eu_total(sseu);
495
496 /*
497 * BDW is expected to always have a uniform distribution of EU across
498 * subslices with the exception that any one EU in any one subslice may
499 * be fused off for die recovery.
500 */
501 sseu->eu_per_subslice =
502 intel_sseu_subslice_total(sseu) ?
503 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :
504 0;
505
506 /*
507 * BDW supports slice power gating on devices with more than
508 * one slice.
509 */
510 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
511 sseu->has_subslice_pg = 0;
512 sseu->has_eu_pg = 0;
513}
514
515static void hsw_sseu_info_init(struct intel_gt *gt)
516{
517 struct drm_i915_private *i915 = gt->i915;
518 struct sseu_dev_info *sseu = >->info.sseu;
519 u32 fuse1;
520 u8 subslice_mask = 0;
521 int s, ss;
522
523 /*
524 * There isn't a register to tell us how many slices/subslices. We
525 * work off the PCI-ids here.
526 */
527 switch (INTEL_INFO(i915)->gt) {
528 default:
529 MISSING_CASE(INTEL_INFO(i915)->gt);
530 fallthrough;
531 case 1:
532 sseu->slice_mask = BIT(0);
533 subslice_mask = BIT(0);
534 break;
535 case 2:
536 sseu->slice_mask = BIT(0);
537 subslice_mask = BIT(0) | BIT(1);
538 break;
539 case 3:
540 sseu->slice_mask = BIT(0) | BIT(1);
541 subslice_mask = BIT(0) | BIT(1);
542 break;
543 }
544
545 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
546 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
547 default:
548 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
549 HSW_F1_EU_DIS_SHIFT);
550 fallthrough;
551 case HSW_F1_EU_DIS_10EUS:
552 sseu->eu_per_subslice = 10;
553 break;
554 case HSW_F1_EU_DIS_8EUS:
555 sseu->eu_per_subslice = 8;
556 break;
557 case HSW_F1_EU_DIS_6EUS:
558 sseu->eu_per_subslice = 6;
559 break;
560 }
561
562 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
563 hweight8(subslice_mask),
564 sseu->eu_per_subslice);
565
566 for (s = 0; s < sseu->max_slices; s++) {
567 intel_sseu_set_subslices(sseu, s, subslice_mask);
568
569 for (ss = 0; ss < sseu->max_subslices; ss++) {
570 sseu_set_eus(sseu, s, ss,
571 (1UL << sseu->eu_per_subslice) - 1);
572 }
573 }
574
575 sseu->eu_total = compute_eu_total(sseu);
576
577 /* No powergating for you. */
578 sseu->has_slice_pg = 0;
579 sseu->has_subslice_pg = 0;
580 sseu->has_eu_pg = 0;
581}
582
583void intel_sseu_info_init(struct intel_gt *gt)
584{
585 struct drm_i915_private *i915 = gt->i915;
586
587 if (IS_HASWELL(i915))
588 hsw_sseu_info_init(gt);
589 else if (IS_CHERRYVIEW(i915))
590 cherryview_sseu_info_init(gt);
591 else if (IS_BROADWELL(i915))
592 bdw_sseu_info_init(gt);
593 else if (GRAPHICS_VER(i915) == 9)
594 gen9_sseu_info_init(gt);
595 else if (GRAPHICS_VER(i915) == 10)
596 gen10_sseu_info_init(gt);
597 else if (GRAPHICS_VER(i915) == 11)
598 gen11_sseu_info_init(gt);
599 else if (GRAPHICS_VER(i915) >= 12)
600 gen12_sseu_info_init(gt);
601}
602
603u32 intel_sseu_make_rpcs(struct intel_gt *gt,
604 const struct intel_sseu *req_sseu)
605{
606 struct drm_i915_private *i915 = gt->i915;
607 const struct sseu_dev_info *sseu = >->info.sseu;
608 bool subslice_pg = sseu->has_subslice_pg;
609 u8 slices, subslices;
610 u32 rpcs = 0;
611
612 /*
613 * No explicit RPCS request is needed to ensure full
614 * slice/subslice/EU enablement prior to Gen9.
615 */
616 if (GRAPHICS_VER(i915) < 9)
617 return 0;
618
619 /*
620 * If i915/perf is active, we want a stable powergating configuration
621 * on the system. Use the configuration pinned by i915/perf.
622 */
623 if (i915->perf.exclusive_stream)
624 req_sseu = &i915->perf.sseu;
625
626 slices = hweight8(req_sseu->slice_mask);
627 subslices = hweight8(req_sseu->subslice_mask);
628
629 /*
630 * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits
631 * wide and Icelake has up to eight subslices, specfial programming is
632 * needed in order to correctly enable all subslices.
633 *
634 * According to documentation software must consider the configuration
635 * as 2x4x8 and hardware will translate this to 1x8x8.
636 *
637 * Furthemore, even though SScount is three bits, maximum documented
638 * value for it is four. From this some rules/restrictions follow:
639 *
640 * 1.
641 * If enabled subslice count is greater than four, two whole slices must
642 * be enabled instead.
643 *
644 * 2.
645 * When more than one slice is enabled, hardware ignores the subslice
646 * count altogether.
647 *
648 * From these restrictions it follows that it is not possible to enable
649 * a count of subslices between the SScount maximum of four restriction,
650 * and the maximum available number on a particular SKU. Either all
651 * subslices are enabled, or a count between one and four on the first
652 * slice.
653 */
654 if (GRAPHICS_VER(i915) == 11 &&
655 slices == 1 &&
656 subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
657 GEM_BUG_ON(subslices & 1);
658
659 subslice_pg = false;
660 slices *= 2;
661 }
662
663 /*
664 * Starting in Gen9, render power gating can leave
665 * slice/subslice/EU in a partially enabled state. We
666 * must make an explicit request through RPCS for full
667 * enablement.
668 */
669 if (sseu->has_slice_pg) {
670 u32 mask, val = slices;
671
672 if (GRAPHICS_VER(i915) >= 11) {
673 mask = GEN11_RPCS_S_CNT_MASK;
674 val <<= GEN11_RPCS_S_CNT_SHIFT;
675 } else {
676 mask = GEN8_RPCS_S_CNT_MASK;
677 val <<= GEN8_RPCS_S_CNT_SHIFT;
678 }
679
680 GEM_BUG_ON(val & ~mask);
681 val &= mask;
682
683 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val;
684 }
685
686 if (subslice_pg) {
687 u32 val = subslices;
688
689 val <<= GEN8_RPCS_SS_CNT_SHIFT;
690
691 GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK);
692 val &= GEN8_RPCS_SS_CNT_MASK;
693
694 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
695 }
696
697 if (sseu->has_eu_pg) {
698 u32 val;
699
700 val = req_sseu->min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;
701 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
702 val &= GEN8_RPCS_EU_MIN_MASK;
703
704 rpcs |= val;
705
706 val = req_sseu->max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;
707 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
708 val &= GEN8_RPCS_EU_MAX_MASK;
709
710 rpcs |= val;
711
712 rpcs |= GEN8_RPCS_ENABLE;
713 }
714
715 return rpcs;
716}
717
718void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
719{
720 int s;
721
722 drm_printf(p, "slice total: %u, mask=%04x\n",
723 hweight8(sseu->slice_mask), sseu->slice_mask);
724 drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
725 for (s = 0; s < sseu->max_slices; s++) {
726 drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
727 s, intel_sseu_subslices_per_slice(sseu, s),
728 intel_sseu_get_subslices(sseu, s));
729 }
730 drm_printf(p, "EU total: %u\n", sseu->eu_total);
731 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
732 drm_printf(p, "has slice power gating: %s\n",
733 yesno(sseu->has_slice_pg));
734 drm_printf(p, "has subslice power gating: %s\n",
735 yesno(sseu->has_subslice_pg));
736 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
737}
738
739void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
740 struct drm_printer *p)
741{
742 int s, ss;
743
744 if (sseu->max_slices == 0) {
745 drm_printf(p, "Unavailable\n");
746 return;
747 }
748
749 for (s = 0; s < sseu->max_slices; s++) {
750 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
751 s, intel_sseu_subslices_per_slice(sseu, s),
752 intel_sseu_get_subslices(sseu, s));
753
754 for (ss = 0; ss < sseu->max_subslices; ss++) {
755 u16 enabled_eus = sseu_get_eus(sseu, s, ss);
756
757 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
758 ss, hweight16(enabled_eus), enabled_eus);
759 }
760 }
761}
1/*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright © 2019 Intel Corporation
5 */
6
7#include "i915_drv.h"
8#include "intel_lrc_reg.h"
9#include "intel_sseu.h"
10
11void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
12 u8 max_subslices, u8 max_eus_per_subslice)
13{
14 sseu->max_slices = max_slices;
15 sseu->max_subslices = max_subslices;
16 sseu->max_eus_per_subslice = max_eus_per_subslice;
17
18 sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
19 GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
20 sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
21 GEM_BUG_ON(sseu->eu_stride > GEN_MAX_EU_STRIDE);
22}
23
24unsigned int
25intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
26{
27 unsigned int i, total = 0;
28
29 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
30 total += hweight8(sseu->subslice_mask[i]);
31
32 return total;
33}
34
35u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
36{
37 int i, offset = slice * sseu->ss_stride;
38 u32 mask = 0;
39
40 GEM_BUG_ON(slice >= sseu->max_slices);
41
42 for (i = 0; i < sseu->ss_stride; i++)
43 mask |= (u32)sseu->subslice_mask[offset + i] <<
44 i * BITS_PER_BYTE;
45
46 return mask;
47}
48
49void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
50 u32 ss_mask)
51{
52 int offset = slice * sseu->ss_stride;
53
54 memcpy(&sseu->subslice_mask[offset], &ss_mask, sseu->ss_stride);
55}
56
57unsigned int
58intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
59{
60 return hweight32(intel_sseu_get_subslices(sseu, slice));
61}
62
63static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
64 int subslice)
65{
66 int slice_stride = sseu->max_subslices * sseu->eu_stride;
67
68 return slice * slice_stride + subslice * sseu->eu_stride;
69}
70
71static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
72 int subslice)
73{
74 int i, offset = sseu_eu_idx(sseu, slice, subslice);
75 u16 eu_mask = 0;
76
77 for (i = 0; i < sseu->eu_stride; i++)
78 eu_mask |=
79 ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE);
80
81 return eu_mask;
82}
83
84static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
85 u16 eu_mask)
86{
87 int i, offset = sseu_eu_idx(sseu, slice, subslice);
88
89 for (i = 0; i < sseu->eu_stride; i++)
90 sseu->eu_mask[offset + i] =
91 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
92}
93
94static u16 compute_eu_total(const struct sseu_dev_info *sseu)
95{
96 u16 i, total = 0;
97
98 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
99 total += hweight8(sseu->eu_mask[i]);
100
101 return total;
102}
103
104static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
105 u8 s_en, u32 ss_en, u16 eu_en)
106{
107 int s, ss;
108
109 /* ss_en represents entire subslice mask across all slices */
110 GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
111 sizeof(ss_en) * BITS_PER_BYTE);
112
113 for (s = 0; s < sseu->max_slices; s++) {
114 if ((s_en & BIT(s)) == 0)
115 continue;
116
117 sseu->slice_mask |= BIT(s);
118
119 intel_sseu_set_subslices(sseu, s, ss_en);
120
121 for (ss = 0; ss < sseu->max_subslices; ss++)
122 if (intel_sseu_has_subslice(sseu, s, ss))
123 sseu_set_eus(sseu, s, ss, eu_en);
124 }
125 sseu->eu_per_subslice = hweight16(eu_en);
126 sseu->eu_total = compute_eu_total(sseu);
127}
128
129static void gen12_sseu_info_init(struct intel_gt *gt)
130{
131 struct sseu_dev_info *sseu = >->info.sseu;
132 struct intel_uncore *uncore = gt->uncore;
133 u32 dss_en;
134 u16 eu_en = 0;
135 u8 eu_en_fuse;
136 u8 s_en;
137 int eu;
138
139 /*
140 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
141 * Instead of splitting these, provide userspace with an array
142 * of DSS to more closely represent the hardware resource.
143 */
144 intel_sseu_set_info(sseu, 1, 6, 16);
145
146 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
147 GEN11_GT_S_ENA_MASK;
148
149 dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE);
150
151 /* one bit per pair of EUs */
152 eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
153 GEN11_EU_DIS_MASK);
154 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
155 if (eu_en_fuse & BIT(eu))
156 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
157
158 gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
159
160 /* TGL only supports slice-level power gating */
161 sseu->has_slice_pg = 1;
162}
163
164static void gen11_sseu_info_init(struct intel_gt *gt)
165{
166 struct sseu_dev_info *sseu = >->info.sseu;
167 struct intel_uncore *uncore = gt->uncore;
168 u32 ss_en;
169 u8 eu_en;
170 u8 s_en;
171
172 if (IS_ELKHARTLAKE(gt->i915))
173 intel_sseu_set_info(sseu, 1, 4, 8);
174 else
175 intel_sseu_set_info(sseu, 1, 8, 8);
176
177 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
178 GEN11_GT_S_ENA_MASK;
179 ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
180
181 eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
182 GEN11_EU_DIS_MASK);
183
184 gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
185
186 /* ICL has no power gating restrictions. */
187 sseu->has_slice_pg = 1;
188 sseu->has_subslice_pg = 1;
189 sseu->has_eu_pg = 1;
190}
191
192static void gen10_sseu_info_init(struct intel_gt *gt)
193{
194 struct intel_uncore *uncore = gt->uncore;
195 struct sseu_dev_info *sseu = >->info.sseu;
196 const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
197 const int eu_mask = 0xff;
198 u32 subslice_mask, eu_en;
199 int s, ss;
200
201 intel_sseu_set_info(sseu, 6, 4, 8);
202
203 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
204 GEN10_F2_S_ENA_SHIFT;
205
206 /* Slice0 */
207 eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
208 for (ss = 0; ss < sseu->max_subslices; ss++)
209 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
210 /* Slice1 */
211 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
212 eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
213 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
214 /* Slice2 */
215 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
216 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
217 /* Slice3 */
218 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
219 eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
220 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
221 /* Slice4 */
222 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
223 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
224 /* Slice5 */
225 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
226 eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
227 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
228
229 subslice_mask = (1 << 4) - 1;
230 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
231 GEN10_F2_SS_DIS_SHIFT);
232
233 for (s = 0; s < sseu->max_slices; s++) {
234 u32 subslice_mask_with_eus = subslice_mask;
235
236 for (ss = 0; ss < sseu->max_subslices; ss++) {
237 if (sseu_get_eus(sseu, s, ss) == 0)
238 subslice_mask_with_eus &= ~BIT(ss);
239 }
240
241 /*
242 * Slice0 can have up to 3 subslices, but there are only 2 in
243 * slice1/2.
244 */
245 intel_sseu_set_subslices(sseu, s, s == 0 ?
246 subslice_mask_with_eus :
247 subslice_mask_with_eus & 0x3);
248 }
249
250 sseu->eu_total = compute_eu_total(sseu);
251
252 /*
253 * CNL is expected to always have a uniform distribution
254 * of EU across subslices with the exception that any one
255 * EU in any one subslice may be fused off for die
256 * recovery.
257 */
258 sseu->eu_per_subslice =
259 intel_sseu_subslice_total(sseu) ?
260 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :
261 0;
262
263 /* No restrictions on Power Gating */
264 sseu->has_slice_pg = 1;
265 sseu->has_subslice_pg = 1;
266 sseu->has_eu_pg = 1;
267}
268
269static void cherryview_sseu_info_init(struct intel_gt *gt)
270{
271 struct sseu_dev_info *sseu = >->info.sseu;
272 u32 fuse;
273 u8 subslice_mask = 0;
274
275 fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
276
277 sseu->slice_mask = BIT(0);
278 intel_sseu_set_info(sseu, 1, 2, 8);
279
280 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
281 u8 disabled_mask =
282 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
283 CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
284 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
285 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
286
287 subslice_mask |= BIT(0);
288 sseu_set_eus(sseu, 0, 0, ~disabled_mask);
289 }
290
291 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
292 u8 disabled_mask =
293 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
294 CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
295 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
296 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
297
298 subslice_mask |= BIT(1);
299 sseu_set_eus(sseu, 0, 1, ~disabled_mask);
300 }
301
302 intel_sseu_set_subslices(sseu, 0, subslice_mask);
303
304 sseu->eu_total = compute_eu_total(sseu);
305
306 /*
307 * CHV expected to always have a uniform distribution of EU
308 * across subslices.
309 */
310 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
311 sseu->eu_total /
312 intel_sseu_subslice_total(sseu) :
313 0;
314 /*
315 * CHV supports subslice power gating on devices with more than
316 * one subslice, and supports EU power gating on devices with
317 * more than one EU pair per subslice.
318 */
319 sseu->has_slice_pg = 0;
320 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1;
321 sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
322}
323
324static void gen9_sseu_info_init(struct intel_gt *gt)
325{
326 struct drm_i915_private *i915 = gt->i915;
327 struct intel_device_info *info = mkwrite_device_info(i915);
328 struct sseu_dev_info *sseu = >->info.sseu;
329 struct intel_uncore *uncore = gt->uncore;
330 u32 fuse2, eu_disable, subslice_mask;
331 const u8 eu_mask = 0xff;
332 int s, ss;
333
334 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
335 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
336
337 /* BXT has a single slice and at most 3 subslices. */
338 intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3,
339 IS_GEN9_LP(i915) ? 3 : 4, 8);
340
341 /*
342 * The subslice disable field is global, i.e. it applies
343 * to each of the enabled slices.
344 */
345 subslice_mask = (1 << sseu->max_subslices) - 1;
346 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
347 GEN9_F2_SS_DIS_SHIFT);
348
349 /*
350 * Iterate through enabled slices and subslices to
351 * count the total enabled EU.
352 */
353 for (s = 0; s < sseu->max_slices; s++) {
354 if (!(sseu->slice_mask & BIT(s)))
355 /* skip disabled slice */
356 continue;
357
358 intel_sseu_set_subslices(sseu, s, subslice_mask);
359
360 eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
361 for (ss = 0; ss < sseu->max_subslices; ss++) {
362 int eu_per_ss;
363 u8 eu_disabled_mask;
364
365 if (!intel_sseu_has_subslice(sseu, s, ss))
366 /* skip disabled subslice */
367 continue;
368
369 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
370
371 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
372
373 eu_per_ss = sseu->max_eus_per_subslice -
374 hweight8(eu_disabled_mask);
375
376 /*
377 * Record which subslice(s) has(have) 7 EUs. we
378 * can tune the hash used to spread work among
379 * subslices if they are unbalanced.
380 */
381 if (eu_per_ss == 7)
382 sseu->subslice_7eu[s] |= BIT(ss);
383 }
384 }
385
386 sseu->eu_total = compute_eu_total(sseu);
387
388 /*
389 * SKL is expected to always have a uniform distribution
390 * of EU across subslices with the exception that any one
391 * EU in any one subslice may be fused off for die
392 * recovery. BXT is expected to be perfectly uniform in EU
393 * distribution.
394 */
395 sseu->eu_per_subslice =
396 intel_sseu_subslice_total(sseu) ?
397 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :
398 0;
399
400 /*
401 * SKL+ supports slice power gating on devices with more than
402 * one slice, and supports EU power gating on devices with
403 * more than one EU pair per subslice. BXT+ supports subslice
404 * power gating on devices with more than one subslice, and
405 * supports EU power gating on devices with more than one EU
406 * pair per subslice.
407 */
408 sseu->has_slice_pg =
409 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1;
410 sseu->has_subslice_pg =
411 IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1;
412 sseu->has_eu_pg = sseu->eu_per_subslice > 2;
413
414 if (IS_GEN9_LP(i915)) {
415#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
416 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
417
418 sseu->min_eu_in_pool = 0;
419 if (info->has_pooled_eu) {
420 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
421 sseu->min_eu_in_pool = 3;
422 else if (IS_SS_DISABLED(1))
423 sseu->min_eu_in_pool = 6;
424 else
425 sseu->min_eu_in_pool = 9;
426 }
427#undef IS_SS_DISABLED
428 }
429}
430
431static void bdw_sseu_info_init(struct intel_gt *gt)
432{
433 struct sseu_dev_info *sseu = >->info.sseu;
434 struct intel_uncore *uncore = gt->uncore;
435 int s, ss;
436 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
437 u32 eu_disable0, eu_disable1, eu_disable2;
438
439 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
440 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
441 intel_sseu_set_info(sseu, 3, 3, 8);
442
443 /*
444 * The subslice disable field is global, i.e. it applies
445 * to each of the enabled slices.
446 */
447 subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
448 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
449 GEN8_F2_SS_DIS_SHIFT);
450 eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
451 eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
452 eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
453 eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
454 eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
455 ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
456 (32 - GEN8_EU_DIS0_S1_SHIFT));
457 eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
458 ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
459 (32 - GEN8_EU_DIS1_S2_SHIFT));
460
461 /*
462 * Iterate through enabled slices and subslices to
463 * count the total enabled EU.
464 */
465 for (s = 0; s < sseu->max_slices; s++) {
466 if (!(sseu->slice_mask & BIT(s)))
467 /* skip disabled slice */
468 continue;
469
470 intel_sseu_set_subslices(sseu, s, subslice_mask);
471
472 for (ss = 0; ss < sseu->max_subslices; ss++) {
473 u8 eu_disabled_mask;
474 u32 n_disabled;
475
476 if (!intel_sseu_has_subslice(sseu, s, ss))
477 /* skip disabled subslice */
478 continue;
479
480 eu_disabled_mask =
481 eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
482
483 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
484
485 n_disabled = hweight8(eu_disabled_mask);
486
487 /*
488 * Record which subslices have 7 EUs.
489 */
490 if (sseu->max_eus_per_subslice - n_disabled == 7)
491 sseu->subslice_7eu[s] |= 1 << ss;
492 }
493 }
494
495 sseu->eu_total = compute_eu_total(sseu);
496
497 /*
498 * BDW is expected to always have a uniform distribution of EU across
499 * subslices with the exception that any one EU in any one subslice may
500 * be fused off for die recovery.
501 */
502 sseu->eu_per_subslice =
503 intel_sseu_subslice_total(sseu) ?
504 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :
505 0;
506
507 /*
508 * BDW supports slice power gating on devices with more than
509 * one slice.
510 */
511 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
512 sseu->has_subslice_pg = 0;
513 sseu->has_eu_pg = 0;
514}
515
516static void hsw_sseu_info_init(struct intel_gt *gt)
517{
518 struct drm_i915_private *i915 = gt->i915;
519 struct sseu_dev_info *sseu = >->info.sseu;
520 u32 fuse1;
521 u8 subslice_mask = 0;
522 int s, ss;
523
524 /*
525 * There isn't a register to tell us how many slices/subslices. We
526 * work off the PCI-ids here.
527 */
528 switch (INTEL_INFO(i915)->gt) {
529 default:
530 MISSING_CASE(INTEL_INFO(i915)->gt);
531 fallthrough;
532 case 1:
533 sseu->slice_mask = BIT(0);
534 subslice_mask = BIT(0);
535 break;
536 case 2:
537 sseu->slice_mask = BIT(0);
538 subslice_mask = BIT(0) | BIT(1);
539 break;
540 case 3:
541 sseu->slice_mask = BIT(0) | BIT(1);
542 subslice_mask = BIT(0) | BIT(1);
543 break;
544 }
545
546 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
547 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
548 default:
549 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
550 HSW_F1_EU_DIS_SHIFT);
551 fallthrough;
552 case HSW_F1_EU_DIS_10EUS:
553 sseu->eu_per_subslice = 10;
554 break;
555 case HSW_F1_EU_DIS_8EUS:
556 sseu->eu_per_subslice = 8;
557 break;
558 case HSW_F1_EU_DIS_6EUS:
559 sseu->eu_per_subslice = 6;
560 break;
561 }
562
563 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
564 hweight8(subslice_mask),
565 sseu->eu_per_subslice);
566
567 for (s = 0; s < sseu->max_slices; s++) {
568 intel_sseu_set_subslices(sseu, s, subslice_mask);
569
570 for (ss = 0; ss < sseu->max_subslices; ss++) {
571 sseu_set_eus(sseu, s, ss,
572 (1UL << sseu->eu_per_subslice) - 1);
573 }
574 }
575
576 sseu->eu_total = compute_eu_total(sseu);
577
578 /* No powergating for you. */
579 sseu->has_slice_pg = 0;
580 sseu->has_subslice_pg = 0;
581 sseu->has_eu_pg = 0;
582}
583
584void intel_sseu_info_init(struct intel_gt *gt)
585{
586 struct drm_i915_private *i915 = gt->i915;
587
588 if (IS_HASWELL(i915))
589 hsw_sseu_info_init(gt);
590 else if (IS_CHERRYVIEW(i915))
591 cherryview_sseu_info_init(gt);
592 else if (IS_BROADWELL(i915))
593 bdw_sseu_info_init(gt);
594 else if (IS_GEN(i915, 9))
595 gen9_sseu_info_init(gt);
596 else if (IS_GEN(i915, 10))
597 gen10_sseu_info_init(gt);
598 else if (IS_GEN(i915, 11))
599 gen11_sseu_info_init(gt);
600 else if (INTEL_GEN(i915) >= 12)
601 gen12_sseu_info_init(gt);
602}
603
604u32 intel_sseu_make_rpcs(struct intel_gt *gt,
605 const struct intel_sseu *req_sseu)
606{
607 struct drm_i915_private *i915 = gt->i915;
608 const struct sseu_dev_info *sseu = >->info.sseu;
609 bool subslice_pg = sseu->has_subslice_pg;
610 u8 slices, subslices;
611 u32 rpcs = 0;
612
613 /*
614 * No explicit RPCS request is needed to ensure full
615 * slice/subslice/EU enablement prior to Gen9.
616 */
617 if (INTEL_GEN(i915) < 9)
618 return 0;
619
620 /*
621 * If i915/perf is active, we want a stable powergating configuration
622 * on the system. Use the configuration pinned by i915/perf.
623 */
624 if (i915->perf.exclusive_stream)
625 req_sseu = &i915->perf.sseu;
626
627 slices = hweight8(req_sseu->slice_mask);
628 subslices = hweight8(req_sseu->subslice_mask);
629
630 /*
631 * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits
632 * wide and Icelake has up to eight subslices, specfial programming is
633 * needed in order to correctly enable all subslices.
634 *
635 * According to documentation software must consider the configuration
636 * as 2x4x8 and hardware will translate this to 1x8x8.
637 *
638 * Furthemore, even though SScount is three bits, maximum documented
639 * value for it is four. From this some rules/restrictions follow:
640 *
641 * 1.
642 * If enabled subslice count is greater than four, two whole slices must
643 * be enabled instead.
644 *
645 * 2.
646 * When more than one slice is enabled, hardware ignores the subslice
647 * count altogether.
648 *
649 * From these restrictions it follows that it is not possible to enable
650 * a count of subslices between the SScount maximum of four restriction,
651 * and the maximum available number on a particular SKU. Either all
652 * subslices are enabled, or a count between one and four on the first
653 * slice.
654 */
655 if (IS_GEN(i915, 11) &&
656 slices == 1 &&
657 subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
658 GEM_BUG_ON(subslices & 1);
659
660 subslice_pg = false;
661 slices *= 2;
662 }
663
664 /*
665 * Starting in Gen9, render power gating can leave
666 * slice/subslice/EU in a partially enabled state. We
667 * must make an explicit request through RPCS for full
668 * enablement.
669 */
670 if (sseu->has_slice_pg) {
671 u32 mask, val = slices;
672
673 if (INTEL_GEN(i915) >= 11) {
674 mask = GEN11_RPCS_S_CNT_MASK;
675 val <<= GEN11_RPCS_S_CNT_SHIFT;
676 } else {
677 mask = GEN8_RPCS_S_CNT_MASK;
678 val <<= GEN8_RPCS_S_CNT_SHIFT;
679 }
680
681 GEM_BUG_ON(val & ~mask);
682 val &= mask;
683
684 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val;
685 }
686
687 if (subslice_pg) {
688 u32 val = subslices;
689
690 val <<= GEN8_RPCS_SS_CNT_SHIFT;
691
692 GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK);
693 val &= GEN8_RPCS_SS_CNT_MASK;
694
695 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
696 }
697
698 if (sseu->has_eu_pg) {
699 u32 val;
700
701 val = req_sseu->min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;
702 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
703 val &= GEN8_RPCS_EU_MIN_MASK;
704
705 rpcs |= val;
706
707 val = req_sseu->max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;
708 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
709 val &= GEN8_RPCS_EU_MAX_MASK;
710
711 rpcs |= val;
712
713 rpcs |= GEN8_RPCS_ENABLE;
714 }
715
716 return rpcs;
717}
718
719void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
720{
721 int s;
722
723 drm_printf(p, "slice total: %u, mask=%04x\n",
724 hweight8(sseu->slice_mask), sseu->slice_mask);
725 drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
726 for (s = 0; s < sseu->max_slices; s++) {
727 drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
728 s, intel_sseu_subslices_per_slice(sseu, s),
729 intel_sseu_get_subslices(sseu, s));
730 }
731 drm_printf(p, "EU total: %u\n", sseu->eu_total);
732 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
733 drm_printf(p, "has slice power gating: %s\n",
734 yesno(sseu->has_slice_pg));
735 drm_printf(p, "has subslice power gating: %s\n",
736 yesno(sseu->has_subslice_pg));
737 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
738}
739
740void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
741 struct drm_printer *p)
742{
743 int s, ss;
744
745 if (sseu->max_slices == 0) {
746 drm_printf(p, "Unavailable\n");
747 return;
748 }
749
750 for (s = 0; s < sseu->max_slices; s++) {
751 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
752 s, intel_sseu_subslices_per_slice(sseu, s),
753 intel_sseu_get_subslices(sseu, s));
754
755 for (ss = 0; ss < sseu->max_subslices; ss++) {
756 u16 enabled_eus = sseu_get_eus(sseu, s, ss);
757
758 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
759 ss, hweight16(enabled_eus), enabled_eus);
760 }
761 }
762}