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1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/hdmi.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
37#include <drm/drm_hdcp.h>
38#include <drm/drm_scdc_helper.h>
39#include <drm/intel_lpe_audio.h>
40
41#include "i915_debugfs.h"
42#include "i915_drv.h"
43#include "intel_atomic.h"
44#include "intel_connector.h"
45#include "intel_ddi.h"
46#include "intel_de.h"
47#include "intel_display_types.h"
48#include "intel_dp.h"
49#include "intel_gmbus.h"
50#include "intel_hdcp.h"
51#include "intel_hdmi.h"
52#include "intel_lspcon.h"
53#include "intel_panel.h"
54
55static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
56{
57 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
58}
59
60static void
61assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
62{
63 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
64 struct drm_i915_private *dev_priv = to_i915(dev);
65 u32 enabled_bits;
66
67 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
68
69 drm_WARN(dev,
70 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
71 "HDMI port enabled, expecting disabled\n");
72}
73
74static void
75assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
76 enum transcoder cpu_transcoder)
77{
78 drm_WARN(&dev_priv->drm,
79 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
80 TRANS_DDI_FUNC_ENABLE,
81 "HDMI transcoder function enabled, expecting disabled\n");
82}
83
84static u32 g4x_infoframe_index(unsigned int type)
85{
86 switch (type) {
87 case HDMI_PACKET_TYPE_GAMUT_METADATA:
88 return VIDEO_DIP_SELECT_GAMUT;
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_SELECT_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_SELECT_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_SELECT_VENDOR;
95 default:
96 MISSING_CASE(type);
97 return 0;
98 }
99}
100
101static u32 g4x_infoframe_enable(unsigned int type)
102{
103 switch (type) {
104 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
105 return VIDEO_DIP_ENABLE_GCP;
106 case HDMI_PACKET_TYPE_GAMUT_METADATA:
107 return VIDEO_DIP_ENABLE_GAMUT;
108 case DP_SDP_VSC:
109 return 0;
110 case HDMI_INFOFRAME_TYPE_AVI:
111 return VIDEO_DIP_ENABLE_AVI;
112 case HDMI_INFOFRAME_TYPE_SPD:
113 return VIDEO_DIP_ENABLE_SPD;
114 case HDMI_INFOFRAME_TYPE_VENDOR:
115 return VIDEO_DIP_ENABLE_VENDOR;
116 case HDMI_INFOFRAME_TYPE_DRM:
117 return 0;
118 default:
119 MISSING_CASE(type);
120 return 0;
121 }
122}
123
124static u32 hsw_infoframe_enable(unsigned int type)
125{
126 switch (type) {
127 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
128 return VIDEO_DIP_ENABLE_GCP_HSW;
129 case HDMI_PACKET_TYPE_GAMUT_METADATA:
130 return VIDEO_DIP_ENABLE_GMP_HSW;
131 case DP_SDP_VSC:
132 return VIDEO_DIP_ENABLE_VSC_HSW;
133 case DP_SDP_PPS:
134 return VDIP_ENABLE_PPS;
135 case HDMI_INFOFRAME_TYPE_AVI:
136 return VIDEO_DIP_ENABLE_AVI_HSW;
137 case HDMI_INFOFRAME_TYPE_SPD:
138 return VIDEO_DIP_ENABLE_SPD_HSW;
139 case HDMI_INFOFRAME_TYPE_VENDOR:
140 return VIDEO_DIP_ENABLE_VS_HSW;
141 case HDMI_INFOFRAME_TYPE_DRM:
142 return VIDEO_DIP_ENABLE_DRM_GLK;
143 default:
144 MISSING_CASE(type);
145 return 0;
146 }
147}
148
149static i915_reg_t
150hsw_dip_data_reg(struct drm_i915_private *dev_priv,
151 enum transcoder cpu_transcoder,
152 unsigned int type,
153 int i)
154{
155 switch (type) {
156 case HDMI_PACKET_TYPE_GAMUT_METADATA:
157 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
158 case DP_SDP_VSC:
159 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
160 case DP_SDP_PPS:
161 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
162 case HDMI_INFOFRAME_TYPE_AVI:
163 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
164 case HDMI_INFOFRAME_TYPE_SPD:
165 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
166 case HDMI_INFOFRAME_TYPE_VENDOR:
167 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
168 case HDMI_INFOFRAME_TYPE_DRM:
169 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
170 default:
171 MISSING_CASE(type);
172 return INVALID_MMIO_REG;
173 }
174}
175
176static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
177 unsigned int type)
178{
179 switch (type) {
180 case DP_SDP_VSC:
181 return VIDEO_DIP_VSC_DATA_SIZE;
182 case DP_SDP_PPS:
183 return VIDEO_DIP_PPS_DATA_SIZE;
184 case HDMI_PACKET_TYPE_GAMUT_METADATA:
185 if (DISPLAY_VER(dev_priv) >= 11)
186 return VIDEO_DIP_GMP_DATA_SIZE;
187 else
188 return VIDEO_DIP_DATA_SIZE;
189 default:
190 return VIDEO_DIP_DATA_SIZE;
191 }
192}
193
194static void g4x_write_infoframe(struct intel_encoder *encoder,
195 const struct intel_crtc_state *crtc_state,
196 unsigned int type,
197 const void *frame, ssize_t len)
198{
199 const u32 *data = frame;
200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
201 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
202 int i;
203
204 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
205 "Writing DIP with CTL reg disabled\n");
206
207 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
208 val |= g4x_infoframe_index(type);
209
210 val &= ~g4x_infoframe_enable(type);
211
212 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
213
214 for (i = 0; i < len; i += 4) {
215 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
216 data++;
217 }
218 /* Write every possible data byte to force correct ECC calculation. */
219 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
220 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
221
222 val |= g4x_infoframe_enable(type);
223 val &= ~VIDEO_DIP_FREQ_MASK;
224 val |= VIDEO_DIP_FREQ_VSYNC;
225
226 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
227 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
228}
229
230static void g4x_read_infoframe(struct intel_encoder *encoder,
231 const struct intel_crtc_state *crtc_state,
232 unsigned int type,
233 void *frame, ssize_t len)
234{
235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
236 u32 val, *data = frame;
237 int i;
238
239 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
240
241 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
242 val |= g4x_infoframe_index(type);
243
244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
245
246 for (i = 0; i < len; i += 4)
247 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
248}
249
250static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
251 const struct intel_crtc_state *pipe_config)
252{
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
254 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
255
256 if ((val & VIDEO_DIP_ENABLE) == 0)
257 return 0;
258
259 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
260 return 0;
261
262 return val & (VIDEO_DIP_ENABLE_AVI |
263 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
264}
265
266static void ibx_write_infoframe(struct intel_encoder *encoder,
267 const struct intel_crtc_state *crtc_state,
268 unsigned int type,
269 const void *frame, ssize_t len)
270{
271 const u32 *data = frame;
272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
274 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
275 u32 val = intel_de_read(dev_priv, reg);
276 int i;
277
278 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
279 "Writing DIP with CTL reg disabled\n");
280
281 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
282 val |= g4x_infoframe_index(type);
283
284 val &= ~g4x_infoframe_enable(type);
285
286 intel_de_write(dev_priv, reg, val);
287
288 for (i = 0; i < len; i += 4) {
289 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
290 *data);
291 data++;
292 }
293 /* Write every possible data byte to force correct ECC calculation. */
294 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
295 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
296
297 val |= g4x_infoframe_enable(type);
298 val &= ~VIDEO_DIP_FREQ_MASK;
299 val |= VIDEO_DIP_FREQ_VSYNC;
300
301 intel_de_write(dev_priv, reg, val);
302 intel_de_posting_read(dev_priv, reg);
303}
304
305static void ibx_read_infoframe(struct intel_encoder *encoder,
306 const struct intel_crtc_state *crtc_state,
307 unsigned int type,
308 void *frame, ssize_t len)
309{
310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
311 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
312 u32 val, *data = frame;
313 int i;
314
315 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
316
317 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
318 val |= g4x_infoframe_index(type);
319
320 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
321
322 for (i = 0; i < len; i += 4)
323 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
324}
325
326static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
327 const struct intel_crtc_state *pipe_config)
328{
329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
330 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
331 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
332 u32 val = intel_de_read(dev_priv, reg);
333
334 if ((val & VIDEO_DIP_ENABLE) == 0)
335 return 0;
336
337 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
338 return 0;
339
340 return val & (VIDEO_DIP_ENABLE_AVI |
341 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
342 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
343}
344
345static void cpt_write_infoframe(struct intel_encoder *encoder,
346 const struct intel_crtc_state *crtc_state,
347 unsigned int type,
348 const void *frame, ssize_t len)
349{
350 const u32 *data = frame;
351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
353 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
354 u32 val = intel_de_read(dev_priv, reg);
355 int i;
356
357 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
358 "Writing DIP with CTL reg disabled\n");
359
360 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
361 val |= g4x_infoframe_index(type);
362
363 /* The DIP control register spec says that we need to update the AVI
364 * infoframe without clearing its enable bit */
365 if (type != HDMI_INFOFRAME_TYPE_AVI)
366 val &= ~g4x_infoframe_enable(type);
367
368 intel_de_write(dev_priv, reg, val);
369
370 for (i = 0; i < len; i += 4) {
371 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
372 *data);
373 data++;
374 }
375 /* Write every possible data byte to force correct ECC calculation. */
376 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
377 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
378
379 val |= g4x_infoframe_enable(type);
380 val &= ~VIDEO_DIP_FREQ_MASK;
381 val |= VIDEO_DIP_FREQ_VSYNC;
382
383 intel_de_write(dev_priv, reg, val);
384 intel_de_posting_read(dev_priv, reg);
385}
386
387static void cpt_read_infoframe(struct intel_encoder *encoder,
388 const struct intel_crtc_state *crtc_state,
389 unsigned int type,
390 void *frame, ssize_t len)
391{
392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
394 u32 val, *data = frame;
395 int i;
396
397 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
398
399 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
400 val |= g4x_infoframe_index(type);
401
402 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
403
404 for (i = 0; i < len; i += 4)
405 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
406}
407
408static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
409 const struct intel_crtc_state *pipe_config)
410{
411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
412 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
413 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
414
415 if ((val & VIDEO_DIP_ENABLE) == 0)
416 return 0;
417
418 return val & (VIDEO_DIP_ENABLE_AVI |
419 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
420 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
421}
422
423static void vlv_write_infoframe(struct intel_encoder *encoder,
424 const struct intel_crtc_state *crtc_state,
425 unsigned int type,
426 const void *frame, ssize_t len)
427{
428 const u32 *data = frame;
429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
431 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
432 u32 val = intel_de_read(dev_priv, reg);
433 int i;
434
435 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
436 "Writing DIP with CTL reg disabled\n");
437
438 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
439 val |= g4x_infoframe_index(type);
440
441 val &= ~g4x_infoframe_enable(type);
442
443 intel_de_write(dev_priv, reg, val);
444
445 for (i = 0; i < len; i += 4) {
446 intel_de_write(dev_priv,
447 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
448 data++;
449 }
450 /* Write every possible data byte to force correct ECC calculation. */
451 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
452 intel_de_write(dev_priv,
453 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
454
455 val |= g4x_infoframe_enable(type);
456 val &= ~VIDEO_DIP_FREQ_MASK;
457 val |= VIDEO_DIP_FREQ_VSYNC;
458
459 intel_de_write(dev_priv, reg, val);
460 intel_de_posting_read(dev_priv, reg);
461}
462
463static void vlv_read_infoframe(struct intel_encoder *encoder,
464 const struct intel_crtc_state *crtc_state,
465 unsigned int type,
466 void *frame, ssize_t len)
467{
468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
470 u32 val, *data = frame;
471 int i;
472
473 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
474
475 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
476 val |= g4x_infoframe_index(type);
477
478 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
479
480 for (i = 0; i < len; i += 4)
481 *data++ = intel_de_read(dev_priv,
482 VLV_TVIDEO_DIP_DATA(crtc->pipe));
483}
484
485static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
486 const struct intel_crtc_state *pipe_config)
487{
488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
490 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
491
492 if ((val & VIDEO_DIP_ENABLE) == 0)
493 return 0;
494
495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
496 return 0;
497
498 return val & (VIDEO_DIP_ENABLE_AVI |
499 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
500 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
501}
502
503void hsw_write_infoframe(struct intel_encoder *encoder,
504 const struct intel_crtc_state *crtc_state,
505 unsigned int type,
506 const void *frame, ssize_t len)
507{
508 const u32 *data = frame;
509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
511 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
512 int data_size;
513 int i;
514 u32 val = intel_de_read(dev_priv, ctl_reg);
515
516 data_size = hsw_dip_data_size(dev_priv, type);
517
518 drm_WARN_ON(&dev_priv->drm, len > data_size);
519
520 val &= ~hsw_infoframe_enable(type);
521 intel_de_write(dev_priv, ctl_reg, val);
522
523 for (i = 0; i < len; i += 4) {
524 intel_de_write(dev_priv,
525 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
526 *data);
527 data++;
528 }
529 /* Write every possible data byte to force correct ECC calculation. */
530 for (; i < data_size; i += 4)
531 intel_de_write(dev_priv,
532 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
533 0);
534
535 /* Wa_14013475917 */
536 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
537 type == DP_SDP_VSC)
538 return;
539
540 val |= hsw_infoframe_enable(type);
541 intel_de_write(dev_priv, ctl_reg, val);
542 intel_de_posting_read(dev_priv, ctl_reg);
543}
544
545void hsw_read_infoframe(struct intel_encoder *encoder,
546 const struct intel_crtc_state *crtc_state,
547 unsigned int type, void *frame, ssize_t len)
548{
549 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
551 u32 *data = frame;
552 int i;
553
554 for (i = 0; i < len; i += 4)
555 *data++ = intel_de_read(dev_priv,
556 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
557}
558
559static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
560 const struct intel_crtc_state *pipe_config)
561{
562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
563 u32 val = intel_de_read(dev_priv,
564 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
565 u32 mask;
566
567 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
568 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
569 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
570
571 if (DISPLAY_VER(dev_priv) >= 10)
572 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
573
574 return val & mask;
575}
576
577static const u8 infoframe_type_to_idx[] = {
578 HDMI_PACKET_TYPE_GENERAL_CONTROL,
579 HDMI_PACKET_TYPE_GAMUT_METADATA,
580 DP_SDP_VSC,
581 HDMI_INFOFRAME_TYPE_AVI,
582 HDMI_INFOFRAME_TYPE_SPD,
583 HDMI_INFOFRAME_TYPE_VENDOR,
584 HDMI_INFOFRAME_TYPE_DRM,
585};
586
587u32 intel_hdmi_infoframe_enable(unsigned int type)
588{
589 int i;
590
591 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
592 if (infoframe_type_to_idx[i] == type)
593 return BIT(i);
594 }
595
596 return 0;
597}
598
599u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
600 const struct intel_crtc_state *crtc_state)
601{
602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
603 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
604 u32 val, ret = 0;
605 int i;
606
607 val = dig_port->infoframes_enabled(encoder, crtc_state);
608
609 /* map from hardware bits to dip idx */
610 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
611 unsigned int type = infoframe_type_to_idx[i];
612
613 if (HAS_DDI(dev_priv)) {
614 if (val & hsw_infoframe_enable(type))
615 ret |= BIT(i);
616 } else {
617 if (val & g4x_infoframe_enable(type))
618 ret |= BIT(i);
619 }
620 }
621
622 return ret;
623}
624
625/*
626 * The data we write to the DIP data buffer registers is 1 byte bigger than the
627 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
628 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
629 * used for both technologies.
630 *
631 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
632 * DW1: DB3 | DB2 | DB1 | DB0
633 * DW2: DB7 | DB6 | DB5 | DB4
634 * DW3: ...
635 *
636 * (HB is Header Byte, DB is Data Byte)
637 *
638 * The hdmi pack() functions don't know about that hardware specific hole so we
639 * trick them by giving an offset into the buffer and moving back the header
640 * bytes by one.
641 */
642static void intel_write_infoframe(struct intel_encoder *encoder,
643 const struct intel_crtc_state *crtc_state,
644 enum hdmi_infoframe_type type,
645 const union hdmi_infoframe *frame)
646{
647 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
648 u8 buffer[VIDEO_DIP_DATA_SIZE];
649 ssize_t len;
650
651 if ((crtc_state->infoframes.enable &
652 intel_hdmi_infoframe_enable(type)) == 0)
653 return;
654
655 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
656 return;
657
658 /* see comment above for the reason for this offset */
659 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
660 if (drm_WARN_ON(encoder->base.dev, len < 0))
661 return;
662
663 /* Insert the 'hole' (see big comment above) at position 3 */
664 memmove(&buffer[0], &buffer[1], 3);
665 buffer[3] = 0;
666 len++;
667
668 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
669}
670
671void intel_read_infoframe(struct intel_encoder *encoder,
672 const struct intel_crtc_state *crtc_state,
673 enum hdmi_infoframe_type type,
674 union hdmi_infoframe *frame)
675{
676 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
677 u8 buffer[VIDEO_DIP_DATA_SIZE];
678 int ret;
679
680 if ((crtc_state->infoframes.enable &
681 intel_hdmi_infoframe_enable(type)) == 0)
682 return;
683
684 dig_port->read_infoframe(encoder, crtc_state,
685 type, buffer, sizeof(buffer));
686
687 /* Fill the 'hole' (see big comment above) at position 3 */
688 memmove(&buffer[1], &buffer[0], 3);
689
690 /* see comment above for the reason for this offset */
691 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
692 if (ret) {
693 drm_dbg_kms(encoder->base.dev,
694 "Failed to unpack infoframe type 0x%02x\n", type);
695 return;
696 }
697
698 if (frame->any.type != type)
699 drm_dbg_kms(encoder->base.dev,
700 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
701 frame->any.type, type);
702}
703
704static bool
705intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
706 struct intel_crtc_state *crtc_state,
707 struct drm_connector_state *conn_state)
708{
709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
710 const struct drm_display_mode *adjusted_mode =
711 &crtc_state->hw.adjusted_mode;
712 struct drm_connector *connector = conn_state->connector;
713 int ret;
714
715 if (!crtc_state->has_infoframe)
716 return true;
717
718 crtc_state->infoframes.enable |=
719 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
720
721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
722 adjusted_mode);
723 if (ret)
724 return false;
725
726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
727 frame->colorspace = HDMI_COLORSPACE_YUV420;
728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
729 frame->colorspace = HDMI_COLORSPACE_YUV444;
730 else
731 frame->colorspace = HDMI_COLORSPACE_RGB;
732
733 drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
734
735 /* nonsense combination */
736 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
738
739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
740 drm_hdmi_avi_infoframe_quant_range(frame, connector,
741 adjusted_mode,
742 crtc_state->limited_color_range ?
743 HDMI_QUANTIZATION_RANGE_LIMITED :
744 HDMI_QUANTIZATION_RANGE_FULL);
745 } else {
746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
748 }
749
750 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
751
752 /* TODO: handle pixel repetition for YCBCR420 outputs */
753
754 ret = hdmi_avi_infoframe_check(frame);
755 if (drm_WARN_ON(encoder->base.dev, ret))
756 return false;
757
758 return true;
759}
760
761static bool
762intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
763 struct intel_crtc_state *crtc_state,
764 struct drm_connector_state *conn_state)
765{
766 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
767 int ret;
768
769 if (!crtc_state->has_infoframe)
770 return true;
771
772 crtc_state->infoframes.enable |=
773 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
774
775 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
776 if (drm_WARN_ON(encoder->base.dev, ret))
777 return false;
778
779 frame->sdi = HDMI_SPD_SDI_PC;
780
781 ret = hdmi_spd_infoframe_check(frame);
782 if (drm_WARN_ON(encoder->base.dev, ret))
783 return false;
784
785 return true;
786}
787
788static bool
789intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
790 struct intel_crtc_state *crtc_state,
791 struct drm_connector_state *conn_state)
792{
793 struct hdmi_vendor_infoframe *frame =
794 &crtc_state->infoframes.hdmi.vendor.hdmi;
795 const struct drm_display_info *info =
796 &conn_state->connector->display_info;
797 int ret;
798
799 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
800 return true;
801
802 crtc_state->infoframes.enable |=
803 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
804
805 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
806 conn_state->connector,
807 &crtc_state->hw.adjusted_mode);
808 if (drm_WARN_ON(encoder->base.dev, ret))
809 return false;
810
811 ret = hdmi_vendor_infoframe_check(frame);
812 if (drm_WARN_ON(encoder->base.dev, ret))
813 return false;
814
815 return true;
816}
817
818static bool
819intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
820 struct intel_crtc_state *crtc_state,
821 struct drm_connector_state *conn_state)
822{
823 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
825 int ret;
826
827 if (DISPLAY_VER(dev_priv) < 10)
828 return true;
829
830 if (!crtc_state->has_infoframe)
831 return true;
832
833 if (!conn_state->hdr_output_metadata)
834 return true;
835
836 crtc_state->infoframes.enable |=
837 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
838
839 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
840 if (ret < 0) {
841 drm_dbg_kms(&dev_priv->drm,
842 "couldn't set HDR metadata in infoframe\n");
843 return false;
844 }
845
846 ret = hdmi_drm_infoframe_check(frame);
847 if (drm_WARN_ON(&dev_priv->drm, ret))
848 return false;
849
850 return true;
851}
852
853static void g4x_set_infoframes(struct intel_encoder *encoder,
854 bool enable,
855 const struct intel_crtc_state *crtc_state,
856 const struct drm_connector_state *conn_state)
857{
858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
860 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
861 i915_reg_t reg = VIDEO_DIP_CTL;
862 u32 val = intel_de_read(dev_priv, reg);
863 u32 port = VIDEO_DIP_PORT(encoder->port);
864
865 assert_hdmi_port_disabled(intel_hdmi);
866
867 /* If the registers were not initialized yet, they might be zeroes,
868 * which means we're selecting the AVI DIP and we're setting its
869 * frequency to once. This seems to really confuse the HW and make
870 * things stop working (the register spec says the AVI always needs to
871 * be sent every VSync). So here we avoid writing to the register more
872 * than we need and also explicitly select the AVI DIP and explicitly
873 * set its frequency to every VSync. Avoiding to write it twice seems to
874 * be enough to solve the problem, but being defensive shouldn't hurt us
875 * either. */
876 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
877
878 if (!enable) {
879 if (!(val & VIDEO_DIP_ENABLE))
880 return;
881 if (port != (val & VIDEO_DIP_PORT_MASK)) {
882 drm_dbg_kms(&dev_priv->drm,
883 "video DIP still enabled on port %c\n",
884 (val & VIDEO_DIP_PORT_MASK) >> 29);
885 return;
886 }
887 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
888 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
889 intel_de_write(dev_priv, reg, val);
890 intel_de_posting_read(dev_priv, reg);
891 return;
892 }
893
894 if (port != (val & VIDEO_DIP_PORT_MASK)) {
895 if (val & VIDEO_DIP_ENABLE) {
896 drm_dbg_kms(&dev_priv->drm,
897 "video DIP already enabled on port %c\n",
898 (val & VIDEO_DIP_PORT_MASK) >> 29);
899 return;
900 }
901 val &= ~VIDEO_DIP_PORT_MASK;
902 val |= port;
903 }
904
905 val |= VIDEO_DIP_ENABLE;
906 val &= ~(VIDEO_DIP_ENABLE_AVI |
907 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
908
909 intel_de_write(dev_priv, reg, val);
910 intel_de_posting_read(dev_priv, reg);
911
912 intel_write_infoframe(encoder, crtc_state,
913 HDMI_INFOFRAME_TYPE_AVI,
914 &crtc_state->infoframes.avi);
915 intel_write_infoframe(encoder, crtc_state,
916 HDMI_INFOFRAME_TYPE_SPD,
917 &crtc_state->infoframes.spd);
918 intel_write_infoframe(encoder, crtc_state,
919 HDMI_INFOFRAME_TYPE_VENDOR,
920 &crtc_state->infoframes.hdmi);
921}
922
923/*
924 * Determine if default_phase=1 can be indicated in the GCP infoframe.
925 *
926 * From HDMI specification 1.4a:
927 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
928 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
929 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
930 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
931 * phase of 0
932 */
933static bool gcp_default_phase_possible(int pipe_bpp,
934 const struct drm_display_mode *mode)
935{
936 unsigned int pixels_per_group;
937
938 switch (pipe_bpp) {
939 case 30:
940 /* 4 pixels in 5 clocks */
941 pixels_per_group = 4;
942 break;
943 case 36:
944 /* 2 pixels in 3 clocks */
945 pixels_per_group = 2;
946 break;
947 case 48:
948 /* 1 pixel in 2 clocks */
949 pixels_per_group = 1;
950 break;
951 default:
952 /* phase information not relevant for 8bpc */
953 return false;
954 }
955
956 return mode->crtc_hdisplay % pixels_per_group == 0 &&
957 mode->crtc_htotal % pixels_per_group == 0 &&
958 mode->crtc_hblank_start % pixels_per_group == 0 &&
959 mode->crtc_hblank_end % pixels_per_group == 0 &&
960 mode->crtc_hsync_start % pixels_per_group == 0 &&
961 mode->crtc_hsync_end % pixels_per_group == 0 &&
962 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
963 mode->crtc_htotal/2 % pixels_per_group == 0);
964}
965
966static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
967 const struct intel_crtc_state *crtc_state,
968 const struct drm_connector_state *conn_state)
969{
970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
972 i915_reg_t reg;
973
974 if ((crtc_state->infoframes.enable &
975 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
976 return false;
977
978 if (HAS_DDI(dev_priv))
979 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
980 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
981 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
982 else if (HAS_PCH_SPLIT(dev_priv))
983 reg = TVIDEO_DIP_GCP(crtc->pipe);
984 else
985 return false;
986
987 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
988
989 return true;
990}
991
992void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
993 struct intel_crtc_state *crtc_state)
994{
995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
996 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
997 i915_reg_t reg;
998
999 if ((crtc_state->infoframes.enable &
1000 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1001 return;
1002
1003 if (HAS_DDI(dev_priv))
1004 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1005 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1006 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1007 else if (HAS_PCH_SPLIT(dev_priv))
1008 reg = TVIDEO_DIP_GCP(crtc->pipe);
1009 else
1010 return;
1011
1012 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1013}
1014
1015static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1016 struct intel_crtc_state *crtc_state,
1017 struct drm_connector_state *conn_state)
1018{
1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1020
1021 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1022 return;
1023
1024 crtc_state->infoframes.enable |=
1025 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1026
1027 /* Indicate color indication for deep color mode */
1028 if (crtc_state->pipe_bpp > 24)
1029 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1030
1031 /* Enable default_phase whenever the display mode is suitably aligned */
1032 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1033 &crtc_state->hw.adjusted_mode))
1034 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1035}
1036
1037static void ibx_set_infoframes(struct intel_encoder *encoder,
1038 bool enable,
1039 const struct intel_crtc_state *crtc_state,
1040 const struct drm_connector_state *conn_state)
1041{
1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1045 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1046 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1047 u32 val = intel_de_read(dev_priv, reg);
1048 u32 port = VIDEO_DIP_PORT(encoder->port);
1049
1050 assert_hdmi_port_disabled(intel_hdmi);
1051
1052 /* See the big comment in g4x_set_infoframes() */
1053 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1054
1055 if (!enable) {
1056 if (!(val & VIDEO_DIP_ENABLE))
1057 return;
1058 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1059 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1060 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1061 intel_de_write(dev_priv, reg, val);
1062 intel_de_posting_read(dev_priv, reg);
1063 return;
1064 }
1065
1066 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1067 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1068 "DIP already enabled on port %c\n",
1069 (val & VIDEO_DIP_PORT_MASK) >> 29);
1070 val &= ~VIDEO_DIP_PORT_MASK;
1071 val |= port;
1072 }
1073
1074 val |= VIDEO_DIP_ENABLE;
1075 val &= ~(VIDEO_DIP_ENABLE_AVI |
1076 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1077 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1078
1079 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1080 val |= VIDEO_DIP_ENABLE_GCP;
1081
1082 intel_de_write(dev_priv, reg, val);
1083 intel_de_posting_read(dev_priv, reg);
1084
1085 intel_write_infoframe(encoder, crtc_state,
1086 HDMI_INFOFRAME_TYPE_AVI,
1087 &crtc_state->infoframes.avi);
1088 intel_write_infoframe(encoder, crtc_state,
1089 HDMI_INFOFRAME_TYPE_SPD,
1090 &crtc_state->infoframes.spd);
1091 intel_write_infoframe(encoder, crtc_state,
1092 HDMI_INFOFRAME_TYPE_VENDOR,
1093 &crtc_state->infoframes.hdmi);
1094}
1095
1096static void cpt_set_infoframes(struct intel_encoder *encoder,
1097 bool enable,
1098 const struct intel_crtc_state *crtc_state,
1099 const struct drm_connector_state *conn_state)
1100{
1101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1103 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1104 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1105 u32 val = intel_de_read(dev_priv, reg);
1106
1107 assert_hdmi_port_disabled(intel_hdmi);
1108
1109 /* See the big comment in g4x_set_infoframes() */
1110 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1111
1112 if (!enable) {
1113 if (!(val & VIDEO_DIP_ENABLE))
1114 return;
1115 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1116 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1117 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1118 intel_de_write(dev_priv, reg, val);
1119 intel_de_posting_read(dev_priv, reg);
1120 return;
1121 }
1122
1123 /* Set both together, unset both together: see the spec. */
1124 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1125 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1126 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1127
1128 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1129 val |= VIDEO_DIP_ENABLE_GCP;
1130
1131 intel_de_write(dev_priv, reg, val);
1132 intel_de_posting_read(dev_priv, reg);
1133
1134 intel_write_infoframe(encoder, crtc_state,
1135 HDMI_INFOFRAME_TYPE_AVI,
1136 &crtc_state->infoframes.avi);
1137 intel_write_infoframe(encoder, crtc_state,
1138 HDMI_INFOFRAME_TYPE_SPD,
1139 &crtc_state->infoframes.spd);
1140 intel_write_infoframe(encoder, crtc_state,
1141 HDMI_INFOFRAME_TYPE_VENDOR,
1142 &crtc_state->infoframes.hdmi);
1143}
1144
1145static void vlv_set_infoframes(struct intel_encoder *encoder,
1146 bool enable,
1147 const struct intel_crtc_state *crtc_state,
1148 const struct drm_connector_state *conn_state)
1149{
1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1152 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1153 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1154 u32 val = intel_de_read(dev_priv, reg);
1155 u32 port = VIDEO_DIP_PORT(encoder->port);
1156
1157 assert_hdmi_port_disabled(intel_hdmi);
1158
1159 /* See the big comment in g4x_set_infoframes() */
1160 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1161
1162 if (!enable) {
1163 if (!(val & VIDEO_DIP_ENABLE))
1164 return;
1165 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1166 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1167 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1168 intel_de_write(dev_priv, reg, val);
1169 intel_de_posting_read(dev_priv, reg);
1170 return;
1171 }
1172
1173 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1174 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1175 "DIP already enabled on port %c\n",
1176 (val & VIDEO_DIP_PORT_MASK) >> 29);
1177 val &= ~VIDEO_DIP_PORT_MASK;
1178 val |= port;
1179 }
1180
1181 val |= VIDEO_DIP_ENABLE;
1182 val &= ~(VIDEO_DIP_ENABLE_AVI |
1183 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1184 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1185
1186 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1187 val |= VIDEO_DIP_ENABLE_GCP;
1188
1189 intel_de_write(dev_priv, reg, val);
1190 intel_de_posting_read(dev_priv, reg);
1191
1192 intel_write_infoframe(encoder, crtc_state,
1193 HDMI_INFOFRAME_TYPE_AVI,
1194 &crtc_state->infoframes.avi);
1195 intel_write_infoframe(encoder, crtc_state,
1196 HDMI_INFOFRAME_TYPE_SPD,
1197 &crtc_state->infoframes.spd);
1198 intel_write_infoframe(encoder, crtc_state,
1199 HDMI_INFOFRAME_TYPE_VENDOR,
1200 &crtc_state->infoframes.hdmi);
1201}
1202
1203static void hsw_set_infoframes(struct intel_encoder *encoder,
1204 bool enable,
1205 const struct intel_crtc_state *crtc_state,
1206 const struct drm_connector_state *conn_state)
1207{
1208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1209 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1210 u32 val = intel_de_read(dev_priv, reg);
1211
1212 assert_hdmi_transcoder_func_disabled(dev_priv,
1213 crtc_state->cpu_transcoder);
1214
1215 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1216 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1217 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1218 VIDEO_DIP_ENABLE_DRM_GLK);
1219
1220 if (!enable) {
1221 intel_de_write(dev_priv, reg, val);
1222 intel_de_posting_read(dev_priv, reg);
1223 return;
1224 }
1225
1226 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1227 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1228
1229 intel_de_write(dev_priv, reg, val);
1230 intel_de_posting_read(dev_priv, reg);
1231
1232 intel_write_infoframe(encoder, crtc_state,
1233 HDMI_INFOFRAME_TYPE_AVI,
1234 &crtc_state->infoframes.avi);
1235 intel_write_infoframe(encoder, crtc_state,
1236 HDMI_INFOFRAME_TYPE_SPD,
1237 &crtc_state->infoframes.spd);
1238 intel_write_infoframe(encoder, crtc_state,
1239 HDMI_INFOFRAME_TYPE_VENDOR,
1240 &crtc_state->infoframes.hdmi);
1241 intel_write_infoframe(encoder, crtc_state,
1242 HDMI_INFOFRAME_TYPE_DRM,
1243 &crtc_state->infoframes.drm);
1244}
1245
1246void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1247{
1248 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1249 struct i2c_adapter *adapter =
1250 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1251
1252 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1253 return;
1254
1255 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1256 enable ? "Enabling" : "Disabling");
1257
1258 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1259}
1260
1261static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1262 unsigned int offset, void *buffer, size_t size)
1263{
1264 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1265 struct intel_hdmi *hdmi = &dig_port->hdmi;
1266 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1267 hdmi->ddc_bus);
1268 int ret;
1269 u8 start = offset & 0xff;
1270 struct i2c_msg msgs[] = {
1271 {
1272 .addr = DRM_HDCP_DDC_ADDR,
1273 .flags = 0,
1274 .len = 1,
1275 .buf = &start,
1276 },
1277 {
1278 .addr = DRM_HDCP_DDC_ADDR,
1279 .flags = I2C_M_RD,
1280 .len = size,
1281 .buf = buffer
1282 }
1283 };
1284 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1285 if (ret == ARRAY_SIZE(msgs))
1286 return 0;
1287 return ret >= 0 ? -EIO : ret;
1288}
1289
1290static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1291 unsigned int offset, void *buffer, size_t size)
1292{
1293 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1294 struct intel_hdmi *hdmi = &dig_port->hdmi;
1295 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1296 hdmi->ddc_bus);
1297 int ret;
1298 u8 *write_buf;
1299 struct i2c_msg msg;
1300
1301 write_buf = kzalloc(size + 1, GFP_KERNEL);
1302 if (!write_buf)
1303 return -ENOMEM;
1304
1305 write_buf[0] = offset & 0xff;
1306 memcpy(&write_buf[1], buffer, size);
1307
1308 msg.addr = DRM_HDCP_DDC_ADDR;
1309 msg.flags = 0,
1310 msg.len = size + 1,
1311 msg.buf = write_buf;
1312
1313 ret = i2c_transfer(adapter, &msg, 1);
1314 if (ret == 1)
1315 ret = 0;
1316 else if (ret >= 0)
1317 ret = -EIO;
1318
1319 kfree(write_buf);
1320 return ret;
1321}
1322
1323static
1324int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1325 u8 *an)
1326{
1327 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1328 struct intel_hdmi *hdmi = &dig_port->hdmi;
1329 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1330 hdmi->ddc_bus);
1331 int ret;
1332
1333 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1334 DRM_HDCP_AN_LEN);
1335 if (ret) {
1336 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1337 ret);
1338 return ret;
1339 }
1340
1341 ret = intel_gmbus_output_aksv(adapter);
1342 if (ret < 0) {
1343 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1344 return ret;
1345 }
1346 return 0;
1347}
1348
1349static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1350 u8 *bksv)
1351{
1352 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1353
1354 int ret;
1355 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1356 DRM_HDCP_KSV_LEN);
1357 if (ret)
1358 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1359 ret);
1360 return ret;
1361}
1362
1363static
1364int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1365 u8 *bstatus)
1366{
1367 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1368
1369 int ret;
1370 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1371 bstatus, DRM_HDCP_BSTATUS_LEN);
1372 if (ret)
1373 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1374 ret);
1375 return ret;
1376}
1377
1378static
1379int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1380 bool *repeater_present)
1381{
1382 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1383 int ret;
1384 u8 val;
1385
1386 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1387 if (ret) {
1388 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1389 ret);
1390 return ret;
1391 }
1392 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1393 return 0;
1394}
1395
1396static
1397int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1398 u8 *ri_prime)
1399{
1400 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1401
1402 int ret;
1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1404 ri_prime, DRM_HDCP_RI_LEN);
1405 if (ret)
1406 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1407 ret);
1408 return ret;
1409}
1410
1411static
1412int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1413 bool *ksv_ready)
1414{
1415 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1416 int ret;
1417 u8 val;
1418
1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1420 if (ret) {
1421 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1422 ret);
1423 return ret;
1424 }
1425 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1426 return 0;
1427}
1428
1429static
1430int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1431 int num_downstream, u8 *ksv_fifo)
1432{
1433 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1434 int ret;
1435 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1436 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1437 if (ret) {
1438 drm_dbg_kms(&i915->drm,
1439 "Read ksv fifo over DDC failed (%d)\n", ret);
1440 return ret;
1441 }
1442 return 0;
1443}
1444
1445static
1446int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1447 int i, u32 *part)
1448{
1449 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1450 int ret;
1451
1452 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1453 return -EINVAL;
1454
1455 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1456 part, DRM_HDCP_V_PRIME_PART_LEN);
1457 if (ret)
1458 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1459 i, ret);
1460 return ret;
1461}
1462
1463static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1464 enum transcoder cpu_transcoder)
1465{
1466 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1467 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1468 struct drm_crtc *crtc = connector->base.state->crtc;
1469 struct intel_crtc *intel_crtc = container_of(crtc,
1470 struct intel_crtc, base);
1471 u32 scanline;
1472 int ret;
1473
1474 for (;;) {
1475 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe));
1476 if (scanline > 100 && scanline < 200)
1477 break;
1478 usleep_range(25, 50);
1479 }
1480
1481 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1482 false, TRANS_DDI_HDCP_SIGNALLING);
1483 if (ret) {
1484 drm_err(&dev_priv->drm,
1485 "Disable HDCP signalling failed (%d)\n", ret);
1486 return ret;
1487 }
1488
1489 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1490 true, TRANS_DDI_HDCP_SIGNALLING);
1491 if (ret) {
1492 drm_err(&dev_priv->drm,
1493 "Enable HDCP signalling failed (%d)\n", ret);
1494 return ret;
1495 }
1496
1497 return 0;
1498}
1499
1500static
1501int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1502 enum transcoder cpu_transcoder,
1503 bool enable)
1504{
1505 struct intel_hdmi *hdmi = &dig_port->hdmi;
1506 struct intel_connector *connector = hdmi->attached_connector;
1507 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1508 int ret;
1509
1510 if (!enable)
1511 usleep_range(6, 60); /* Bspec says >= 6us */
1512
1513 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1514 cpu_transcoder, enable,
1515 TRANS_DDI_HDCP_SIGNALLING);
1516 if (ret) {
1517 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1518 enable ? "Enable" : "Disable", ret);
1519 return ret;
1520 }
1521
1522 /*
1523 * WA: To fix incorrect positioning of the window of
1524 * opportunity and enc_en signalling in KABYLAKE.
1525 */
1526 if (IS_KABYLAKE(dev_priv) && enable)
1527 return kbl_repositioning_enc_en_signal(connector,
1528 cpu_transcoder);
1529
1530 return 0;
1531}
1532
1533static
1534bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1535 struct intel_connector *connector)
1536{
1537 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1538 enum port port = dig_port->base.port;
1539 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1540 int ret;
1541 union {
1542 u32 reg;
1543 u8 shim[DRM_HDCP_RI_LEN];
1544 } ri;
1545
1546 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1547 if (ret)
1548 return false;
1549
1550 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1551
1552 /* Wait for Ri prime match */
1553 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1554 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1555 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1556 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1557 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1558 port)));
1559 return false;
1560 }
1561 return true;
1562}
1563
1564static
1565bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1566 struct intel_connector *connector)
1567{
1568 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1569 int retry;
1570
1571 for (retry = 0; retry < 3; retry++)
1572 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1573 return true;
1574
1575 drm_err(&i915->drm, "Link check failed\n");
1576 return false;
1577}
1578
1579struct hdcp2_hdmi_msg_timeout {
1580 u8 msg_id;
1581 u16 timeout;
1582};
1583
1584static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1585 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1586 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1587 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1588 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1589 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1590};
1591
1592static
1593int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1594 u8 *rx_status)
1595{
1596 return intel_hdmi_hdcp_read(dig_port,
1597 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1598 rx_status,
1599 HDCP_2_2_HDMI_RXSTATUS_LEN);
1600}
1601
1602static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1603{
1604 int i;
1605
1606 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1607 if (is_paired)
1608 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1609 else
1610 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1611 }
1612
1613 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1614 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1615 return hdcp2_msg_timeout[i].timeout;
1616 }
1617
1618 return -EINVAL;
1619}
1620
1621static int
1622hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1623 u8 msg_id, bool *msg_ready,
1624 ssize_t *msg_sz)
1625{
1626 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1627 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1628 int ret;
1629
1630 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1631 if (ret < 0) {
1632 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1633 ret);
1634 return ret;
1635 }
1636
1637 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1638 rx_status[0]);
1639
1640 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1641 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1642 *msg_sz);
1643 else
1644 *msg_ready = *msg_sz;
1645
1646 return 0;
1647}
1648
1649static ssize_t
1650intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1651 u8 msg_id, bool paired)
1652{
1653 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1654 bool msg_ready = false;
1655 int timeout, ret;
1656 ssize_t msg_sz = 0;
1657
1658 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1659 if (timeout < 0)
1660 return timeout;
1661
1662 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1663 msg_id, &msg_ready,
1664 &msg_sz),
1665 !ret && msg_ready && msg_sz, timeout * 1000,
1666 1000, 5 * 1000);
1667 if (ret)
1668 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1669 msg_id, ret, timeout);
1670
1671 return ret ? ret : msg_sz;
1672}
1673
1674static
1675int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1676 void *buf, size_t size)
1677{
1678 unsigned int offset;
1679
1680 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1681 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1682}
1683
1684static
1685int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1686 u8 msg_id, void *buf, size_t size)
1687{
1688 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1689 struct intel_hdmi *hdmi = &dig_port->hdmi;
1690 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1691 unsigned int offset;
1692 ssize_t ret;
1693
1694 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1695 hdcp->is_paired);
1696 if (ret < 0)
1697 return ret;
1698
1699 /*
1700 * Available msg size should be equal to or lesser than the
1701 * available buffer.
1702 */
1703 if (ret > size) {
1704 drm_dbg_kms(&i915->drm,
1705 "msg_sz(%zd) is more than exp size(%zu)\n",
1706 ret, size);
1707 return -1;
1708 }
1709
1710 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1711 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1712 if (ret)
1713 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1714 msg_id, ret);
1715
1716 return ret;
1717}
1718
1719static
1720int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1721 struct intel_connector *connector)
1722{
1723 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1724 int ret;
1725
1726 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1727 if (ret)
1728 return ret;
1729
1730 /*
1731 * Re-auth request and Link Integrity Failures are represented by
1732 * same bit. i.e reauth_req.
1733 */
1734 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1735 ret = HDCP_REAUTH_REQUEST;
1736 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1737 ret = HDCP_TOPOLOGY_CHANGE;
1738
1739 return ret;
1740}
1741
1742static
1743int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1744 bool *capable)
1745{
1746 u8 hdcp2_version;
1747 int ret;
1748
1749 *capable = false;
1750 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1751 &hdcp2_version, sizeof(hdcp2_version));
1752 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1753 *capable = true;
1754
1755 return ret;
1756}
1757
1758static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1759 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1760 .read_bksv = intel_hdmi_hdcp_read_bksv,
1761 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1762 .repeater_present = intel_hdmi_hdcp_repeater_present,
1763 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1764 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1765 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1766 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1767 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1768 .check_link = intel_hdmi_hdcp_check_link,
1769 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1770 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1771 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1772 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1773 .protocol = HDCP_PROTOCOL_HDMI,
1774};
1775
1776static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1777{
1778 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1779 int max_tmds_clock, vbt_max_tmds_clock;
1780
1781 if (DISPLAY_VER(dev_priv) >= 10)
1782 max_tmds_clock = 594000;
1783 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1784 max_tmds_clock = 300000;
1785 else if (DISPLAY_VER(dev_priv) >= 5)
1786 max_tmds_clock = 225000;
1787 else
1788 max_tmds_clock = 165000;
1789
1790 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1791 if (vbt_max_tmds_clock)
1792 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1793
1794 return max_tmds_clock;
1795}
1796
1797static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1798 const struct drm_connector_state *conn_state)
1799{
1800 return hdmi->has_hdmi_sink &&
1801 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1802}
1803
1804static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1805 bool respect_downstream_limits,
1806 bool has_hdmi_sink)
1807{
1808 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1809 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1810
1811 if (respect_downstream_limits) {
1812 struct intel_connector *connector = hdmi->attached_connector;
1813 const struct drm_display_info *info = &connector->base.display_info;
1814
1815 if (hdmi->dp_dual_mode.max_tmds_clock)
1816 max_tmds_clock = min(max_tmds_clock,
1817 hdmi->dp_dual_mode.max_tmds_clock);
1818
1819 if (info->max_tmds_clock)
1820 max_tmds_clock = min(max_tmds_clock,
1821 info->max_tmds_clock);
1822 else if (!has_hdmi_sink)
1823 max_tmds_clock = min(max_tmds_clock, 165000);
1824 }
1825
1826 return max_tmds_clock;
1827}
1828
1829static enum drm_mode_status
1830hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1831 int clock, bool respect_downstream_limits,
1832 bool has_hdmi_sink)
1833{
1834 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1835
1836 if (clock < 25000)
1837 return MODE_CLOCK_LOW;
1838 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1839 has_hdmi_sink))
1840 return MODE_CLOCK_HIGH;
1841
1842 /* GLK DPLL can't generate 446-480 MHz */
1843 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1844 return MODE_CLOCK_RANGE;
1845
1846 /* BXT/GLK DPLL can't generate 223-240 MHz */
1847 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1848 clock > 223333 && clock < 240000)
1849 return MODE_CLOCK_RANGE;
1850
1851 /* CHV DPLL can't generate 216-240 MHz */
1852 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1853 return MODE_CLOCK_RANGE;
1854
1855 return MODE_OK;
1856}
1857
1858static int intel_hdmi_port_clock(int clock, int bpc)
1859{
1860 /*
1861 * Need to adjust the port link by:
1862 * 1.5x for 12bpc
1863 * 1.25x for 10bpc
1864 */
1865 return clock * bpc / 8;
1866}
1867
1868static bool intel_hdmi_bpc_possible(struct drm_connector *connector,
1869 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1870{
1871 struct drm_i915_private *i915 = to_i915(connector->dev);
1872 const struct drm_display_info *info = &connector->display_info;
1873 const struct drm_hdmi_info *hdmi = &info->hdmi;
1874
1875 switch (bpc) {
1876 case 12:
1877 if (HAS_GMCH(i915))
1878 return false;
1879
1880 if (!has_hdmi_sink)
1881 return false;
1882
1883 if (ycbcr420_output)
1884 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1885 else
1886 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36;
1887 case 10:
1888 if (DISPLAY_VER(i915) < 11)
1889 return false;
1890
1891 if (!has_hdmi_sink)
1892 return false;
1893
1894 if (ycbcr420_output)
1895 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1896 else
1897 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30;
1898 case 8:
1899 return true;
1900 default:
1901 MISSING_CASE(bpc);
1902 return false;
1903 }
1904}
1905
1906static enum drm_mode_status
1907intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1908 bool has_hdmi_sink, bool ycbcr420_output)
1909{
1910 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1911 enum drm_mode_status status;
1912
1913 if (ycbcr420_output)
1914 clock /= 2;
1915
1916 /* check if we can do 8bpc */
1917 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
1918 true, has_hdmi_sink);
1919
1920 /* if we can't do 8bpc we may still be able to do 12bpc */
1921 if (status != MODE_OK &&
1922 intel_hdmi_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
1923 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
1924 true, has_hdmi_sink);
1925
1926 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1927 if (status != MODE_OK &&
1928 intel_hdmi_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
1929 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
1930 true, has_hdmi_sink);
1931
1932 return status;
1933}
1934
1935static enum drm_mode_status
1936intel_hdmi_mode_valid(struct drm_connector *connector,
1937 struct drm_display_mode *mode)
1938{
1939 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1940 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1941 struct drm_i915_private *dev_priv = to_i915(dev);
1942 enum drm_mode_status status;
1943 int clock = mode->clock;
1944 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1945 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1946 bool ycbcr_420_only;
1947
1948 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1949 return MODE_NO_DBLESCAN;
1950
1951 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1952 clock *= 2;
1953
1954 if (clock > max_dotclk)
1955 return MODE_CLOCK_HIGH;
1956
1957 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1958 if (!has_hdmi_sink)
1959 return MODE_CLOCK_LOW;
1960 clock *= 2;
1961 }
1962
1963 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
1964
1965 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
1966 if (status != MODE_OK) {
1967 if (ycbcr_420_only ||
1968 !connector->ycbcr_420_allowed ||
1969 !drm_mode_is_420_also(&connector->display_info, mode))
1970 return status;
1971
1972 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
1973 if (status != MODE_OK)
1974 return status;
1975 }
1976
1977 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
1978}
1979
1980bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1981 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1982{
1983 struct drm_atomic_state *state = crtc_state->uapi.state;
1984 struct drm_connector_state *connector_state;
1985 struct drm_connector *connector;
1986 int i;
1987
1988 if (crtc_state->pipe_bpp < bpc * 3)
1989 return false;
1990
1991 for_each_new_connector_in_state(state, connector, connector_state, i) {
1992 if (connector_state->crtc != crtc_state->uapi.crtc)
1993 continue;
1994
1995 if (!intel_hdmi_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1996 return false;
1997 }
1998
1999 return true;
2000}
2001
2002static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2003 int bpc)
2004{
2005 struct drm_i915_private *dev_priv =
2006 to_i915(crtc_state->uapi.crtc->dev);
2007 const struct drm_display_mode *adjusted_mode =
2008 &crtc_state->hw.adjusted_mode;
2009
2010 /*
2011 * HDMI deep color affects the clocks, so it's only possible
2012 * when not cloning with other encoder types.
2013 */
2014 if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2015 return false;
2016
2017 /* Display Wa_1405510057:icl,ehl */
2018 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2019 bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2020 (adjusted_mode->crtc_hblank_end -
2021 adjusted_mode->crtc_hblank_start) % 8 == 2)
2022 return false;
2023
2024 return intel_hdmi_deep_color_possible(crtc_state, bpc,
2025 crtc_state->has_hdmi_sink,
2026 crtc_state->output_format ==
2027 INTEL_OUTPUT_FORMAT_YCBCR420);
2028}
2029
2030static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2031 struct intel_crtc_state *crtc_state,
2032 int clock)
2033{
2034 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2035 int bpc;
2036
2037 for (bpc = 12; bpc >= 10; bpc -= 2) {
2038 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2039 hdmi_port_clock_valid(intel_hdmi,
2040 intel_hdmi_port_clock(clock, bpc),
2041 true, crtc_state->has_hdmi_sink) == MODE_OK)
2042 return bpc;
2043 }
2044
2045 return 8;
2046}
2047
2048static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2049 struct intel_crtc_state *crtc_state)
2050{
2051 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2052 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2053 const struct drm_display_mode *adjusted_mode =
2054 &crtc_state->hw.adjusted_mode;
2055 int bpc, clock = adjusted_mode->crtc_clock;
2056
2057 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2058 clock *= 2;
2059
2060 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2061 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2062 clock /= 2;
2063
2064 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2065
2066 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2067
2068 /*
2069 * pipe_bpp could already be below 8bpc due to
2070 * FDI bandwidth constraints. We shouldn't bump it
2071 * back up to 8bpc in that case.
2072 */
2073 if (crtc_state->pipe_bpp > bpc * 3)
2074 crtc_state->pipe_bpp = bpc * 3;
2075
2076 drm_dbg_kms(&i915->drm,
2077 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2078 bpc, crtc_state->pipe_bpp);
2079
2080 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2081 false, crtc_state->has_hdmi_sink) != MODE_OK) {
2082 drm_dbg_kms(&i915->drm,
2083 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2084 crtc_state->port_clock);
2085 return -EINVAL;
2086 }
2087
2088 return 0;
2089}
2090
2091bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2092 const struct drm_connector_state *conn_state)
2093{
2094 const struct intel_digital_connector_state *intel_conn_state =
2095 to_intel_digital_connector_state(conn_state);
2096 const struct drm_display_mode *adjusted_mode =
2097 &crtc_state->hw.adjusted_mode;
2098
2099 /*
2100 * Our YCbCr output is always limited range.
2101 * crtc_state->limited_color_range only applies to RGB,
2102 * and it must never be set for YCbCr or we risk setting
2103 * some conflicting bits in PIPECONF which will mess up
2104 * the colors on the monitor.
2105 */
2106 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2107 return false;
2108
2109 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2110 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2111 return crtc_state->has_hdmi_sink &&
2112 drm_default_rgb_quant_range(adjusted_mode) ==
2113 HDMI_QUANTIZATION_RANGE_LIMITED;
2114 } else {
2115 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2116 }
2117}
2118
2119static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2120 const struct intel_crtc_state *crtc_state,
2121 const struct drm_connector_state *conn_state)
2122{
2123 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2124 const struct intel_digital_connector_state *intel_conn_state =
2125 to_intel_digital_connector_state(conn_state);
2126
2127 if (!crtc_state->has_hdmi_sink)
2128 return false;
2129
2130 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2131 return intel_hdmi->has_audio;
2132 else
2133 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2134}
2135
2136static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2137 struct intel_crtc_state *crtc_state,
2138 const struct drm_connector_state *conn_state)
2139{
2140 struct drm_connector *connector = conn_state->connector;
2141 struct drm_i915_private *i915 = to_i915(connector->dev);
2142 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2143 int ret;
2144 bool ycbcr_420_only;
2145
2146 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, adjusted_mode);
2147 if (connector->ycbcr_420_allowed && ycbcr_420_only) {
2148 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2149 } else {
2150 if (!connector->ycbcr_420_allowed && ycbcr_420_only)
2151 drm_dbg_kms(&i915->drm,
2152 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2153 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2154 }
2155
2156 ret = intel_hdmi_compute_clock(encoder, crtc_state);
2157 if (ret) {
2158 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
2159 connector->ycbcr_420_allowed &&
2160 drm_mode_is_420_also(&connector->display_info, adjusted_mode)) {
2161 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2162 ret = intel_hdmi_compute_clock(encoder, crtc_state);
2163 }
2164 }
2165
2166 return ret;
2167}
2168
2169int intel_hdmi_compute_config(struct intel_encoder *encoder,
2170 struct intel_crtc_state *pipe_config,
2171 struct drm_connector_state *conn_state)
2172{
2173 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2175 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2176 struct drm_connector *connector = conn_state->connector;
2177 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2178 int ret;
2179
2180 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2181 return -EINVAL;
2182
2183 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2184 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2185 conn_state);
2186
2187 if (pipe_config->has_hdmi_sink)
2188 pipe_config->has_infoframe = true;
2189
2190 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2191 pipe_config->pixel_multiplier = 2;
2192
2193 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2194 pipe_config->has_pch_encoder = true;
2195
2196 pipe_config->has_audio =
2197 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2198
2199 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state);
2200 if (ret)
2201 return ret;
2202
2203 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2204 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2205 if (ret)
2206 return ret;
2207 }
2208
2209 pipe_config->limited_color_range =
2210 intel_hdmi_limited_color_range(pipe_config, conn_state);
2211
2212 if (conn_state->picture_aspect_ratio)
2213 adjusted_mode->picture_aspect_ratio =
2214 conn_state->picture_aspect_ratio;
2215
2216 pipe_config->lane_count = 4;
2217
2218 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2219 if (scdc->scrambling.low_rates)
2220 pipe_config->hdmi_scrambling = true;
2221
2222 if (pipe_config->port_clock > 340000) {
2223 pipe_config->hdmi_scrambling = true;
2224 pipe_config->hdmi_high_tmds_clock_ratio = true;
2225 }
2226 }
2227
2228 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2229 conn_state);
2230
2231 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2232 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2233 return -EINVAL;
2234 }
2235
2236 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2237 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2238 return -EINVAL;
2239 }
2240
2241 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2242 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2243 return -EINVAL;
2244 }
2245
2246 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2247 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2248 return -EINVAL;
2249 }
2250
2251 return 0;
2252}
2253
2254static void
2255intel_hdmi_unset_edid(struct drm_connector *connector)
2256{
2257 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2258
2259 intel_hdmi->has_hdmi_sink = false;
2260 intel_hdmi->has_audio = false;
2261
2262 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2263 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2264
2265 kfree(to_intel_connector(connector)->detect_edid);
2266 to_intel_connector(connector)->detect_edid = NULL;
2267}
2268
2269static void
2270intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2271{
2272 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2273 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2274 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2275 struct i2c_adapter *adapter =
2276 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2277 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2278
2279 /*
2280 * Type 1 DVI adaptors are not required to implement any
2281 * registers, so we can't always detect their presence.
2282 * Ideally we should be able to check the state of the
2283 * CONFIG1 pin, but no such luck on our hardware.
2284 *
2285 * The only method left to us is to check the VBT to see
2286 * if the port is a dual mode capable DP port. But let's
2287 * only do that when we sucesfully read the EDID, to avoid
2288 * confusing log messages about DP dual mode adaptors when
2289 * there's nothing connected to the port.
2290 */
2291 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2292 /* An overridden EDID imply that we want this port for testing.
2293 * Make sure not to set limits for that port.
2294 */
2295 if (has_edid && !connector->override_edid &&
2296 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2297 drm_dbg_kms(&dev_priv->drm,
2298 "Assuming DP dual mode adaptor presence based on VBT\n");
2299 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2300 } else {
2301 type = DRM_DP_DUAL_MODE_NONE;
2302 }
2303 }
2304
2305 if (type == DRM_DP_DUAL_MODE_NONE)
2306 return;
2307
2308 hdmi->dp_dual_mode.type = type;
2309 hdmi->dp_dual_mode.max_tmds_clock =
2310 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2311
2312 drm_dbg_kms(&dev_priv->drm,
2313 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2314 drm_dp_get_dual_mode_type_name(type),
2315 hdmi->dp_dual_mode.max_tmds_clock);
2316}
2317
2318static bool
2319intel_hdmi_set_edid(struct drm_connector *connector)
2320{
2321 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2322 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2323 intel_wakeref_t wakeref;
2324 struct edid *edid;
2325 bool connected = false;
2326 struct i2c_adapter *i2c;
2327
2328 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2329
2330 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2331
2332 edid = drm_get_edid(connector, i2c);
2333
2334 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2335 drm_dbg_kms(&dev_priv->drm,
2336 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2337 intel_gmbus_force_bit(i2c, true);
2338 edid = drm_get_edid(connector, i2c);
2339 intel_gmbus_force_bit(i2c, false);
2340 }
2341
2342 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2343
2344 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2345
2346 to_intel_connector(connector)->detect_edid = edid;
2347 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2348 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2349 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2350
2351 connected = true;
2352 }
2353
2354 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2355
2356 return connected;
2357}
2358
2359static enum drm_connector_status
2360intel_hdmi_detect(struct drm_connector *connector, bool force)
2361{
2362 enum drm_connector_status status = connector_status_disconnected;
2363 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2364 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2365 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2366 intel_wakeref_t wakeref;
2367
2368 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2369 connector->base.id, connector->name);
2370
2371 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2372 return connector_status_disconnected;
2373
2374 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2375
2376 if (DISPLAY_VER(dev_priv) >= 11 &&
2377 !intel_digital_port_connected(encoder))
2378 goto out;
2379
2380 intel_hdmi_unset_edid(connector);
2381
2382 if (intel_hdmi_set_edid(connector))
2383 status = connector_status_connected;
2384
2385out:
2386 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2387
2388 if (status != connector_status_connected)
2389 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2390
2391 /*
2392 * Make sure the refs for power wells enabled during detect are
2393 * dropped to avoid a new detect cycle triggered by HPD polling.
2394 */
2395 intel_display_power_flush_work(dev_priv);
2396
2397 return status;
2398}
2399
2400static void
2401intel_hdmi_force(struct drm_connector *connector)
2402{
2403 struct drm_i915_private *i915 = to_i915(connector->dev);
2404
2405 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2406 connector->base.id, connector->name);
2407
2408 intel_hdmi_unset_edid(connector);
2409
2410 if (connector->status != connector_status_connected)
2411 return;
2412
2413 intel_hdmi_set_edid(connector);
2414}
2415
2416static int intel_hdmi_get_modes(struct drm_connector *connector)
2417{
2418 struct edid *edid;
2419
2420 edid = to_intel_connector(connector)->detect_edid;
2421 if (edid == NULL)
2422 return 0;
2423
2424 return intel_connector_update_modes(connector, edid);
2425}
2426
2427static struct i2c_adapter *
2428intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2429{
2430 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2431 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2432
2433 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2434}
2435
2436static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2437{
2438 struct drm_i915_private *i915 = to_i915(connector->dev);
2439 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2440 struct kobject *i2c_kobj = &adapter->dev.kobj;
2441 struct kobject *connector_kobj = &connector->kdev->kobj;
2442 int ret;
2443
2444 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2445 if (ret)
2446 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2447}
2448
2449static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2450{
2451 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2452 struct kobject *i2c_kobj = &adapter->dev.kobj;
2453 struct kobject *connector_kobj = &connector->kdev->kobj;
2454
2455 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2456}
2457
2458static int
2459intel_hdmi_connector_register(struct drm_connector *connector)
2460{
2461 int ret;
2462
2463 ret = intel_connector_register(connector);
2464 if (ret)
2465 return ret;
2466
2467 intel_hdmi_create_i2c_symlink(connector);
2468
2469 return ret;
2470}
2471
2472static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2473{
2474 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2475
2476 cec_notifier_conn_unregister(n);
2477
2478 intel_hdmi_remove_i2c_symlink(connector);
2479 intel_connector_unregister(connector);
2480}
2481
2482static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2483 .detect = intel_hdmi_detect,
2484 .force = intel_hdmi_force,
2485 .fill_modes = drm_helper_probe_single_connector_modes,
2486 .atomic_get_property = intel_digital_connector_atomic_get_property,
2487 .atomic_set_property = intel_digital_connector_atomic_set_property,
2488 .late_register = intel_hdmi_connector_register,
2489 .early_unregister = intel_hdmi_connector_unregister,
2490 .destroy = intel_connector_destroy,
2491 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2492 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2493};
2494
2495static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2496 .get_modes = intel_hdmi_get_modes,
2497 .mode_valid = intel_hdmi_mode_valid,
2498 .atomic_check = intel_digital_connector_atomic_check,
2499};
2500
2501static void
2502intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2503{
2504 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2505
2506 intel_attach_force_audio_property(connector);
2507 intel_attach_broadcast_rgb_property(connector);
2508 intel_attach_aspect_ratio_property(connector);
2509
2510 intel_attach_hdmi_colorspace_property(connector);
2511 drm_connector_attach_content_type_property(connector);
2512
2513 if (DISPLAY_VER(dev_priv) >= 10)
2514 drm_connector_attach_hdr_output_metadata_property(connector);
2515
2516 if (!HAS_GMCH(dev_priv))
2517 drm_connector_attach_max_bpc_property(connector, 8, 12);
2518}
2519
2520/*
2521 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2522 * @encoder: intel_encoder
2523 * @connector: drm_connector
2524 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2525 * or reset the high tmds clock ratio for scrambling
2526 * @scrambling: bool to Indicate if the function needs to set or reset
2527 * sink scrambling
2528 *
2529 * This function handles scrambling on HDMI 2.0 capable sinks.
2530 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2531 * it enables scrambling. This should be called before enabling the HDMI
2532 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2533 * detect a scrambled clock within 100 ms.
2534 *
2535 * Returns:
2536 * True on success, false on failure.
2537 */
2538bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2539 struct drm_connector *connector,
2540 bool high_tmds_clock_ratio,
2541 bool scrambling)
2542{
2543 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2544 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2545 struct drm_scrambling *sink_scrambling =
2546 &connector->display_info.hdmi.scdc.scrambling;
2547 struct i2c_adapter *adapter =
2548 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2549
2550 if (!sink_scrambling->supported)
2551 return true;
2552
2553 drm_dbg_kms(&dev_priv->drm,
2554 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2555 connector->base.id, connector->name,
2556 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2557
2558 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2559 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2560 high_tmds_clock_ratio) &&
2561 drm_scdc_set_scrambling(adapter, scrambling);
2562}
2563
2564static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2565{
2566 u8 ddc_pin;
2567
2568 switch (port) {
2569 case PORT_B:
2570 ddc_pin = GMBUS_PIN_DPB;
2571 break;
2572 case PORT_C:
2573 ddc_pin = GMBUS_PIN_DPC;
2574 break;
2575 case PORT_D:
2576 ddc_pin = GMBUS_PIN_DPD_CHV;
2577 break;
2578 default:
2579 MISSING_CASE(port);
2580 ddc_pin = GMBUS_PIN_DPB;
2581 break;
2582 }
2583 return ddc_pin;
2584}
2585
2586static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2587{
2588 u8 ddc_pin;
2589
2590 switch (port) {
2591 case PORT_B:
2592 ddc_pin = GMBUS_PIN_1_BXT;
2593 break;
2594 case PORT_C:
2595 ddc_pin = GMBUS_PIN_2_BXT;
2596 break;
2597 default:
2598 MISSING_CASE(port);
2599 ddc_pin = GMBUS_PIN_1_BXT;
2600 break;
2601 }
2602 return ddc_pin;
2603}
2604
2605static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2606 enum port port)
2607{
2608 u8 ddc_pin;
2609
2610 switch (port) {
2611 case PORT_B:
2612 ddc_pin = GMBUS_PIN_1_BXT;
2613 break;
2614 case PORT_C:
2615 ddc_pin = GMBUS_PIN_2_BXT;
2616 break;
2617 case PORT_D:
2618 ddc_pin = GMBUS_PIN_4_CNP;
2619 break;
2620 case PORT_F:
2621 ddc_pin = GMBUS_PIN_3_BXT;
2622 break;
2623 default:
2624 MISSING_CASE(port);
2625 ddc_pin = GMBUS_PIN_1_BXT;
2626 break;
2627 }
2628 return ddc_pin;
2629}
2630
2631static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2632{
2633 enum phy phy = intel_port_to_phy(dev_priv, port);
2634
2635 if (intel_phy_is_combo(dev_priv, phy))
2636 return GMBUS_PIN_1_BXT + port;
2637 else if (intel_phy_is_tc(dev_priv, phy))
2638 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2639
2640 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2641 return GMBUS_PIN_2_BXT;
2642}
2643
2644static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2645{
2646 enum phy phy = intel_port_to_phy(dev_priv, port);
2647 u8 ddc_pin;
2648
2649 switch (phy) {
2650 case PHY_A:
2651 ddc_pin = GMBUS_PIN_1_BXT;
2652 break;
2653 case PHY_B:
2654 ddc_pin = GMBUS_PIN_2_BXT;
2655 break;
2656 case PHY_C:
2657 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2658 break;
2659 default:
2660 MISSING_CASE(phy);
2661 ddc_pin = GMBUS_PIN_1_BXT;
2662 break;
2663 }
2664 return ddc_pin;
2665}
2666
2667static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2668{
2669 enum phy phy = intel_port_to_phy(dev_priv, port);
2670
2671 WARN_ON(port == PORT_C);
2672
2673 /*
2674 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2675 * final two outputs use type-c pins, even though they're actually
2676 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2677 * all outputs.
2678 */
2679 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2680 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2681
2682 return GMBUS_PIN_1_BXT + phy;
2683}
2684
2685static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2686{
2687 enum phy phy = intel_port_to_phy(i915, port);
2688
2689 drm_WARN_ON(&i915->drm, port == PORT_A);
2690
2691 /*
2692 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2693 * final two outputs use type-c pins, even though they're actually
2694 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2695 * all outputs.
2696 */
2697 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2698 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2699
2700 return GMBUS_PIN_1_BXT + phy;
2701}
2702
2703static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2704{
2705 return intel_port_to_phy(dev_priv, port) + 1;
2706}
2707
2708static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2709{
2710 enum phy phy = intel_port_to_phy(dev_priv, port);
2711
2712 WARN_ON(port == PORT_B || port == PORT_C);
2713
2714 /*
2715 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2716 * except first combo output.
2717 */
2718 if (phy == PHY_A)
2719 return GMBUS_PIN_1_BXT;
2720
2721 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2722}
2723
2724static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2725 enum port port)
2726{
2727 u8 ddc_pin;
2728
2729 switch (port) {
2730 case PORT_B:
2731 ddc_pin = GMBUS_PIN_DPB;
2732 break;
2733 case PORT_C:
2734 ddc_pin = GMBUS_PIN_DPC;
2735 break;
2736 case PORT_D:
2737 ddc_pin = GMBUS_PIN_DPD;
2738 break;
2739 default:
2740 MISSING_CASE(port);
2741 ddc_pin = GMBUS_PIN_DPB;
2742 break;
2743 }
2744 return ddc_pin;
2745}
2746
2747static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2748{
2749 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2750 enum port port = encoder->port;
2751 u8 ddc_pin;
2752
2753 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2754 if (ddc_pin) {
2755 drm_dbg_kms(&dev_priv->drm,
2756 "Using DDC pin 0x%x for port %c (VBT)\n",
2757 ddc_pin, port_name(port));
2758 return ddc_pin;
2759 }
2760
2761 if (IS_ALDERLAKE_S(dev_priv))
2762 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2763 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2764 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2765 else if (IS_ROCKETLAKE(dev_priv))
2766 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2767 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2768 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2769 else if (HAS_PCH_MCC(dev_priv))
2770 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2771 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2772 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2773 else if (HAS_PCH_CNP(dev_priv))
2774 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2775 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2776 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2777 else if (IS_CHERRYVIEW(dev_priv))
2778 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2779 else
2780 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2781
2782 drm_dbg_kms(&dev_priv->drm,
2783 "Using DDC pin 0x%x for port %c (platform default)\n",
2784 ddc_pin, port_name(port));
2785
2786 return ddc_pin;
2787}
2788
2789void intel_infoframe_init(struct intel_digital_port *dig_port)
2790{
2791 struct drm_i915_private *dev_priv =
2792 to_i915(dig_port->base.base.dev);
2793
2794 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2795 dig_port->write_infoframe = vlv_write_infoframe;
2796 dig_port->read_infoframe = vlv_read_infoframe;
2797 dig_port->set_infoframes = vlv_set_infoframes;
2798 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2799 } else if (IS_G4X(dev_priv)) {
2800 dig_port->write_infoframe = g4x_write_infoframe;
2801 dig_port->read_infoframe = g4x_read_infoframe;
2802 dig_port->set_infoframes = g4x_set_infoframes;
2803 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2804 } else if (HAS_DDI(dev_priv)) {
2805 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2806 dig_port->write_infoframe = lspcon_write_infoframe;
2807 dig_port->read_infoframe = lspcon_read_infoframe;
2808 dig_port->set_infoframes = lspcon_set_infoframes;
2809 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2810 } else {
2811 dig_port->write_infoframe = hsw_write_infoframe;
2812 dig_port->read_infoframe = hsw_read_infoframe;
2813 dig_port->set_infoframes = hsw_set_infoframes;
2814 dig_port->infoframes_enabled = hsw_infoframes_enabled;
2815 }
2816 } else if (HAS_PCH_IBX(dev_priv)) {
2817 dig_port->write_infoframe = ibx_write_infoframe;
2818 dig_port->read_infoframe = ibx_read_infoframe;
2819 dig_port->set_infoframes = ibx_set_infoframes;
2820 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2821 } else {
2822 dig_port->write_infoframe = cpt_write_infoframe;
2823 dig_port->read_infoframe = cpt_read_infoframe;
2824 dig_port->set_infoframes = cpt_set_infoframes;
2825 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2826 }
2827}
2828
2829void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2830 struct intel_connector *intel_connector)
2831{
2832 struct drm_connector *connector = &intel_connector->base;
2833 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2834 struct intel_encoder *intel_encoder = &dig_port->base;
2835 struct drm_device *dev = intel_encoder->base.dev;
2836 struct drm_i915_private *dev_priv = to_i915(dev);
2837 struct i2c_adapter *ddc;
2838 enum port port = intel_encoder->port;
2839 struct cec_connector_info conn_info;
2840
2841 drm_dbg_kms(&dev_priv->drm,
2842 "Adding HDMI connector on [ENCODER:%d:%s]\n",
2843 intel_encoder->base.base.id, intel_encoder->base.name);
2844
2845 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2846 return;
2847
2848 if (drm_WARN(dev, dig_port->max_lanes < 4,
2849 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2850 dig_port->max_lanes, intel_encoder->base.base.id,
2851 intel_encoder->base.name))
2852 return;
2853
2854 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2855 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2856
2857 drm_connector_init_with_ddc(dev, connector,
2858 &intel_hdmi_connector_funcs,
2859 DRM_MODE_CONNECTOR_HDMIA,
2860 ddc);
2861 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2862
2863 connector->interlace_allowed = 1;
2864 connector->doublescan_allowed = 0;
2865 connector->stereo_allowed = 1;
2866
2867 if (DISPLAY_VER(dev_priv) >= 10)
2868 connector->ycbcr_420_allowed = true;
2869
2870 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2871
2872 if (HAS_DDI(dev_priv))
2873 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2874 else
2875 intel_connector->get_hw_state = intel_connector_get_hw_state;
2876
2877 intel_hdmi_add_properties(intel_hdmi, connector);
2878
2879 intel_connector_attach_encoder(intel_connector, intel_encoder);
2880 intel_hdmi->attached_connector = intel_connector;
2881
2882 if (is_hdcp_supported(dev_priv, port)) {
2883 int ret = intel_hdcp_init(intel_connector, dig_port,
2884 &intel_hdmi_hdcp_shim);
2885 if (ret)
2886 drm_dbg_kms(&dev_priv->drm,
2887 "HDCP init failed, skipping.\n");
2888 }
2889
2890 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2891 * 0xd. Failure to do so will result in spurious interrupts being
2892 * generated on the port when a cable is not attached.
2893 */
2894 if (IS_G45(dev_priv)) {
2895 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2896 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2897 (temp & ~0xf) | 0xd);
2898 }
2899
2900 cec_fill_conn_info_from_drm(&conn_info, connector);
2901
2902 intel_hdmi->cec_notifier =
2903 cec_notifier_conn_register(dev->dev, port_identifier(port),
2904 &conn_info);
2905 if (!intel_hdmi->cec_notifier)
2906 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2907}
2908
2909/*
2910 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
2911 * @vactive: Vactive of a display mode
2912 *
2913 * @return: appropriate dsc slice height for a given mode.
2914 */
2915int intel_hdmi_dsc_get_slice_height(int vactive)
2916{
2917 int slice_height;
2918
2919 /*
2920 * Slice Height determination : HDMI2.1 Section 7.7.5.2
2921 * Select smallest slice height >=96, that results in a valid PPS and
2922 * requires minimum padding lines required for final slice.
2923 *
2924 * Assumption : Vactive is even.
2925 */
2926 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
2927 if (vactive % slice_height == 0)
2928 return slice_height;
2929
2930 return 0;
2931}
2932
2933/*
2934 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
2935 * and dsc decoder capabilities
2936 *
2937 * @crtc_state: intel crtc_state
2938 * @src_max_slices: maximum slices supported by the DSC encoder
2939 * @src_max_slice_width: maximum slice width supported by DSC encoder
2940 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
2941 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
2942 *
2943 * @return: num of dsc slices that can be supported by the dsc encoder
2944 * and decoder.
2945 */
2946int
2947intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
2948 int src_max_slices, int src_max_slice_width,
2949 int hdmi_max_slices, int hdmi_throughput)
2950{
2951/* Pixel rates in KPixels/sec */
2952#define HDMI_DSC_PEAK_PIXEL_RATE 2720000
2953/*
2954 * Rates at which the source and sink are required to process pixels in each
2955 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
2956 */
2957#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
2958#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
2959
2960/* Spec limits the slice width to 2720 pixels */
2961#define MAX_HDMI_SLICE_WIDTH 2720
2962 int kslice_adjust;
2963 int adjusted_clk_khz;
2964 int min_slices;
2965 int target_slices;
2966 int max_throughput; /* max clock freq. in khz per slice */
2967 int max_slice_width;
2968 int slice_width;
2969 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
2970
2971 if (!hdmi_throughput)
2972 return 0;
2973
2974 /*
2975 * Slice Width determination : HDMI2.1 Section 7.7.5.1
2976 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
2977 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
2978 * dividing adjusted clock value by 10.
2979 */
2980 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
2981 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2982 kslice_adjust = 10;
2983 else
2984 kslice_adjust = 5;
2985
2986 /*
2987 * As per spec, the rate at which the source and the sink process
2988 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
2989 * This depends upon the pixel clock rate and output formats
2990 * (kslice adjust).
2991 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
2992 * at max 340MHz, otherwise they can be processed at max 400MHz.
2993 */
2994
2995 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
2996
2997 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
2998 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
2999 else
3000 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3001
3002 /*
3003 * Taking into account the sink's capability for maximum
3004 * clock per slice (in MHz) as read from HF-VSDB.
3005 */
3006 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3007
3008 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3009 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3010
3011 /*
3012 * Keep on increasing the num of slices/line, starting from min_slices
3013 * per line till we get such a number, for which the slice_width is
3014 * just less than max_slice_width. The slices/line selected should be
3015 * less than or equal to the max horizontal slices that the combination
3016 * of PCON encoder and HDMI decoder can support.
3017 */
3018 slice_width = max_slice_width;
3019
3020 do {
3021 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3022 target_slices = 1;
3023 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3024 target_slices = 2;
3025 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3026 target_slices = 4;
3027 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3028 target_slices = 8;
3029 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3030 target_slices = 12;
3031 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3032 target_slices = 16;
3033 else
3034 return 0;
3035
3036 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3037 if (slice_width >= max_slice_width)
3038 min_slices = target_slices + 1;
3039 } while (slice_width >= max_slice_width);
3040
3041 return target_slices;
3042}
3043
3044/*
3045 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3046 * source and sink capabilities.
3047 *
3048 * @src_fraction_bpp: fractional bpp supported by the source
3049 * @slice_width: dsc slice width supported by the source and sink
3050 * @num_slices: num of slices supported by the source and sink
3051 * @output_format: video output format
3052 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3053 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3054 *
3055 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3056 */
3057int
3058intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3059 int output_format, bool hdmi_all_bpp,
3060 int hdmi_max_chunk_bytes)
3061{
3062 int max_dsc_bpp, min_dsc_bpp;
3063 int target_bytes;
3064 bool bpp_found = false;
3065 int bpp_decrement_x16;
3066 int bpp_target;
3067 int bpp_target_x16;
3068
3069 /*
3070 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3071 * Start with the max bpp and keep on decrementing with
3072 * fractional bpp, if supported by PCON DSC encoder
3073 *
3074 * for each bpp we check if no of bytes can be supported by HDMI sink
3075 */
3076
3077 /* Assuming: bpc as 8*/
3078 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3079 min_dsc_bpp = 6;
3080 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3081 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3082 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3083 min_dsc_bpp = 8;
3084 max_dsc_bpp = 3 * 8; /* 3*bpc */
3085 } else {
3086 /* Assuming 4:2:2 encoding */
3087 min_dsc_bpp = 7;
3088 max_dsc_bpp = 2 * 8; /* 2*bpc */
3089 }
3090
3091 /*
3092 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3093 * Section 7.7.34 : Source shall not enable compressed Video
3094 * Transport with bpp_target settings above 12 bpp unless
3095 * DSC_all_bpp is set to 1.
3096 */
3097 if (!hdmi_all_bpp)
3098 max_dsc_bpp = min(max_dsc_bpp, 12);
3099
3100 /*
3101 * The Sink has a limit of compressed data in bytes for a scanline,
3102 * as described in max_chunk_bytes field in HFVSDB block of edid.
3103 * The no. of bytes depend on the target bits per pixel that the
3104 * source configures. So we start with the max_bpp and calculate
3105 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3106 * till we get the target_chunk_bytes just less than what the sink's
3107 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3108 *
3109 * The decrement is according to the fractional support from PCON DSC
3110 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3111 *
3112 * bpp_target_x16 = bpp_target * 16
3113 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3114 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3115 */
3116
3117 bpp_target = max_dsc_bpp;
3118
3119 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3120 if (!src_fractional_bpp)
3121 src_fractional_bpp = 1;
3122 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3123 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3124
3125 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3126 int bpp;
3127
3128 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3129 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3130 if (target_bytes <= hdmi_max_chunk_bytes) {
3131 bpp_found = true;
3132 break;
3133 }
3134 bpp_target_x16 -= bpp_decrement_x16;
3135 }
3136 if (bpp_found)
3137 return bpp_target_x16;
3138
3139 return 0;
3140}
1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/hdmi.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
37#include <drm/drm_hdcp.h>
38#include <drm/drm_scdc_helper.h>
39#include <drm/intel_lpe_audio.h>
40
41#include "i915_debugfs.h"
42#include "i915_drv.h"
43#include "intel_atomic.h"
44#include "intel_audio.h"
45#include "intel_connector.h"
46#include "intel_ddi.h"
47#include "intel_display_types.h"
48#include "intel_dp.h"
49#include "intel_dpio_phy.h"
50#include "intel_fifo_underrun.h"
51#include "intel_gmbus.h"
52#include "intel_hdcp.h"
53#include "intel_hdmi.h"
54#include "intel_hotplug.h"
55#include "intel_lspcon.h"
56#include "intel_panel.h"
57#include "intel_sdvo.h"
58#include "intel_sideband.h"
59
60static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
61{
62 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
63}
64
65static void
66assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
67{
68 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
69 struct drm_i915_private *dev_priv = to_i915(dev);
70 u32 enabled_bits;
71
72 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
73
74 drm_WARN(dev,
75 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
76 "HDMI port enabled, expecting disabled\n");
77}
78
79static void
80assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
81 enum transcoder cpu_transcoder)
82{
83 drm_WARN(&dev_priv->drm,
84 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
85 TRANS_DDI_FUNC_ENABLE,
86 "HDMI transcoder function enabled, expecting disabled\n");
87}
88
89struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder)
90{
91 struct intel_digital_port *dig_port =
92 container_of(&encoder->base, struct intel_digital_port,
93 base.base);
94 return &dig_port->hdmi;
95}
96
97static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector)
98{
99 return enc_to_intel_hdmi(intel_attached_encoder(connector));
100}
101
102static u32 g4x_infoframe_index(unsigned int type)
103{
104 switch (type) {
105 case HDMI_PACKET_TYPE_GAMUT_METADATA:
106 return VIDEO_DIP_SELECT_GAMUT;
107 case HDMI_INFOFRAME_TYPE_AVI:
108 return VIDEO_DIP_SELECT_AVI;
109 case HDMI_INFOFRAME_TYPE_SPD:
110 return VIDEO_DIP_SELECT_SPD;
111 case HDMI_INFOFRAME_TYPE_VENDOR:
112 return VIDEO_DIP_SELECT_VENDOR;
113 default:
114 MISSING_CASE(type);
115 return 0;
116 }
117}
118
119static u32 g4x_infoframe_enable(unsigned int type)
120{
121 switch (type) {
122 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
123 return VIDEO_DIP_ENABLE_GCP;
124 case HDMI_PACKET_TYPE_GAMUT_METADATA:
125 return VIDEO_DIP_ENABLE_GAMUT;
126 case DP_SDP_VSC:
127 return 0;
128 case HDMI_INFOFRAME_TYPE_AVI:
129 return VIDEO_DIP_ENABLE_AVI;
130 case HDMI_INFOFRAME_TYPE_SPD:
131 return VIDEO_DIP_ENABLE_SPD;
132 case HDMI_INFOFRAME_TYPE_VENDOR:
133 return VIDEO_DIP_ENABLE_VENDOR;
134 case HDMI_INFOFRAME_TYPE_DRM:
135 return 0;
136 default:
137 MISSING_CASE(type);
138 return 0;
139 }
140}
141
142static u32 hsw_infoframe_enable(unsigned int type)
143{
144 switch (type) {
145 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
146 return VIDEO_DIP_ENABLE_GCP_HSW;
147 case HDMI_PACKET_TYPE_GAMUT_METADATA:
148 return VIDEO_DIP_ENABLE_GMP_HSW;
149 case DP_SDP_VSC:
150 return VIDEO_DIP_ENABLE_VSC_HSW;
151 case DP_SDP_PPS:
152 return VDIP_ENABLE_PPS;
153 case HDMI_INFOFRAME_TYPE_AVI:
154 return VIDEO_DIP_ENABLE_AVI_HSW;
155 case HDMI_INFOFRAME_TYPE_SPD:
156 return VIDEO_DIP_ENABLE_SPD_HSW;
157 case HDMI_INFOFRAME_TYPE_VENDOR:
158 return VIDEO_DIP_ENABLE_VS_HSW;
159 case HDMI_INFOFRAME_TYPE_DRM:
160 return VIDEO_DIP_ENABLE_DRM_GLK;
161 default:
162 MISSING_CASE(type);
163 return 0;
164 }
165}
166
167static i915_reg_t
168hsw_dip_data_reg(struct drm_i915_private *dev_priv,
169 enum transcoder cpu_transcoder,
170 unsigned int type,
171 int i)
172{
173 switch (type) {
174 case HDMI_PACKET_TYPE_GAMUT_METADATA:
175 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
176 case DP_SDP_VSC:
177 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
178 case DP_SDP_PPS:
179 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
180 case HDMI_INFOFRAME_TYPE_AVI:
181 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
182 case HDMI_INFOFRAME_TYPE_SPD:
183 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
184 case HDMI_INFOFRAME_TYPE_VENDOR:
185 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
186 case HDMI_INFOFRAME_TYPE_DRM:
187 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
188 default:
189 MISSING_CASE(type);
190 return INVALID_MMIO_REG;
191 }
192}
193
194static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
195 unsigned int type)
196{
197 switch (type) {
198 case DP_SDP_VSC:
199 return VIDEO_DIP_VSC_DATA_SIZE;
200 case DP_SDP_PPS:
201 return VIDEO_DIP_PPS_DATA_SIZE;
202 case HDMI_PACKET_TYPE_GAMUT_METADATA:
203 if (INTEL_GEN(dev_priv) >= 11)
204 return VIDEO_DIP_GMP_DATA_SIZE;
205 else
206 return VIDEO_DIP_DATA_SIZE;
207 default:
208 return VIDEO_DIP_DATA_SIZE;
209 }
210}
211
212static void g4x_write_infoframe(struct intel_encoder *encoder,
213 const struct intel_crtc_state *crtc_state,
214 unsigned int type,
215 const void *frame, ssize_t len)
216{
217 const u32 *data = frame;
218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
219 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
220 int i;
221
222 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
223 "Writing DIP with CTL reg disabled\n");
224
225 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
226 val |= g4x_infoframe_index(type);
227
228 val &= ~g4x_infoframe_enable(type);
229
230 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
231
232 for (i = 0; i < len; i += 4) {
233 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
234 data++;
235 }
236 /* Write every possible data byte to force correct ECC calculation. */
237 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
238 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
239
240 val |= g4x_infoframe_enable(type);
241 val &= ~VIDEO_DIP_FREQ_MASK;
242 val |= VIDEO_DIP_FREQ_VSYNC;
243
244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
245 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
246}
247
248static void g4x_read_infoframe(struct intel_encoder *encoder,
249 const struct intel_crtc_state *crtc_state,
250 unsigned int type,
251 void *frame, ssize_t len)
252{
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
254 u32 val, *data = frame;
255 int i;
256
257 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
258
259 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
260 val |= g4x_infoframe_index(type);
261
262 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
263
264 for (i = 0; i < len; i += 4)
265 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
266}
267
268static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
269 const struct intel_crtc_state *pipe_config)
270{
271 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
272 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
273
274 if ((val & VIDEO_DIP_ENABLE) == 0)
275 return 0;
276
277 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
278 return 0;
279
280 return val & (VIDEO_DIP_ENABLE_AVI |
281 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
282}
283
284static void ibx_write_infoframe(struct intel_encoder *encoder,
285 const struct intel_crtc_state *crtc_state,
286 unsigned int type,
287 const void *frame, ssize_t len)
288{
289 const u32 *data = frame;
290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
292 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
293 u32 val = intel_de_read(dev_priv, reg);
294 int i;
295
296 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
297 "Writing DIP with CTL reg disabled\n");
298
299 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
300 val |= g4x_infoframe_index(type);
301
302 val &= ~g4x_infoframe_enable(type);
303
304 intel_de_write(dev_priv, reg, val);
305
306 for (i = 0; i < len; i += 4) {
307 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
308 *data);
309 data++;
310 }
311 /* Write every possible data byte to force correct ECC calculation. */
312 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
313 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
314
315 val |= g4x_infoframe_enable(type);
316 val &= ~VIDEO_DIP_FREQ_MASK;
317 val |= VIDEO_DIP_FREQ_VSYNC;
318
319 intel_de_write(dev_priv, reg, val);
320 intel_de_posting_read(dev_priv, reg);
321}
322
323static void ibx_read_infoframe(struct intel_encoder *encoder,
324 const struct intel_crtc_state *crtc_state,
325 unsigned int type,
326 void *frame, ssize_t len)
327{
328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
329 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
330 u32 val, *data = frame;
331 int i;
332
333 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
334
335 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
336 val |= g4x_infoframe_index(type);
337
338 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
339
340 for (i = 0; i < len; i += 4)
341 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
342}
343
344static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
346{
347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
348 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
349 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
350 u32 val = intel_de_read(dev_priv, reg);
351
352 if ((val & VIDEO_DIP_ENABLE) == 0)
353 return 0;
354
355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
356 return 0;
357
358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
361}
362
363static void cpt_write_infoframe(struct intel_encoder *encoder,
364 const struct intel_crtc_state *crtc_state,
365 unsigned int type,
366 const void *frame, ssize_t len)
367{
368 const u32 *data = frame;
369 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
371 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
372 u32 val = intel_de_read(dev_priv, reg);
373 int i;
374
375 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
376 "Writing DIP with CTL reg disabled\n");
377
378 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
379 val |= g4x_infoframe_index(type);
380
381 /* The DIP control register spec says that we need to update the AVI
382 * infoframe without clearing its enable bit */
383 if (type != HDMI_INFOFRAME_TYPE_AVI)
384 val &= ~g4x_infoframe_enable(type);
385
386 intel_de_write(dev_priv, reg, val);
387
388 for (i = 0; i < len; i += 4) {
389 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
390 *data);
391 data++;
392 }
393 /* Write every possible data byte to force correct ECC calculation. */
394 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
395 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
396
397 val |= g4x_infoframe_enable(type);
398 val &= ~VIDEO_DIP_FREQ_MASK;
399 val |= VIDEO_DIP_FREQ_VSYNC;
400
401 intel_de_write(dev_priv, reg, val);
402 intel_de_posting_read(dev_priv, reg);
403}
404
405static void cpt_read_infoframe(struct intel_encoder *encoder,
406 const struct intel_crtc_state *crtc_state,
407 unsigned int type,
408 void *frame, ssize_t len)
409{
410 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
412 u32 val, *data = frame;
413 int i;
414
415 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
416
417 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
418 val |= g4x_infoframe_index(type);
419
420 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
421
422 for (i = 0; i < len; i += 4)
423 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
424}
425
426static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
427 const struct intel_crtc_state *pipe_config)
428{
429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
430 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
431 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
432
433 if ((val & VIDEO_DIP_ENABLE) == 0)
434 return 0;
435
436 return val & (VIDEO_DIP_ENABLE_AVI |
437 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
438 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
439}
440
441static void vlv_write_infoframe(struct intel_encoder *encoder,
442 const struct intel_crtc_state *crtc_state,
443 unsigned int type,
444 const void *frame, ssize_t len)
445{
446 const u32 *data = frame;
447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
449 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
450 u32 val = intel_de_read(dev_priv, reg);
451 int i;
452
453 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
454 "Writing DIP with CTL reg disabled\n");
455
456 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
457 val |= g4x_infoframe_index(type);
458
459 val &= ~g4x_infoframe_enable(type);
460
461 intel_de_write(dev_priv, reg, val);
462
463 for (i = 0; i < len; i += 4) {
464 intel_de_write(dev_priv,
465 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
466 data++;
467 }
468 /* Write every possible data byte to force correct ECC calculation. */
469 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
470 intel_de_write(dev_priv,
471 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
472
473 val |= g4x_infoframe_enable(type);
474 val &= ~VIDEO_DIP_FREQ_MASK;
475 val |= VIDEO_DIP_FREQ_VSYNC;
476
477 intel_de_write(dev_priv, reg, val);
478 intel_de_posting_read(dev_priv, reg);
479}
480
481static void vlv_read_infoframe(struct intel_encoder *encoder,
482 const struct intel_crtc_state *crtc_state,
483 unsigned int type,
484 void *frame, ssize_t len)
485{
486 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
488 u32 val, *data = frame;
489 int i;
490
491 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
492
493 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
494 val |= g4x_infoframe_index(type);
495
496 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
497
498 for (i = 0; i < len; i += 4)
499 *data++ = intel_de_read(dev_priv,
500 VLV_TVIDEO_DIP_DATA(crtc->pipe));
501}
502
503static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
504 const struct intel_crtc_state *pipe_config)
505{
506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
507 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
508 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
509
510 if ((val & VIDEO_DIP_ENABLE) == 0)
511 return 0;
512
513 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
514 return 0;
515
516 return val & (VIDEO_DIP_ENABLE_AVI |
517 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
518 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
519}
520
521static void hsw_write_infoframe(struct intel_encoder *encoder,
522 const struct intel_crtc_state *crtc_state,
523 unsigned int type,
524 const void *frame, ssize_t len)
525{
526 const u32 *data = frame;
527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
529 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
530 int data_size;
531 int i;
532 u32 val = intel_de_read(dev_priv, ctl_reg);
533
534 data_size = hsw_dip_data_size(dev_priv, type);
535
536 drm_WARN_ON(&dev_priv->drm, len > data_size);
537
538 val &= ~hsw_infoframe_enable(type);
539 intel_de_write(dev_priv, ctl_reg, val);
540
541 for (i = 0; i < len; i += 4) {
542 intel_de_write(dev_priv,
543 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
544 *data);
545 data++;
546 }
547 /* Write every possible data byte to force correct ECC calculation. */
548 for (; i < data_size; i += 4)
549 intel_de_write(dev_priv,
550 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
551 0);
552
553 val |= hsw_infoframe_enable(type);
554 intel_de_write(dev_priv, ctl_reg, val);
555 intel_de_posting_read(dev_priv, ctl_reg);
556}
557
558static void hsw_read_infoframe(struct intel_encoder *encoder,
559 const struct intel_crtc_state *crtc_state,
560 unsigned int type,
561 void *frame, ssize_t len)
562{
563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
564 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
565 u32 val, *data = frame;
566 int i;
567
568 val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder));
569
570 for (i = 0; i < len; i += 4)
571 *data++ = intel_de_read(dev_priv,
572 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
573}
574
575static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
576 const struct intel_crtc_state *pipe_config)
577{
578 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
579 u32 val = intel_de_read(dev_priv,
580 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
581 u32 mask;
582
583 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
584 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
585 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
586
587 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
588 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
589
590 return val & mask;
591}
592
593static const u8 infoframe_type_to_idx[] = {
594 HDMI_PACKET_TYPE_GENERAL_CONTROL,
595 HDMI_PACKET_TYPE_GAMUT_METADATA,
596 DP_SDP_VSC,
597 HDMI_INFOFRAME_TYPE_AVI,
598 HDMI_INFOFRAME_TYPE_SPD,
599 HDMI_INFOFRAME_TYPE_VENDOR,
600 HDMI_INFOFRAME_TYPE_DRM,
601};
602
603u32 intel_hdmi_infoframe_enable(unsigned int type)
604{
605 int i;
606
607 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
608 if (infoframe_type_to_idx[i] == type)
609 return BIT(i);
610 }
611
612 return 0;
613}
614
615u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
616 const struct intel_crtc_state *crtc_state)
617{
618 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
619 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
620 u32 val, ret = 0;
621 int i;
622
623 val = dig_port->infoframes_enabled(encoder, crtc_state);
624
625 /* map from hardware bits to dip idx */
626 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
627 unsigned int type = infoframe_type_to_idx[i];
628
629 if (HAS_DDI(dev_priv)) {
630 if (val & hsw_infoframe_enable(type))
631 ret |= BIT(i);
632 } else {
633 if (val & g4x_infoframe_enable(type))
634 ret |= BIT(i);
635 }
636 }
637
638 return ret;
639}
640
641/*
642 * The data we write to the DIP data buffer registers is 1 byte bigger than the
643 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
644 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
645 * used for both technologies.
646 *
647 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
648 * DW1: DB3 | DB2 | DB1 | DB0
649 * DW2: DB7 | DB6 | DB5 | DB4
650 * DW3: ...
651 *
652 * (HB is Header Byte, DB is Data Byte)
653 *
654 * The hdmi pack() functions don't know about that hardware specific hole so we
655 * trick them by giving an offset into the buffer and moving back the header
656 * bytes by one.
657 */
658static void intel_write_infoframe(struct intel_encoder *encoder,
659 const struct intel_crtc_state *crtc_state,
660 enum hdmi_infoframe_type type,
661 const union hdmi_infoframe *frame)
662{
663 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
664 u8 buffer[VIDEO_DIP_DATA_SIZE];
665 ssize_t len;
666
667 if ((crtc_state->infoframes.enable &
668 intel_hdmi_infoframe_enable(type)) == 0)
669 return;
670
671 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
672 return;
673
674 /* see comment above for the reason for this offset */
675 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
676 if (drm_WARN_ON(encoder->base.dev, len < 0))
677 return;
678
679 /* Insert the 'hole' (see big comment above) at position 3 */
680 memmove(&buffer[0], &buffer[1], 3);
681 buffer[3] = 0;
682 len++;
683
684 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
685}
686
687void intel_read_infoframe(struct intel_encoder *encoder,
688 const struct intel_crtc_state *crtc_state,
689 enum hdmi_infoframe_type type,
690 union hdmi_infoframe *frame)
691{
692 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
693 u8 buffer[VIDEO_DIP_DATA_SIZE];
694 int ret;
695
696 if ((crtc_state->infoframes.enable &
697 intel_hdmi_infoframe_enable(type)) == 0)
698 return;
699
700 dig_port->read_infoframe(encoder, crtc_state,
701 type, buffer, sizeof(buffer));
702
703 /* Fill the 'hole' (see big comment above) at position 3 */
704 memmove(&buffer[1], &buffer[0], 3);
705
706 /* see comment above for the reason for this offset */
707 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
708 if (ret) {
709 drm_dbg_kms(encoder->base.dev,
710 "Failed to unpack infoframe type 0x%02x\n", type);
711 return;
712 }
713
714 if (frame->any.type != type)
715 drm_dbg_kms(encoder->base.dev,
716 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
717 frame->any.type, type);
718}
719
720static bool
721intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
722 struct intel_crtc_state *crtc_state,
723 struct drm_connector_state *conn_state)
724{
725 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
726 const struct drm_display_mode *adjusted_mode =
727 &crtc_state->hw.adjusted_mode;
728 struct drm_connector *connector = conn_state->connector;
729 int ret;
730
731 if (!crtc_state->has_infoframe)
732 return true;
733
734 crtc_state->infoframes.enable |=
735 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
736
737 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
738 adjusted_mode);
739 if (ret)
740 return false;
741
742 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
743 frame->colorspace = HDMI_COLORSPACE_YUV420;
744 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
745 frame->colorspace = HDMI_COLORSPACE_YUV444;
746 else
747 frame->colorspace = HDMI_COLORSPACE_RGB;
748
749 drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
750
751 /* nonsense combination */
752 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
753 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
754
755 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
756 drm_hdmi_avi_infoframe_quant_range(frame, connector,
757 adjusted_mode,
758 crtc_state->limited_color_range ?
759 HDMI_QUANTIZATION_RANGE_LIMITED :
760 HDMI_QUANTIZATION_RANGE_FULL);
761 } else {
762 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
763 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
764 }
765
766 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
767
768 /* TODO: handle pixel repetition for YCBCR420 outputs */
769
770 ret = hdmi_avi_infoframe_check(frame);
771 if (drm_WARN_ON(encoder->base.dev, ret))
772 return false;
773
774 return true;
775}
776
777static bool
778intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
779 struct intel_crtc_state *crtc_state,
780 struct drm_connector_state *conn_state)
781{
782 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
783 int ret;
784
785 if (!crtc_state->has_infoframe)
786 return true;
787
788 crtc_state->infoframes.enable |=
789 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
790
791 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
792 if (drm_WARN_ON(encoder->base.dev, ret))
793 return false;
794
795 frame->sdi = HDMI_SPD_SDI_PC;
796
797 ret = hdmi_spd_infoframe_check(frame);
798 if (drm_WARN_ON(encoder->base.dev, ret))
799 return false;
800
801 return true;
802}
803
804static bool
805intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
806 struct intel_crtc_state *crtc_state,
807 struct drm_connector_state *conn_state)
808{
809 struct hdmi_vendor_infoframe *frame =
810 &crtc_state->infoframes.hdmi.vendor.hdmi;
811 const struct drm_display_info *info =
812 &conn_state->connector->display_info;
813 int ret;
814
815 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
816 return true;
817
818 crtc_state->infoframes.enable |=
819 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
820
821 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
822 conn_state->connector,
823 &crtc_state->hw.adjusted_mode);
824 if (drm_WARN_ON(encoder->base.dev, ret))
825 return false;
826
827 ret = hdmi_vendor_infoframe_check(frame);
828 if (drm_WARN_ON(encoder->base.dev, ret))
829 return false;
830
831 return true;
832}
833
834static bool
835intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
836 struct intel_crtc_state *crtc_state,
837 struct drm_connector_state *conn_state)
838{
839 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
840 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
841 int ret;
842
843 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
844 return true;
845
846 if (!crtc_state->has_infoframe)
847 return true;
848
849 if (!conn_state->hdr_output_metadata)
850 return true;
851
852 crtc_state->infoframes.enable |=
853 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
854
855 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
856 if (ret < 0) {
857 drm_dbg_kms(&dev_priv->drm,
858 "couldn't set HDR metadata in infoframe\n");
859 return false;
860 }
861
862 ret = hdmi_drm_infoframe_check(frame);
863 if (drm_WARN_ON(&dev_priv->drm, ret))
864 return false;
865
866 return true;
867}
868
869static void g4x_set_infoframes(struct intel_encoder *encoder,
870 bool enable,
871 const struct intel_crtc_state *crtc_state,
872 const struct drm_connector_state *conn_state)
873{
874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
875 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
876 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
877 i915_reg_t reg = VIDEO_DIP_CTL;
878 u32 val = intel_de_read(dev_priv, reg);
879 u32 port = VIDEO_DIP_PORT(encoder->port);
880
881 assert_hdmi_port_disabled(intel_hdmi);
882
883 /* If the registers were not initialized yet, they might be zeroes,
884 * which means we're selecting the AVI DIP and we're setting its
885 * frequency to once. This seems to really confuse the HW and make
886 * things stop working (the register spec says the AVI always needs to
887 * be sent every VSync). So here we avoid writing to the register more
888 * than we need and also explicitly select the AVI DIP and explicitly
889 * set its frequency to every VSync. Avoiding to write it twice seems to
890 * be enough to solve the problem, but being defensive shouldn't hurt us
891 * either. */
892 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
893
894 if (!enable) {
895 if (!(val & VIDEO_DIP_ENABLE))
896 return;
897 if (port != (val & VIDEO_DIP_PORT_MASK)) {
898 drm_dbg_kms(&dev_priv->drm,
899 "video DIP still enabled on port %c\n",
900 (val & VIDEO_DIP_PORT_MASK) >> 29);
901 return;
902 }
903 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
904 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
905 intel_de_write(dev_priv, reg, val);
906 intel_de_posting_read(dev_priv, reg);
907 return;
908 }
909
910 if (port != (val & VIDEO_DIP_PORT_MASK)) {
911 if (val & VIDEO_DIP_ENABLE) {
912 drm_dbg_kms(&dev_priv->drm,
913 "video DIP already enabled on port %c\n",
914 (val & VIDEO_DIP_PORT_MASK) >> 29);
915 return;
916 }
917 val &= ~VIDEO_DIP_PORT_MASK;
918 val |= port;
919 }
920
921 val |= VIDEO_DIP_ENABLE;
922 val &= ~(VIDEO_DIP_ENABLE_AVI |
923 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
924
925 intel_de_write(dev_priv, reg, val);
926 intel_de_posting_read(dev_priv, reg);
927
928 intel_write_infoframe(encoder, crtc_state,
929 HDMI_INFOFRAME_TYPE_AVI,
930 &crtc_state->infoframes.avi);
931 intel_write_infoframe(encoder, crtc_state,
932 HDMI_INFOFRAME_TYPE_SPD,
933 &crtc_state->infoframes.spd);
934 intel_write_infoframe(encoder, crtc_state,
935 HDMI_INFOFRAME_TYPE_VENDOR,
936 &crtc_state->infoframes.hdmi);
937}
938
939/*
940 * Determine if default_phase=1 can be indicated in the GCP infoframe.
941 *
942 * From HDMI specification 1.4a:
943 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
944 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
945 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
946 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
947 * phase of 0
948 */
949static bool gcp_default_phase_possible(int pipe_bpp,
950 const struct drm_display_mode *mode)
951{
952 unsigned int pixels_per_group;
953
954 switch (pipe_bpp) {
955 case 30:
956 /* 4 pixels in 5 clocks */
957 pixels_per_group = 4;
958 break;
959 case 36:
960 /* 2 pixels in 3 clocks */
961 pixels_per_group = 2;
962 break;
963 case 48:
964 /* 1 pixel in 2 clocks */
965 pixels_per_group = 1;
966 break;
967 default:
968 /* phase information not relevant for 8bpc */
969 return false;
970 }
971
972 return mode->crtc_hdisplay % pixels_per_group == 0 &&
973 mode->crtc_htotal % pixels_per_group == 0 &&
974 mode->crtc_hblank_start % pixels_per_group == 0 &&
975 mode->crtc_hblank_end % pixels_per_group == 0 &&
976 mode->crtc_hsync_start % pixels_per_group == 0 &&
977 mode->crtc_hsync_end % pixels_per_group == 0 &&
978 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
979 mode->crtc_htotal/2 % pixels_per_group == 0);
980}
981
982static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
983 const struct intel_crtc_state *crtc_state,
984 const struct drm_connector_state *conn_state)
985{
986 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
987 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
988 i915_reg_t reg;
989
990 if ((crtc_state->infoframes.enable &
991 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
992 return false;
993
994 if (HAS_DDI(dev_priv))
995 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
996 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
997 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
998 else if (HAS_PCH_SPLIT(dev_priv))
999 reg = TVIDEO_DIP_GCP(crtc->pipe);
1000 else
1001 return false;
1002
1003 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
1004
1005 return true;
1006}
1007
1008void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
1009 struct intel_crtc_state *crtc_state)
1010{
1011 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1012 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1013 i915_reg_t reg;
1014
1015 if ((crtc_state->infoframes.enable &
1016 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1017 return;
1018
1019 if (HAS_DDI(dev_priv))
1020 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1021 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1022 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1023 else if (HAS_PCH_SPLIT(dev_priv))
1024 reg = TVIDEO_DIP_GCP(crtc->pipe);
1025 else
1026 return;
1027
1028 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1029}
1030
1031static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1032 struct intel_crtc_state *crtc_state,
1033 struct drm_connector_state *conn_state)
1034{
1035 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1036
1037 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1038 return;
1039
1040 crtc_state->infoframes.enable |=
1041 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1042
1043 /* Indicate color indication for deep color mode */
1044 if (crtc_state->pipe_bpp > 24)
1045 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1046
1047 /* Enable default_phase whenever the display mode is suitably aligned */
1048 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1049 &crtc_state->hw.adjusted_mode))
1050 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1051}
1052
1053static void ibx_set_infoframes(struct intel_encoder *encoder,
1054 bool enable,
1055 const struct intel_crtc_state *crtc_state,
1056 const struct drm_connector_state *conn_state)
1057{
1058 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1060 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1061 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1062 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1063 u32 val = intel_de_read(dev_priv, reg);
1064 u32 port = VIDEO_DIP_PORT(encoder->port);
1065
1066 assert_hdmi_port_disabled(intel_hdmi);
1067
1068 /* See the big comment in g4x_set_infoframes() */
1069 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1070
1071 if (!enable) {
1072 if (!(val & VIDEO_DIP_ENABLE))
1073 return;
1074 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1075 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1076 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1077 intel_de_write(dev_priv, reg, val);
1078 intel_de_posting_read(dev_priv, reg);
1079 return;
1080 }
1081
1082 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1083 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1084 "DIP already enabled on port %c\n",
1085 (val & VIDEO_DIP_PORT_MASK) >> 29);
1086 val &= ~VIDEO_DIP_PORT_MASK;
1087 val |= port;
1088 }
1089
1090 val |= VIDEO_DIP_ENABLE;
1091 val &= ~(VIDEO_DIP_ENABLE_AVI |
1092 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1093 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1094
1095 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1096 val |= VIDEO_DIP_ENABLE_GCP;
1097
1098 intel_de_write(dev_priv, reg, val);
1099 intel_de_posting_read(dev_priv, reg);
1100
1101 intel_write_infoframe(encoder, crtc_state,
1102 HDMI_INFOFRAME_TYPE_AVI,
1103 &crtc_state->infoframes.avi);
1104 intel_write_infoframe(encoder, crtc_state,
1105 HDMI_INFOFRAME_TYPE_SPD,
1106 &crtc_state->infoframes.spd);
1107 intel_write_infoframe(encoder, crtc_state,
1108 HDMI_INFOFRAME_TYPE_VENDOR,
1109 &crtc_state->infoframes.hdmi);
1110}
1111
1112static void cpt_set_infoframes(struct intel_encoder *encoder,
1113 bool enable,
1114 const struct intel_crtc_state *crtc_state,
1115 const struct drm_connector_state *conn_state)
1116{
1117 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1119 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1120 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1121 u32 val = intel_de_read(dev_priv, reg);
1122
1123 assert_hdmi_port_disabled(intel_hdmi);
1124
1125 /* See the big comment in g4x_set_infoframes() */
1126 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1127
1128 if (!enable) {
1129 if (!(val & VIDEO_DIP_ENABLE))
1130 return;
1131 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1132 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1133 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1134 intel_de_write(dev_priv, reg, val);
1135 intel_de_posting_read(dev_priv, reg);
1136 return;
1137 }
1138
1139 /* Set both together, unset both together: see the spec. */
1140 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1141 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1142 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1143
1144 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1145 val |= VIDEO_DIP_ENABLE_GCP;
1146
1147 intel_de_write(dev_priv, reg, val);
1148 intel_de_posting_read(dev_priv, reg);
1149
1150 intel_write_infoframe(encoder, crtc_state,
1151 HDMI_INFOFRAME_TYPE_AVI,
1152 &crtc_state->infoframes.avi);
1153 intel_write_infoframe(encoder, crtc_state,
1154 HDMI_INFOFRAME_TYPE_SPD,
1155 &crtc_state->infoframes.spd);
1156 intel_write_infoframe(encoder, crtc_state,
1157 HDMI_INFOFRAME_TYPE_VENDOR,
1158 &crtc_state->infoframes.hdmi);
1159}
1160
1161static void vlv_set_infoframes(struct intel_encoder *encoder,
1162 bool enable,
1163 const struct intel_crtc_state *crtc_state,
1164 const struct drm_connector_state *conn_state)
1165{
1166 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1168 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1169 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1170 u32 val = intel_de_read(dev_priv, reg);
1171 u32 port = VIDEO_DIP_PORT(encoder->port);
1172
1173 assert_hdmi_port_disabled(intel_hdmi);
1174
1175 /* See the big comment in g4x_set_infoframes() */
1176 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1177
1178 if (!enable) {
1179 if (!(val & VIDEO_DIP_ENABLE))
1180 return;
1181 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1182 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1183 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1184 intel_de_write(dev_priv, reg, val);
1185 intel_de_posting_read(dev_priv, reg);
1186 return;
1187 }
1188
1189 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1190 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1191 "DIP already enabled on port %c\n",
1192 (val & VIDEO_DIP_PORT_MASK) >> 29);
1193 val &= ~VIDEO_DIP_PORT_MASK;
1194 val |= port;
1195 }
1196
1197 val |= VIDEO_DIP_ENABLE;
1198 val &= ~(VIDEO_DIP_ENABLE_AVI |
1199 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1200 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1201
1202 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1203 val |= VIDEO_DIP_ENABLE_GCP;
1204
1205 intel_de_write(dev_priv, reg, val);
1206 intel_de_posting_read(dev_priv, reg);
1207
1208 intel_write_infoframe(encoder, crtc_state,
1209 HDMI_INFOFRAME_TYPE_AVI,
1210 &crtc_state->infoframes.avi);
1211 intel_write_infoframe(encoder, crtc_state,
1212 HDMI_INFOFRAME_TYPE_SPD,
1213 &crtc_state->infoframes.spd);
1214 intel_write_infoframe(encoder, crtc_state,
1215 HDMI_INFOFRAME_TYPE_VENDOR,
1216 &crtc_state->infoframes.hdmi);
1217}
1218
1219static void hsw_set_infoframes(struct intel_encoder *encoder,
1220 bool enable,
1221 const struct intel_crtc_state *crtc_state,
1222 const struct drm_connector_state *conn_state)
1223{
1224 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1225 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1226 u32 val = intel_de_read(dev_priv, reg);
1227
1228 assert_hdmi_transcoder_func_disabled(dev_priv,
1229 crtc_state->cpu_transcoder);
1230
1231 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1232 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1233 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1234 VIDEO_DIP_ENABLE_DRM_GLK);
1235
1236 if (!enable) {
1237 intel_de_write(dev_priv, reg, val);
1238 intel_de_posting_read(dev_priv, reg);
1239 return;
1240 }
1241
1242 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1243 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1244
1245 intel_de_write(dev_priv, reg, val);
1246 intel_de_posting_read(dev_priv, reg);
1247
1248 intel_write_infoframe(encoder, crtc_state,
1249 HDMI_INFOFRAME_TYPE_AVI,
1250 &crtc_state->infoframes.avi);
1251 intel_write_infoframe(encoder, crtc_state,
1252 HDMI_INFOFRAME_TYPE_SPD,
1253 &crtc_state->infoframes.spd);
1254 intel_write_infoframe(encoder, crtc_state,
1255 HDMI_INFOFRAME_TYPE_VENDOR,
1256 &crtc_state->infoframes.hdmi);
1257 intel_write_infoframe(encoder, crtc_state,
1258 HDMI_INFOFRAME_TYPE_DRM,
1259 &crtc_state->infoframes.drm);
1260}
1261
1262void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1263{
1264 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1265 struct i2c_adapter *adapter =
1266 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1267
1268 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1269 return;
1270
1271 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1272 enable ? "Enabling" : "Disabling");
1273
1274 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1275 adapter, enable);
1276}
1277
1278static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1279 unsigned int offset, void *buffer, size_t size)
1280{
1281 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1282 struct intel_hdmi *hdmi = &dig_port->hdmi;
1283 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1284 hdmi->ddc_bus);
1285 int ret;
1286 u8 start = offset & 0xff;
1287 struct i2c_msg msgs[] = {
1288 {
1289 .addr = DRM_HDCP_DDC_ADDR,
1290 .flags = 0,
1291 .len = 1,
1292 .buf = &start,
1293 },
1294 {
1295 .addr = DRM_HDCP_DDC_ADDR,
1296 .flags = I2C_M_RD,
1297 .len = size,
1298 .buf = buffer
1299 }
1300 };
1301 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1302 if (ret == ARRAY_SIZE(msgs))
1303 return 0;
1304 return ret >= 0 ? -EIO : ret;
1305}
1306
1307static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1308 unsigned int offset, void *buffer, size_t size)
1309{
1310 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1311 struct intel_hdmi *hdmi = &dig_port->hdmi;
1312 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1313 hdmi->ddc_bus);
1314 int ret;
1315 u8 *write_buf;
1316 struct i2c_msg msg;
1317
1318 write_buf = kzalloc(size + 1, GFP_KERNEL);
1319 if (!write_buf)
1320 return -ENOMEM;
1321
1322 write_buf[0] = offset & 0xff;
1323 memcpy(&write_buf[1], buffer, size);
1324
1325 msg.addr = DRM_HDCP_DDC_ADDR;
1326 msg.flags = 0,
1327 msg.len = size + 1,
1328 msg.buf = write_buf;
1329
1330 ret = i2c_transfer(adapter, &msg, 1);
1331 if (ret == 1)
1332 ret = 0;
1333 else if (ret >= 0)
1334 ret = -EIO;
1335
1336 kfree(write_buf);
1337 return ret;
1338}
1339
1340static
1341int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1342 u8 *an)
1343{
1344 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1345 struct intel_hdmi *hdmi = &dig_port->hdmi;
1346 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1347 hdmi->ddc_bus);
1348 int ret;
1349
1350 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1351 DRM_HDCP_AN_LEN);
1352 if (ret) {
1353 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1354 ret);
1355 return ret;
1356 }
1357
1358 ret = intel_gmbus_output_aksv(adapter);
1359 if (ret < 0) {
1360 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1361 return ret;
1362 }
1363 return 0;
1364}
1365
1366static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1367 u8 *bksv)
1368{
1369 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1370
1371 int ret;
1372 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1373 DRM_HDCP_KSV_LEN);
1374 if (ret)
1375 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1376 ret);
1377 return ret;
1378}
1379
1380static
1381int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1382 u8 *bstatus)
1383{
1384 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1385
1386 int ret;
1387 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1388 bstatus, DRM_HDCP_BSTATUS_LEN);
1389 if (ret)
1390 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1391 ret);
1392 return ret;
1393}
1394
1395static
1396int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1397 bool *repeater_present)
1398{
1399 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1400 int ret;
1401 u8 val;
1402
1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1404 if (ret) {
1405 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1406 ret);
1407 return ret;
1408 }
1409 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1410 return 0;
1411}
1412
1413static
1414int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1415 u8 *ri_prime)
1416{
1417 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1418
1419 int ret;
1420 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1421 ri_prime, DRM_HDCP_RI_LEN);
1422 if (ret)
1423 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1424 ret);
1425 return ret;
1426}
1427
1428static
1429int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1430 bool *ksv_ready)
1431{
1432 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1433 int ret;
1434 u8 val;
1435
1436 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1437 if (ret) {
1438 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1439 ret);
1440 return ret;
1441 }
1442 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1443 return 0;
1444}
1445
1446static
1447int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1448 int num_downstream, u8 *ksv_fifo)
1449{
1450 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1451 int ret;
1452 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1453 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1454 if (ret) {
1455 drm_dbg_kms(&i915->drm,
1456 "Read ksv fifo over DDC failed (%d)\n", ret);
1457 return ret;
1458 }
1459 return 0;
1460}
1461
1462static
1463int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1464 int i, u32 *part)
1465{
1466 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1467 int ret;
1468
1469 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1470 return -EINVAL;
1471
1472 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1473 part, DRM_HDCP_V_PRIME_PART_LEN);
1474 if (ret)
1475 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1476 i, ret);
1477 return ret;
1478}
1479
1480static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1481{
1482 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1483 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1484 struct drm_crtc *crtc = connector->base.state->crtc;
1485 struct intel_crtc *intel_crtc = container_of(crtc,
1486 struct intel_crtc, base);
1487 u32 scanline;
1488 int ret;
1489
1490 for (;;) {
1491 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe));
1492 if (scanline > 100 && scanline < 200)
1493 break;
1494 usleep_range(25, 50);
1495 }
1496
1497 ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, false);
1498 if (ret) {
1499 drm_err(&dev_priv->drm,
1500 "Disable HDCP signalling failed (%d)\n", ret);
1501 return ret;
1502 }
1503 ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, true);
1504 if (ret) {
1505 drm_err(&dev_priv->drm,
1506 "Enable HDCP signalling failed (%d)\n", ret);
1507 return ret;
1508 }
1509
1510 return 0;
1511}
1512
1513static
1514int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1515 bool enable)
1516{
1517 struct intel_hdmi *hdmi = &dig_port->hdmi;
1518 struct intel_connector *connector = hdmi->attached_connector;
1519 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1520 int ret;
1521
1522 if (!enable)
1523 usleep_range(6, 60); /* Bspec says >= 6us */
1524
1525 ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, enable);
1526 if (ret) {
1527 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1528 enable ? "Enable" : "Disable", ret);
1529 return ret;
1530 }
1531
1532 /*
1533 * WA: To fix incorrect positioning of the window of
1534 * opportunity and enc_en signalling in KABYLAKE.
1535 */
1536 if (IS_KABYLAKE(dev_priv) && enable)
1537 return kbl_repositioning_enc_en_signal(connector);
1538
1539 return 0;
1540}
1541
1542static
1543bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port)
1544{
1545 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1546 struct intel_connector *connector =
1547 dig_port->hdmi.attached_connector;
1548 enum port port = dig_port->base.port;
1549 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1550 int ret;
1551 union {
1552 u32 reg;
1553 u8 shim[DRM_HDCP_RI_LEN];
1554 } ri;
1555
1556 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1557 if (ret)
1558 return false;
1559
1560 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1561
1562 /* Wait for Ri prime match */
1563 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1564 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1565 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1566 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1567 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1568 port)));
1569 return false;
1570 }
1571 return true;
1572}
1573
1574static
1575bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port)
1576{
1577 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1578 int retry;
1579
1580 for (retry = 0; retry < 3; retry++)
1581 if (intel_hdmi_hdcp_check_link_once(dig_port))
1582 return true;
1583
1584 drm_err(&i915->drm, "Link check failed\n");
1585 return false;
1586}
1587
1588struct hdcp2_hdmi_msg_timeout {
1589 u8 msg_id;
1590 u16 timeout;
1591};
1592
1593static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1594 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1595 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1596 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1597 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1598 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1599};
1600
1601static
1602int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1603 u8 *rx_status)
1604{
1605 return intel_hdmi_hdcp_read(dig_port,
1606 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1607 rx_status,
1608 HDCP_2_2_HDMI_RXSTATUS_LEN);
1609}
1610
1611static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1612{
1613 int i;
1614
1615 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1616 if (is_paired)
1617 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1618 else
1619 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1620 }
1621
1622 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1623 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1624 return hdcp2_msg_timeout[i].timeout;
1625 }
1626
1627 return -EINVAL;
1628}
1629
1630static int
1631hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1632 u8 msg_id, bool *msg_ready,
1633 ssize_t *msg_sz)
1634{
1635 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1636 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1637 int ret;
1638
1639 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1640 if (ret < 0) {
1641 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1642 ret);
1643 return ret;
1644 }
1645
1646 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1647 rx_status[0]);
1648
1649 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1650 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1651 *msg_sz);
1652 else
1653 *msg_ready = *msg_sz;
1654
1655 return 0;
1656}
1657
1658static ssize_t
1659intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1660 u8 msg_id, bool paired)
1661{
1662 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1663 bool msg_ready = false;
1664 int timeout, ret;
1665 ssize_t msg_sz = 0;
1666
1667 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1668 if (timeout < 0)
1669 return timeout;
1670
1671 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1672 msg_id, &msg_ready,
1673 &msg_sz),
1674 !ret && msg_ready && msg_sz, timeout * 1000,
1675 1000, 5 * 1000);
1676 if (ret)
1677 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1678 msg_id, ret, timeout);
1679
1680 return ret ? ret : msg_sz;
1681}
1682
1683static
1684int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1685 void *buf, size_t size)
1686{
1687 unsigned int offset;
1688
1689 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1690 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1691}
1692
1693static
1694int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1695 u8 msg_id, void *buf, size_t size)
1696{
1697 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1698 struct intel_hdmi *hdmi = &dig_port->hdmi;
1699 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1700 unsigned int offset;
1701 ssize_t ret;
1702
1703 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1704 hdcp->is_paired);
1705 if (ret < 0)
1706 return ret;
1707
1708 /*
1709 * Available msg size should be equal to or lesser than the
1710 * available buffer.
1711 */
1712 if (ret > size) {
1713 drm_dbg_kms(&i915->drm,
1714 "msg_sz(%zd) is more than exp size(%zu)\n",
1715 ret, size);
1716 return -1;
1717 }
1718
1719 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1720 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1721 if (ret)
1722 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1723 msg_id, ret);
1724
1725 return ret;
1726}
1727
1728static
1729int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
1730{
1731 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1732 int ret;
1733
1734 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1735 if (ret)
1736 return ret;
1737
1738 /*
1739 * Re-auth request and Link Integrity Failures are represented by
1740 * same bit. i.e reauth_req.
1741 */
1742 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1743 ret = HDCP_REAUTH_REQUEST;
1744 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1745 ret = HDCP_TOPOLOGY_CHANGE;
1746
1747 return ret;
1748}
1749
1750static
1751int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1752 bool *capable)
1753{
1754 u8 hdcp2_version;
1755 int ret;
1756
1757 *capable = false;
1758 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1759 &hdcp2_version, sizeof(hdcp2_version));
1760 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1761 *capable = true;
1762
1763 return ret;
1764}
1765
1766static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1767 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1768 .read_bksv = intel_hdmi_hdcp_read_bksv,
1769 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1770 .repeater_present = intel_hdmi_hdcp_repeater_present,
1771 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1772 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1773 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1774 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1775 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1776 .check_link = intel_hdmi_hdcp_check_link,
1777 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1778 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1779 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1780 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1781 .protocol = HDCP_PROTOCOL_HDMI,
1782};
1783
1784static void intel_hdmi_prepare(struct intel_encoder *encoder,
1785 const struct intel_crtc_state *crtc_state)
1786{
1787 struct drm_device *dev = encoder->base.dev;
1788 struct drm_i915_private *dev_priv = to_i915(dev);
1789 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1790 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1791 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1792 u32 hdmi_val;
1793
1794 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1795
1796 hdmi_val = SDVO_ENCODING_HDMI;
1797 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1798 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1799 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1800 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1801 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1802 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1803
1804 if (crtc_state->pipe_bpp > 24)
1805 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1806 else
1807 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1808
1809 if (crtc_state->has_hdmi_sink)
1810 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1811
1812 if (HAS_PCH_CPT(dev_priv))
1813 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1814 else if (IS_CHERRYVIEW(dev_priv))
1815 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1816 else
1817 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1818
1819 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
1820 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1821}
1822
1823static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1824 enum pipe *pipe)
1825{
1826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1827 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1828 intel_wakeref_t wakeref;
1829 bool ret;
1830
1831 wakeref = intel_display_power_get_if_enabled(dev_priv,
1832 encoder->power_domain);
1833 if (!wakeref)
1834 return false;
1835
1836 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1837
1838 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1839
1840 return ret;
1841}
1842
1843static void intel_hdmi_get_config(struct intel_encoder *encoder,
1844 struct intel_crtc_state *pipe_config)
1845{
1846 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1847 struct drm_device *dev = encoder->base.dev;
1848 struct drm_i915_private *dev_priv = to_i915(dev);
1849 u32 tmp, flags = 0;
1850 int dotclock;
1851
1852 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1853
1854 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
1855
1856 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1857 flags |= DRM_MODE_FLAG_PHSYNC;
1858 else
1859 flags |= DRM_MODE_FLAG_NHSYNC;
1860
1861 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1862 flags |= DRM_MODE_FLAG_PVSYNC;
1863 else
1864 flags |= DRM_MODE_FLAG_NVSYNC;
1865
1866 if (tmp & HDMI_MODE_SELECT_HDMI)
1867 pipe_config->has_hdmi_sink = true;
1868
1869 pipe_config->infoframes.enable |=
1870 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1871
1872 if (pipe_config->infoframes.enable)
1873 pipe_config->has_infoframe = true;
1874
1875 if (tmp & HDMI_AUDIO_ENABLE)
1876 pipe_config->has_audio = true;
1877
1878 if (!HAS_PCH_SPLIT(dev_priv) &&
1879 tmp & HDMI_COLOR_RANGE_16_235)
1880 pipe_config->limited_color_range = true;
1881
1882 pipe_config->hw.adjusted_mode.flags |= flags;
1883
1884 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1885 dotclock = pipe_config->port_clock * 2 / 3;
1886 else
1887 dotclock = pipe_config->port_clock;
1888
1889 if (pipe_config->pixel_multiplier)
1890 dotclock /= pipe_config->pixel_multiplier;
1891
1892 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1893
1894 pipe_config->lane_count = 4;
1895
1896 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1897
1898 intel_read_infoframe(encoder, pipe_config,
1899 HDMI_INFOFRAME_TYPE_AVI,
1900 &pipe_config->infoframes.avi);
1901 intel_read_infoframe(encoder, pipe_config,
1902 HDMI_INFOFRAME_TYPE_SPD,
1903 &pipe_config->infoframes.spd);
1904 intel_read_infoframe(encoder, pipe_config,
1905 HDMI_INFOFRAME_TYPE_VENDOR,
1906 &pipe_config->infoframes.hdmi);
1907}
1908
1909static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1910 const struct intel_crtc_state *pipe_config,
1911 const struct drm_connector_state *conn_state)
1912{
1913 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1914 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1915
1916 drm_WARN_ON(&i915->drm, !pipe_config->has_hdmi_sink);
1917 drm_dbg_kms(&i915->drm, "Enabling HDMI audio on pipe %c\n",
1918 pipe_name(crtc->pipe));
1919 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1920}
1921
1922static void g4x_enable_hdmi(struct intel_atomic_state *state,
1923 struct intel_encoder *encoder,
1924 const struct intel_crtc_state *pipe_config,
1925 const struct drm_connector_state *conn_state)
1926{
1927 struct drm_device *dev = encoder->base.dev;
1928 struct drm_i915_private *dev_priv = to_i915(dev);
1929 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1930 u32 temp;
1931
1932 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
1933
1934 temp |= SDVO_ENABLE;
1935 if (pipe_config->has_audio)
1936 temp |= HDMI_AUDIO_ENABLE;
1937
1938 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1939 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1940
1941 if (pipe_config->has_audio)
1942 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1943}
1944
1945static void ibx_enable_hdmi(struct intel_atomic_state *state,
1946 struct intel_encoder *encoder,
1947 const struct intel_crtc_state *pipe_config,
1948 const struct drm_connector_state *conn_state)
1949{
1950 struct drm_device *dev = encoder->base.dev;
1951 struct drm_i915_private *dev_priv = to_i915(dev);
1952 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1953 u32 temp;
1954
1955 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
1956
1957 temp |= SDVO_ENABLE;
1958 if (pipe_config->has_audio)
1959 temp |= HDMI_AUDIO_ENABLE;
1960
1961 /*
1962 * HW workaround, need to write this twice for issue
1963 * that may result in first write getting masked.
1964 */
1965 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1966 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1967 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1968 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1969
1970 /*
1971 * HW workaround, need to toggle enable bit off and on
1972 * for 12bpc with pixel repeat.
1973 *
1974 * FIXME: BSpec says this should be done at the end of
1975 * of the modeset sequence, so not sure if this isn't too soon.
1976 */
1977 if (pipe_config->pipe_bpp > 24 &&
1978 pipe_config->pixel_multiplier > 1) {
1979 intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
1980 temp & ~SDVO_ENABLE);
1981 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1982
1983 /*
1984 * HW workaround, need to write this twice for issue
1985 * that may result in first write getting masked.
1986 */
1987 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1988 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1989 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1990 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1991 }
1992
1993 if (pipe_config->has_audio)
1994 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1995}
1996
1997static void cpt_enable_hdmi(struct intel_atomic_state *state,
1998 struct intel_encoder *encoder,
1999 const struct intel_crtc_state *pipe_config,
2000 const struct drm_connector_state *conn_state)
2001{
2002 struct drm_device *dev = encoder->base.dev;
2003 struct drm_i915_private *dev_priv = to_i915(dev);
2004 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2005 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2006 enum pipe pipe = crtc->pipe;
2007 u32 temp;
2008
2009 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
2010
2011 temp |= SDVO_ENABLE;
2012 if (pipe_config->has_audio)
2013 temp |= HDMI_AUDIO_ENABLE;
2014
2015 /*
2016 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
2017 *
2018 * The procedure for 12bpc is as follows:
2019 * 1. disable HDMI clock gating
2020 * 2. enable HDMI with 8bpc
2021 * 3. enable HDMI with 12bpc
2022 * 4. enable HDMI clock gating
2023 */
2024
2025 if (pipe_config->pipe_bpp > 24) {
2026 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
2027 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
2028
2029 temp &= ~SDVO_COLOR_FORMAT_MASK;
2030 temp |= SDVO_COLOR_FORMAT_8bpc;
2031 }
2032
2033 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2034 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2035
2036 if (pipe_config->pipe_bpp > 24) {
2037 temp &= ~SDVO_COLOR_FORMAT_MASK;
2038 temp |= HDMI_COLOR_FORMAT_12bpc;
2039
2040 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2041 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2042
2043 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
2044 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
2045 }
2046
2047 if (pipe_config->has_audio)
2048 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
2049}
2050
2051static void vlv_enable_hdmi(struct intel_atomic_state *state,
2052 struct intel_encoder *encoder,
2053 const struct intel_crtc_state *pipe_config,
2054 const struct drm_connector_state *conn_state)
2055{
2056}
2057
2058static void intel_disable_hdmi(struct intel_atomic_state *state,
2059 struct intel_encoder *encoder,
2060 const struct intel_crtc_state *old_crtc_state,
2061 const struct drm_connector_state *old_conn_state)
2062{
2063 struct drm_device *dev = encoder->base.dev;
2064 struct drm_i915_private *dev_priv = to_i915(dev);
2065 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2066 struct intel_digital_port *dig_port =
2067 hdmi_to_dig_port(intel_hdmi);
2068 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2069 u32 temp;
2070
2071 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
2072
2073 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2074 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2075 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2076
2077 /*
2078 * HW workaround for IBX, we need to move the port
2079 * to transcoder A after disabling it to allow the
2080 * matching DP port to be enabled on transcoder A.
2081 */
2082 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2083 /*
2084 * We get CPU/PCH FIFO underruns on the other pipe when
2085 * doing the workaround. Sweep them under the rug.
2086 */
2087 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2088 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2089
2090 temp &= ~SDVO_PIPE_SEL_MASK;
2091 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2092 /*
2093 * HW workaround, need to write this twice for issue
2094 * that may result in first write getting masked.
2095 */
2096 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2097 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2098 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2099 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2100
2101 temp &= ~SDVO_ENABLE;
2102 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2103 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2104
2105 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2106 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2107 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2108 }
2109
2110 dig_port->set_infoframes(encoder,
2111 false,
2112 old_crtc_state, old_conn_state);
2113
2114 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2115}
2116
2117static void g4x_disable_hdmi(struct intel_atomic_state *state,
2118 struct intel_encoder *encoder,
2119 const struct intel_crtc_state *old_crtc_state,
2120 const struct drm_connector_state *old_conn_state)
2121{
2122 if (old_crtc_state->has_audio)
2123 intel_audio_codec_disable(encoder,
2124 old_crtc_state, old_conn_state);
2125
2126 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
2127}
2128
2129static void pch_disable_hdmi(struct intel_atomic_state *state,
2130 struct intel_encoder *encoder,
2131 const struct intel_crtc_state *old_crtc_state,
2132 const struct drm_connector_state *old_conn_state)
2133{
2134 if (old_crtc_state->has_audio)
2135 intel_audio_codec_disable(encoder,
2136 old_crtc_state, old_conn_state);
2137}
2138
2139static void pch_post_disable_hdmi(struct intel_atomic_state *state,
2140 struct intel_encoder *encoder,
2141 const struct intel_crtc_state *old_crtc_state,
2142 const struct drm_connector_state *old_conn_state)
2143{
2144 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
2145}
2146
2147static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2148{
2149 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2150 int max_tmds_clock, vbt_max_tmds_clock;
2151
2152 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2153 max_tmds_clock = 594000;
2154 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2155 max_tmds_clock = 300000;
2156 else if (INTEL_GEN(dev_priv) >= 5)
2157 max_tmds_clock = 225000;
2158 else
2159 max_tmds_clock = 165000;
2160
2161 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
2162 if (vbt_max_tmds_clock)
2163 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
2164
2165 return max_tmds_clock;
2166}
2167
2168static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
2169 const struct drm_connector_state *conn_state)
2170{
2171 return hdmi->has_hdmi_sink &&
2172 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
2173}
2174
2175static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2176 bool respect_downstream_limits,
2177 bool has_hdmi_sink)
2178{
2179 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2180 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2181
2182 if (respect_downstream_limits) {
2183 struct intel_connector *connector = hdmi->attached_connector;
2184 const struct drm_display_info *info = &connector->base.display_info;
2185
2186 if (hdmi->dp_dual_mode.max_tmds_clock)
2187 max_tmds_clock = min(max_tmds_clock,
2188 hdmi->dp_dual_mode.max_tmds_clock);
2189
2190 if (info->max_tmds_clock)
2191 max_tmds_clock = min(max_tmds_clock,
2192 info->max_tmds_clock);
2193 else if (!has_hdmi_sink)
2194 max_tmds_clock = min(max_tmds_clock, 165000);
2195 }
2196
2197 return max_tmds_clock;
2198}
2199
2200static enum drm_mode_status
2201hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2202 int clock, bool respect_downstream_limits,
2203 bool has_hdmi_sink)
2204{
2205 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2206
2207 if (clock < 25000)
2208 return MODE_CLOCK_LOW;
2209 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
2210 has_hdmi_sink))
2211 return MODE_CLOCK_HIGH;
2212
2213 /* BXT DPLL can't generate 223-240 MHz */
2214 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2215 return MODE_CLOCK_RANGE;
2216
2217 /* CHV DPLL can't generate 216-240 MHz */
2218 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2219 return MODE_CLOCK_RANGE;
2220
2221 return MODE_OK;
2222}
2223
2224static enum drm_mode_status
2225intel_hdmi_mode_valid(struct drm_connector *connector,
2226 struct drm_display_mode *mode)
2227{
2228 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2229 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2230 struct drm_i915_private *dev_priv = to_i915(dev);
2231 enum drm_mode_status status;
2232 int clock = mode->clock;
2233 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2234 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
2235
2236 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2237 return MODE_NO_DBLESCAN;
2238
2239 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2240 clock *= 2;
2241
2242 if (clock > max_dotclk)
2243 return MODE_CLOCK_HIGH;
2244
2245 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2246 if (!has_hdmi_sink)
2247 return MODE_CLOCK_LOW;
2248 clock *= 2;
2249 }
2250
2251 if (drm_mode_is_420_only(&connector->display_info, mode))
2252 clock /= 2;
2253
2254 /* check if we can do 8bpc */
2255 status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink);
2256
2257 if (has_hdmi_sink) {
2258 /* if we can't do 8bpc we may still be able to do 12bpc */
2259 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2260 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2261 true, has_hdmi_sink);
2262
2263 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2264 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2265 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2266 true, has_hdmi_sink);
2267 }
2268 if (status != MODE_OK)
2269 return status;
2270
2271 return intel_mode_valid_max_plane_size(dev_priv, mode);
2272}
2273
2274static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2275 int bpc)
2276{
2277 struct drm_i915_private *dev_priv =
2278 to_i915(crtc_state->uapi.crtc->dev);
2279 struct drm_atomic_state *state = crtc_state->uapi.state;
2280 struct drm_connector_state *connector_state;
2281 struct drm_connector *connector;
2282 const struct drm_display_mode *adjusted_mode =
2283 &crtc_state->hw.adjusted_mode;
2284 int i;
2285
2286 if (HAS_GMCH(dev_priv))
2287 return false;
2288
2289 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2290 return false;
2291
2292 if (crtc_state->pipe_bpp < bpc * 3)
2293 return false;
2294
2295 if (!crtc_state->has_hdmi_sink)
2296 return false;
2297
2298 /*
2299 * HDMI deep color affects the clocks, so it's only possible
2300 * when not cloning with other encoder types.
2301 */
2302 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2303 return false;
2304
2305 for_each_new_connector_in_state(state, connector, connector_state, i) {
2306 const struct drm_display_info *info = &connector->display_info;
2307
2308 if (connector_state->crtc != crtc_state->uapi.crtc)
2309 continue;
2310
2311 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2312 const struct drm_hdmi_info *hdmi = &info->hdmi;
2313
2314 if (bpc == 12 && !(hdmi->y420_dc_modes &
2315 DRM_EDID_YCBCR420_DC_36))
2316 return false;
2317 else if (bpc == 10 && !(hdmi->y420_dc_modes &
2318 DRM_EDID_YCBCR420_DC_30))
2319 return false;
2320 } else {
2321 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2322 DRM_EDID_HDMI_DC_36))
2323 return false;
2324 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2325 DRM_EDID_HDMI_DC_30))
2326 return false;
2327 }
2328 }
2329
2330 /* Display Wa_1405510057:icl,ehl */
2331 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2332 bpc == 10 && IS_GEN(dev_priv, 11) &&
2333 (adjusted_mode->crtc_hblank_end -
2334 adjusted_mode->crtc_hblank_start) % 8 == 2)
2335 return false;
2336
2337 return true;
2338}
2339
2340static int
2341intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
2342 const struct drm_connector_state *conn_state)
2343{
2344 struct drm_connector *connector = conn_state->connector;
2345 struct drm_i915_private *i915 = to_i915(connector->dev);
2346 const struct drm_display_mode *adjusted_mode =
2347 &crtc_state->hw.adjusted_mode;
2348
2349 if (!drm_mode_is_420_only(&connector->display_info, adjusted_mode))
2350 return 0;
2351
2352 if (!connector->ycbcr_420_allowed) {
2353 drm_err(&i915->drm,
2354 "Platform doesn't support YCBCR420 output\n");
2355 return -EINVAL;
2356 }
2357
2358 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2359
2360 return intel_pch_panel_fitting(crtc_state, conn_state);
2361}
2362
2363static int intel_hdmi_port_clock(int clock, int bpc)
2364{
2365 /*
2366 * Need to adjust the port link by:
2367 * 1.5x for 12bpc
2368 * 1.25x for 10bpc
2369 */
2370 return clock * bpc / 8;
2371}
2372
2373static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2374 struct intel_crtc_state *crtc_state,
2375 int clock)
2376{
2377 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2378 int bpc;
2379
2380 for (bpc = 12; bpc >= 10; bpc -= 2) {
2381 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2382 hdmi_port_clock_valid(intel_hdmi,
2383 intel_hdmi_port_clock(clock, bpc),
2384 true, crtc_state->has_hdmi_sink) == MODE_OK)
2385 return bpc;
2386 }
2387
2388 return 8;
2389}
2390
2391static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2392 struct intel_crtc_state *crtc_state)
2393{
2394 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2395 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2396 const struct drm_display_mode *adjusted_mode =
2397 &crtc_state->hw.adjusted_mode;
2398 int bpc, clock = adjusted_mode->crtc_clock;
2399
2400 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2401 clock *= 2;
2402
2403 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2404 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2405 clock /= 2;
2406
2407 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2408
2409 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2410
2411 /*
2412 * pipe_bpp could already be below 8bpc due to
2413 * FDI bandwidth constraints. We shouldn't bump it
2414 * back up to 8bpc in that case.
2415 */
2416 if (crtc_state->pipe_bpp > bpc * 3)
2417 crtc_state->pipe_bpp = bpc * 3;
2418
2419 drm_dbg_kms(&i915->drm,
2420 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2421 bpc, crtc_state->pipe_bpp);
2422
2423 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2424 false, crtc_state->has_hdmi_sink) != MODE_OK) {
2425 drm_dbg_kms(&i915->drm,
2426 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2427 crtc_state->port_clock);
2428 return -EINVAL;
2429 }
2430
2431 return 0;
2432}
2433
2434bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2435 const struct drm_connector_state *conn_state)
2436{
2437 const struct intel_digital_connector_state *intel_conn_state =
2438 to_intel_digital_connector_state(conn_state);
2439 const struct drm_display_mode *adjusted_mode =
2440 &crtc_state->hw.adjusted_mode;
2441
2442 /*
2443 * Our YCbCr output is always limited range.
2444 * crtc_state->limited_color_range only applies to RGB,
2445 * and it must never be set for YCbCr or we risk setting
2446 * some conflicting bits in PIPECONF which will mess up
2447 * the colors on the monitor.
2448 */
2449 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2450 return false;
2451
2452 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2453 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2454 return crtc_state->has_hdmi_sink &&
2455 drm_default_rgb_quant_range(adjusted_mode) ==
2456 HDMI_QUANTIZATION_RANGE_LIMITED;
2457 } else {
2458 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2459 }
2460}
2461
2462int intel_hdmi_compute_config(struct intel_encoder *encoder,
2463 struct intel_crtc_state *pipe_config,
2464 struct drm_connector_state *conn_state)
2465{
2466 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2467 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2468 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2469 struct drm_connector *connector = conn_state->connector;
2470 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2471 struct intel_digital_connector_state *intel_conn_state =
2472 to_intel_digital_connector_state(conn_state);
2473 int ret;
2474
2475 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2476 return -EINVAL;
2477
2478 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2479 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2480 conn_state);
2481
2482 if (pipe_config->has_hdmi_sink)
2483 pipe_config->has_infoframe = true;
2484
2485 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2486 pipe_config->pixel_multiplier = 2;
2487
2488 ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state);
2489 if (ret)
2490 return ret;
2491
2492 pipe_config->limited_color_range =
2493 intel_hdmi_limited_color_range(pipe_config, conn_state);
2494
2495 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2496 pipe_config->has_pch_encoder = true;
2497
2498 if (pipe_config->has_hdmi_sink) {
2499 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2500 pipe_config->has_audio = intel_hdmi->has_audio;
2501 else
2502 pipe_config->has_audio =
2503 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2504 }
2505
2506 ret = intel_hdmi_compute_clock(encoder, pipe_config);
2507 if (ret)
2508 return ret;
2509
2510 if (conn_state->picture_aspect_ratio)
2511 adjusted_mode->picture_aspect_ratio =
2512 conn_state->picture_aspect_ratio;
2513
2514 pipe_config->lane_count = 4;
2515
2516 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2517 IS_GEMINILAKE(dev_priv))) {
2518 if (scdc->scrambling.low_rates)
2519 pipe_config->hdmi_scrambling = true;
2520
2521 if (pipe_config->port_clock > 340000) {
2522 pipe_config->hdmi_scrambling = true;
2523 pipe_config->hdmi_high_tmds_clock_ratio = true;
2524 }
2525 }
2526
2527 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2528 conn_state);
2529
2530 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2531 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2532 return -EINVAL;
2533 }
2534
2535 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2536 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2537 return -EINVAL;
2538 }
2539
2540 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2541 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2542 return -EINVAL;
2543 }
2544
2545 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2546 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2547 return -EINVAL;
2548 }
2549
2550 return 0;
2551}
2552
2553static void
2554intel_hdmi_unset_edid(struct drm_connector *connector)
2555{
2556 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2557
2558 intel_hdmi->has_hdmi_sink = false;
2559 intel_hdmi->has_audio = false;
2560
2561 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2562 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2563
2564 kfree(to_intel_connector(connector)->detect_edid);
2565 to_intel_connector(connector)->detect_edid = NULL;
2566}
2567
2568static void
2569intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2570{
2571 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2572 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2573 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2574 struct i2c_adapter *adapter =
2575 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2576 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2577
2578 /*
2579 * Type 1 DVI adaptors are not required to implement any
2580 * registers, so we can't always detect their presence.
2581 * Ideally we should be able to check the state of the
2582 * CONFIG1 pin, but no such luck on our hardware.
2583 *
2584 * The only method left to us is to check the VBT to see
2585 * if the port is a dual mode capable DP port. But let's
2586 * only do that when we sucesfully read the EDID, to avoid
2587 * confusing log messages about DP dual mode adaptors when
2588 * there's nothing connected to the port.
2589 */
2590 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2591 /* An overridden EDID imply that we want this port for testing.
2592 * Make sure not to set limits for that port.
2593 */
2594 if (has_edid && !connector->override_edid &&
2595 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2596 drm_dbg_kms(&dev_priv->drm,
2597 "Assuming DP dual mode adaptor presence based on VBT\n");
2598 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2599 } else {
2600 type = DRM_DP_DUAL_MODE_NONE;
2601 }
2602 }
2603
2604 if (type == DRM_DP_DUAL_MODE_NONE)
2605 return;
2606
2607 hdmi->dp_dual_mode.type = type;
2608 hdmi->dp_dual_mode.max_tmds_clock =
2609 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2610
2611 drm_dbg_kms(&dev_priv->drm,
2612 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2613 drm_dp_get_dual_mode_type_name(type),
2614 hdmi->dp_dual_mode.max_tmds_clock);
2615}
2616
2617static bool
2618intel_hdmi_set_edid(struct drm_connector *connector)
2619{
2620 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2621 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2622 intel_wakeref_t wakeref;
2623 struct edid *edid;
2624 bool connected = false;
2625 struct i2c_adapter *i2c;
2626
2627 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2628
2629 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2630
2631 edid = drm_get_edid(connector, i2c);
2632
2633 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2634 drm_dbg_kms(&dev_priv->drm,
2635 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2636 intel_gmbus_force_bit(i2c, true);
2637 edid = drm_get_edid(connector, i2c);
2638 intel_gmbus_force_bit(i2c, false);
2639 }
2640
2641 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2642
2643 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2644
2645 to_intel_connector(connector)->detect_edid = edid;
2646 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2647 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2648 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2649
2650 connected = true;
2651 }
2652
2653 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2654
2655 return connected;
2656}
2657
2658static enum drm_connector_status
2659intel_hdmi_detect(struct drm_connector *connector, bool force)
2660{
2661 enum drm_connector_status status = connector_status_disconnected;
2662 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2663 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2664 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2665 intel_wakeref_t wakeref;
2666
2667 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2668 connector->base.id, connector->name);
2669
2670 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2671
2672 if (INTEL_GEN(dev_priv) >= 11 &&
2673 !intel_digital_port_connected(encoder))
2674 goto out;
2675
2676 intel_hdmi_unset_edid(connector);
2677
2678 if (intel_hdmi_set_edid(connector))
2679 status = connector_status_connected;
2680
2681out:
2682 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2683
2684 if (status != connector_status_connected)
2685 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2686
2687 /*
2688 * Make sure the refs for power wells enabled during detect are
2689 * dropped to avoid a new detect cycle triggered by HPD polling.
2690 */
2691 intel_display_power_flush_work(dev_priv);
2692
2693 return status;
2694}
2695
2696static void
2697intel_hdmi_force(struct drm_connector *connector)
2698{
2699 struct drm_i915_private *i915 = to_i915(connector->dev);
2700
2701 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2702 connector->base.id, connector->name);
2703
2704 intel_hdmi_unset_edid(connector);
2705
2706 if (connector->status != connector_status_connected)
2707 return;
2708
2709 intel_hdmi_set_edid(connector);
2710}
2711
2712static int intel_hdmi_get_modes(struct drm_connector *connector)
2713{
2714 struct edid *edid;
2715
2716 edid = to_intel_connector(connector)->detect_edid;
2717 if (edid == NULL)
2718 return 0;
2719
2720 return intel_connector_update_modes(connector, edid);
2721}
2722
2723static void intel_hdmi_pre_enable(struct intel_atomic_state *state,
2724 struct intel_encoder *encoder,
2725 const struct intel_crtc_state *pipe_config,
2726 const struct drm_connector_state *conn_state)
2727{
2728 struct intel_digital_port *dig_port =
2729 enc_to_dig_port(encoder);
2730
2731 intel_hdmi_prepare(encoder, pipe_config);
2732
2733 dig_port->set_infoframes(encoder,
2734 pipe_config->has_infoframe,
2735 pipe_config, conn_state);
2736}
2737
2738static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
2739 struct intel_encoder *encoder,
2740 const struct intel_crtc_state *pipe_config,
2741 const struct drm_connector_state *conn_state)
2742{
2743 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2744 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2745
2746 vlv_phy_pre_encoder_enable(encoder, pipe_config);
2747
2748 /* HDMI 1.0V-2dB */
2749 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2750 0x2b247878);
2751
2752 dig_port->set_infoframes(encoder,
2753 pipe_config->has_infoframe,
2754 pipe_config, conn_state);
2755
2756 g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
2757
2758 vlv_wait_port_ready(dev_priv, dig_port, 0x0);
2759}
2760
2761static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
2762 struct intel_encoder *encoder,
2763 const struct intel_crtc_state *pipe_config,
2764 const struct drm_connector_state *conn_state)
2765{
2766 intel_hdmi_prepare(encoder, pipe_config);
2767
2768 vlv_phy_pre_pll_enable(encoder, pipe_config);
2769}
2770
2771static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
2772 struct intel_encoder *encoder,
2773 const struct intel_crtc_state *pipe_config,
2774 const struct drm_connector_state *conn_state)
2775{
2776 intel_hdmi_prepare(encoder, pipe_config);
2777
2778 chv_phy_pre_pll_enable(encoder, pipe_config);
2779}
2780
2781static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state,
2782 struct intel_encoder *encoder,
2783 const struct intel_crtc_state *old_crtc_state,
2784 const struct drm_connector_state *old_conn_state)
2785{
2786 chv_phy_post_pll_disable(encoder, old_crtc_state);
2787}
2788
2789static void vlv_hdmi_post_disable(struct intel_atomic_state *state,
2790 struct intel_encoder *encoder,
2791 const struct intel_crtc_state *old_crtc_state,
2792 const struct drm_connector_state *old_conn_state)
2793{
2794 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2795 vlv_phy_reset_lanes(encoder, old_crtc_state);
2796}
2797
2798static void chv_hdmi_post_disable(struct intel_atomic_state *state,
2799 struct intel_encoder *encoder,
2800 const struct intel_crtc_state *old_crtc_state,
2801 const struct drm_connector_state *old_conn_state)
2802{
2803 struct drm_device *dev = encoder->base.dev;
2804 struct drm_i915_private *dev_priv = to_i915(dev);
2805
2806 vlv_dpio_get(dev_priv);
2807
2808 /* Assert data lane reset */
2809 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2810
2811 vlv_dpio_put(dev_priv);
2812}
2813
2814static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
2815 struct intel_encoder *encoder,
2816 const struct intel_crtc_state *pipe_config,
2817 const struct drm_connector_state *conn_state)
2818{
2819 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2820 struct drm_device *dev = encoder->base.dev;
2821 struct drm_i915_private *dev_priv = to_i915(dev);
2822
2823 chv_phy_pre_encoder_enable(encoder, pipe_config);
2824
2825 /* FIXME: Program the support xxx V-dB */
2826 /* Use 800mV-0dB */
2827 chv_set_phy_signal_level(encoder, 128, 102, false);
2828
2829 dig_port->set_infoframes(encoder,
2830 pipe_config->has_infoframe,
2831 pipe_config, conn_state);
2832
2833 g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
2834
2835 vlv_wait_port_ready(dev_priv, dig_port, 0x0);
2836
2837 /* Second common lane will stay alive on its own now */
2838 chv_phy_release_cl2_override(encoder);
2839}
2840
2841static struct i2c_adapter *
2842intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2843{
2844 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2845 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2846
2847 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2848}
2849
2850static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2851{
2852 struct drm_i915_private *i915 = to_i915(connector->dev);
2853 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2854 struct kobject *i2c_kobj = &adapter->dev.kobj;
2855 struct kobject *connector_kobj = &connector->kdev->kobj;
2856 int ret;
2857
2858 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2859 if (ret)
2860 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2861}
2862
2863static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2864{
2865 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2866 struct kobject *i2c_kobj = &adapter->dev.kobj;
2867 struct kobject *connector_kobj = &connector->kdev->kobj;
2868
2869 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2870}
2871
2872static int
2873intel_hdmi_connector_register(struct drm_connector *connector)
2874{
2875 int ret;
2876
2877 ret = intel_connector_register(connector);
2878 if (ret)
2879 return ret;
2880
2881 intel_hdmi_create_i2c_symlink(connector);
2882
2883 return ret;
2884}
2885
2886static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2887{
2888 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2889
2890 cec_notifier_conn_unregister(n);
2891
2892 intel_hdmi_remove_i2c_symlink(connector);
2893 intel_connector_unregister(connector);
2894}
2895
2896static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2897 .detect = intel_hdmi_detect,
2898 .force = intel_hdmi_force,
2899 .fill_modes = drm_helper_probe_single_connector_modes,
2900 .atomic_get_property = intel_digital_connector_atomic_get_property,
2901 .atomic_set_property = intel_digital_connector_atomic_set_property,
2902 .late_register = intel_hdmi_connector_register,
2903 .early_unregister = intel_hdmi_connector_unregister,
2904 .destroy = intel_connector_destroy,
2905 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2906 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2907};
2908
2909static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2910 .get_modes = intel_hdmi_get_modes,
2911 .mode_valid = intel_hdmi_mode_valid,
2912 .atomic_check = intel_digital_connector_atomic_check,
2913};
2914
2915static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2916 .destroy = intel_encoder_destroy,
2917};
2918
2919static void
2920intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2921{
2922 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2923 struct intel_digital_port *dig_port =
2924 hdmi_to_dig_port(intel_hdmi);
2925
2926 intel_attach_force_audio_property(connector);
2927 intel_attach_broadcast_rgb_property(connector);
2928 intel_attach_aspect_ratio_property(connector);
2929
2930 /*
2931 * Attach Colorspace property for Non LSPCON based device
2932 * ToDo: This needs to be extended for LSPCON implementation
2933 * as well. Will be implemented separately.
2934 */
2935 if (!dig_port->lspcon.active)
2936 intel_attach_colorspace_property(connector);
2937
2938 drm_connector_attach_content_type_property(connector);
2939
2940 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2941 drm_object_attach_property(&connector->base,
2942 connector->dev->mode_config.hdr_output_metadata_property, 0);
2943
2944 if (!HAS_GMCH(dev_priv))
2945 drm_connector_attach_max_bpc_property(connector, 8, 12);
2946}
2947
2948/*
2949 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2950 * @encoder: intel_encoder
2951 * @connector: drm_connector
2952 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2953 * or reset the high tmds clock ratio for scrambling
2954 * @scrambling: bool to Indicate if the function needs to set or reset
2955 * sink scrambling
2956 *
2957 * This function handles scrambling on HDMI 2.0 capable sinks.
2958 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2959 * it enables scrambling. This should be called before enabling the HDMI
2960 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2961 * detect a scrambled clock within 100 ms.
2962 *
2963 * Returns:
2964 * True on success, false on failure.
2965 */
2966bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2967 struct drm_connector *connector,
2968 bool high_tmds_clock_ratio,
2969 bool scrambling)
2970{
2971 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2972 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2973 struct drm_scrambling *sink_scrambling =
2974 &connector->display_info.hdmi.scdc.scrambling;
2975 struct i2c_adapter *adapter =
2976 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2977
2978 if (!sink_scrambling->supported)
2979 return true;
2980
2981 drm_dbg_kms(&dev_priv->drm,
2982 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2983 connector->base.id, connector->name,
2984 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2985
2986 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2987 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2988 high_tmds_clock_ratio) &&
2989 drm_scdc_set_scrambling(adapter, scrambling);
2990}
2991
2992static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2993{
2994 u8 ddc_pin;
2995
2996 switch (port) {
2997 case PORT_B:
2998 ddc_pin = GMBUS_PIN_DPB;
2999 break;
3000 case PORT_C:
3001 ddc_pin = GMBUS_PIN_DPC;
3002 break;
3003 case PORT_D:
3004 ddc_pin = GMBUS_PIN_DPD_CHV;
3005 break;
3006 default:
3007 MISSING_CASE(port);
3008 ddc_pin = GMBUS_PIN_DPB;
3009 break;
3010 }
3011 return ddc_pin;
3012}
3013
3014static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3015{
3016 u8 ddc_pin;
3017
3018 switch (port) {
3019 case PORT_B:
3020 ddc_pin = GMBUS_PIN_1_BXT;
3021 break;
3022 case PORT_C:
3023 ddc_pin = GMBUS_PIN_2_BXT;
3024 break;
3025 default:
3026 MISSING_CASE(port);
3027 ddc_pin = GMBUS_PIN_1_BXT;
3028 break;
3029 }
3030 return ddc_pin;
3031}
3032
3033static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3034 enum port port)
3035{
3036 u8 ddc_pin;
3037
3038 switch (port) {
3039 case PORT_B:
3040 ddc_pin = GMBUS_PIN_1_BXT;
3041 break;
3042 case PORT_C:
3043 ddc_pin = GMBUS_PIN_2_BXT;
3044 break;
3045 case PORT_D:
3046 ddc_pin = GMBUS_PIN_4_CNP;
3047 break;
3048 case PORT_F:
3049 ddc_pin = GMBUS_PIN_3_BXT;
3050 break;
3051 default:
3052 MISSING_CASE(port);
3053 ddc_pin = GMBUS_PIN_1_BXT;
3054 break;
3055 }
3056 return ddc_pin;
3057}
3058
3059static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3060{
3061 enum phy phy = intel_port_to_phy(dev_priv, port);
3062
3063 if (intel_phy_is_combo(dev_priv, phy))
3064 return GMBUS_PIN_1_BXT + port;
3065 else if (intel_phy_is_tc(dev_priv, phy))
3066 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
3067
3068 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
3069 return GMBUS_PIN_2_BXT;
3070}
3071
3072static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3073{
3074 enum phy phy = intel_port_to_phy(dev_priv, port);
3075 u8 ddc_pin;
3076
3077 switch (phy) {
3078 case PHY_A:
3079 ddc_pin = GMBUS_PIN_1_BXT;
3080 break;
3081 case PHY_B:
3082 ddc_pin = GMBUS_PIN_2_BXT;
3083 break;
3084 case PHY_C:
3085 ddc_pin = GMBUS_PIN_9_TC1_ICP;
3086 break;
3087 default:
3088 MISSING_CASE(phy);
3089 ddc_pin = GMBUS_PIN_1_BXT;
3090 break;
3091 }
3092 return ddc_pin;
3093}
3094
3095static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3096{
3097 enum phy phy = intel_port_to_phy(dev_priv, port);
3098
3099 WARN_ON(port == PORT_C);
3100
3101 /*
3102 * Pin mapping for RKL depends on which PCH is present. With TGP, the
3103 * final two outputs use type-c pins, even though they're actually
3104 * combo outputs. With CMP, the traditional DDI A-D pins are used for
3105 * all outputs.
3106 */
3107 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
3108 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
3109
3110 return GMBUS_PIN_1_BXT + phy;
3111}
3112
3113static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3114 enum port port)
3115{
3116 u8 ddc_pin;
3117
3118 switch (port) {
3119 case PORT_B:
3120 ddc_pin = GMBUS_PIN_DPB;
3121 break;
3122 case PORT_C:
3123 ddc_pin = GMBUS_PIN_DPC;
3124 break;
3125 case PORT_D:
3126 ddc_pin = GMBUS_PIN_DPD;
3127 break;
3128 default:
3129 MISSING_CASE(port);
3130 ddc_pin = GMBUS_PIN_DPB;
3131 break;
3132 }
3133 return ddc_pin;
3134}
3135
3136static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
3137{
3138 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3139 enum port port = encoder->port;
3140 u8 ddc_pin;
3141
3142 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
3143 if (ddc_pin) {
3144 drm_dbg_kms(&dev_priv->drm,
3145 "Using DDC pin 0x%x for port %c (VBT)\n",
3146 ddc_pin, port_name(port));
3147 return ddc_pin;
3148 }
3149
3150 if (IS_ROCKETLAKE(dev_priv))
3151 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
3152 else if (HAS_PCH_MCC(dev_priv))
3153 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3154 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3155 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3156 else if (HAS_PCH_CNP(dev_priv))
3157 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3158 else if (IS_GEN9_LP(dev_priv))
3159 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3160 else if (IS_CHERRYVIEW(dev_priv))
3161 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3162 else
3163 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3164
3165 drm_dbg_kms(&dev_priv->drm,
3166 "Using DDC pin 0x%x for port %c (platform default)\n",
3167 ddc_pin, port_name(port));
3168
3169 return ddc_pin;
3170}
3171
3172void intel_infoframe_init(struct intel_digital_port *dig_port)
3173{
3174 struct drm_i915_private *dev_priv =
3175 to_i915(dig_port->base.base.dev);
3176
3177 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3178 dig_port->write_infoframe = vlv_write_infoframe;
3179 dig_port->read_infoframe = vlv_read_infoframe;
3180 dig_port->set_infoframes = vlv_set_infoframes;
3181 dig_port->infoframes_enabled = vlv_infoframes_enabled;
3182 } else if (IS_G4X(dev_priv)) {
3183 dig_port->write_infoframe = g4x_write_infoframe;
3184 dig_port->read_infoframe = g4x_read_infoframe;
3185 dig_port->set_infoframes = g4x_set_infoframes;
3186 dig_port->infoframes_enabled = g4x_infoframes_enabled;
3187 } else if (HAS_DDI(dev_priv)) {
3188 if (dig_port->lspcon.active) {
3189 dig_port->write_infoframe = lspcon_write_infoframe;
3190 dig_port->read_infoframe = lspcon_read_infoframe;
3191 dig_port->set_infoframes = lspcon_set_infoframes;
3192 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3193 } else {
3194 dig_port->write_infoframe = hsw_write_infoframe;
3195 dig_port->read_infoframe = hsw_read_infoframe;
3196 dig_port->set_infoframes = hsw_set_infoframes;
3197 dig_port->infoframes_enabled = hsw_infoframes_enabled;
3198 }
3199 } else if (HAS_PCH_IBX(dev_priv)) {
3200 dig_port->write_infoframe = ibx_write_infoframe;
3201 dig_port->read_infoframe = ibx_read_infoframe;
3202 dig_port->set_infoframes = ibx_set_infoframes;
3203 dig_port->infoframes_enabled = ibx_infoframes_enabled;
3204 } else {
3205 dig_port->write_infoframe = cpt_write_infoframe;
3206 dig_port->read_infoframe = cpt_read_infoframe;
3207 dig_port->set_infoframes = cpt_set_infoframes;
3208 dig_port->infoframes_enabled = cpt_infoframes_enabled;
3209 }
3210}
3211
3212void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
3213 struct intel_connector *intel_connector)
3214{
3215 struct drm_connector *connector = &intel_connector->base;
3216 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3217 struct intel_encoder *intel_encoder = &dig_port->base;
3218 struct drm_device *dev = intel_encoder->base.dev;
3219 struct drm_i915_private *dev_priv = to_i915(dev);
3220 struct i2c_adapter *ddc;
3221 enum port port = intel_encoder->port;
3222 struct cec_connector_info conn_info;
3223
3224 drm_dbg_kms(&dev_priv->drm,
3225 "Adding HDMI connector on [ENCODER:%d:%s]\n",
3226 intel_encoder->base.base.id, intel_encoder->base.name);
3227
3228 if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
3229 return;
3230
3231 if (drm_WARN(dev, dig_port->max_lanes < 4,
3232 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3233 dig_port->max_lanes, intel_encoder->base.base.id,
3234 intel_encoder->base.name))
3235 return;
3236
3237 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
3238 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
3239
3240 drm_connector_init_with_ddc(dev, connector,
3241 &intel_hdmi_connector_funcs,
3242 DRM_MODE_CONNECTOR_HDMIA,
3243 ddc);
3244 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3245
3246 connector->interlace_allowed = 1;
3247 connector->doublescan_allowed = 0;
3248 connector->stereo_allowed = 1;
3249
3250 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3251 connector->ycbcr_420_allowed = true;
3252
3253 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3254 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
3255
3256 if (HAS_DDI(dev_priv))
3257 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3258 else
3259 intel_connector->get_hw_state = intel_connector_get_hw_state;
3260
3261 intel_hdmi_add_properties(intel_hdmi, connector);
3262
3263 intel_connector_attach_encoder(intel_connector, intel_encoder);
3264 intel_hdmi->attached_connector = intel_connector;
3265
3266 if (is_hdcp_supported(dev_priv, port)) {
3267 int ret = intel_hdcp_init(intel_connector,
3268 &intel_hdmi_hdcp_shim);
3269 if (ret)
3270 drm_dbg_kms(&dev_priv->drm,
3271 "HDCP init failed, skipping.\n");
3272 }
3273
3274 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3275 * 0xd. Failure to do so will result in spurious interrupts being
3276 * generated on the port when a cable is not attached.
3277 */
3278 if (IS_G45(dev_priv)) {
3279 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
3280 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
3281 (temp & ~0xf) | 0xd);
3282 }
3283
3284 cec_fill_conn_info_from_drm(&conn_info, connector);
3285
3286 intel_hdmi->cec_notifier =
3287 cec_notifier_conn_register(dev->dev, port_identifier(port),
3288 &conn_info);
3289 if (!intel_hdmi->cec_notifier)
3290 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3291}
3292
3293static enum intel_hotplug_state
3294intel_hdmi_hotplug(struct intel_encoder *encoder,
3295 struct intel_connector *connector)
3296{
3297 enum intel_hotplug_state state;
3298
3299 state = intel_encoder_hotplug(encoder, connector);
3300
3301 /*
3302 * On many platforms the HDMI live state signal is known to be
3303 * unreliable, so we can't use it to detect if a sink is connected or
3304 * not. Instead we detect if it's connected based on whether we can
3305 * read the EDID or not. That in turn has a problem during disconnect,
3306 * since the HPD interrupt may be raised before the DDC lines get
3307 * disconnected (due to how the required length of DDC vs. HPD
3308 * connector pins are specified) and so we'll still be able to get a
3309 * valid EDID. To solve this schedule another detection cycle if this
3310 * time around we didn't detect any change in the sink's connection
3311 * status.
3312 */
3313 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
3314 state = INTEL_HOTPLUG_RETRY;
3315
3316 return state;
3317}
3318
3319void intel_hdmi_init(struct drm_i915_private *dev_priv,
3320 i915_reg_t hdmi_reg, enum port port)
3321{
3322 struct intel_digital_port *dig_port;
3323 struct intel_encoder *intel_encoder;
3324 struct intel_connector *intel_connector;
3325
3326 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
3327 if (!dig_port)
3328 return;
3329
3330 intel_connector = intel_connector_alloc();
3331 if (!intel_connector) {
3332 kfree(dig_port);
3333 return;
3334 }
3335
3336 intel_encoder = &dig_port->base;
3337
3338 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3339 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3340 "HDMI %c", port_name(port));
3341
3342 intel_encoder->hotplug = intel_hdmi_hotplug;
3343 intel_encoder->compute_config = intel_hdmi_compute_config;
3344 if (HAS_PCH_SPLIT(dev_priv)) {
3345 intel_encoder->disable = pch_disable_hdmi;
3346 intel_encoder->post_disable = pch_post_disable_hdmi;
3347 } else {
3348 intel_encoder->disable = g4x_disable_hdmi;
3349 }
3350 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3351 intel_encoder->get_config = intel_hdmi_get_config;
3352 if (IS_CHERRYVIEW(dev_priv)) {
3353 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3354 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3355 intel_encoder->enable = vlv_enable_hdmi;
3356 intel_encoder->post_disable = chv_hdmi_post_disable;
3357 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3358 } else if (IS_VALLEYVIEW(dev_priv)) {
3359 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3360 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3361 intel_encoder->enable = vlv_enable_hdmi;
3362 intel_encoder->post_disable = vlv_hdmi_post_disable;
3363 } else {
3364 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3365 if (HAS_PCH_CPT(dev_priv))
3366 intel_encoder->enable = cpt_enable_hdmi;
3367 else if (HAS_PCH_IBX(dev_priv))
3368 intel_encoder->enable = ibx_enable_hdmi;
3369 else
3370 intel_encoder->enable = g4x_enable_hdmi;
3371 }
3372
3373 intel_encoder->type = INTEL_OUTPUT_HDMI;
3374 intel_encoder->power_domain = intel_port_to_power_domain(port);
3375 intel_encoder->port = port;
3376 if (IS_CHERRYVIEW(dev_priv)) {
3377 if (port == PORT_D)
3378 intel_encoder->pipe_mask = BIT(PIPE_C);
3379 else
3380 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
3381 } else {
3382 intel_encoder->pipe_mask = ~0;
3383 }
3384 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3385 /*
3386 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3387 * to work on real hardware. And since g4x can send infoframes to
3388 * only one port anyway, nothing is lost by allowing it.
3389 */
3390 if (IS_G4X(dev_priv))
3391 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3392
3393 dig_port->hdmi.hdmi_reg = hdmi_reg;
3394 dig_port->dp.output_reg = INVALID_MMIO_REG;
3395 dig_port->max_lanes = 4;
3396
3397 intel_infoframe_init(dig_port);
3398
3399 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3400 intel_hdmi_init_connector(dig_port, intel_connector);
3401}