1/*
   2 * Copyright © 2014 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21 * DEALINGS IN THE SOFTWARE.
  22 */
  23
  24/**
  25 * DOC: Frame Buffer Compression (FBC)
  26 *
  27 * FBC tries to save memory bandwidth (and so power consumption) by
  28 * compressing the amount of memory used by the display. It is total
  29 * transparent to user space and completely handled in the kernel.
  30 *
  31 * The benefits of FBC are mostly visible with solid backgrounds and
  32 * variation-less patterns. It comes from keeping the memory footprint small
  33 * and having fewer memory pages opened and accessed for refreshing the display.
  34 *
  35 * i915 is responsible to reserve stolen memory for FBC and configure its
  36 * offset on proper registers. The hardware takes care of all
  37 * compress/decompress. However there are many known cases where we have to
  38 * forcibly disable it to allow proper screen updates.
  39 */
  40
  41#include <drm/drm_fourcc.h>
  42
  43#include "i915_drv.h"
  44#include "i915_trace.h"
  45#include "i915_vgpu.h"
  46#include "intel_de.h"
  47#include "intel_display_types.h"
  48#include "intel_fbc.h"
  49#include "intel_frontbuffer.h"
  50
  51/*
  52 * For SKL+, the plane source size used by the hardware is based on the value we
  53 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  54 * we wrote to PIPESRC.
  55 */
  56static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
  57					    int *width, int *height)
  58{
  59	if (width)
  60		*width = cache->plane.src_w;
  61	if (height)
  62		*height = cache->plane.src_h;
  63}
  64
  65static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  66					const struct intel_fbc_state_cache *cache)
  67{
  68	int lines;
  69
  70	intel_fbc_get_plane_source_size(cache, NULL, &lines);
  71	if (DISPLAY_VER(dev_priv) == 7)
  72		lines = min(lines, 2048);
  73	else if (DISPLAY_VER(dev_priv) >= 8)
  74		lines = min(lines, 2560);
  75
  76	/* Hardware needs the full buffer stride, not just the active area. */
  77	return lines * cache->fb.stride;
  78}
  79
  80static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  81{
  82	u32 fbc_ctl;
  83
  84	/* Disable compression */
  85	fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
  86	if ((fbc_ctl & FBC_CTL_EN) == 0)
  87		return;
  88
  89	fbc_ctl &= ~FBC_CTL_EN;
  90	intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
  91
  92	/* Wait for compressing bit to clear */
  93	if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
  94				    FBC_STAT_COMPRESSING, 10)) {
  95		drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n");
  96		return;
  97	}
  98}
  99
 100static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 101{
 102	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 103	int cfb_pitch;
 104	int i;
 105	u32 fbc_ctl;
 106
 107	/* Note: fbc.threshold == 1 for i8xx */
 108	cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 109	if (params->fb.stride < cfb_pitch)
 110		cfb_pitch = params->fb.stride;
 111
 112	/* FBC_CTL wants 32B or 64B units */
 113	if (DISPLAY_VER(dev_priv) == 2)
 114		cfb_pitch = (cfb_pitch / 32) - 1;
 115	else
 116		cfb_pitch = (cfb_pitch / 64) - 1;
 117
 118	/* Clear old tags */
 119	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 120		intel_de_write(dev_priv, FBC_TAG(i), 0);
 121
 122	if (DISPLAY_VER(dev_priv) == 4) {
 123		u32 fbc_ctl2;
 124
 125		/* Set it up... */
 126		fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM;
 127		fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 128		if (params->fence_id >= 0)
 129			fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 130		intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
 131		intel_de_write(dev_priv, FBC_FENCE_OFF,
 132			       params->fence_y_offset);
 133	}
 134
 135	/* enable it... */
 136	fbc_ctl = FBC_CTL_INTERVAL(params->interval);
 137	fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 138	if (IS_I945GM(dev_priv))
 139		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 140	fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff);
 141	if (params->fence_id >= 0)
 142		fbc_ctl |= FBC_CTL_FENCENO(params->fence_id);
 143	intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
 144}
 145
 146static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 147{
 148	return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN;
 149}
 150
 151static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 152{
 153	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 154	u32 dpfc_ctl;
 155
 156	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 157	if (params->fb.format->cpp[0] == 2)
 158		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 159	else
 160		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 161
 162	if (params->fence_id >= 0) {
 163		dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
 164		intel_de_write(dev_priv, DPFC_FENCE_YOFF,
 165			       params->fence_y_offset);
 166	} else {
 167		intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
 168	}
 169
 170	/* enable it... */
 171	intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 172}
 173
 174static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 175{
 176	u32 dpfc_ctl;
 177
 178	/* Disable compression */
 179	dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL);
 180	if (dpfc_ctl & DPFC_CTL_EN) {
 181		dpfc_ctl &= ~DPFC_CTL_EN;
 182		intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl);
 183	}
 184}
 185
 186static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 187{
 188	return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
 189}
 190
 191static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
 192{
 193	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 194	enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
 195
 196	spin_lock_irq(&dev_priv->uncore.lock);
 197	intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
 198			  intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
 199	spin_unlock_irq(&dev_priv->uncore.lock);
 200}
 201
 202static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
 203{
 204	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 205	enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
 206
 207	spin_lock_irq(&dev_priv->uncore.lock);
 208	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
 209			  intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
 210	spin_unlock_irq(&dev_priv->uncore.lock);
 211}
 212
 213/* This function forces a CFB recompression through the nuke operation. */
 214static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
 215{
 216	struct intel_fbc *fbc = &dev_priv->fbc;
 217
 218	trace_intel_fbc_nuke(fbc->crtc);
 219
 220	intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
 221	intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
 222}
 223
 224static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 225{
 226	if (DISPLAY_VER(dev_priv) >= 6)
 227		snb_fbc_recompress(dev_priv);
 228	else if (DISPLAY_VER(dev_priv) >= 4)
 229		i965_fbc_recompress(dev_priv);
 230	else
 231		i8xx_fbc_recompress(dev_priv);
 232}
 233
 234static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 235{
 236	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 237	u32 dpfc_ctl;
 238	int threshold = dev_priv->fbc.threshold;
 239
 240	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 241	if (params->fb.format->cpp[0] == 2)
 242		threshold++;
 243
 244	switch (threshold) {
 245	case 4:
 246	case 3:
 247		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 248		break;
 249	case 2:
 250		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 251		break;
 252	case 1:
 253		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 254		break;
 255	}
 256
 257	if (params->fence_id >= 0) {
 258		dpfc_ctl |= DPFC_CTL_FENCE_EN;
 259		if (IS_IRONLAKE(dev_priv))
 260			dpfc_ctl |= params->fence_id;
 261		if (IS_SANDYBRIDGE(dev_priv)) {
 262			intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 263				       SNB_CPU_FENCE_ENABLE | params->fence_id);
 264			intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 265				       params->fence_y_offset);
 266		}
 267	} else {
 268		if (IS_SANDYBRIDGE(dev_priv)) {
 269			intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 270			intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 271		}
 272	}
 273
 274	intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
 275		       params->fence_y_offset);
 276	/* enable it... */
 277	intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 278
 279	intel_fbc_recompress(dev_priv);
 280}
 281
 282static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 283{
 284	u32 dpfc_ctl;
 285
 286	/* Disable compression */
 287	dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
 288	if (dpfc_ctl & DPFC_CTL_EN) {
 289		dpfc_ctl &= ~DPFC_CTL_EN;
 290		intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl);
 291	}
 292}
 293
 294static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 295{
 296	return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 297}
 298
 299static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 300{
 301	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 302	u32 dpfc_ctl;
 303	int threshold = dev_priv->fbc.threshold;
 304
 305	/* Display WA #0529: skl, kbl, bxt. */
 306	if (DISPLAY_VER(dev_priv) == 9) {
 307		u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
 308
 309		val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 310
 311		if (params->gen9_wa_cfb_stride)
 312			val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 313
 314		intel_de_write(dev_priv, CHICKEN_MISC_4, val);
 315	}
 316
 317	dpfc_ctl = 0;
 318	if (IS_IVYBRIDGE(dev_priv))
 319		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 320
 321	if (params->fb.format->cpp[0] == 2)
 322		threshold++;
 323
 324	switch (threshold) {
 325	case 4:
 326	case 3:
 327		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 328		break;
 329	case 2:
 330		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 331		break;
 332	case 1:
 333		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 334		break;
 335	}
 336
 337	if (params->fence_id >= 0) {
 338		dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 339		intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 340			       SNB_CPU_FENCE_ENABLE | params->fence_id);
 341		intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 342			       params->fence_y_offset);
 343	} else if (dev_priv->ggtt.num_fences) {
 344		intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 345		intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 346	}
 347
 348	if (dev_priv->fbc.false_color)
 349		dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 350
 351	intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 352
 353	intel_fbc_recompress(dev_priv);
 354}
 355
 356static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 357{
 358	if (DISPLAY_VER(dev_priv) >= 5)
 359		return ilk_fbc_is_active(dev_priv);
 360	else if (IS_GM45(dev_priv))
 361		return g4x_fbc_is_active(dev_priv);
 362	else
 363		return i8xx_fbc_is_active(dev_priv);
 364}
 365
 366static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 367{
 368	struct intel_fbc *fbc = &dev_priv->fbc;
 369
 370	trace_intel_fbc_activate(fbc->crtc);
 371
 372	fbc->active = true;
 373	fbc->activated = true;
 374
 375	if (DISPLAY_VER(dev_priv) >= 7)
 376		gen7_fbc_activate(dev_priv);
 377	else if (DISPLAY_VER(dev_priv) >= 5)
 378		ilk_fbc_activate(dev_priv);
 379	else if (IS_GM45(dev_priv))
 380		g4x_fbc_activate(dev_priv);
 381	else
 382		i8xx_fbc_activate(dev_priv);
 383}
 384
 385static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 386{
 387	struct intel_fbc *fbc = &dev_priv->fbc;
 388
 389	trace_intel_fbc_deactivate(fbc->crtc);
 390
 391	fbc->active = false;
 392
 393	if (DISPLAY_VER(dev_priv) >= 5)
 394		ilk_fbc_deactivate(dev_priv);
 395	else if (IS_GM45(dev_priv))
 396		g4x_fbc_deactivate(dev_priv);
 397	else
 398		i8xx_fbc_deactivate(dev_priv);
 399}
 400
 401/**
 402 * intel_fbc_is_active - Is FBC active?
 403 * @dev_priv: i915 device instance
 404 *
 405 * This function is used to verify the current state of FBC.
 406 *
 407 * FIXME: This should be tracked in the plane config eventually
 408 * instead of queried at runtime for most callers.
 409 */
 410bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 411{
 412	return dev_priv->fbc.active;
 413}
 414
 415static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 416				 const char *reason)
 417{
 418	struct intel_fbc *fbc = &dev_priv->fbc;
 419
 420	drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
 421
 422	if (fbc->active)
 423		intel_fbc_hw_deactivate(dev_priv);
 424
 425	fbc->no_fbc_reason = reason;
 426}
 427
 428static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
 429{
 430	if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
 431		return BIT_ULL(28);
 432	else
 433		return BIT_ULL(32);
 434}
 435
 436static int find_compression_threshold(struct drm_i915_private *dev_priv,
 437				      struct drm_mm_node *node,
 438				      unsigned int size,
 439				      unsigned int fb_cpp)
 440{
 441	int compression_threshold = 1;
 442	int ret;
 443	u64 end;
 444
 445	/* The FBC hardware for BDW/SKL doesn't have access to the stolen
 446	 * reserved range size, so it always assumes the maximum (8mb) is used.
 447	 * If we enable FBC using a CFB on that memory range we'll get FIFO
 448	 * underruns, even if that range is not reserved by the BIOS. */
 449	if (IS_BROADWELL(dev_priv) || (DISPLAY_VER(dev_priv) == 9 &&
 450				       !IS_BROXTON(dev_priv)))
 451		end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 452	else
 453		end = U64_MAX;
 454
 455	end = min(end, intel_fbc_cfb_base_max(dev_priv));
 456
 457	/* HACK: This code depends on what we will do in *_enable_fbc. If that
 458	 * code changes, this code needs to change as well.
 459	 *
 460	 * The enable_fbc code will attempt to use one of our 2 compression
 461	 * thresholds, therefore, in that case, we only have 1 resort.
 462	 */
 463
 464	/* Try to over-allocate to reduce reallocations and fragmentation. */
 465	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 466						   4096, 0, end);
 467	if (ret == 0)
 468		return compression_threshold;
 469
 470again:
 471	/* HW's ability to limit the CFB is 1:4 */
 472	if (compression_threshold > 4 ||
 473	    (fb_cpp == 2 && compression_threshold == 2))
 474		return 0;
 475
 476	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 477						   4096, 0, end);
 478	if (ret && DISPLAY_VER(dev_priv) <= 4) {
 479		return 0;
 480	} else if (ret) {
 481		compression_threshold <<= 1;
 482		goto again;
 483	} else {
 484		return compression_threshold;
 485	}
 486}
 487
 488static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
 489			       unsigned int size, unsigned int fb_cpp)
 490{
 491	struct intel_fbc *fbc = &dev_priv->fbc;
 492	struct drm_mm_node *compressed_llb;
 493	int ret;
 494
 495	drm_WARN_ON(&dev_priv->drm,
 496		    drm_mm_node_allocated(&fbc->compressed_fb));
 497
 498	ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 499					 size, fb_cpp);
 500	if (!ret)
 501		goto err_llb;
 502	else if (ret > 1) {
 503		drm_info_once(&dev_priv->drm,
 504			      "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 505	}
 506
 507	fbc->threshold = ret;
 508
 509	if (DISPLAY_VER(dev_priv) >= 5)
 510		intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
 511			       fbc->compressed_fb.start);
 512	else if (IS_GM45(dev_priv)) {
 513		intel_de_write(dev_priv, DPFC_CB_BASE,
 514			       fbc->compressed_fb.start);
 515	} else {
 516		compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 517		if (!compressed_llb)
 518			goto err_fb;
 519
 520		ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 521						  4096, 4096);
 522		if (ret)
 523			goto err_fb;
 524
 525		fbc->compressed_llb = compressed_llb;
 526
 527		GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 528						 fbc->compressed_fb.start,
 529						 U32_MAX));
 530		GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 531						 fbc->compressed_llb->start,
 532						 U32_MAX));
 533		intel_de_write(dev_priv, FBC_CFB_BASE,
 534			       dev_priv->dsm.start + fbc->compressed_fb.start);
 535		intel_de_write(dev_priv, FBC_LL_BASE,
 536			       dev_priv->dsm.start + compressed_llb->start);
 537	}
 538
 539	drm_dbg_kms(&dev_priv->drm,
 540		    "reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 541		    fbc->compressed_fb.size, fbc->threshold);
 542
 543	return 0;
 544
 545err_fb:
 546	kfree(compressed_llb);
 547	i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 548err_llb:
 549	if (drm_mm_initialized(&dev_priv->mm.stolen))
 550		drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 551	return -ENOSPC;
 552}
 553
 554static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 555{
 556	struct intel_fbc *fbc = &dev_priv->fbc;
 557
 558	if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
 559		return;
 560
 561	if (!drm_mm_node_allocated(&fbc->compressed_fb))
 562		return;
 563
 564	if (fbc->compressed_llb) {
 565		i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 566		kfree(fbc->compressed_llb);
 567	}
 568
 569	i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 570}
 571
 572void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 573{
 574	struct intel_fbc *fbc = &dev_priv->fbc;
 575
 576	if (!HAS_FBC(dev_priv))
 577		return;
 578
 579	mutex_lock(&fbc->lock);
 580	__intel_fbc_cleanup_cfb(dev_priv);
 581	mutex_unlock(&fbc->lock);
 582}
 583
 584static bool stride_is_valid(struct drm_i915_private *dev_priv,
 585			    u64 modifier, unsigned int stride)
 586{
 587	/* This should have been caught earlier. */
 588	if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0))
 589		return false;
 590
 591	/* Below are the additional FBC restrictions. */
 592	if (stride < 512)
 593		return false;
 594
 595	if (DISPLAY_VER(dev_priv) == 2 || DISPLAY_VER(dev_priv) == 3)
 596		return stride == 4096 || stride == 8192;
 597
 598	if (DISPLAY_VER(dev_priv) == 4 && !IS_G4X(dev_priv) && stride < 2048)
 599		return false;
 600
 601	/* Display WA #1105: skl,bxt,kbl,cfl,glk */
 602	if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
 603	    modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
 604		return false;
 605
 606	if (stride > 16384)
 607		return false;
 608
 609	return true;
 610}
 611
 612static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 613				  u32 pixel_format)
 614{
 615	switch (pixel_format) {
 616	case DRM_FORMAT_XRGB8888:
 617	case DRM_FORMAT_XBGR8888:
 618		return true;
 619	case DRM_FORMAT_XRGB1555:
 620	case DRM_FORMAT_RGB565:
 621		/* 16bpp not supported on gen2 */
 622		if (DISPLAY_VER(dev_priv) == 2)
 623			return false;
 624		/* WaFbcOnly1to1Ratio:ctg */
 625		if (IS_G4X(dev_priv))
 626			return false;
 627		return true;
 628	default:
 629		return false;
 630	}
 631}
 632
 633static bool rotation_is_valid(struct drm_i915_private *dev_priv,
 634			      u32 pixel_format, unsigned int rotation)
 635{
 636	if (DISPLAY_VER(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
 637	    drm_rotation_90_or_270(rotation))
 638		return false;
 639	else if (DISPLAY_VER(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 640		 rotation != DRM_MODE_ROTATE_0)
 641		return false;
 642
 643	return true;
 644}
 645
 646/*
 647 * For some reason, the hardware tracking starts looking at whatever we
 648 * programmed as the display plane base address register. It does not look at
 649 * the X and Y offset registers. That's why we include the src x/y offsets
 650 * instead of just looking at the plane size.
 651 */
 652static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 653{
 654	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 655	struct intel_fbc *fbc = &dev_priv->fbc;
 656	unsigned int effective_w, effective_h, max_w, max_h;
 657
 658	if (DISPLAY_VER(dev_priv) >= 10) {
 659		max_w = 5120;
 660		max_h = 4096;
 661	} else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 662		max_w = 4096;
 663		max_h = 4096;
 664	} else if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) {
 665		max_w = 4096;
 666		max_h = 2048;
 667	} else {
 668		max_w = 2048;
 669		max_h = 1536;
 670	}
 671
 672	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 673					&effective_h);
 674	effective_w += fbc->state_cache.plane.adjusted_x;
 675	effective_h += fbc->state_cache.plane.adjusted_y;
 676
 677	return effective_w <= max_w && effective_h <= max_h;
 678}
 679
 680static bool tiling_is_valid(struct drm_i915_private *dev_priv,
 681			    u64 modifier)
 682{
 683	switch (modifier) {
 684	case DRM_FORMAT_MOD_LINEAR:
 685		if (DISPLAY_VER(dev_priv) >= 9)
 686			return true;
 687		return false;
 688	case I915_FORMAT_MOD_X_TILED:
 689	case I915_FORMAT_MOD_Y_TILED:
 690		return true;
 691	default:
 692		return false;
 693	}
 694}
 695
 696static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 697					 const struct intel_crtc_state *crtc_state,
 698					 const struct intel_plane_state *plane_state)
 699{
 700	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 701	struct intel_fbc *fbc = &dev_priv->fbc;
 702	struct intel_fbc_state_cache *cache = &fbc->state_cache;
 703	struct drm_framebuffer *fb = plane_state->hw.fb;
 704
 705	cache->plane.visible = plane_state->uapi.visible;
 706	if (!cache->plane.visible)
 707		return;
 708
 709	cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
 710	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 711		cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 712
 713	cache->plane.rotation = plane_state->hw.rotation;
 714	/*
 715	 * Src coordinates are already rotated by 270 degrees for
 716	 * the 90/270 degree plane rotation cases (to match the
 717	 * GTT mapping), hence no need to account for rotation here.
 718	 */
 719	cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 720	cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 721	cache->plane.adjusted_x = plane_state->view.color_plane[0].x;
 722	cache->plane.adjusted_y = plane_state->view.color_plane[0].y;
 723
 724	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 725
 726	cache->fb.format = fb->format;
 727	cache->fb.modifier = fb->modifier;
 728
 729	/* FIXME is this correct? */
 730	cache->fb.stride = plane_state->view.color_plane[0].stride;
 731	if (drm_rotation_90_or_270(plane_state->hw.rotation))
 732		cache->fb.stride *= fb->format->cpp[0];
 733
 734	/* FBC1 compression interval: arbitrary choice of 1 second */
 735	cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
 736
 737	cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
 738
 739	drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
 740		    !plane_state->ggtt_vma->fence);
 741
 742	if (plane_state->flags & PLANE_HAS_FENCE &&
 743	    plane_state->ggtt_vma->fence)
 744		cache->fence_id = plane_state->ggtt_vma->fence->id;
 745	else
 746		cache->fence_id = -1;
 747
 748	cache->psr2_active = crtc_state->has_psr2;
 749}
 750
 751static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
 752{
 753	struct intel_fbc *fbc = &dev_priv->fbc;
 754
 755	return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 756		fbc->compressed_fb.size * fbc->threshold;
 757}
 758
 759static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
 760{
 761	struct intel_fbc *fbc = &dev_priv->fbc;
 762	struct intel_fbc_state_cache *cache = &fbc->state_cache;
 763
 764	if ((DISPLAY_VER(dev_priv) == 9) &&
 765	    cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
 766		return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
 767	else
 768		return 0;
 769}
 770
 771static bool intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private *dev_priv)
 772{
 773	struct intel_fbc *fbc = &dev_priv->fbc;
 774
 775	return fbc->params.gen9_wa_cfb_stride != intel_fbc_gen9_wa_cfb_stride(dev_priv);
 776}
 777
 778static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 779{
 780	struct intel_fbc *fbc = &dev_priv->fbc;
 781
 782	if (intel_vgpu_active(dev_priv)) {
 783		fbc->no_fbc_reason = "VGPU is active";
 784		return false;
 785	}
 786
 787	if (!dev_priv->params.enable_fbc) {
 788		fbc->no_fbc_reason = "disabled per module param or by default";
 789		return false;
 790	}
 791
 792	if (fbc->underrun_detected) {
 793		fbc->no_fbc_reason = "underrun detected";
 794		return false;
 795	}
 796
 797	return true;
 798}
 799
 800static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 801{
 802	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 803	struct intel_fbc *fbc = &dev_priv->fbc;
 804	struct intel_fbc_state_cache *cache = &fbc->state_cache;
 805
 806	if (!intel_fbc_can_enable(dev_priv))
 807		return false;
 808
 809	if (!cache->plane.visible) {
 810		fbc->no_fbc_reason = "primary plane not visible";
 811		return false;
 812	}
 813
 814	/* We don't need to use a state cache here since this information is
 815	 * global for all CRTC.
 816	 */
 817	if (fbc->underrun_detected) {
 818		fbc->no_fbc_reason = "underrun detected";
 819		return false;
 820	}
 821
 822	if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 823		fbc->no_fbc_reason = "incompatible mode";
 824		return false;
 825	}
 826
 827	if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 828		fbc->no_fbc_reason = "mode too large for compression";
 829		return false;
 830	}
 831
 832	/* The use of a CPU fence is one of two ways to detect writes by the
 833	 * CPU to the scanout and trigger updates to the FBC.
 834	 *
 835	 * The other method is by software tracking (see
 836	 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
 837	 * the current compressed buffer and recompress it.
 838	 *
 839	 * Note that is possible for a tiled surface to be unmappable (and
 840	 * so have no fence associated with it) due to aperture constraints
 841	 * at the time of pinning.
 842	 *
 843	 * FIXME with 90/270 degree rotation we should use the fence on
 844	 * the normal GTT view (the rotated view doesn't even have a
 845	 * fence). Would need changes to the FBC fence Y offset as well.
 846	 * For now this will effectively disable FBC with 90/270 degree
 847	 * rotation.
 848	 */
 849	if (DISPLAY_VER(dev_priv) < 9 && cache->fence_id < 0) {
 850		fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 851		return false;
 852	}
 853
 854	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 855		fbc->no_fbc_reason = "pixel format is invalid";
 856		return false;
 857	}
 858
 859	if (!rotation_is_valid(dev_priv, cache->fb.format->format,
 860			       cache->plane.rotation)) {
 861		fbc->no_fbc_reason = "rotation unsupported";
 862		return false;
 863	}
 864
 865	if (!tiling_is_valid(dev_priv, cache->fb.modifier)) {
 866		fbc->no_fbc_reason = "tiling unsupported";
 867		return false;
 868	}
 869
 870	if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
 871		fbc->no_fbc_reason = "framebuffer stride not supported";
 872		return false;
 873	}
 874
 875	if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 876	    cache->fb.format->has_alpha) {
 877		fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 878		return false;
 879	}
 880
 881	/* WaFbcExceedCdClockThreshold:hsw,bdw */
 882	if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 883	    cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 884		fbc->no_fbc_reason = "pixel rate is too big";
 885		return false;
 886	}
 887
 888	/* It is possible for the required CFB size change without a
 889	 * crtc->disable + crtc->enable since it is possible to change the
 890	 * stride without triggering a full modeset. Since we try to
 891	 * over-allocate the CFB, there's a chance we may keep FBC enabled even
 892	 * if this happens, but if we exceed the current CFB size we'll have to
 893	 * disable FBC. Notice that it would be possible to disable FBC, wait
 894	 * for a frame, free the stolen node, then try to reenable FBC in case
 895	 * we didn't get any invalidate/deactivate calls, but this would require
 896	 * a lot of tracking just for a specific case. If we conclude it's an
 897	 * important case, we can implement it later. */
 898	if (intel_fbc_cfb_size_changed(dev_priv)) {
 899		fbc->no_fbc_reason = "CFB requirements changed";
 900		return false;
 901	}
 902
 903	/*
 904	 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 905	 * having a Y offset that isn't divisible by 4 causes FIFO underrun
 906	 * and screen flicker.
 907	 */
 908	if (DISPLAY_VER(dev_priv) >= 9 &&
 909	    (fbc->state_cache.plane.adjusted_y & 3)) {
 910		fbc->no_fbc_reason = "plane Y offset is misaligned";
 911		return false;
 912	}
 913
 914	/* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
 915	if (DISPLAY_VER(dev_priv) >= 11 &&
 916	    (cache->plane.src_h + cache->plane.adjusted_y) % 4) {
 917		fbc->no_fbc_reason = "plane height + offset is non-modulo of 4";
 918		return false;
 919	}
 920
 921	/*
 922	 * Tigerlake is not supporting FBC with PSR2.
 923	 * Recommendation is to keep this combination disabled
 924	 * Bspec: 50422 HSD: 14010260002
 925	 */
 926	if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
 927		fbc->no_fbc_reason = "not supported with PSR2";
 928		return false;
 929	}
 930
 931	return true;
 932}
 933
 934static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 935				     struct intel_fbc_reg_params *params)
 936{
 937	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 938	struct intel_fbc *fbc = &dev_priv->fbc;
 939	struct intel_fbc_state_cache *cache = &fbc->state_cache;
 940
 941	/* Since all our fields are integer types, use memset here so the
 942	 * comparison function can rely on memcmp because the padding will be
 943	 * zero. */
 944	memset(params, 0, sizeof(*params));
 945
 946	params->fence_id = cache->fence_id;
 947	params->fence_y_offset = cache->fence_y_offset;
 948
 949	params->interval = cache->interval;
 950
 951	params->crtc.pipe = crtc->pipe;
 952	params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 953
 954	params->fb.format = cache->fb.format;
 955	params->fb.modifier = cache->fb.modifier;
 956	params->fb.stride = cache->fb.stride;
 957
 958	params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 959
 960	params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
 961
 962	params->plane_visible = cache->plane.visible;
 963}
 964
 965static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
 966{
 967	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 968	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 969	const struct intel_fbc *fbc = &dev_priv->fbc;
 970	const struct intel_fbc_state_cache *cache = &fbc->state_cache;
 971	const struct intel_fbc_reg_params *params = &fbc->params;
 972
 973	if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
 974		return false;
 975
 976	if (!params->plane_visible)
 977		return false;
 978
 979	if (!intel_fbc_can_activate(crtc))
 980		return false;
 981
 982	if (params->fb.format != cache->fb.format)
 983		return false;
 984
 985	if (params->fb.modifier != cache->fb.modifier)
 986		return false;
 987
 988	if (params->fb.stride != cache->fb.stride)
 989		return false;
 990
 991	if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
 992		return false;
 993
 994	if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
 995		return false;
 996
 997	return true;
 998}
 999
1000bool intel_fbc_pre_update(struct intel_atomic_state *state,
1001			  struct intel_crtc *crtc)
1002{
1003	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1004	const struct intel_crtc_state *crtc_state =
1005		intel_atomic_get_new_crtc_state(state, crtc);
1006	const struct intel_plane_state *plane_state =
1007		intel_atomic_get_new_plane_state(state, plane);
1008	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1009	struct intel_fbc *fbc = &dev_priv->fbc;
1010	const char *reason = "update pending";
1011	bool need_vblank_wait = false;
1012
1013	if (!plane->has_fbc || !plane_state)
1014		return need_vblank_wait;
1015
1016	mutex_lock(&fbc->lock);
1017
1018	if (fbc->crtc != crtc)
1019		goto unlock;
1020
1021	intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1022	fbc->flip_pending = true;
1023
1024	if (!intel_fbc_can_flip_nuke(crtc_state)) {
1025		intel_fbc_deactivate(dev_priv, reason);
1026
1027		/*
1028		 * Display WA #1198: glk+
1029		 * Need an extra vblank wait between FBC disable and most plane
1030		 * updates. Bspec says this is only needed for plane disable, but
1031		 * that is not true. Touching most plane registers will cause the
1032		 * corruption to appear. Also SKL/derivatives do not seem to be
1033		 * affected.
1034		 *
1035		 * TODO: could optimize this a bit by sampling the frame
1036		 * counter when we disable FBC (if it was already done earlier)
1037		 * and skipping the extra vblank wait before the plane update
1038		 * if at least one frame has already passed.
1039		 */
1040		if (fbc->activated &&
1041		    DISPLAY_VER(dev_priv) >= 10)
1042			need_vblank_wait = true;
1043		fbc->activated = false;
1044	}
1045unlock:
1046	mutex_unlock(&fbc->lock);
1047
1048	return need_vblank_wait;
1049}
1050
1051/**
1052 * __intel_fbc_disable - disable FBC
1053 * @dev_priv: i915 device instance
1054 *
1055 * This is the low level function that actually disables FBC. Callers should
1056 * grab the FBC lock.
1057 */
1058static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1059{
1060	struct intel_fbc *fbc = &dev_priv->fbc;
1061	struct intel_crtc *crtc = fbc->crtc;
1062
1063	drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1064	drm_WARN_ON(&dev_priv->drm, !fbc->crtc);
1065	drm_WARN_ON(&dev_priv->drm, fbc->active);
1066
1067	drm_dbg_kms(&dev_priv->drm, "Disabling FBC on pipe %c\n",
1068		    pipe_name(crtc->pipe));
1069
1070	__intel_fbc_cleanup_cfb(dev_priv);
1071
1072	fbc->crtc = NULL;
1073}
1074
1075static void __intel_fbc_post_update(struct intel_crtc *crtc)
1076{
1077	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1078	struct intel_fbc *fbc = &dev_priv->fbc;
1079
1080	drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1081
1082	if (fbc->crtc != crtc)
1083		return;
1084
1085	fbc->flip_pending = false;
1086
1087	if (!dev_priv->params.enable_fbc) {
1088		intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
1089		__intel_fbc_disable(dev_priv);
1090
1091		return;
1092	}
1093
1094	intel_fbc_get_reg_params(crtc, &fbc->params);
1095
1096	if (!intel_fbc_can_activate(crtc))
1097		return;
1098
1099	if (!fbc->busy_bits)
1100		intel_fbc_hw_activate(dev_priv);
1101	else
1102		intel_fbc_deactivate(dev_priv, "frontbuffer write");
1103}
1104
1105void intel_fbc_post_update(struct intel_atomic_state *state,
1106			   struct intel_crtc *crtc)
1107{
1108	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1109	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1110	const struct intel_plane_state *plane_state =
1111		intel_atomic_get_new_plane_state(state, plane);
1112	struct intel_fbc *fbc = &dev_priv->fbc;
1113
1114	if (!plane->has_fbc || !plane_state)
1115		return;
1116
1117	mutex_lock(&fbc->lock);
1118	__intel_fbc_post_update(crtc);
1119	mutex_unlock(&fbc->lock);
1120}
1121
1122static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1123{
1124	if (fbc->crtc)
1125		return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1126	else
1127		return fbc->possible_framebuffer_bits;
1128}
1129
1130void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1131			  unsigned int frontbuffer_bits,
1132			  enum fb_op_origin origin)
1133{
1134	struct intel_fbc *fbc = &dev_priv->fbc;
1135
1136	if (!HAS_FBC(dev_priv))
1137		return;
1138
1139	if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1140		return;
1141
1142	mutex_lock(&fbc->lock);
1143
1144	fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1145
1146	if (fbc->crtc && fbc->busy_bits)
1147		intel_fbc_deactivate(dev_priv, "frontbuffer write");
1148
1149	mutex_unlock(&fbc->lock);
1150}
1151
1152void intel_fbc_flush(struct drm_i915_private *dev_priv,
1153		     unsigned int frontbuffer_bits, enum fb_op_origin origin)
1154{
1155	struct intel_fbc *fbc = &dev_priv->fbc;
1156
1157	if (!HAS_FBC(dev_priv))
1158		return;
1159
1160	/*
1161	 * GTT tracking does not nuke the entire cfb
1162	 * so don't clear busy_bits set for some other
1163	 * reason.
1164	 */
1165	if (origin == ORIGIN_GTT)
1166		return;
1167
1168	mutex_lock(&fbc->lock);
1169
1170	fbc->busy_bits &= ~frontbuffer_bits;
1171
1172	if (origin == ORIGIN_FLIP)
1173		goto out;
1174
1175	if (!fbc->busy_bits && fbc->crtc &&
1176	    (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1177		if (fbc->active)
1178			intel_fbc_recompress(dev_priv);
1179		else if (!fbc->flip_pending)
1180			__intel_fbc_post_update(fbc->crtc);
1181	}
1182
1183out:
1184	mutex_unlock(&fbc->lock);
1185}
1186
1187/**
1188 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1189 * @dev_priv: i915 device instance
1190 * @state: the atomic state structure
1191 *
1192 * This function looks at the proposed state for CRTCs and planes, then chooses
1193 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1194 * true.
1195 *
1196 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1197 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1198 */
1199void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1200			   struct intel_atomic_state *state)
1201{
1202	struct intel_fbc *fbc = &dev_priv->fbc;
1203	struct intel_plane *plane;
1204	struct intel_plane_state *plane_state;
1205	bool crtc_chosen = false;
1206	int i;
1207
1208	mutex_lock(&fbc->lock);
1209
1210	/* Does this atomic commit involve the CRTC currently tied to FBC? */
1211	if (fbc->crtc &&
1212	    !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1213		goto out;
1214
1215	if (!intel_fbc_can_enable(dev_priv))
1216		goto out;
1217
1218	/* Simply choose the first CRTC that is compatible and has a visible
1219	 * plane. We could go for fancier schemes such as checking the plane
1220	 * size, but this would just affect the few platforms that don't tie FBC
1221	 * to pipe or plane A. */
1222	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1223		struct intel_crtc_state *crtc_state;
1224		struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1225
1226		if (!plane->has_fbc)
1227			continue;
1228
1229		if (!plane_state->uapi.visible)
1230			continue;
1231
1232		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1233
1234		crtc_state->enable_fbc = true;
1235		crtc_chosen = true;
1236		break;
1237	}
1238
1239	if (!crtc_chosen)
1240		fbc->no_fbc_reason = "no suitable CRTC for FBC";
1241
1242out:
1243	mutex_unlock(&fbc->lock);
1244}
1245
1246/**
1247 * intel_fbc_enable: tries to enable FBC on the CRTC
1248 * @crtc: the CRTC
1249 * @state: corresponding &drm_crtc_state for @crtc
1250 *
1251 * This function checks if the given CRTC was chosen for FBC, then enables it if
1252 * possible. Notice that it doesn't activate FBC. It is valid to call
1253 * intel_fbc_enable multiple times for the same pipe without an
1254 * intel_fbc_disable in the middle, as long as it is deactivated.
1255 */
1256void intel_fbc_enable(struct intel_atomic_state *state,
1257		      struct intel_crtc *crtc)
1258{
1259	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1260	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1261	const struct intel_crtc_state *crtc_state =
1262		intel_atomic_get_new_crtc_state(state, crtc);
1263	const struct intel_plane_state *plane_state =
1264		intel_atomic_get_new_plane_state(state, plane);
1265	struct intel_fbc *fbc = &dev_priv->fbc;
1266	struct intel_fbc_state_cache *cache = &fbc->state_cache;
1267
1268	if (!plane->has_fbc || !plane_state)
1269		return;
1270
1271	mutex_lock(&fbc->lock);
1272
1273	if (fbc->crtc) {
1274		if (fbc->crtc != crtc ||
1275		    (!intel_fbc_cfb_size_changed(dev_priv) &&
1276		     !intel_fbc_gen9_wa_cfb_stride_changed(dev_priv)))
1277			goto out;
1278
1279		__intel_fbc_disable(dev_priv);
1280	}
1281
1282	drm_WARN_ON(&dev_priv->drm, fbc->active);
1283
1284	intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1285
1286	/* FIXME crtc_state->enable_fbc lies :( */
1287	if (!cache->plane.visible)
1288		goto out;
1289
1290	if (intel_fbc_alloc_cfb(dev_priv,
1291				intel_fbc_calculate_cfb_size(dev_priv, cache),
1292				plane_state->hw.fb->format->cpp[0])) {
1293		cache->plane.visible = false;
1294		fbc->no_fbc_reason = "not enough stolen memory";
1295		goto out;
1296	}
1297
1298	cache->gen9_wa_cfb_stride = intel_fbc_gen9_wa_cfb_stride(dev_priv);
1299
1300	drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
1301		    pipe_name(crtc->pipe));
1302	fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1303
1304	fbc->crtc = crtc;
1305out:
1306	mutex_unlock(&fbc->lock);
1307}
1308
1309/**
1310 * intel_fbc_disable - disable FBC if it's associated with crtc
1311 * @crtc: the CRTC
1312 *
1313 * This function disables FBC if it's associated with the provided CRTC.
1314 */
1315void intel_fbc_disable(struct intel_crtc *crtc)
1316{
1317	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1318	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1319	struct intel_fbc *fbc = &dev_priv->fbc;
1320
1321	if (!plane->has_fbc)
1322		return;
1323
1324	mutex_lock(&fbc->lock);
1325	if (fbc->crtc == crtc)
1326		__intel_fbc_disable(dev_priv);
1327	mutex_unlock(&fbc->lock);
1328}
1329
1330/**
1331 * intel_fbc_global_disable - globally disable FBC
1332 * @dev_priv: i915 device instance
1333 *
1334 * This function disables FBC regardless of which CRTC is associated with it.
1335 */
1336void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1337{
1338	struct intel_fbc *fbc = &dev_priv->fbc;
1339
1340	if (!HAS_FBC(dev_priv))
1341		return;
1342
1343	mutex_lock(&fbc->lock);
1344	if (fbc->crtc) {
1345		drm_WARN_ON(&dev_priv->drm, fbc->crtc->active);
1346		__intel_fbc_disable(dev_priv);
1347	}
1348	mutex_unlock(&fbc->lock);
1349}
1350
1351static void intel_fbc_underrun_work_fn(struct work_struct *work)
1352{
1353	struct drm_i915_private *dev_priv =
1354		container_of(work, struct drm_i915_private, fbc.underrun_work);
1355	struct intel_fbc *fbc = &dev_priv->fbc;
1356
1357	mutex_lock(&fbc->lock);
1358
1359	/* Maybe we were scheduled twice. */
1360	if (fbc->underrun_detected || !fbc->crtc)
1361		goto out;
1362
1363	drm_dbg_kms(&dev_priv->drm, "Disabling FBC due to FIFO underrun.\n");
1364	fbc->underrun_detected = true;
1365
1366	intel_fbc_deactivate(dev_priv, "FIFO underrun");
1367out:
1368	mutex_unlock(&fbc->lock);
1369}
1370
1371/*
1372 * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1373 * @dev_priv: i915 device instance
1374 *
1375 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1376 * want to re-enable FBC after an underrun to increase test coverage.
1377 */
1378int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1379{
1380	int ret;
1381
1382	cancel_work_sync(&dev_priv->fbc.underrun_work);
1383
1384	ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1385	if (ret)
1386		return ret;
1387
1388	if (dev_priv->fbc.underrun_detected) {
1389		drm_dbg_kms(&dev_priv->drm,
1390			    "Re-allowing FBC after fifo underrun\n");
1391		dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1392	}
1393
1394	dev_priv->fbc.underrun_detected = false;
1395	mutex_unlock(&dev_priv->fbc.lock);
1396
1397	return 0;
1398}
1399
1400/**
1401 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1402 * @dev_priv: i915 device instance
1403 *
1404 * Without FBC, most underruns are harmless and don't really cause too many
1405 * problems, except for an annoying message on dmesg. With FBC, underruns can
1406 * become black screens or even worse, especially when paired with bad
1407 * watermarks. So in order for us to be on the safe side, completely disable FBC
1408 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1409 * already suggests that watermarks may be bad, so try to be as safe as
1410 * possible.
1411 *
1412 * This function is called from the IRQ handler.
1413 */
1414void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1415{
1416	struct intel_fbc *fbc = &dev_priv->fbc;
1417
1418	if (!HAS_FBC(dev_priv))
1419		return;
1420
1421	/* There's no guarantee that underrun_detected won't be set to true
1422	 * right after this check and before the work is scheduled, but that's
1423	 * not a problem since we'll check it again under the work function
1424	 * while FBC is locked. This check here is just to prevent us from
1425	 * unnecessarily scheduling the work, and it relies on the fact that we
1426	 * never switch underrun_detect back to false after it's true. */
1427	if (READ_ONCE(fbc->underrun_detected))
1428		return;
1429
1430	schedule_work(&fbc->underrun_work);
1431}
1432
1433/*
1434 * The DDX driver changes its behavior depending on the value it reads from
1435 * i915.enable_fbc, so sanitize it by translating the default value into either
1436 * 0 or 1 in order to allow it to know what's going on.
1437 *
1438 * Notice that this is done at driver initialization and we still allow user
1439 * space to change the value during runtime without sanitizing it again. IGT
1440 * relies on being able to change i915.enable_fbc at runtime.
1441 */
1442static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1443{
1444	if (dev_priv->params.enable_fbc >= 0)
1445		return !!dev_priv->params.enable_fbc;
1446
1447	if (!HAS_FBC(dev_priv))
1448		return 0;
1449
1450	if (IS_BROADWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 9)
1451		return 1;
1452
1453	return 0;
1454}
1455
1456static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1457{
1458	/* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1459	if (intel_vtd_active() &&
1460	    (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1461		drm_info(&dev_priv->drm,
1462			 "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1463		return true;
1464	}
1465
1466	return false;
1467}
1468
1469/**
1470 * intel_fbc_init - Initialize FBC
1471 * @dev_priv: the i915 device
1472 *
1473 * This function might be called during PM init process.
1474 */
1475void intel_fbc_init(struct drm_i915_private *dev_priv)
1476{
1477	struct intel_fbc *fbc = &dev_priv->fbc;
1478
1479	INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1480	mutex_init(&fbc->lock);
1481	fbc->active = false;
1482
1483	if (!drm_mm_initialized(&dev_priv->mm.stolen))
1484		mkwrite_device_info(dev_priv)->display.has_fbc = false;
1485
1486	if (need_fbc_vtd_wa(dev_priv))
1487		mkwrite_device_info(dev_priv)->display.has_fbc = false;
1488
1489	dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1490	drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n",
1491		    dev_priv->params.enable_fbc);
1492
1493	if (!HAS_FBC(dev_priv)) {
1494		fbc->no_fbc_reason = "unsupported by this chipset";
1495		return;
1496	}
1497
1498	/* We still don't have any sort of hardware state readout for FBC, so
1499	 * deactivate it in case the BIOS activated it to make sure software
1500	 * matches the hardware state. */
1501	if (intel_fbc_hw_is_active(dev_priv))
1502		intel_fbc_hw_deactivate(dev_priv);
1503}