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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * OpenRISC time.c
4 *
5 * Linux architectural port borrowing liberally from similar works of
6 * others. All original copyrights apply as per the original source
7 * declaration.
8 *
9 * Modifications for the OpenRISC architecture:
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 */
12
13#include <linux/kernel.h>
14#include <linux/time.h>
15#include <linux/timex.h>
16#include <linux/interrupt.h>
17#include <linux/ftrace.h>
18
19#include <linux/clocksource.h>
20#include <linux/clockchips.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23
24#include <asm/cpuinfo.h>
25
26/* Test the timer ticks to count, used in sync routine */
27inline void openrisc_timer_set(unsigned long count)
28{
29 mtspr(SPR_TTCR, count);
30}
31
32/* Set the timer to trigger in delta cycles */
33inline void openrisc_timer_set_next(unsigned long delta)
34{
35 u32 c;
36
37 /* Read 32-bit counter value, add delta, mask off the low 28 bits.
38 * We're guaranteed delta won't be bigger than 28 bits because the
39 * generic timekeeping code ensures that for us.
40 */
41 c = mfspr(SPR_TTCR);
42 c += delta;
43 c &= SPR_TTMR_TP;
44
45 /* Set counter and enable interrupt.
46 * Keep timer in continuous mode always.
47 */
48 mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
49}
50
51static int openrisc_timer_set_next_event(unsigned long delta,
52 struct clock_event_device *dev)
53{
54 openrisc_timer_set_next(delta);
55 return 0;
56}
57
58/* This is the clock event device based on the OR1K tick timer.
59 * As the timer is being used as a continuous clock-source (required for HR
60 * timers) we cannot enable the PERIODIC feature. The tick timer can run using
61 * one-shot events, so no problem.
62 */
63DEFINE_PER_CPU(struct clock_event_device, clockevent_openrisc_timer);
64
65void openrisc_clockevent_init(void)
66{
67 unsigned int cpu = smp_processor_id();
68 struct clock_event_device *evt =
69 &per_cpu(clockevent_openrisc_timer, cpu);
70 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu];
71
72 mtspr(SPR_TTMR, SPR_TTMR_CR);
73
74#ifdef CONFIG_SMP
75 evt->broadcast = tick_broadcast;
76#endif
77 evt->name = "openrisc_timer_clockevent",
78 evt->features = CLOCK_EVT_FEAT_ONESHOT,
79 evt->rating = 300,
80 evt->set_next_event = openrisc_timer_set_next_event,
81
82 evt->cpumask = cpumask_of(cpu);
83
84 /* We only have 28 bits */
85 clockevents_config_and_register(evt, cpuinfo->clock_frequency,
86 100, 0x0fffffff);
87
88}
89
90static inline void timer_ack(void)
91{
92 /* Clear the IP bit and disable further interrupts */
93 /* This can be done very simply... we just need to keep the timer
94 running, so just maintain the CR bits while clearing the rest
95 of the register
96 */
97 mtspr(SPR_TTMR, SPR_TTMR_CR);
98}
99
100/*
101 * The timer interrupt is mostly handled in generic code nowadays... this
102 * function just acknowledges the interrupt and fires the event handler that
103 * has been set on the clockevent device by the generic time management code.
104 *
105 * This function needs to be called by the timer exception handler and that's
106 * all the exception handler needs to do.
107 */
108
109irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
110{
111 struct pt_regs *old_regs = set_irq_regs(regs);
112 unsigned int cpu = smp_processor_id();
113 struct clock_event_device *evt =
114 &per_cpu(clockevent_openrisc_timer, cpu);
115
116 timer_ack();
117
118 /*
119 * update_process_times() expects us to have called irq_enter().
120 */
121 irq_enter();
122 evt->event_handler(evt);
123 irq_exit();
124
125 set_irq_regs(old_regs);
126
127 return IRQ_HANDLED;
128}
129
130/**
131 * Clocksource: Based on OpenRISC timer/counter
132 *
133 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer
134 * is 32 bits wide and runs at the CPU clock frequency.
135 */
136static u64 openrisc_timer_read(struct clocksource *cs)
137{
138 return (u64) mfspr(SPR_TTCR);
139}
140
141static struct clocksource openrisc_timer = {
142 .name = "openrisc_timer",
143 .rating = 200,
144 .read = openrisc_timer_read,
145 .mask = CLOCKSOURCE_MASK(32),
146 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
147};
148
149static int __init openrisc_timer_init(void)
150{
151 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
152
153 if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency))
154 panic("failed to register clocksource");
155
156 /* Enable the incrementer: 'continuous' mode with interrupt disabled */
157 mtspr(SPR_TTMR, SPR_TTMR_CR);
158
159 return 0;
160}
161
162void __init time_init(void)
163{
164 u32 upr;
165
166 upr = mfspr(SPR_UPR);
167 if (!(upr & SPR_UPR_TTP))
168 panic("Linux not supported on devices without tick timer");
169
170 openrisc_timer_init();
171 openrisc_clockevent_init();
172}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * OpenRISC time.c
4 *
5 * Linux architectural port borrowing liberally from similar works of
6 * others. All original copyrights apply as per the original source
7 * declaration.
8 *
9 * Modifications for the OpenRISC architecture:
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 */
12
13#include <linux/kernel.h>
14#include <linux/time.h>
15#include <linux/timex.h>
16#include <linux/interrupt.h>
17#include <linux/ftrace.h>
18
19#include <linux/clocksource.h>
20#include <linux/clockchips.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23
24#include <asm/cpuinfo.h>
25
26/* Test the timer ticks to count, used in sync routine */
27inline void openrisc_timer_set(unsigned long count)
28{
29 mtspr(SPR_TTCR, count);
30}
31
32/* Set the timer to trigger in delta cycles */
33inline void openrisc_timer_set_next(unsigned long delta)
34{
35 u32 c;
36
37 /* Read 32-bit counter value, add delta, mask off the low 28 bits.
38 * We're guaranteed delta won't be bigger than 28 bits because the
39 * generic timekeeping code ensures that for us.
40 */
41 c = mfspr(SPR_TTCR);
42 c += delta;
43 c &= SPR_TTMR_TP;
44
45 /* Set counter and enable interrupt.
46 * Keep timer in continuous mode always.
47 */
48 mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
49}
50
51static int openrisc_timer_set_next_event(unsigned long delta,
52 struct clock_event_device *dev)
53{
54 openrisc_timer_set_next(delta);
55 return 0;
56}
57
58/* This is the clock event device based on the OR1K tick timer.
59 * As the timer is being used as a continuous clock-source (required for HR
60 * timers) we cannot enable the PERIODIC feature. The tick timer can run using
61 * one-shot events, so no problem.
62 */
63DEFINE_PER_CPU(struct clock_event_device, clockevent_openrisc_timer);
64
65void openrisc_clockevent_init(void)
66{
67 unsigned int cpu = smp_processor_id();
68 struct clock_event_device *evt =
69 &per_cpu(clockevent_openrisc_timer, cpu);
70 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu];
71
72 mtspr(SPR_TTMR, SPR_TTMR_CR);
73
74#ifdef CONFIG_SMP
75 evt->broadcast = tick_broadcast;
76#endif
77 evt->name = "openrisc_timer_clockevent",
78 evt->features = CLOCK_EVT_FEAT_ONESHOT,
79 evt->rating = 300,
80 evt->set_next_event = openrisc_timer_set_next_event,
81
82 evt->cpumask = cpumask_of(cpu);
83
84 /* We only have 28 bits */
85 clockevents_config_and_register(evt, cpuinfo->clock_frequency,
86 100, 0x0fffffff);
87
88}
89
90static inline void timer_ack(void)
91{
92 /* Clear the IP bit and disable further interrupts */
93 /* This can be done very simply... we just need to keep the timer
94 running, so just maintain the CR bits while clearing the rest
95 of the register
96 */
97 mtspr(SPR_TTMR, SPR_TTMR_CR);
98}
99
100/*
101 * The timer interrupt is mostly handled in generic code nowadays... this
102 * function just acknowledges the interrupt and fires the event handler that
103 * has been set on the clockevent device by the generic time management code.
104 *
105 * This function needs to be called by the timer exception handler and that's
106 * all the exception handler needs to do.
107 */
108
109irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
110{
111 struct pt_regs *old_regs = set_irq_regs(regs);
112 unsigned int cpu = smp_processor_id();
113 struct clock_event_device *evt =
114 &per_cpu(clockevent_openrisc_timer, cpu);
115
116 timer_ack();
117
118 /*
119 * update_process_times() expects us to have called irq_enter().
120 */
121 irq_enter();
122 evt->event_handler(evt);
123 irq_exit();
124
125 set_irq_regs(old_regs);
126
127 return IRQ_HANDLED;
128}
129
130/**
131 * Clocksource: Based on OpenRISC timer/counter
132 *
133 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer
134 * is 32 bits wide and runs at the CPU clock frequency.
135 */
136static u64 openrisc_timer_read(struct clocksource *cs)
137{
138 return (u64) mfspr(SPR_TTCR);
139}
140
141static struct clocksource openrisc_timer = {
142 .name = "openrisc_timer",
143 .rating = 200,
144 .read = openrisc_timer_read,
145 .mask = CLOCKSOURCE_MASK(32),
146 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
147};
148
149static int __init openrisc_timer_init(void)
150{
151 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
152
153 if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency))
154 panic("failed to register clocksource");
155
156 /* Enable the incrementer: 'continuous' mode with interrupt disabled */
157 mtspr(SPR_TTMR, SPR_TTMR_CR);
158
159 return 0;
160}
161
162void __init time_init(void)
163{
164 u32 upr;
165
166 upr = mfspr(SPR_UPR);
167 if (!(upr & SPR_UPR_TTP))
168 panic("Linux not supported on devices without tick timer");
169
170 openrisc_timer_init();
171 openrisc_clockevent_init();
172}