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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include "tegra30-cardhu.dtsi"
5
6/* This dts file support the cardhu A04 and later versions of board */
7
8/ {
9 model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
10 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
11
12 mmc@78000400 {
13 status = "okay";
14 power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
15 bus-width = <4>;
16 keep-power-in-suspend;
17 };
18
19 ddr_reg: regulator@100 {
20 compatible = "regulator-fixed";
21 regulator-name = "ddr";
22 regulator-min-microvolt = <1500000>;
23 regulator-max-microvolt = <1500000>;
24 regulator-always-on;
25 regulator-boot-on;
26 enable-active-high;
27 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
28 };
29
30 sys_3v3_reg: regulator@101 {
31 compatible = "regulator-fixed";
32 regulator-name = "sys_3v3";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-always-on;
36 regulator-boot-on;
37 enable-active-high;
38 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
39 };
40
41 usb1_vbus_reg: regulator@102 {
42 compatible = "regulator-fixed";
43 regulator-name = "usb1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 enable-active-high;
47 gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
48 gpio-open-drain;
49 vin-supply = <&vdd_5v0_reg>;
50 };
51
52 usb3_vbus_reg: regulator@103 {
53 compatible = "regulator-fixed";
54 regulator-name = "usb3_vbus";
55 regulator-min-microvolt = <5000000>;
56 regulator-max-microvolt = <5000000>;
57 enable-active-high;
58 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
59 gpio-open-drain;
60 vin-supply = <&vdd_5v0_reg>;
61 };
62
63 vdd_5v0_reg: regulator@104 {
64 compatible = "regulator-fixed";
65 regulator-name = "5v0";
66 regulator-min-microvolt = <5000000>;
67 regulator-max-microvolt = <5000000>;
68 enable-active-high;
69 gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
70 };
71
72 vdd_bl_reg: regulator@105 {
73 compatible = "regulator-fixed";
74 regulator-name = "vdd_bl";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 regulator-always-on;
78 regulator-boot-on;
79 enable-active-high;
80 gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
81 };
82
83 vdd_bl2_reg: regulator@106 {
84 compatible = "regulator-fixed";
85 regulator-name = "vdd_bl2";
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 regulator-always-on;
89 regulator-boot-on;
90 enable-active-high;
91 gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
92 };
93};
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include "tegra30-cardhu.dtsi"
5#include "tegra30-cpu-opp.dtsi"
6#include "tegra30-cpu-opp-microvolt.dtsi"
7
8/* This dts file support the cardhu A04 and later versions of board */
9
10/ {
11 model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
12 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
13
14 mmc@78000400 {
15 status = "okay";
16 power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
17 bus-width = <4>;
18 keep-power-in-suspend;
19 };
20
21 ddr_reg: regulator@100 {
22 compatible = "regulator-fixed";
23 regulator-name = "ddr";
24 regulator-min-microvolt = <1500000>;
25 regulator-max-microvolt = <1500000>;
26 regulator-always-on;
27 regulator-boot-on;
28 enable-active-high;
29 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
30 };
31
32 sys_3v3_reg: regulator@101 {
33 compatible = "regulator-fixed";
34 regulator-name = "sys_3v3";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 regulator-always-on;
38 regulator-boot-on;
39 enable-active-high;
40 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
41 };
42
43 usb1_vbus_reg: regulator@102 {
44 compatible = "regulator-fixed";
45 regulator-name = "usb1_vbus";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 enable-active-high;
49 gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
50 gpio-open-drain;
51 vin-supply = <&vdd_5v0_reg>;
52 };
53
54 usb3_vbus_reg: regulator@103 {
55 compatible = "regulator-fixed";
56 regulator-name = "usb3_vbus";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 enable-active-high;
60 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
61 gpio-open-drain;
62 vin-supply = <&vdd_5v0_reg>;
63 };
64
65 vdd_5v0_reg: regulator@104 {
66 compatible = "regulator-fixed";
67 regulator-name = "5v0";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 enable-active-high;
71 gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
72 };
73
74 vdd_bl_reg: regulator@105 {
75 compatible = "regulator-fixed";
76 regulator-name = "vdd_bl";
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5000000>;
79 regulator-always-on;
80 regulator-boot-on;
81 enable-active-high;
82 gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
83 };
84
85 vdd_bl2_reg: regulator@106 {
86 compatible = "regulator-fixed";
87 regulator-name = "vdd_bl2";
88 regulator-min-microvolt = <5000000>;
89 regulator-max-microvolt = <5000000>;
90 regulator-always-on;
91 regulator-boot-on;
92 enable-active-high;
93 gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
94 };
95
96 i2c@7000d000 {
97 pmic: tps65911@2d {
98 regulators {
99 vddctrl_reg: vddctrl {
100 regulator-min-microvolt = <800000>;
101 regulator-max-microvolt = <1125000>;
102 regulator-coupled-with = <&vddcore_reg>;
103 regulator-coupled-max-spread = <300000>;
104 regulator-max-step-microvolt = <100000>;
105
106 nvidia,tegra-cpu-regulator;
107 };
108 };
109 };
110
111 vddcore_reg: tps62361@60 {
112 regulator-coupled-with = <&vddctrl_reg>;
113 regulator-coupled-max-spread = <300000>;
114 regulator-max-step-microvolt = <100000>;
115
116 nvidia,tegra-core-regulator;
117 };
118 };
119
120 cpus {
121 cpu0: cpu@0 {
122 cpu-supply = <&vddctrl_reg>;
123 operating-points-v2 = <&cpu0_opp_table>;
124 };
125
126 cpu@1 {
127 cpu-supply = <&vddctrl_reg>;
128 operating-points-v2 = <&cpu0_opp_table>;
129 };
130
131 cpu@2 {
132 cpu-supply = <&vddctrl_reg>;
133 operating-points-v2 = <&cpu0_opp_table>;
134 };
135
136 cpu@3 {
137 cpu-supply = <&vddctrl_reg>;
138 operating-points-v2 = <&cpu0_opp_table>;
139 };
140 };
141};