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1/*
2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include <dt-bindings/interrupt-controller/arm-gic.h>
45#include <dt-bindings/clock/sun8i-v3s-ccu.h>
46#include <dt-bindings/reset/sun8i-v3s-ccu.h>
47#include <dt-bindings/clock/sun8i-de2.h>
48
49/ {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&gic>;
53
54 chosen {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 framebuffer-lcd {
60 compatible = "allwinner,simple-framebuffer",
61 "simple-framebuffer";
62 allwinner,pipeline = "mixer0-lcd0";
63 clocks = <&display_clocks CLK_MIXER0>,
64 <&ccu CLK_TCON0>;
65 status = "disabled";
66 };
67 };
68
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 cpu@0 {
74 compatible = "arm,cortex-a7";
75 device_type = "cpu";
76 reg = <0>;
77 clocks = <&ccu CLK_CPU>;
78 };
79 };
80
81 de: display-engine {
82 compatible = "allwinner,sun8i-v3s-display-engine";
83 allwinner,pipelines = <&mixer0>;
84 status = "disabled";
85 };
86
87 timer {
88 compatible = "arm,armv7-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93 };
94
95 clocks {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99
100 osc24M: osc24M_clk {
101 #clock-cells = <0>;
102 compatible = "fixed-clock";
103 clock-frequency = <24000000>;
104 clock-accuracy = <50000>;
105 clock-output-names = "osc24M";
106 };
107
108 osc32k: osc32k_clk {
109 #clock-cells = <0>;
110 compatible = "fixed-clock";
111 clock-frequency = <32768>;
112 clock-accuracy = <50000>;
113 clock-output-names = "ext-osc32k";
114 };
115 };
116
117 soc {
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 ranges;
122
123 display_clocks: clock@1000000 {
124 compatible = "allwinner,sun8i-v3s-de2-clk";
125 reg = <0x01000000 0x10000>;
126 clocks = <&ccu CLK_BUS_DE>,
127 <&ccu CLK_DE>;
128 clock-names = "bus",
129 "mod";
130 resets = <&ccu RST_BUS_DE>;
131 #clock-cells = <1>;
132 #reset-cells = <1>;
133 };
134
135 mixer0: mixer@1100000 {
136 compatible = "allwinner,sun8i-v3s-de2-mixer";
137 reg = <0x01100000 0x100000>;
138 clocks = <&display_clocks 0>,
139 <&display_clocks 6>;
140 clock-names = "bus",
141 "mod";
142 resets = <&display_clocks 0>;
143
144 ports {
145 #address-cells = <1>;
146 #size-cells = <0>;
147
148 mixer0_out: port@1 {
149 reg = <1>;
150
151 mixer0_out_tcon0: endpoint {
152 remote-endpoint = <&tcon0_in_mixer0>;
153 };
154 };
155 };
156 };
157
158 syscon: system-control@1c00000 {
159 compatible = "allwinner,sun8i-v3s-system-control",
160 "allwinner,sun8i-h3-system-control";
161 reg = <0x01c00000 0xd0>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
165 };
166
167 nmi_intc: interrupt-controller@1c000d0 {
168 compatible = "allwinner,sun8i-v3s-nmi",
169 "allwinner,sun9i-a80-nmi";
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 reg = <0x01c000d0 0x0c>;
173 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
174 };
175
176 dma: dma-controller@1c02000 {
177 compatible = "allwinner,sun8i-v3s-dma";
178 reg = <0x01c02000 0x1000>;
179 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&ccu CLK_BUS_DMA>;
181 resets = <&ccu RST_BUS_DMA>;
182 #dma-cells = <1>;
183 };
184
185 tcon0: lcd-controller@1c0c000 {
186 compatible = "allwinner,sun8i-v3s-tcon";
187 reg = <0x01c0c000 0x1000>;
188 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&ccu CLK_BUS_TCON0>,
190 <&ccu CLK_TCON0>;
191 clock-names = "ahb",
192 "tcon-ch0";
193 clock-output-names = "tcon-pixel-clock";
194 #clock-cells = <0>;
195 resets = <&ccu RST_BUS_TCON0>;
196 reset-names = "lcd";
197 status = "disabled";
198
199 ports {
200 #address-cells = <1>;
201 #size-cells = <0>;
202
203 tcon0_in: port@0 {
204 reg = <0>;
205
206 tcon0_in_mixer0: endpoint {
207 remote-endpoint = <&mixer0_out_tcon0>;
208 };
209 };
210
211 tcon0_out: port@1 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 reg = <1>;
215 };
216 };
217 };
218
219
220 mmc0: mmc@1c0f000 {
221 compatible = "allwinner,sun7i-a20-mmc";
222 reg = <0x01c0f000 0x1000>;
223 clocks = <&ccu CLK_BUS_MMC0>,
224 <&ccu CLK_MMC0>,
225 <&ccu CLK_MMC0_OUTPUT>,
226 <&ccu CLK_MMC0_SAMPLE>;
227 clock-names = "ahb",
228 "mmc",
229 "output",
230 "sample";
231 resets = <&ccu RST_BUS_MMC0>;
232 reset-names = "ahb";
233 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&mmc0_pins>;
236 status = "disabled";
237 #address-cells = <1>;
238 #size-cells = <0>;
239 };
240
241 mmc1: mmc@1c10000 {
242 compatible = "allwinner,sun7i-a20-mmc";
243 reg = <0x01c10000 0x1000>;
244 clocks = <&ccu CLK_BUS_MMC1>,
245 <&ccu CLK_MMC1>,
246 <&ccu CLK_MMC1_OUTPUT>,
247 <&ccu CLK_MMC1_SAMPLE>;
248 clock-names = "ahb",
249 "mmc",
250 "output",
251 "sample";
252 resets = <&ccu RST_BUS_MMC1>;
253 reset-names = "ahb";
254 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&mmc1_pins>;
257 status = "disabled";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 };
261
262 mmc2: mmc@1c11000 {
263 compatible = "allwinner,sun7i-a20-mmc";
264 reg = <0x01c11000 0x1000>;
265 clocks = <&ccu CLK_BUS_MMC2>,
266 <&ccu CLK_MMC2>,
267 <&ccu CLK_MMC2_OUTPUT>,
268 <&ccu CLK_MMC2_SAMPLE>;
269 clock-names = "ahb",
270 "mmc",
271 "output",
272 "sample";
273 resets = <&ccu RST_BUS_MMC2>;
274 reset-names = "ahb";
275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
276 status = "disabled";
277 #address-cells = <1>;
278 #size-cells = <0>;
279 };
280
281 crypto@1c15000 {
282 compatible = "allwinner,sun8i-v3s-crypto",
283 "allwinner,sun8i-a33-crypto";
284 reg = <0x01c15000 0x1000>;
285 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
287 clock-names = "ahb", "mod";
288 dmas = <&dma 16>, <&dma 16>;
289 dma-names = "rx", "tx";
290 resets = <&ccu RST_BUS_CE>;
291 reset-names = "ahb";
292 };
293
294 usb_otg: usb@1c19000 {
295 compatible = "allwinner,sun8i-h3-musb";
296 reg = <0x01c19000 0x0400>;
297 clocks = <&ccu CLK_BUS_OTG>;
298 resets = <&ccu RST_BUS_OTG>;
299 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
300 interrupt-names = "mc";
301 phys = <&usbphy 0>;
302 phy-names = "usb";
303 extcon = <&usbphy 0>;
304 status = "disabled";
305 };
306
307 usbphy: phy@1c19400 {
308 compatible = "allwinner,sun8i-v3s-usb-phy";
309 reg = <0x01c19400 0x2c>,
310 <0x01c1a800 0x4>;
311 reg-names = "phy_ctrl",
312 "pmu0";
313 clocks = <&ccu CLK_USB_PHY0>;
314 clock-names = "usb0_phy";
315 resets = <&ccu RST_USB_PHY0>;
316 reset-names = "usb0_reset";
317 status = "disabled";
318 #phy-cells = <1>;
319 };
320
321 ccu: clock@1c20000 {
322 compatible = "allwinner,sun8i-v3s-ccu";
323 reg = <0x01c20000 0x400>;
324 clocks = <&osc24M>, <&rtc 0>;
325 clock-names = "hosc", "losc";
326 #clock-cells = <1>;
327 #reset-cells = <1>;
328 };
329
330 rtc: rtc@1c20400 {
331 #clock-cells = <1>;
332 compatible = "allwinner,sun8i-v3-rtc";
333 reg = <0x01c20400 0x54>;
334 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&osc32k>;
337 clock-output-names = "osc32k", "osc32k-out";
338 };
339
340 pio: pinctrl@1c20800 {
341 compatible = "allwinner,sun8i-v3s-pinctrl";
342 reg = <0x01c20800 0x400>;
343 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
346 clock-names = "apb", "hosc", "losc";
347 gpio-controller;
348 #gpio-cells = <3>;
349 interrupt-controller;
350 #interrupt-cells = <3>;
351
352 /omit-if-no-ref/
353 csi0_mclk_pin: csi0-mclk-pin {
354 pins = "PE20";
355 function = "csi_mipi";
356 };
357
358 /omit-if-no-ref/
359 csi1_8bit_pins: csi1-8bit-pins {
360 pins = "PE0", "PE2", "PE3", "PE8", "PE9",
361 "PE10", "PE11", "PE12", "PE13", "PE14",
362 "PE15";
363 function = "csi";
364 };
365
366 /omit-if-no-ref/
367 csi1_mclk_pin: csi1-mclk-pin {
368 pins = "PE1";
369 function = "csi";
370 };
371
372 i2c0_pins: i2c0-pins {
373 pins = "PB6", "PB7";
374 function = "i2c0";
375 };
376
377 /omit-if-no-ref/
378 i2c1_pb_pins: i2c1-pb-pins {
379 pins = "PB8", "PB9";
380 function = "i2c1";
381 };
382
383 /omit-if-no-ref/
384 i2c1_pe_pins: i2c1-pe-pins {
385 pins = "PE21", "PE22";
386 function = "i2c1";
387 };
388
389 uart0_pb_pins: uart0-pb-pins {
390 pins = "PB8", "PB9";
391 function = "uart0";
392 };
393
394 uart2_pins: uart2-pins {
395 pins = "PB0", "PB1";
396 function = "uart2";
397 };
398
399 mmc0_pins: mmc0-pins {
400 pins = "PF0", "PF1", "PF2", "PF3",
401 "PF4", "PF5";
402 function = "mmc0";
403 drive-strength = <30>;
404 bias-pull-up;
405 };
406
407 mmc1_pins: mmc1-pins {
408 pins = "PG0", "PG1", "PG2", "PG3",
409 "PG4", "PG5";
410 function = "mmc1";
411 drive-strength = <30>;
412 bias-pull-up;
413 };
414
415 spi0_pins: spi0-pins {
416 pins = "PC0", "PC1", "PC2", "PC3";
417 function = "spi0";
418 };
419 };
420
421 timer@1c20c00 {
422 compatible = "allwinner,sun8i-v3s-timer";
423 reg = <0x01c20c00 0xa0>;
424 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&osc24M>;
428 };
429
430 wdt0: watchdog@1c20ca0 {
431 compatible = "allwinner,sun6i-a31-wdt";
432 reg = <0x01c20ca0 0x20>;
433 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&osc24M>;
435 };
436
437 pwm: pwm@1c21400 {
438 compatible = "allwinner,sun8i-v3s-pwm",
439 "allwinner,sun7i-a20-pwm";
440 reg = <0x01c21400 0xc>;
441 clocks = <&osc24M>;
442 #pwm-cells = <3>;
443 status = "disabled";
444 };
445
446 lradc: lradc@1c22800 {
447 compatible = "allwinner,sun4i-a10-lradc-keys";
448 reg = <0x01c22800 0x400>;
449 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
450 status = "disabled";
451 };
452
453 codec: codec@1c22c00 {
454 #sound-dai-cells = <0>;
455 compatible = "allwinner,sun8i-v3s-codec";
456 reg = <0x01c22c00 0x400>;
457 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
459 clock-names = "apb", "codec";
460 resets = <&ccu RST_BUS_CODEC>;
461 dmas = <&dma 15>, <&dma 15>;
462 dma-names = "rx", "tx";
463 allwinner,codec-analog-controls = <&codec_analog>;
464 status = "disabled";
465 };
466
467 codec_analog: codec-analog@1c23000 {
468 compatible = "allwinner,sun8i-v3s-codec-analog";
469 reg = <0x01c23000 0x4>;
470 };
471
472 uart0: serial@1c28000 {
473 compatible = "snps,dw-apb-uart";
474 reg = <0x01c28000 0x400>;
475 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
476 reg-shift = <2>;
477 reg-io-width = <4>;
478 clocks = <&ccu CLK_BUS_UART0>;
479 dmas = <&dma 6>, <&dma 6>;
480 dma-names = "rx", "tx";
481 resets = <&ccu RST_BUS_UART0>;
482 status = "disabled";
483 };
484
485 uart1: serial@1c28400 {
486 compatible = "snps,dw-apb-uart";
487 reg = <0x01c28400 0x400>;
488 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
489 reg-shift = <2>;
490 reg-io-width = <4>;
491 clocks = <&ccu CLK_BUS_UART1>;
492 dmas = <&dma 7>, <&dma 7>;
493 dma-names = "rx", "tx";
494 resets = <&ccu RST_BUS_UART1>;
495 status = "disabled";
496 };
497
498 uart2: serial@1c28800 {
499 compatible = "snps,dw-apb-uart";
500 reg = <0x01c28800 0x400>;
501 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
502 reg-shift = <2>;
503 reg-io-width = <4>;
504 clocks = <&ccu CLK_BUS_UART2>;
505 dmas = <&dma 8>, <&dma 8>;
506 dma-names = "rx", "tx";
507 resets = <&ccu RST_BUS_UART2>;
508 pinctrl-0 = <&uart2_pins>;
509 pinctrl-names = "default";
510 status = "disabled";
511 };
512
513 i2c0: i2c@1c2ac00 {
514 compatible = "allwinner,sun6i-a31-i2c";
515 reg = <0x01c2ac00 0x400>;
516 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&ccu CLK_BUS_I2C0>;
518 resets = <&ccu RST_BUS_I2C0>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&i2c0_pins>;
521 status = "disabled";
522 #address-cells = <1>;
523 #size-cells = <0>;
524 };
525
526 i2c1: i2c@1c2b000 {
527 compatible = "allwinner,sun6i-a31-i2c";
528 reg = <0x01c2b000 0x400>;
529 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&ccu CLK_BUS_I2C1>;
531 resets = <&ccu RST_BUS_I2C1>;
532 status = "disabled";
533 #address-cells = <1>;
534 #size-cells = <0>;
535 };
536
537 emac: ethernet@1c30000 {
538 compatible = "allwinner,sun8i-v3s-emac";
539 syscon = <&syscon>;
540 reg = <0x01c30000 0x10000>;
541 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
542 interrupt-names = "macirq";
543 resets = <&ccu RST_BUS_EMAC>;
544 reset-names = "stmmaceth";
545 clocks = <&ccu CLK_BUS_EMAC>;
546 clock-names = "stmmaceth";
547 phy-handle = <&int_mii_phy>;
548 phy-mode = "mii";
549 status = "disabled";
550
551 mdio: mdio {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "snps,dwmac-mdio";
555 };
556
557 mdio_mux: mdio-mux {
558 compatible = "allwinner,sun8i-h3-mdio-mux";
559 #address-cells = <1>;
560 #size-cells = <0>;
561
562 mdio-parent-bus = <&mdio>;
563 /* Only one MDIO is usable at the time */
564 internal_mdio: mdio@1 {
565 compatible = "allwinner,sun8i-h3-mdio-internal";
566 reg = <1>;
567 #address-cells = <1>;
568 #size-cells = <0>;
569
570 int_mii_phy: ethernet-phy@1 {
571 compatible = "ethernet-phy-ieee802.3-c22";
572 reg = <1>;
573 clocks = <&ccu CLK_BUS_EPHY>;
574 resets = <&ccu RST_BUS_EPHY>;
575 };
576 };
577 };
578 };
579
580 spi0: spi@1c68000 {
581 compatible = "allwinner,sun8i-h3-spi";
582 reg = <0x01c68000 0x1000>;
583 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
585 clock-names = "ahb", "mod";
586 dmas = <&dma 23>, <&dma 23>;
587 dma-names = "rx", "tx";
588 pinctrl-names = "default";
589 pinctrl-0 = <&spi0_pins>;
590 resets = <&ccu RST_BUS_SPI0>;
591 status = "disabled";
592 #address-cells = <1>;
593 #size-cells = <0>;
594 };
595
596 csi1: camera@1cb4000 {
597 compatible = "allwinner,sun8i-v3s-csi";
598 reg = <0x01cb4000 0x3000>;
599 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&ccu CLK_BUS_CSI>,
601 <&ccu CLK_CSI1_SCLK>,
602 <&ccu CLK_DRAM_CSI>;
603 clock-names = "bus", "mod", "ram";
604 resets = <&ccu RST_BUS_CSI>;
605 status = "disabled";
606 };
607
608 gic: interrupt-controller@1c81000 {
609 compatible = "arm,gic-400";
610 reg = <0x01c81000 0x1000>,
611 <0x01c82000 0x2000>,
612 <0x01c84000 0x2000>,
613 <0x01c86000 0x2000>;
614 interrupt-controller;
615 #interrupt-cells = <3>;
616 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
617 };
618 };
619};
1/*
2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/clock/sun8i-v3s-ccu.h>
45#include <dt-bindings/reset/sun8i-v3s-ccu.h>
46
47/ {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 interrupt-parent = <&gic>;
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 cpu@0 {
57 compatible = "arm,cortex-a7";
58 device_type = "cpu";
59 reg = <0>;
60 clocks = <&ccu CLK_CPU>;
61 };
62 };
63
64 de: display-engine {
65 compatible = "allwinner,sun8i-v3s-display-engine";
66 allwinner,pipelines = <&mixer0>;
67 status = "disabled";
68 };
69
70 timer {
71 compatible = "arm,armv7-timer";
72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
76 };
77
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <1>;
81 ranges;
82
83 osc24M: osc24M_clk {
84 #clock-cells = <0>;
85 compatible = "fixed-clock";
86 clock-frequency = <24000000>;
87 clock-accuracy = <50000>;
88 clock-output-names = "osc24M";
89 };
90
91 osc32k: osc32k_clk {
92 #clock-cells = <0>;
93 compatible = "fixed-clock";
94 clock-frequency = <32768>;
95 clock-accuracy = <50000>;
96 clock-output-names = "ext-osc32k";
97 };
98 };
99
100 soc {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges;
105
106 display_clocks: clock@1000000 {
107 compatible = "allwinner,sun8i-v3s-de2-clk";
108 reg = <0x01000000 0x10000>;
109 clocks = <&ccu CLK_BUS_DE>,
110 <&ccu CLK_DE>;
111 clock-names = "bus",
112 "mod";
113 resets = <&ccu RST_BUS_DE>;
114 #clock-cells = <1>;
115 #reset-cells = <1>;
116 };
117
118 mixer0: mixer@1100000 {
119 compatible = "allwinner,sun8i-v3s-de2-mixer";
120 reg = <0x01100000 0x100000>;
121 clocks = <&display_clocks 0>,
122 <&display_clocks 6>;
123 clock-names = "bus",
124 "mod";
125 resets = <&display_clocks 0>;
126
127 ports {
128 #address-cells = <1>;
129 #size-cells = <0>;
130
131 mixer0_out: port@1 {
132 reg = <1>;
133
134 mixer0_out_tcon0: endpoint {
135 remote-endpoint = <&tcon0_in_mixer0>;
136 };
137 };
138 };
139 };
140
141 tcon0: lcd-controller@1c0c000 {
142 compatible = "allwinner,sun8i-v3s-tcon";
143 reg = <0x01c0c000 0x1000>;
144 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&ccu CLK_BUS_TCON0>,
146 <&ccu CLK_TCON0>;
147 clock-names = "ahb",
148 "tcon-ch0";
149 clock-output-names = "tcon-pixel-clock";
150 #clock-cells = <0>;
151 resets = <&ccu RST_BUS_TCON0>;
152 reset-names = "lcd";
153 status = "disabled";
154
155 ports {
156 #address-cells = <1>;
157 #size-cells = <0>;
158
159 tcon0_in: port@0 {
160 reg = <0>;
161
162 tcon0_in_mixer0: endpoint {
163 remote-endpoint = <&mixer0_out_tcon0>;
164 };
165 };
166
167 tcon0_out: port@1 {
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <1>;
171 };
172 };
173 };
174
175
176 mmc0: mmc@1c0f000 {
177 compatible = "allwinner,sun7i-a20-mmc";
178 reg = <0x01c0f000 0x1000>;
179 clocks = <&ccu CLK_BUS_MMC0>,
180 <&ccu CLK_MMC0>,
181 <&ccu CLK_MMC0_OUTPUT>,
182 <&ccu CLK_MMC0_SAMPLE>;
183 clock-names = "ahb",
184 "mmc",
185 "output",
186 "sample";
187 resets = <&ccu RST_BUS_MMC0>;
188 reset-names = "ahb";
189 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&mmc0_pins>;
192 status = "disabled";
193 #address-cells = <1>;
194 #size-cells = <0>;
195 };
196
197 mmc1: mmc@1c10000 {
198 compatible = "allwinner,sun7i-a20-mmc";
199 reg = <0x01c10000 0x1000>;
200 clocks = <&ccu CLK_BUS_MMC1>,
201 <&ccu CLK_MMC1>,
202 <&ccu CLK_MMC1_OUTPUT>,
203 <&ccu CLK_MMC1_SAMPLE>;
204 clock-names = "ahb",
205 "mmc",
206 "output",
207 "sample";
208 resets = <&ccu RST_BUS_MMC1>;
209 reset-names = "ahb";
210 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&mmc1_pins>;
213 status = "disabled";
214 #address-cells = <1>;
215 #size-cells = <0>;
216 };
217
218 mmc2: mmc@1c11000 {
219 compatible = "allwinner,sun7i-a20-mmc";
220 reg = <0x01c11000 0x1000>;
221 clocks = <&ccu CLK_BUS_MMC2>,
222 <&ccu CLK_MMC2>,
223 <&ccu CLK_MMC2_OUTPUT>,
224 <&ccu CLK_MMC2_SAMPLE>;
225 clock-names = "ahb",
226 "mmc",
227 "output",
228 "sample";
229 resets = <&ccu RST_BUS_MMC2>;
230 reset-names = "ahb";
231 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
232 status = "disabled";
233 #address-cells = <1>;
234 #size-cells = <0>;
235 };
236
237 usb_otg: usb@1c19000 {
238 compatible = "allwinner,sun8i-h3-musb";
239 reg = <0x01c19000 0x0400>;
240 clocks = <&ccu CLK_BUS_OTG>;
241 resets = <&ccu RST_BUS_OTG>;
242 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-names = "mc";
244 phys = <&usbphy 0>;
245 phy-names = "usb";
246 extcon = <&usbphy 0>;
247 status = "disabled";
248 };
249
250 usbphy: phy@1c19400 {
251 compatible = "allwinner,sun8i-v3s-usb-phy";
252 reg = <0x01c19400 0x2c>,
253 <0x01c1a800 0x4>;
254 reg-names = "phy_ctrl",
255 "pmu0";
256 clocks = <&ccu CLK_USB_PHY0>;
257 clock-names = "usb0_phy";
258 resets = <&ccu RST_USB_PHY0>;
259 reset-names = "usb0_reset";
260 status = "disabled";
261 #phy-cells = <1>;
262 };
263
264 ccu: clock@1c20000 {
265 compatible = "allwinner,sun8i-v3s-ccu";
266 reg = <0x01c20000 0x400>;
267 clocks = <&osc24M>, <&rtc 0>;
268 clock-names = "hosc", "losc";
269 #clock-cells = <1>;
270 #reset-cells = <1>;
271 };
272
273 rtc: rtc@1c20400 {
274 #clock-cells = <1>;
275 compatible = "allwinner,sun8i-v3-rtc";
276 reg = <0x01c20400 0x54>;
277 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&osc32k>;
280 clock-output-names = "osc32k", "osc32k-out";
281 };
282
283 pio: pinctrl@1c20800 {
284 compatible = "allwinner,sun8i-v3s-pinctrl";
285 reg = <0x01c20800 0x400>;
286 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
289 clock-names = "apb", "hosc", "losc";
290 gpio-controller;
291 #gpio-cells = <3>;
292 interrupt-controller;
293 #interrupt-cells = <3>;
294
295 i2c0_pins: i2c0-pins {
296 pins = "PB6", "PB7";
297 function = "i2c0";
298 };
299
300 uart0_pb_pins: uart0-pb-pins {
301 pins = "PB8", "PB9";
302 function = "uart0";
303 };
304
305 mmc0_pins: mmc0-pins {
306 pins = "PF0", "PF1", "PF2", "PF3",
307 "PF4", "PF5";
308 function = "mmc0";
309 drive-strength = <30>;
310 bias-pull-up;
311 };
312
313 mmc1_pins: mmc1-pins {
314 pins = "PG0", "PG1", "PG2", "PG3",
315 "PG4", "PG5";
316 function = "mmc1";
317 drive-strength = <30>;
318 bias-pull-up;
319 };
320
321 spi0_pins: spi0-pins {
322 pins = "PC0", "PC1", "PC2", "PC3";
323 function = "spi0";
324 };
325 };
326
327 timer@1c20c00 {
328 compatible = "allwinner,sun8i-v3s-timer";
329 reg = <0x01c20c00 0xa0>;
330 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&osc24M>;
334 };
335
336 wdt0: watchdog@1c20ca0 {
337 compatible = "allwinner,sun6i-a31-wdt";
338 reg = <0x01c20ca0 0x20>;
339 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&osc24M>;
341 };
342
343 lradc: lradc@1c22800 {
344 compatible = "allwinner,sun4i-a10-lradc-keys";
345 reg = <0x01c22800 0x400>;
346 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
347 status = "disabled";
348 };
349
350 uart0: serial@1c28000 {
351 compatible = "snps,dw-apb-uart";
352 reg = <0x01c28000 0x400>;
353 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
354 reg-shift = <2>;
355 reg-io-width = <4>;
356 clocks = <&ccu CLK_BUS_UART0>;
357 resets = <&ccu RST_BUS_UART0>;
358 status = "disabled";
359 };
360
361 uart1: serial@1c28400 {
362 compatible = "snps,dw-apb-uart";
363 reg = <0x01c28400 0x400>;
364 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
365 reg-shift = <2>;
366 reg-io-width = <4>;
367 clocks = <&ccu CLK_BUS_UART1>;
368 resets = <&ccu RST_BUS_UART1>;
369 status = "disabled";
370 };
371
372 uart2: serial@1c28800 {
373 compatible = "snps,dw-apb-uart";
374 reg = <0x01c28800 0x400>;
375 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
376 reg-shift = <2>;
377 reg-io-width = <4>;
378 clocks = <&ccu CLK_BUS_UART2>;
379 resets = <&ccu RST_BUS_UART2>;
380 status = "disabled";
381 };
382
383 i2c0: i2c@1c2ac00 {
384 compatible = "allwinner,sun6i-a31-i2c";
385 reg = <0x01c2ac00 0x400>;
386 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&ccu CLK_BUS_I2C0>;
388 resets = <&ccu RST_BUS_I2C0>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&i2c0_pins>;
391 status = "disabled";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 };
395
396 i2c1: i2c@1c2b000 {
397 compatible = "allwinner,sun6i-a31-i2c";
398 reg = <0x01c2b000 0x400>;
399 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&ccu CLK_BUS_I2C1>;
401 resets = <&ccu RST_BUS_I2C1>;
402 status = "disabled";
403 #address-cells = <1>;
404 #size-cells = <0>;
405 };
406
407 spi0: spi@1c68000 {
408 compatible = "allwinner,sun8i-h3-spi";
409 reg = <0x01c68000 0x1000>;
410 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
412 clock-names = "ahb", "mod";
413 pinctrl-names = "default";
414 pinctrl-0 = <&spi0_pins>;
415 resets = <&ccu RST_BUS_SPI0>;
416 status = "disabled";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 };
420
421 gic: interrupt-controller@1c81000 {
422 compatible = "arm,gic-400";
423 reg = <0x01c81000 0x1000>,
424 <0x01c82000 0x1000>,
425 <0x01c84000 0x2000>,
426 <0x01c86000 0x2000>;
427 interrupt-controller;
428 #interrupt-cells = <3>;
429 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
430 };
431 };
432};