1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright 2012 Linaro Ltd
   4 */
   5
   6#include <dt-bindings/interrupt-controller/irq.h>
   7#include <dt-bindings/interrupt-controller/arm-gic.h>
   8#include <dt-bindings/mfd/dbx500-prcmu.h>
   9#include <dt-bindings/arm/ux500_pm_domains.h>
  10#include <dt-bindings/gpio/gpio.h>
  11#include <dt-bindings/thermal/thermal.h>
  12
  13/ {
  14	#address-cells = <1>;
  15	#size-cells = <1>;
  16
  17	/* This stablilizes the device enumeration */
  18	aliases {
  19		i2c0 = &i2c0;
  20		i2c1 = &i2c1;
  21		i2c2 = &i2c2;
  22		i2c3 = &i2c3;
  23		i2c4 = &i2c4;
  24		spi0 = &spi0;
  25		spi1 = &spi1;
  26		spi2 = &spi2;
  27		spi3 = &spi3;
  28		serial0 = &serial0;
  29		serial1 = &serial1;
  30		serial2 = &serial2;
  31	};
  32
  33	chosen {
  34	};
  35
  36	cpus {
  37		#address-cells = <1>;
  38		#size-cells = <0>;
  39		enable-method = "ste,dbx500-smp";
  40
  41		cpu-map {
  42			cluster0 {
  43				core0 {
  44					cpu = <&CPU0>;
  45				};
  46				core1 {
  47					cpu = <&CPU1>;
  48				};
  49			};
  50		};
  51		CPU0: cpu@300 {
  52			device_type = "cpu";
  53			compatible = "arm,cortex-a9";
  54			reg = <0x300>;
  55			clocks = <&prcmu_clk PRCMU_ARMSS>;
  56			clock-names = "cpu";
  57			clock-latency = <20000>;
  58			#cooling-cells = <2>;
  59		};
  60		CPU1: cpu@301 {
  61			device_type = "cpu";
  62			compatible = "arm,cortex-a9";
  63			reg = <0x301>;
  64		};
  65	};
  66
  67	thermal-zones {
  68		/*
  69		 * Thermal zone for the SoC, using the thermal sensor in the
  70		 * PRCMU for temperature and the cpufreq driver for passive
  71		 * cooling.
  72		 */
  73		cpu_thermal: cpu-thermal {
  74			polling-delay-passive = <250>;
  75			/*
  76			 * This sensor fires interrupts to update the thermal
  77			 * zone, so no polling is needed.
  78			 */
  79			polling-delay = <0>;
  80
  81			thermal-sensors = <&thermal>;
  82
  83			trips {
  84				cpu_alert: cpu-alert {
  85					temperature = <70000>;
  86					hysteresis = <2000>;
  87					type = "passive";
  88				};
  89				cpu-crit {
  90					temperature = <85000>;
  91					hysteresis = <0>;
  92					type = "critical";
  93				};
  94			};
  95
  96			cooling-maps {
  97				trip = <&cpu_alert>;
  98				cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  99				contribution = <100>;
 100			};
 101		};
 102	};
 103
 104	soc {
 105		#address-cells = <1>;
 106		#size-cells = <1>;
 107		compatible = "stericsson,db8500", "simple-bus";
 108		interrupt-parent = <&intc>;
 109		ranges;
 110
 111		ptm@801ae000 {
 112			compatible = "arm,coresight-etm3x", "arm,primecell";
 113			reg = <0x801ae000 0x1000>;
 114
 115			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 116			clock-names = "apb_pclk", "atclk";
 117			cpu = <&CPU0>;
 118			out-ports {
 119				port {
 120					ptm0_out_port: endpoint {
 121						remote-endpoint = <&funnel_in_port0>;
 122					};
 123				};
 124			};
 125		};
 126
 127		ptm@801af000 {
 128			compatible = "arm,coresight-etm3x", "arm,primecell";
 129			reg = <0x801af000 0x1000>;
 130
 131			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 132			clock-names = "apb_pclk", "atclk";
 133			cpu = <&CPU1>;
 134			out-ports {
 135				port {
 136					ptm1_out_port: endpoint {
 137						remote-endpoint = <&funnel_in_port1>;
 138					};
 139				};
 140			};
 141		};
 142
 143		funnel@801a6000 {
 144			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 145			reg = <0x801a6000 0x1000>;
 146
 147			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 148			clock-names = "apb_pclk", "atclk";
 149			out-ports {
 150				port {
 151					funnel_out_port: endpoint {
 152						remote-endpoint =
 153							<&replicator_in_port0>;
 154					};
 155				};
 156			};
 157
 158			in-ports {
 159				#address-cells = <1>;
 160				#size-cells = <0>;
 161
 162				port@0 {
 163					reg = <0>;
 164					funnel_in_port0: endpoint {
 165						remote-endpoint = <&ptm0_out_port>;
 166					};
 167				};
 168
 169				port@1 {
 170					reg = <1>;
 171					funnel_in_port1: endpoint {
 172						remote-endpoint = <&ptm1_out_port>;
 173					};
 174				};
 175			};
 176		};
 177
 178		replicator {
 179			compatible = "arm,coresight-static-replicator";
 180			clocks = <&prcmu_clk PRCMU_APEATCLK>;
 181			clock-names = "atclk";
 182
 183			out-ports {
 184				#address-cells = <1>;
 185				#size-cells = <0>;
 186
 187				port@0 {
 188					reg = <0>;
 189					replicator_out_port0: endpoint {
 190						remote-endpoint = <&tpiu_in_port>;
 191					};
 192				};
 193				port@1 {
 194					reg = <1>;
 195					replicator_out_port1: endpoint {
 196						remote-endpoint = <&etb_in_port>;
 197					};
 198				};
 199			};
 200
 201			in-ports {
 202				port {
 203					replicator_in_port0: endpoint {
 204						remote-endpoint = <&funnel_out_port>;
 205					};
 206				};
 207			};
 208		};
 209
 210		tpiu@80190000 {
 211			compatible = "arm,coresight-tpiu", "arm,primecell";
 212			reg = <0x80190000 0x1000>;
 213
 214			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 215			clock-names = "apb_pclk", "atclk";
 216			in-ports {
 217				port {
 218					tpiu_in_port: endpoint {
 219						remote-endpoint = <&replicator_out_port0>;
 220					};
 221				};
 222			};
 223		};
 224
 225		etb@801a4000 {
 226			compatible = "arm,coresight-etb10", "arm,primecell";
 227			reg = <0x801a4000 0x1000>;
 228
 229			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 230			clock-names = "apb_pclk", "atclk";
 231			in-ports {
 232				port {
 233					etb_in_port: endpoint {
 234						remote-endpoint = <&replicator_out_port1>;
 235					};
 236				};
 237			};
 238		};
 239
 240		intc: interrupt-controller@a0411000 {
 241			compatible = "arm,cortex-a9-gic";
 242			#interrupt-cells = <3>;
 243			#address-cells = <1>;
 244			interrupt-controller;
 245			reg = <0xa0411000 0x1000>,
 246			      <0xa0410100 0x100>;
 247		};
 248
 249		scu@a0410000 {
 250			compatible = "arm,cortex-a9-scu";
 251			reg = <0xa0410000 0x100>;
 252		};
 253
 254		/*
 255		 * The backup RAM is used for retention during sleep
 256		 * and various things like spin tables
 257		 */
 258		backupram@80150000 {
 259			compatible = "ste,dbx500-backupram";
 260			reg = <0x80150000 0x2000>;
 261		};
 262
 263		L2: cache-controller {
 264			compatible = "arm,pl310-cache";
 265			reg = <0xa0412000 0x1000>;
 266			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 267			cache-unified;
 268			cache-level = <2>;
 269		};
 270
 271		pmu {
 272			compatible = "arm,cortex-a9-pmu";
 273			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 274		};
 275
 276		pm_domains: pm_domains0 {
 277			compatible = "stericsson,ux500-pm-domains";
 278			#power-domain-cells = <1>;
 279		};
 280
 281		clocks {
 282			compatible = "stericsson,u8500-clks";
 283			/*
 284			 * Registers for the CLKRST block on peripheral
 285			 * groups 1, 2, 3, 5, 6,
 286			 */
 287			reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
 288			    <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
 289			    <0xa03cf000 0x1000>;
 290
 291			prcmu_clk: prcmu-clock {
 292				#clock-cells = <1>;
 293			};
 294
 295			prcc_pclk: prcc-periph-clock {
 296				#clock-cells = <2>;
 297			};
 298
 299			prcc_kclk: prcc-kernel-clock {
 300				#clock-cells = <2>;
 301			};
 302
 303			rtc_clk: rtc32k-clock {
 304				#clock-cells = <0>;
 305			};
 306
 307			smp_twd_clk: smp-twd-clock {
 308				#clock-cells = <0>;
 309			};
 310		};
 311
 312		mtu@a03c6000 {
 313			/* Nomadik System Timer */
 314			compatible = "st,nomadik-mtu";
 315			reg = <0xa03c6000 0x1000>;
 316			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 317
 318			clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 319			clock-names = "timclk", "apb_pclk";
 320		};
 321
 322		timer@a0410600 {
 323			compatible = "arm,cortex-a9-twd-timer";
 324			reg = <0xa0410600 0x20>;
 325			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 326
 327			clocks = <&smp_twd_clk>;
 328		};
 329
 330		watchdog@a0410620 {
 331			compatible = "arm,cortex-a9-twd-wdt";
 332			reg = <0xa0410620 0x20>;
 333			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 334			clocks = <&smp_twd_clk>;
 335		};
 336
 337		rtc@80154000 {
 338			compatible = "arm,pl031", "arm,primecell";
 339			reg = <0x80154000 0x1000>;
 340			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 341
 342			clocks = <&rtc_clk>;
 343			clock-names = "apb_pclk";
 344		};
 345
 346		gpio0: gpio@8012e000 {
 347			compatible = "stericsson,db8500-gpio",
 348				"st,nomadik-gpio";
 349			reg =  <0x8012e000 0x80>;
 350			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 351			interrupt-controller;
 352			#interrupt-cells = <2>;
 353			st,supports-sleepmode;
 354			gpio-controller;
 355			#gpio-cells = <2>;
 356			gpio-bank = <0>;
 357			gpio-ranges = <&pinctrl 0 0 32>;
 358			clocks = <&prcc_pclk 1 9>;
 359		};
 360
 361		gpio1: gpio@8012e080 {
 362			compatible = "stericsson,db8500-gpio",
 363				"st,nomadik-gpio";
 364			reg =  <0x8012e080 0x80>;
 365			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 366			interrupt-controller;
 367			#interrupt-cells = <2>;
 368			st,supports-sleepmode;
 369			gpio-controller;
 370			#gpio-cells = <2>;
 371			gpio-bank = <1>;
 372			gpio-ranges = <&pinctrl 0 32 5>;
 373			clocks = <&prcc_pclk 1 9>;
 374		};
 375
 376		gpio2: gpio@8000e000 {
 377			compatible = "stericsson,db8500-gpio",
 378				"st,nomadik-gpio";
 379			reg =  <0x8000e000 0x80>;
 380			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 381			interrupt-controller;
 382			#interrupt-cells = <2>;
 383			st,supports-sleepmode;
 384			gpio-controller;
 385			#gpio-cells = <2>;
 386			gpio-bank = <2>;
 387			gpio-ranges = <&pinctrl 0 64 32>;
 388			clocks = <&prcc_pclk 3 8>;
 389		};
 390
 391		gpio3: gpio@8000e080 {
 392			compatible = "stericsson,db8500-gpio",
 393				"st,nomadik-gpio";
 394			reg =  <0x8000e080 0x80>;
 395			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 396			interrupt-controller;
 397			#interrupt-cells = <2>;
 398			st,supports-sleepmode;
 399			gpio-controller;
 400			#gpio-cells = <2>;
 401			gpio-bank = <3>;
 402			gpio-ranges = <&pinctrl 0 96 2>;
 403			clocks = <&prcc_pclk 3 8>;
 404		};
 405
 406		gpio4: gpio@8000e100 {
 407			compatible = "stericsson,db8500-gpio",
 408				"st,nomadik-gpio";
 409			reg =  <0x8000e100 0x80>;
 410			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 411			interrupt-controller;
 412			#interrupt-cells = <2>;
 413			st,supports-sleepmode;
 414			gpio-controller;
 415			#gpio-cells = <2>;
 416			gpio-bank = <4>;
 417			gpio-ranges = <&pinctrl 0 128 32>;
 418			clocks = <&prcc_pclk 3 8>;
 419		};
 420
 421		gpio5: gpio@8000e180 {
 422			compatible = "stericsson,db8500-gpio",
 423				"st,nomadik-gpio";
 424			reg =  <0x8000e180 0x80>;
 425			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 426			interrupt-controller;
 427			#interrupt-cells = <2>;
 428			st,supports-sleepmode;
 429			gpio-controller;
 430			#gpio-cells = <2>;
 431			gpio-bank = <5>;
 432			gpio-ranges = <&pinctrl 0 160 12>;
 433			clocks = <&prcc_pclk 3 8>;
 434		};
 435
 436		gpio6: gpio@8011e000 {
 437			compatible = "stericsson,db8500-gpio",
 438				"st,nomadik-gpio";
 439			reg =  <0x8011e000 0x80>;
 440			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 441			interrupt-controller;
 442			#interrupt-cells = <2>;
 443			st,supports-sleepmode;
 444			gpio-controller;
 445			#gpio-cells = <2>;
 446			gpio-bank = <6>;
 447			gpio-ranges = <&pinctrl 0 192 32>;
 448			clocks = <&prcc_pclk 2 11>;
 449		};
 450
 451		gpio7: gpio@8011e080 {
 452			compatible = "stericsson,db8500-gpio",
 453				"st,nomadik-gpio";
 454			reg =  <0x8011e080 0x80>;
 455			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 456			interrupt-controller;
 457			#interrupt-cells = <2>;
 458			st,supports-sleepmode;
 459			gpio-controller;
 460			#gpio-cells = <2>;
 461			gpio-bank = <7>;
 462			gpio-ranges = <&pinctrl 0 224 7>;
 463			clocks = <&prcc_pclk 2 11>;
 464		};
 465
 466		gpio8: gpio@a03fe000 {
 467			compatible = "stericsson,db8500-gpio",
 468				"st,nomadik-gpio";
 469			reg =  <0xa03fe000 0x80>;
 470			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 471			interrupt-controller;
 472			#interrupt-cells = <2>;
 473			st,supports-sleepmode;
 474			gpio-controller;
 475			#gpio-cells = <2>;
 476			gpio-bank = <8>;
 477			gpio-ranges = <&pinctrl 0 256 12>;
 478			clocks = <&prcc_pclk 5 1>;
 479		};
 480
 481		pinctrl: pinctrl {
 482			compatible = "stericsson,db8500-pinctrl";
 483			nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
 484						<&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
 485						<&gpio8>;
 486			prcm = <&prcmu>;
 487		};
 488
 489		usb_per5@a03e0000 {
 490			compatible = "stericsson,db8500-musb";
 491			reg = <0xa03e0000 0x10000>;
 492			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 493			interrupt-names = "mc";
 494
 495			dr_mode = "otg";
 496
 497			dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
 498			       <&dma 38 0 0x0>, /* Logical - MemToDev */
 499			       <&dma 37 0 0x2>, /* Logical - DevToMem */
 500			       <&dma 37 0 0x0>, /* Logical - MemToDev */
 501			       <&dma 36 0 0x2>, /* Logical - DevToMem */
 502			       <&dma 36 0 0x0>, /* Logical - MemToDev */
 503			       <&dma 19 0 0x2>, /* Logical - DevToMem */
 504			       <&dma 19 0 0x0>, /* Logical - MemToDev */
 505			       <&dma 18 0 0x2>, /* Logical - DevToMem */
 506			       <&dma 18 0 0x0>, /* Logical - MemToDev */
 507			       <&dma 17 0 0x2>, /* Logical - DevToMem */
 508			       <&dma 17 0 0x0>, /* Logical - MemToDev */
 509			       <&dma 16 0 0x2>, /* Logical - DevToMem */
 510			       <&dma 16 0 0x0>, /* Logical - MemToDev */
 511			       <&dma 39 0 0x2>, /* Logical - DevToMem */
 512			       <&dma 39 0 0x0>; /* Logical - MemToDev */
 513
 514			dma-names = "iep_1_9",  "oep_1_9",
 515				    "iep_2_10", "oep_2_10",
 516				    "iep_3_11", "oep_3_11",
 517				    "iep_4_12", "oep_4_12",
 518				    "iep_5_13", "oep_5_13",
 519				    "iep_6_14", "oep_6_14",
 520				    "iep_7_15", "oep_7_15",
 521				    "iep_8",    "oep_8";
 522
 523			clocks = <&prcc_pclk 5 0>;
 524		};
 525
 526		dma: dma-controller@801C0000 {
 527			compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 528			reg = <0x801C0000 0x1000 0x40010000 0x800>;
 529			reg-names = "base", "lcpa";
 530			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 531
 532			#dma-cells = <3>;
 533			memcpy-channels = <56 57 58 59 60>;
 534
 535			clocks = <&prcmu_clk PRCMU_DMACLK>;
 536		};
 537
 538		prcmu: prcmu@80157000 {
 539			compatible = "stericsson,db8500-prcmu", "syscon";
 540			reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 541			reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 542			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 543			#address-cells = <1>;
 544			#size-cells = <1>;
 545			interrupt-controller;
 546			#interrupt-cells = <2>;
 547			ranges;
 548
 549			prcmu-timer-4@80157450 {
 550				compatible = "stericsson,db8500-prcmu-timer-4";
 551				reg = <0x80157450 0xC>;
 552			};
 553
 554			thermal: thermal@801573c0 {
 555				compatible = "stericsson,db8500-thermal";
 556				reg = <0x801573c0 0x40>;
 557				interrupt-parent = <&prcmu>;
 558				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
 559					     <22 IRQ_TYPE_LEVEL_HIGH>;
 560				interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 561				#thermal-sensor-cells = <0>;
 562			};
 563
 564			db8500-prcmu-regulators {
 565				compatible = "stericsson,db8500-prcmu-regulator";
 566
 567				// DB8500_REGULATOR_VAPE
 568				db8500_vape_reg: db8500_vape {
 569					regulator-always-on;
 570				};
 571
 572				// DB8500_REGULATOR_VARM
 573				db8500_varm_reg: db8500_varm {
 574				};
 575
 576				// DB8500_REGULATOR_VMODEM
 577				db8500_vmodem_reg: db8500_vmodem {
 578				};
 579
 580				// DB8500_REGULATOR_VPLL
 581				db8500_vpll_reg: db8500_vpll {
 582				};
 583
 584				// DB8500_REGULATOR_VSMPS1
 585				db8500_vsmps1_reg: db8500_vsmps1 {
 586				};
 587
 588				// DB8500_REGULATOR_VSMPS2
 589				db8500_vsmps2_reg: db8500_vsmps2 {
 590				};
 591
 592				// DB8500_REGULATOR_VSMPS3
 593				db8500_vsmps3_reg: db8500_vsmps3 {
 594				};
 595
 596				// DB8500_REGULATOR_VRF1
 597				db8500_vrf1_reg: db8500_vrf1 {
 598				};
 599
 600				// DB8500_REGULATOR_SWITCH_SVAMMDSP
 601				db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
 602				};
 603
 604				// DB8500_REGULATOR_SWITCH_SVAMMDSPRET
 605				db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
 606				};
 607
 608				// DB8500_REGULATOR_SWITCH_SVAPIPE
 609				db8500_sva_pipe_reg: db8500_sva_pipe {
 610				};
 611
 612				// DB8500_REGULATOR_SWITCH_SIAMMDSP
 613				db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
 614				};
 615
 616				// DB8500_REGULATOR_SWITCH_SIAMMDSPRET
 617				db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
 618				};
 619
 620				// DB8500_REGULATOR_SWITCH_SIAPIPE
 621				db8500_sia_pipe_reg: db8500_sia_pipe {
 622				};
 623
 624				// DB8500_REGULATOR_SWITCH_SGA
 625				db8500_sga_reg: db8500_sga {
 626					vin-supply = <&db8500_vape_reg>;
 627				};
 628
 629				// DB8500_REGULATOR_SWITCH_B2R2_MCDE
 630				db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
 631					vin-supply = <&db8500_vape_reg>;
 632				};
 633
 634				// DB8500_REGULATOR_SWITCH_ESRAM12
 635				db8500_esram12_reg: db8500_esram12 {
 636				};
 637
 638				// DB8500_REGULATOR_SWITCH_ESRAM12RET
 639				db8500_esram12_ret_reg: db8500_esram12_ret {
 640				};
 641
 642				// DB8500_REGULATOR_SWITCH_ESRAM34
 643				db8500_esram34_reg: db8500_esram34 {
 644				};
 645
 646				// DB8500_REGULATOR_SWITCH_ESRAM34RET
 647				db8500_esram34_ret_reg: db8500_esram34_ret {
 648				};
 649			};
 650		};
 651
 652		i2c0: i2c@80004000 {
 653			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 654			reg = <0x80004000 0x1000>;
 655			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 656
 657			#address-cells = <1>;
 658			#size-cells = <0>;
 659			v-i2c-supply = <&db8500_vape_reg>;
 660
 661			clock-frequency = <400000>;
 662			clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
 663			clock-names = "i2cclk", "apb_pclk";
 664			power-domains = <&pm_domains DOMAIN_VAPE>;
 665
 666			status = "disabled";
 667		};
 668
 669		i2c1: i2c@80122000 {
 670			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 671			reg = <0x80122000 0x1000>;
 672			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 673
 674			#address-cells = <1>;
 675			#size-cells = <0>;
 676			v-i2c-supply = <&db8500_vape_reg>;
 677
 678			clock-frequency = <400000>;
 679
 680			clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
 681			clock-names = "i2cclk", "apb_pclk";
 682			power-domains = <&pm_domains DOMAIN_VAPE>;
 683
 684			status = "disabled";
 685		};
 686
 687		i2c2: i2c@80128000 {
 688			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 689			reg = <0x80128000 0x1000>;
 690			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 691
 692			#address-cells = <1>;
 693			#size-cells = <0>;
 694			v-i2c-supply = <&db8500_vape_reg>;
 695
 696			clock-frequency = <400000>;
 697
 698			clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
 699			clock-names = "i2cclk", "apb_pclk";
 700			power-domains = <&pm_domains DOMAIN_VAPE>;
 701
 702			status = "disabled";
 703		};
 704
 705		i2c3: i2c@80110000 {
 706			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 707			reg = <0x80110000 0x1000>;
 708			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 709
 710			#address-cells = <1>;
 711			#size-cells = <0>;
 712			v-i2c-supply = <&db8500_vape_reg>;
 713
 714			clock-frequency = <400000>;
 715
 716			clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
 717			clock-names = "i2cclk", "apb_pclk";
 718			power-domains = <&pm_domains DOMAIN_VAPE>;
 719
 720			status = "disabled";
 721		};
 722
 723		i2c4: i2c@8012a000 {
 724			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 725			reg = <0x8012a000 0x1000>;
 726			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 727
 728			#address-cells = <1>;
 729			#size-cells = <0>;
 730			v-i2c-supply = <&db8500_vape_reg>;
 731
 732			clock-frequency = <400000>;
 733
 734			clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
 735			clock-names = "i2cclk", "apb_pclk";
 736			power-domains = <&pm_domains DOMAIN_VAPE>;
 737
 738			status = "disabled";
 739		};
 740
 741		ssp0: spi@80002000 {
 742			compatible = "arm,pl022", "arm,primecell";
 743			reg = <0x80002000 0x1000>;
 744			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 745			#address-cells = <1>;
 746			#size-cells = <0>;
 747			clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
 748			clock-names = "SSPCLK", "apb_pclk";
 749			dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
 750			       <&dma 8 0 0x0>; /* Logical - MemToDev */
 751			dma-names = "rx", "tx";
 752			power-domains = <&pm_domains DOMAIN_VAPE>;
 753
 754			status = "disabled";
 755		};
 756
 757		ssp1: spi@80003000 {
 758			compatible = "arm,pl022", "arm,primecell";
 759			reg = <0x80003000 0x1000>;
 760			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 761			#address-cells = <1>;
 762			#size-cells = <0>;
 763			clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
 764			clock-names = "SSPCLK", "apb_pclk";
 765			dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
 766			       <&dma 9 0 0x0>; /* Logical - MemToDev */
 767			dma-names = "rx", "tx";
 768			power-domains = <&pm_domains DOMAIN_VAPE>;
 769
 770			status = "disabled";
 771		};
 772
 773		spi0: spi@8011a000 {
 774			compatible = "arm,pl022", "arm,primecell";
 775			reg = <0x8011a000 0x1000>;
 776			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 777			#address-cells = <1>;
 778			#size-cells = <0>;
 779			/* Same clock wired to kernel and pclk */
 780			clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
 781			clock-names = "SSPCLK", "apb_pclk";
 782			dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
 783			       <&dma 0 0 0x0>; /* Logical - MemToDev */
 784			dma-names = "rx", "tx";
 785			power-domains = <&pm_domains DOMAIN_VAPE>;
 786
 787			status = "disabled";
 788		};
 789
 790		spi1: spi@80112000 {
 791			compatible = "arm,pl022", "arm,primecell";
 792			reg = <0x80112000 0x1000>;
 793			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 794			#address-cells = <1>;
 795			#size-cells = <0>;
 796			/* Same clock wired to kernel and pclk */
 797			clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
 798			clock-names = "SSPCLK", "apb_pclk";
 799			dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
 800			       <&dma 35 0 0x0>; /* Logical - MemToDev */
 801			dma-names = "rx", "tx";
 802			power-domains = <&pm_domains DOMAIN_VAPE>;
 803
 804			status = "disabled";
 805		};
 806
 807		spi2: spi@80111000 {
 808			compatible = "arm,pl022", "arm,primecell";
 809			reg = <0x80111000 0x1000>;
 810			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 811			#address-cells = <1>;
 812			#size-cells = <0>;
 813			/* Same clock wired to kernel and pclk */
 814			clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
 815			clock-names = "SSPCLK", "apb_pclk";
 816			dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
 817			       <&dma 33 0 0x0>; /* Logical - MemToDev */
 818			dma-names = "rx", "tx";
 819			power-domains = <&pm_domains DOMAIN_VAPE>;
 820
 821			status = "disabled";
 822		};
 823
 824		spi3: spi@80129000 {
 825			compatible = "arm,pl022", "arm,primecell";
 826			reg = <0x80129000 0x1000>;
 827			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 828			#address-cells = <1>;
 829			#size-cells = <0>;
 830			/* Same clock wired to kernel and pclk */
 831			clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
 832			clock-names = "SSPCLK", "apb_pclk";
 833			dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
 834			       <&dma 40 0 0x0>; /* Logical - MemToDev */
 835			dma-names = "rx", "tx";
 836			power-domains = <&pm_domains DOMAIN_VAPE>;
 837
 838			status = "disabled";
 839		};
 840
 841		serial0: uart@80120000 {
 842			compatible = "arm,pl011", "arm,primecell";
 843			reg = <0x80120000 0x1000>;
 844			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 845
 846			dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 847			       <&dma 13 0 0x0>; /* Logical - MemToDev */
 848			dma-names = "rx", "tx";
 849
 850			clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
 851			clock-names = "uart", "apb_pclk";
 852
 853			status = "disabled";
 854		};
 855
 856		serial1: uart@80121000 {
 857			compatible = "arm,pl011", "arm,primecell";
 858			reg = <0x80121000 0x1000>;
 859			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 860
 861			dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
 862			       <&dma 12 0 0x0>; /* Logical - MemToDev */
 863			dma-names = "rx", "tx";
 864
 865			clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
 866			clock-names = "uart", "apb_pclk";
 867
 868			status = "disabled";
 869		};
 870
 871		serial2: uart@80007000 {
 872			compatible = "arm,pl011", "arm,primecell";
 873			reg = <0x80007000 0x1000>;
 874			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 875
 876			dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
 877			       <&dma 11 0 0x0>; /* Logical - MemToDev */
 878			dma-names = "rx", "tx";
 879
 880			clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
 881			clock-names = "uart", "apb_pclk";
 882
 883			status = "disabled";
 884		};
 885
 886		mmc@80126000 {
 887			compatible = "arm,pl18x", "arm,primecell";
 888			reg = <0x80126000 0x1000>;
 889			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 890
 891			dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
 892			       <&dma 29 0 0x0>; /* Logical - MemToDev */
 893			dma-names = "rx", "tx";
 894
 895			clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
 896			clock-names = "sdi", "apb_pclk";
 897			power-domains = <&pm_domains DOMAIN_VAPE>;
 898
 899			status = "disabled";
 900		};
 901
 902		mmc@80118000 {
 903			compatible = "arm,pl18x", "arm,primecell";
 904			reg = <0x80118000 0x1000>;
 905			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 906
 907			dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
 908			       <&dma 32 0 0x0>; /* Logical - MemToDev */
 909			dma-names = "rx", "tx";
 910
 911			clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
 912			clock-names = "sdi", "apb_pclk";
 913			power-domains = <&pm_domains DOMAIN_VAPE>;
 914
 915			status = "disabled";
 916		};
 917
 918		mmc@80005000 {
 919			compatible = "arm,pl18x", "arm,primecell";
 920			reg = <0x80005000 0x1000>;
 921			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 922
 923			dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
 924			       <&dma 28 0 0x0>; /* Logical - MemToDev */
 925			dma-names = "rx", "tx";
 926
 927			clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
 928			clock-names = "sdi", "apb_pclk";
 929			power-domains = <&pm_domains DOMAIN_VAPE>;
 930
 931			status = "disabled";
 932		};
 933
 934		mmc@80119000 {
 935			compatible = "arm,pl18x", "arm,primecell";
 936			reg = <0x80119000 0x1000>;
 937			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 938
 939			dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
 940			       <&dma 41 0 0x0>; /* Logical - MemToDev */
 941			dma-names = "rx", "tx";
 942
 943			clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
 944			clock-names = "sdi", "apb_pclk";
 945			power-domains = <&pm_domains DOMAIN_VAPE>;
 946
 947			status = "disabled";
 948		};
 949
 950		mmc@80114000 {
 951			compatible = "arm,pl18x", "arm,primecell";
 952			reg = <0x80114000 0x1000>;
 953			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 954
 955			dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
 956			       <&dma 42 0 0x0>; /* Logical - MemToDev */
 957			dma-names = "rx", "tx";
 958
 959			clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
 960			clock-names = "sdi", "apb_pclk";
 961			power-domains = <&pm_domains DOMAIN_VAPE>;
 962
 963			status = "disabled";
 964		};
 965
 966		mmc@80008000 {
 967			compatible = "arm,pl18x", "arm,primecell";
 968			reg = <0x80008000 0x1000>;
 969			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 970
 971			dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
 972			       <&dma 43 0 0x0>; /* Logical - MemToDev */
 973			dma-names = "rx", "tx";
 974
 975			clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
 976			clock-names = "sdi", "apb_pclk";
 977			power-domains = <&pm_domains DOMAIN_VAPE>;
 978
 979			status = "disabled";
 980		};
 981
 982		sound {
 983			compatible = "stericsson,snd-soc-mop500";
 984			stericsson,cpu-dai = <&msp1 &msp3>;
 985		};
 986
 987		msp0: msp@80123000 {
 988			compatible = "stericsson,ux500-msp-i2s";
 989			reg = <0x80123000 0x1000>;
 990			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 991			v-ape-supply = <&db8500_vape_reg>;
 992
 993			dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
 994			       <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
 995			dma-names = "rx", "tx";
 996
 997			clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
 998			clock-names = "msp", "apb_pclk";
 999
1000			status = "disabled";
1001		};
1002
1003		msp1: msp@80124000 {
1004			compatible = "stericsson,ux500-msp-i2s";
1005			reg = <0x80124000 0x1000>;
1006			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1007			v-ape-supply = <&db8500_vape_reg>;
1008
1009			/* This DMA channel only exist on DB8500 v1 */
1010			dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1011			dma-names = "tx";
1012
1013			clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1014			clock-names = "msp", "apb_pclk";
1015
1016			status = "disabled";
1017		};
1018
1019		// HDMI sound
1020		msp2: msp@80117000 {
1021			compatible = "stericsson,ux500-msp-i2s";
1022			reg = <0x80117000 0x1000>;
1023			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1024			v-ape-supply = <&db8500_vape_reg>;
1025
1026			dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
1027			       <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1028                                                    HighPrio - Fixed */
1029			dma-names = "rx", "tx";
1030
1031			clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1032			clock-names = "msp", "apb_pclk";
1033
1034			status = "disabled";
1035		};
1036
1037		msp3: msp@80125000 {
1038			compatible = "stericsson,ux500-msp-i2s";
1039			reg = <0x80125000 0x1000>;
1040			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1041			v-ape-supply = <&db8500_vape_reg>;
1042
1043			/* This DMA channel only exist on DB8500 v2 */
1044			dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1045			dma-names = "rx";
1046
1047			clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1048			clock-names = "msp", "apb_pclk";
1049
1050			status = "disabled";
1051		};
1052
1053		external-bus@50000000 {
1054			compatible = "simple-bus";
1055			reg = <0x50000000 0x4000000>;
1056			#address-cells = <1>;
1057			#size-cells = <1>;
1058			ranges = <0 0x50000000 0x4000000>;
1059			status = "disabled";
1060		};
1061
1062		gpu@a0300000 {
1063			/*
1064			 * This block is referred to as "Smart Graphics Adapter SGA500"
1065			 * in documentation but is in practice a pretty straight-forward
1066			 * MALI-400 GPU block.
1067			 */
1068			compatible = "stericsson,db8500-mali", "arm,mali-400";
1069			reg = <0xa0300000 0x10000>;
1070			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1071				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1072				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1073				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1074				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1075			interrupt-names = "gp",
1076					  "gpmmu",
1077					  "pp0",
1078					  "ppmmu0",
1079					  "combined";
1080			clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
1081			clock-names = "bus", "core";
1082			mali-supply = <&db8500_sga_reg>;
1083			power-domains = <&pm_domains DOMAIN_VAPE>;
1084		};
1085
1086		mcde@a0350000 {
1087			compatible = "ste,mcde";
1088			reg = <0xa0350000 0x1000>;
1089			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1090			epod-supply = <&db8500_b2r2_mcde_reg>;
1091			clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1092				 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1093				 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
1094			clock-names = "mcde", "lcd", "hdmi";
1095			#address-cells = <1>;
1096			#size-cells = <1>;
1097			ranges;
1098			status = "disabled";
1099
1100			dsi0: dsi@a0351000 {
1101				compatible = "ste,mcde-dsi";
1102				reg = <0xa0351000 0x1000>;
1103				clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1104				clock-names = "hs", "lp";
1105				#address-cells = <1>;
1106				#size-cells = <0>;
1107			};
1108			dsi1: dsi@a0352000 {
1109				compatible = "ste,mcde-dsi";
1110				reg = <0xa0352000 0x1000>;
1111				clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1112				clock-names = "hs", "lp";
1113				#address-cells = <1>;
1114				#size-cells = <0>;
1115			};
1116			dsi2: dsi@a0353000 {
1117				compatible = "ste,mcde-dsi";
1118				reg = <0xa0353000 0x1000>;
1119				/* This DSI port only has the Low Power / Energy Save clock */
1120				clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1121				clock-names = "lp";
1122				#address-cells = <1>;
1123				#size-cells = <0>;
1124			};
1125		};
1126
1127		cryp@a03cb000 {
1128			compatible = "stericsson,ux500-cryp";
1129			reg = <0xa03cb000 0x1000>;
1130			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1131
1132			v-ape-supply = <&db8500_vape_reg>;
1133			clocks = <&prcc_pclk 6 1>;
1134		};
1135
1136		hash@a03c2000 {
1137			compatible = "stericsson,ux500-hash";
1138			reg = <0xa03c2000 0x1000>;
1139
1140			v-ape-supply = <&db8500_vape_reg>;
1141			clocks = <&prcc_pclk 6 2>;
1142		};
1143	};
1144};