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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
4 *
5 * Copyright (C) 2014 Atmel,
6 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
7 */
8
9#include <dt-bindings/clock/at91.h>
10#include <dt-bindings/dma/at91.h>
11#include <dt-bindings/pinctrl/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Atmel SAMA5D4 family SoC";
19 compatible = "atmel,sama5d4";
20 interrupt-parent = <&aic>;
21
22 aliases {
23 serial0 = &usart3;
24 serial1 = &usart4;
25 serial2 = &usart2;
26 serial3 = &usart0;
27 serial4 = &usart1;
28 serial5 = &uart0;
29 serial6 = &uart1;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 pwm0 = &pwm0;
36 ssc0 = &ssc0;
37 ssc1 = &ssc1;
38 tcb0 = &tcb0;
39 tcb1 = &tcb1;
40 i2c0 = &i2c0;
41 i2c1 = &i2c1;
42 i2c2 = &i2c2;
43 };
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a5";
51 reg = <0>;
52 next-level-cache = <&L2>;
53 };
54 };
55
56 memory@20000000 {
57 device_type = "memory";
58 reg = <0x20000000 0x20000000>;
59 };
60
61 clocks {
62 slow_xtal: slow_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
67
68 main_xtal: main_xtal {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
73
74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <1000000>;
78 };
79 };
80
81 ns_sram: sram@210000 {
82 compatible = "mmio-sram";
83 reg = <0x00210000 0x10000>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges = <0 0x00210000 0x10000>;
87 };
88
89 ahb {
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges;
94
95 nfc_sram: sram@100000 {
96 compatible = "mmio-sram";
97 no-memory-wc;
98 reg = <0x100000 0x2400>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x100000 0x2400>;
102 };
103
104 vdec0: vdec@300000 {
105 compatible = "microchip,sama5d4-vdec";
106 reg = <0x00300000 0x100000>;
107 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
108 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
109 };
110
111 usb0: gadget@400000 {
112 compatible = "atmel,sama5d3-udc";
113 reg = <0x00400000 0x100000
114 0xfc02c000 0x4000>;
115 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
116 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
117 clock-names = "pclk", "hclk";
118 status = "disabled";
119 };
120
121 usb1: ohci@500000 {
122 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
123 reg = <0x00500000 0x100000>;
124 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
125 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>;
126 clock-names = "ohci_clk", "hclk", "uhpck";
127 status = "disabled";
128 };
129
130 usb2: ehci@600000 {
131 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
132 reg = <0x00600000 0x100000>;
133 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
134 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
135 clock-names = "usb_clk", "ehci_clk";
136 status = "disabled";
137 };
138
139 L2: cache-controller@a00000 {
140 compatible = "arm,pl310-cache";
141 reg = <0x00a00000 0x1000>;
142 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
143 cache-unified;
144 cache-level = <2>;
145 };
146
147 ebi: ebi@10000000 {
148 compatible = "atmel,sama5d3-ebi";
149 #address-cells = <2>;
150 #size-cells = <1>;
151 atmel,smc = <&hsmc>;
152 reg = <0x10000000 0x10000000
153 0x60000000 0x28000000>;
154 ranges = <0x0 0x0 0x10000000 0x10000000
155 0x1 0x0 0x60000000 0x10000000
156 0x2 0x0 0x70000000 0x10000000
157 0x3 0x0 0x80000000 0x8000000>;
158 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
159 status = "disabled";
160
161 nand_controller: nand-controller {
162 compatible = "atmel,sama5d3-nand-controller";
163 atmel,nfc-sram = <&nfc_sram>;
164 atmel,nfc-io = <&nfc_io>;
165 ecc-engine = <&pmecc>;
166 #address-cells = <2>;
167 #size-cells = <1>;
168 ranges;
169 status = "disabled";
170 };
171 };
172
173 nfc_io: nfc-io@90000000 {
174 compatible = "atmel,sama5d3-nfc-io", "syscon";
175 reg = <0x90000000 0x8000000>;
176 };
177
178 apb {
179 compatible = "simple-bus";
180 #address-cells = <1>;
181 #size-cells = <1>;
182 ranges;
183
184 hlcdc: hlcdc@f0000000 {
185 compatible = "atmel,sama5d4-hlcdc";
186 reg = <0xf0000000 0x4000>;
187 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
188 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
189 clock-names = "periph_clk","sys_clk", "slow_clk";
190 status = "disabled";
191
192 hlcdc-display-controller {
193 compatible = "atmel,hlcdc-display-controller";
194 #address-cells = <1>;
195 #size-cells = <0>;
196
197 port@0 {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 reg = <0>;
201 };
202 };
203
204 hlcdc_pwm: hlcdc-pwm {
205 compatible = "atmel,hlcdc-pwm";
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_lcd_pwm>;
208 #pwm-cells = <3>;
209 };
210 };
211
212 dma1: dma-controller@f0004000 {
213 compatible = "atmel,sama5d4-dma";
214 reg = <0xf0004000 0x200>;
215 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
216 #dma-cells = <1>;
217 clocks = <&pmc PMC_TYPE_PERIPHERAL 50>;
218 clock-names = "dma_clk";
219 };
220
221 isi: isi@f0008000 {
222 compatible = "atmel,at91sam9g45-isi";
223 reg = <0xf0008000 0x4000>;
224 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_isi_data_0_7>;
227 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
228 clock-names = "isi_clk";
229 status = "disabled";
230 port {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 };
234 };
235
236 ramc0: ramc@f0010000 {
237 compatible = "atmel,sama5d3-ddramc";
238 reg = <0xf0010000 0x200>;
239 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>;
240 clock-names = "ddrck", "mpddr";
241 };
242
243 dma0: dma-controller@f0014000 {
244 compatible = "atmel,sama5d4-dma";
245 reg = <0xf0014000 0x200>;
246 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
247 #dma-cells = <1>;
248 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
249 clock-names = "dma_clk";
250 };
251
252 pmc: pmc@f0018000 {
253 compatible = "atmel,sama5d4-pmc", "syscon";
254 reg = <0xf0018000 0x120>;
255 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
256 #clock-cells = <2>;
257 clocks = <&clk32k>, <&main_xtal>;
258 clock-names = "slow_clk", "main_xtal";
259 };
260
261 mmc0: mmc@f8000000 {
262 compatible = "atmel,hsmci";
263 reg = <0xf8000000 0x600>;
264 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
265 dmas = <&dma1
266 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
267 | AT91_XDMAC_DT_PERID(0))>;
268 dma-names = "rxtx";
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
271 status = "disabled";
272 #address-cells = <1>;
273 #size-cells = <0>;
274 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
275 clock-names = "mci_clk";
276 };
277
278 uart0: serial@f8004000 {
279 compatible = "atmel,at91sam9260-usart";
280 reg = <0xf8004000 0x100>;
281 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
282 dmas = <&dma0
283 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
284 | AT91_XDMAC_DT_PERID(22))>,
285 <&dma0
286 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
287 | AT91_XDMAC_DT_PERID(23))>;
288 dma-names = "tx", "rx";
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_uart0>;
291 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
292 clock-names = "usart";
293 status = "disabled";
294 };
295
296 ssc0: ssc@f8008000 {
297 compatible = "atmel,at91sam9g45-ssc";
298 reg = <0xf8008000 0x4000>;
299 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
302 dmas = <&dma1
303 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
304 | AT91_XDMAC_DT_PERID(26))>,
305 <&dma1
306 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
307 | AT91_XDMAC_DT_PERID(27))>;
308 dma-names = "tx", "rx";
309 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
310 clock-names = "pclk";
311 status = "disabled";
312 };
313
314 pwm0: pwm@f800c000 {
315 compatible = "atmel,sama5d3-pwm";
316 reg = <0xf800c000 0x300>;
317 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
318 #pwm-cells = <3>;
319 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
320 status = "disabled";
321 };
322
323 spi0: spi@f8010000 {
324 #address-cells = <1>;
325 #size-cells = <0>;
326 compatible = "atmel,at91rm9200-spi";
327 reg = <0xf8010000 0x100>;
328 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
329 dmas = <&dma1
330 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
331 | AT91_XDMAC_DT_PERID(10))>,
332 <&dma1
333 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
334 | AT91_XDMAC_DT_PERID(11))>;
335 dma-names = "tx", "rx";
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_spi0>;
338 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
339 clock-names = "spi_clk";
340 status = "disabled";
341 };
342
343 i2c0: i2c@f8014000 {
344 compatible = "atmel,sama5d4-i2c";
345 reg = <0xf8014000 0x4000>;
346 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
347 dmas = <&dma1
348 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
349 | AT91_XDMAC_DT_PERID(2))>,
350 <&dma1
351 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
352 | AT91_XDMAC_DT_PERID(3))>;
353 dma-names = "tx", "rx";
354 pinctrl-names = "default", "gpio";
355 pinctrl-0 = <&pinctrl_i2c0>;
356 pinctrl-1 = <&pinctrl_i2c0_gpio>;
357 sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
358 scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
362 status = "disabled";
363 };
364
365 i2c1: i2c@f8018000 {
366 compatible = "atmel,sama5d4-i2c";
367 reg = <0xf8018000 0x4000>;
368 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
369 dmas = <&dma0
370 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
371 | AT91_XDMAC_DT_PERID(4))>,
372 <&dma0
373 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
374 | AT91_XDMAC_DT_PERID(5))>;
375 dma-names = "tx", "rx";
376 pinctrl-names = "default", "gpio";
377 pinctrl-0 = <&pinctrl_i2c1>;
378 pinctrl-1 = <&pinctrl_i2c1_gpio>;
379 sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
380 scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
384 status = "disabled";
385 };
386
387 tcb0: timer@f801c000 {
388 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
389 #address-cells = <1>;
390 #size-cells = <0>;
391 reg = <0xf801c000 0x100>;
392 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
393 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>;
394 clock-names = "t0_clk", "slow_clk";
395 };
396
397 macb0: ethernet@f8020000 {
398 compatible = "atmel,sama5d4-gem";
399 reg = <0xf8020000 0x100>;
400 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_macb0_rmii>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>;
406 clock-names = "hclk", "pclk";
407 status = "disabled";
408 };
409
410 i2c2: i2c@f8024000 {
411 compatible = "atmel,sama5d4-i2c";
412 reg = <0xf8024000 0x4000>;
413 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
414 dmas = <&dma1
415 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
416 | AT91_XDMAC_DT_PERID(6))>,
417 <&dma1
418 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
419 | AT91_XDMAC_DT_PERID(7))>;
420 dma-names = "tx", "rx";
421 pinctrl-names = "default", "gpio";
422 pinctrl-0 = <&pinctrl_i2c2>;
423 pinctrl-1 = <&pinctrl_i2c2_gpio>;
424 sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>;
425 scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
429 status = "disabled";
430 };
431
432 sfr: sfr@f8028000 {
433 compatible = "atmel,sama5d4-sfr", "syscon";
434 reg = <0xf8028000 0x60>;
435 };
436
437 usart0: serial@f802c000 {
438 compatible = "atmel,at91sam9260-usart";
439 reg = <0xf802c000 0x100>;
440 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
441 dmas = <&dma0
442 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
443 | AT91_XDMAC_DT_PERID(36))>,
444 <&dma0
445 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
446 | AT91_XDMAC_DT_PERID(37))>;
447 dma-names = "tx", "rx";
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
450 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
451 clock-names = "usart";
452 status = "disabled";
453 };
454
455 usart1: serial@f8030000 {
456 compatible = "atmel,at91sam9260-usart";
457 reg = <0xf8030000 0x100>;
458 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
459 dmas = <&dma0
460 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
461 | AT91_XDMAC_DT_PERID(38))>,
462 <&dma0
463 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
464 | AT91_XDMAC_DT_PERID(39))>;
465 dma-names = "tx", "rx";
466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
468 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
469 clock-names = "usart";
470 status = "disabled";
471 };
472
473 mmc1: mmc@fc000000 {
474 compatible = "atmel,hsmci";
475 reg = <0xfc000000 0x600>;
476 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
477 dmas = <&dma1
478 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
479 | AT91_XDMAC_DT_PERID(1))>;
480 dma-names = "rxtx";
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
483 status = "disabled";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
487 clock-names = "mci_clk";
488 };
489
490 uart1: serial@fc004000 {
491 compatible = "atmel,at91sam9260-usart";
492 reg = <0xfc004000 0x100>;
493 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
494 dmas = <&dma0
495 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
496 | AT91_XDMAC_DT_PERID(24))>,
497 <&dma0
498 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
499 | AT91_XDMAC_DT_PERID(25))>;
500 dma-names = "tx", "rx";
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_uart1>;
503 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
504 clock-names = "usart";
505 status = "disabled";
506 };
507
508 usart2: serial@fc008000 {
509 compatible = "atmel,at91sam9260-usart";
510 reg = <0xfc008000 0x100>;
511 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
512 dmas = <&dma1
513 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
514 | AT91_XDMAC_DT_PERID(16))>,
515 <&dma1
516 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
517 | AT91_XDMAC_DT_PERID(17))>;
518 dma-names = "tx", "rx";
519 pinctrl-names = "default";
520 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
521 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
522 clock-names = "usart";
523 status = "disabled";
524 };
525
526 usart3: serial@fc00c000 {
527 compatible = "atmel,at91sam9260-usart";
528 reg = <0xfc00c000 0x100>;
529 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
530 dmas = <&dma1
531 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
532 | AT91_XDMAC_DT_PERID(18))>,
533 <&dma1
534 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
535 | AT91_XDMAC_DT_PERID(19))>;
536 dma-names = "tx", "rx";
537 pinctrl-names = "default";
538 pinctrl-0 = <&pinctrl_usart3>;
539 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
540 clock-names = "usart";
541 status = "disabled";
542 };
543
544 usart4: serial@fc010000 {
545 compatible = "atmel,at91sam9260-usart";
546 reg = <0xfc010000 0x100>;
547 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
548 dmas = <&dma1
549 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
550 | AT91_XDMAC_DT_PERID(20))>,
551 <&dma1
552 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
553 | AT91_XDMAC_DT_PERID(21))>;
554 dma-names = "tx", "rx";
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_usart4>;
557 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
558 clock-names = "usart";
559 status = "disabled";
560 };
561
562 ssc1: ssc@fc014000 {
563 compatible = "atmel,at91sam9g45-ssc";
564 reg = <0xfc014000 0x4000>;
565 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
568 dmas = <&dma1
569 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
570 | AT91_XDMAC_DT_PERID(28))>,
571 <&dma1
572 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
573 | AT91_XDMAC_DT_PERID(29))>;
574 dma-names = "tx", "rx";
575 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
576 clock-names = "pclk";
577 status = "disabled";
578 };
579
580 spi1: spi@fc018000 {
581 #address-cells = <1>;
582 #size-cells = <0>;
583 compatible = "atmel,at91rm9200-spi";
584 reg = <0xfc018000 0x100>;
585 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
586 dmas = <&dma1
587 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
588 | AT91_XDMAC_DT_PERID(12))>,
589 <&dma1
590 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
591 | AT91_XDMAC_DT_PERID(13))>;
592 dma-names = "tx", "rx";
593 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_spi1>;
595 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
596 clock-names = "spi_clk";
597 status = "disabled";
598 };
599
600 spi2: spi@fc01c000 {
601 #address-cells = <1>;
602 #size-cells = <0>;
603 compatible = "atmel,at91rm9200-spi";
604 reg = <0xfc01c000 0x100>;
605 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
606 dmas = <&dma0
607 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
608 | AT91_XDMAC_DT_PERID(14))>,
609 <&dma0
610 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
611 | AT91_XDMAC_DT_PERID(15))>;
612 dma-names = "tx", "rx";
613 pinctrl-names = "default";
614 pinctrl-0 = <&pinctrl_spi2>;
615 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
616 clock-names = "spi_clk";
617 status = "disabled";
618 };
619
620 tcb1: timer@fc020000 {
621 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
622 #address-cells = <1>;
623 #size-cells = <0>;
624 reg = <0xfc020000 0x100>;
625 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
626 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>;
627 clock-names = "t0_clk", "slow_clk";
628 };
629
630 tcb2: timer@fc024000 {
631 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
632 #address-cells = <1>;
633 #size-cells = <0>;
634 reg = <0xfc024000 0x100>;
635 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
636 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>;
637 clock-names = "t0_clk", "slow_clk";
638 };
639
640 macb1: ethernet@fc028000 {
641 compatible = "atmel,sama5d4-gem";
642 reg = <0xfc028000 0x100>;
643 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_macb1_rmii>;
646 #address-cells = <1>;
647 #size-cells = <0>;
648 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>;
649 clock-names = "hclk", "pclk";
650 status = "disabled";
651 };
652
653 trng@fc030000 {
654 compatible = "atmel,at91sam9g45-trng";
655 reg = <0xfc030000 0x100>;
656 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
657 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
658 };
659
660 adc0: adc@fc034000 {
661 compatible = "atmel,at91sam9x5-adc";
662 reg = <0xfc034000 0x100>;
663 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
664 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>,
665 <&adc_op_clk>;
666 clock-names = "adc_clk", "adc_op_clk";
667 atmel,adc-channels-used = <0x01f>;
668 atmel,adc-startup-time = <40>;
669 atmel,adc-use-external-triggers;
670 atmel,adc-vref = <3000>;
671 atmel,adc-sample-hold-time = <11>;
672 atmel,adc-ts-pressure-threshold = <10000>;
673 status = "disabled";
674 };
675
676 aes@fc044000 {
677 compatible = "atmel,at91sam9g46-aes";
678 reg = <0xfc044000 0x100>;
679 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
680 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
681 | AT91_XDMAC_DT_PERID(41))>,
682 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
683 | AT91_XDMAC_DT_PERID(40))>;
684 dma-names = "tx", "rx";
685 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
686 clock-names = "aes_clk";
687 status = "okay";
688 };
689
690 tdes@fc04c000 {
691 compatible = "atmel,at91sam9g46-tdes";
692 reg = <0xfc04c000 0x100>;
693 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
694 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
695 | AT91_XDMAC_DT_PERID(42))>,
696 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
697 | AT91_XDMAC_DT_PERID(43))>;
698 dma-names = "tx", "rx";
699 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
700 clock-names = "tdes_clk";
701 status = "okay";
702 };
703
704 sha@fc050000 {
705 compatible = "atmel,at91sam9g46-sha";
706 reg = <0xfc050000 0x100>;
707 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
708 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
709 | AT91_XDMAC_DT_PERID(44))>;
710 dma-names = "tx";
711 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
712 clock-names = "sha_clk";
713 status = "okay";
714 };
715
716 hsmc: smc@fc05c000 {
717 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
718 reg = <0xfc05c000 0x1000>;
719 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
720 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
721 #address-cells = <1>;
722 #size-cells = <1>;
723 ranges;
724
725 pmecc: ecc-engine@ffffc070 {
726 compatible = "atmel,sama5d4-pmecc";
727 reg = <0xfc05c070 0x490>,
728 <0xfc05c500 0x100>;
729 };
730 };
731
732 reset_controller: rstc@fc068600 {
733 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
734 reg = <0xfc068600 0x10>;
735 clocks = <&clk32k>;
736 };
737
738 shutdown_controller: shdwc@fc068610 {
739 compatible = "atmel,at91sam9x5-shdwc";
740 reg = <0xfc068610 0x10>;
741 clocks = <&clk32k>;
742 };
743
744 pit: timer@fc068630 {
745 compatible = "atmel,at91sam9260-pit";
746 reg = <0xfc068630 0x10>;
747 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
748 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
749 };
750
751 watchdog: watchdog@fc068640 {
752 compatible = "atmel,sama5d4-wdt";
753 reg = <0xfc068640 0x10>;
754 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
755 clocks = <&clk32k>;
756 status = "disabled";
757 };
758
759 clk32k: sckc@fc068650 {
760 compatible = "atmel,sama5d4-sckc";
761 reg = <0xfc068650 0x4>;
762 #clock-cells = <0>;
763 clocks = <&slow_xtal>;
764 };
765
766 rtc@fc0686b0 {
767 compatible = "atmel,sama5d4-rtc";
768 reg = <0xfc0686b0 0x30>;
769 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
770 clocks = <&clk32k>;
771 };
772
773 dbgu: serial@fc069000 {
774 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
775 reg = <0xfc069000 0x200>;
776 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
777 pinctrl-names = "default";
778 pinctrl-0 = <&pinctrl_dbgu>;
779 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
780 clock-names = "usart";
781 status = "disabled";
782 };
783
784
785 pinctrl: pinctrl@fc06a000 {
786 #address-cells = <1>;
787 #size-cells = <1>;
788 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
789 ranges = <0xfc068000 0xfc068000 0x100
790 0xfc06a000 0xfc06a000 0x4000>;
791 /* WARNING: revisit as pin spec has changed */
792 atmel,mux-mask = <
793 /* A B C */
794 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
795 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
796 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
797 0xb003ff00 0x8002a800 0x00000000 /* pioD */
798 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
799 >;
800
801 pioA: gpio@fc06a000 {
802 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
803 reg = <0xfc06a000 0x100>;
804 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
805 #gpio-cells = <2>;
806 gpio-controller;
807 interrupt-controller;
808 #interrupt-cells = <2>;
809 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
810 };
811
812 pioB: gpio@fc06b000 {
813 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
814 reg = <0xfc06b000 0x100>;
815 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
816 #gpio-cells = <2>;
817 gpio-controller;
818 interrupt-controller;
819 #interrupt-cells = <2>;
820 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
821 };
822
823 pioC: gpio@fc06c000 {
824 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
825 reg = <0xfc06c000 0x100>;
826 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
827 #gpio-cells = <2>;
828 gpio-controller;
829 interrupt-controller;
830 #interrupt-cells = <2>;
831 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
832 };
833
834 pioD: gpio@fc068000 {
835 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
836 reg = <0xfc068000 0x100>;
837 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
838 #gpio-cells = <2>;
839 gpio-controller;
840 interrupt-controller;
841 #interrupt-cells = <2>;
842 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
843 };
844
845 pioE: gpio@fc06d000 {
846 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
847 reg = <0xfc06d000 0x100>;
848 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
849 #gpio-cells = <2>;
850 gpio-controller;
851 interrupt-controller;
852 #interrupt-cells = <2>;
853 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
854 };
855
856 /* pinctrl pin settings */
857 adc0 {
858 pinctrl_adc0_adtrg: adc0_adtrg {
859 atmel,pins =
860 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
861 };
862 pinctrl_adc0_ad0: adc0_ad0 {
863 atmel,pins =
864 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
865 };
866 pinctrl_adc0_ad1: adc0_ad1 {
867 atmel,pins =
868 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
869 };
870 pinctrl_adc0_ad2: adc0_ad2 {
871 atmel,pins =
872 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
873 };
874 pinctrl_adc0_ad3: adc0_ad3 {
875 atmel,pins =
876 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
877 };
878 pinctrl_adc0_ad4: adc0_ad4 {
879 atmel,pins =
880 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
881 };
882 };
883
884 dbgu {
885 pinctrl_dbgu: dbgu-0 {
886 atmel,pins =
887 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */
888 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */
889 };
890 };
891
892 ebi {
893 pinctrl_ebi_addr: ebi-addr-0 {
894 atmel,pins =
895 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
896 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
897 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
898 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
899 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
900 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
901 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
902 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
903 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
904 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
905 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
906 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
907 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
908 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
909 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
910 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
911 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
912 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
913 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
914 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
915 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
916 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
917 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
918 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
919 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
920 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
921 };
922
923 pinctrl_ebi_nand_addr: ebi-addr-1 {
924 atmel,pins =
925 <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
926 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
927 };
928
929 pinctrl_ebi_cs0: ebi-cs0-0 {
930 atmel,pins =
931 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
932 };
933
934 pinctrl_ebi_cs1: ebi-cs1-0 {
935 atmel,pins =
936 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
937 };
938
939 pinctrl_ebi_cs2: ebi-cs2-0 {
940 atmel,pins =
941 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
942 };
943
944 pinctrl_ebi_cs3: ebi-cs3-0 {
945 atmel,pins =
946 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
947 };
948
949 pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
950 atmel,pins =
951 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
952 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
953 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
954 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
955 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
956 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
957 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
958 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
959 };
960
961 pinctrl_ebi_data_8_15: ebi-data-msb-0 {
962 atmel,pins =
963 <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
964 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
965 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
966 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
967 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
968 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
969 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
970 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
971 };
972
973 pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
974 atmel,pins =
975 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
976 };
977
978 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
979 atmel,pins =
980 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
981 };
982
983 pinctrl_ebi_nwait: ebi-nwait-0 {
984 atmel,pins =
985 <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
986 };
987
988 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
989 atmel,pins =
990 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
991 };
992
993 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
994 atmel,pins =
995 <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
996 };
997 };
998
999 i2c0 {
1000 pinctrl_i2c0: i2c0-0 {
1001 atmel,pins =
1002 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1003 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1004 };
1005
1006 pinctrl_i2c0_gpio: i2c0-gpio {
1007 atmel,pins =
1008 <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
1009 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
1010 };
1011 };
1012
1013 i2c1 {
1014 pinctrl_i2c1: i2c1-0 {
1015 atmel,pins =
1016 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1017 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1018 };
1019
1020 pinctrl_i2c1_gpio: i2c1-gpio {
1021 atmel,pins =
1022 <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
1023 AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
1024 };
1025 };
1026
1027 i2c2 {
1028 pinctrl_i2c2: i2c2-0 {
1029 atmel,pins =
1030 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1031 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1032 };
1033
1034 pinctrl_i2c2_gpio: i2c2-gpio {
1035 atmel,pins =
1036 <AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
1037 AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
1038 };
1039 };
1040
1041 isi {
1042 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1043 atmel,pins =
1044 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1045 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1046 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1047 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1048 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1049 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1050 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1051 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1052 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1053 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1054 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1055 };
1056 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1057 atmel,pins =
1058 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1059 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1060 };
1061 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1062 atmel,pins =
1063 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1064 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1065 };
1066 };
1067
1068 lcd {
1069 pinctrl_lcd_base: lcd-base-0 {
1070 atmel,pins =
1071 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1072 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1073 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1074 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1075 };
1076 pinctrl_lcd_pwm: lcd-pwm-0 {
1077 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1078 };
1079 pinctrl_lcd_rgb444: lcd-rgb-0 {
1080 atmel,pins =
1081 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1082 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1083 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1084 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1085 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1086 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1087 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1088 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1089 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1090 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1091 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1092 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1093 };
1094 pinctrl_lcd_rgb565: lcd-rgb-1 {
1095 atmel,pins =
1096 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1097 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1098 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1099 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1100 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1101 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1102 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1103 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1104 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1105 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1106 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1107 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1108 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1109 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1110 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1111 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1112 };
1113 pinctrl_lcd_rgb666: lcd-rgb-2 {
1114 atmel,pins =
1115 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1116 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1117 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1118 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1119 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1120 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1121 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1122 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1123 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1124 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1125 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1126 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1127 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1128 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1129 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1130 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1131 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1132 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1133 };
1134 pinctrl_lcd_rgb777: lcd-rgb-3 {
1135 atmel,pins =
1136 /* LCDDAT0 conflicts with TMS */
1137 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1138 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1139 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1140 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1141 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1142 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1143 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1144 /* LCDDAT8 conflicts with TCK */
1145 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1146 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1147 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1148 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1149 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1150 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1151 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1152 /* LCDDAT16 conflicts with NTRST */
1153 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1154 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1155 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1156 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1157 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1158 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1159 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1160 };
1161 pinctrl_lcd_rgb888: lcd-rgb-4 {
1162 atmel,pins =
1163 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1164 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1165 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1166 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1167 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1168 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1169 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1170 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1171 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1172 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1173 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1174 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1175 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1176 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1177 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1178 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1179 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1180 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1181 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1182 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1183 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1184 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1185 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1186 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1187 };
1188 };
1189
1190 macb0 {
1191 pinctrl_macb0_rmii: macb0_rmii-0 {
1192 atmel,pins =
1193 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1194 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1195 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1196 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1197 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1198 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1199 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1200 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1201 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1202 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1203 >;
1204 };
1205 };
1206
1207 macb1 {
1208 pinctrl_macb1_rmii: macb1_rmii-0 {
1209 atmel,pins =
1210 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */
1211 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */
1212 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */
1213 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */
1214 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */
1215 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */
1216 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */
1217 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */
1218 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */
1219 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */
1220 >;
1221 };
1222 };
1223
1224 mmc0 {
1225 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1226 atmel,pins =
1227 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1228 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */
1229 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */
1230 >;
1231 };
1232 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1233 atmel,pins =
1234 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */
1235 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */
1236 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */
1237 >;
1238 };
1239 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
1240 atmel,pins =
1241 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */
1242 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */
1243 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */
1244 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */
1245 >;
1246 };
1247 };
1248
1249 mmc1 {
1250 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1251 atmel,pins =
1252 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1253 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1254 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1255 >;
1256 };
1257 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1258 atmel,pins =
1259 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1260 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1261 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1262 >;
1263 };
1264 };
1265
1266 nand0 {
1267 pinctrl_nand: nand-0 {
1268 atmel,pins =
1269 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1270 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1271
1272 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1273 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1274
1275 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1276 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1277 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1278 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1279 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1280 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1281 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1282 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1283 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1284 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1285 };
1286 };
1287
1288 spi0 {
1289 pinctrl_spi0: spi0-0 {
1290 atmel,pins =
1291 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1292 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1293 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1294 >;
1295 };
1296 };
1297
1298 ssc0 {
1299 pinctrl_ssc0_tx: ssc0_tx {
1300 atmel,pins =
1301 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1302 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1303 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1304 };
1305
1306 pinctrl_ssc0_rx: ssc0_rx {
1307 atmel,pins =
1308 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1309 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1310 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1311 };
1312 };
1313
1314 ssc1 {
1315 pinctrl_ssc1_tx: ssc1_tx {
1316 atmel,pins =
1317 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1318 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1319 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1320 };
1321
1322 pinctrl_ssc1_rx: ssc1_rx {
1323 atmel,pins =
1324 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1325 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1326 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1327 };
1328 };
1329
1330 spi1 {
1331 pinctrl_spi1: spi1-0 {
1332 atmel,pins =
1333 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
1334 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
1335 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
1336 >;
1337 };
1338 };
1339
1340 spi2 {
1341 pinctrl_spi2: spi2-0 {
1342 atmel,pins =
1343 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
1344 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
1345 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
1346 >;
1347 };
1348 };
1349
1350 uart0 {
1351 pinctrl_uart0: uart0-0 {
1352 atmel,pins =
1353 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1354 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1355 >;
1356 };
1357 };
1358
1359 uart1 {
1360 pinctrl_uart1: uart1-0 {
1361 atmel,pins =
1362 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */
1363 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */
1364 >;
1365 };
1366 };
1367
1368 usart0 {
1369 pinctrl_usart0: usart0-0 {
1370 atmel,pins =
1371 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1372 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1373 >;
1374 };
1375 pinctrl_usart0_rts: usart0_rts-0 {
1376 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1377 };
1378 pinctrl_usart0_cts: usart0_cts-0 {
1379 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1380 };
1381 };
1382
1383 usart1 {
1384 pinctrl_usart1: usart1-0 {
1385 atmel,pins =
1386 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1387 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1388 >;
1389 };
1390 pinctrl_usart1_rts: usart1_rts-0 {
1391 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1392 };
1393 pinctrl_usart1_cts: usart1_cts-0 {
1394 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1395 };
1396 };
1397
1398 usart2 {
1399 pinctrl_usart2: usart2-0 {
1400 atmel,pins =
1401 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1402 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */
1403 >;
1404 };
1405 pinctrl_usart2_rts: usart2_rts-0 {
1406 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1407 };
1408 pinctrl_usart2_cts: usart2_cts-0 {
1409 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1410 };
1411 };
1412
1413 usart3 {
1414 pinctrl_usart3: usart3-0 {
1415 atmel,pins =
1416 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1417 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1418 >;
1419 };
1420 };
1421
1422 usart4 {
1423 pinctrl_usart4: usart4-0 {
1424 atmel,pins =
1425 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1426 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1427 >;
1428 };
1429 pinctrl_usart4_rts: usart4_rts-0 {
1430 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1431 };
1432 pinctrl_usart4_cts: usart4_cts-0 {
1433 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1434 };
1435 };
1436 };
1437
1438 aic: interrupt-controller@fc06e000 {
1439 #interrupt-cells = <3>;
1440 compatible = "atmel,sama5d4-aic";
1441 interrupt-controller;
1442 reg = <0xfc06e000 0x200>;
1443 atmel,external-irqs = <56>;
1444 };
1445 };
1446 };
1447};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
4 *
5 * Copyright (C) 2014 Atmel,
6 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
7 */
8
9#include <dt-bindings/clock/at91.h>
10#include <dt-bindings/dma/at91.h>
11#include <dt-bindings/pinctrl/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Atmel SAMA5D4 family SoC";
19 compatible = "atmel,sama5d4";
20 interrupt-parent = <&aic>;
21
22 aliases {
23 serial0 = &usart3;
24 serial1 = &usart4;
25 serial2 = &usart2;
26 serial3 = &usart0;
27 serial4 = &usart1;
28 serial5 = &uart0;
29 serial6 = &uart1;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 pwm0 = &pwm0;
36 ssc0 = &ssc0;
37 ssc1 = &ssc1;
38 tcb0 = &tcb0;
39 tcb1 = &tcb1;
40 i2c0 = &i2c0;
41 i2c1 = &i2c1;
42 i2c2 = &i2c2;
43 };
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a5";
51 reg = <0>;
52 next-level-cache = <&L2>;
53 };
54 };
55
56 memory {
57 device_type = "memory";
58 reg = <0x20000000 0x20000000>;
59 };
60
61 clocks {
62 slow_xtal: slow_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
67
68 main_xtal: main_xtal {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
73
74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <1000000>;
78 };
79 };
80
81 ns_sram: sram@210000 {
82 compatible = "mmio-sram";
83 reg = <0x00210000 0x10000>;
84 };
85
86 ahb {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91
92 nfc_sram: sram@100000 {
93 compatible = "mmio-sram";
94 no-memory-wc;
95 reg = <0x100000 0x2400>;
96 };
97
98 usb0: gadget@400000 {
99 compatible = "atmel,sama5d3-udc";
100 reg = <0x00400000 0x100000
101 0xfc02c000 0x4000>;
102 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
103 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
104 clock-names = "pclk", "hclk";
105 status = "disabled";
106 };
107
108 usb1: ohci@500000 {
109 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
110 reg = <0x00500000 0x100000>;
111 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
112 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>;
113 clock-names = "ohci_clk", "hclk", "uhpck";
114 status = "disabled";
115 };
116
117 usb2: ehci@600000 {
118 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
119 reg = <0x00600000 0x100000>;
120 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
121 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
122 clock-names = "usb_clk", "ehci_clk";
123 status = "disabled";
124 };
125
126 L2: cache-controller@a00000 {
127 compatible = "arm,pl310-cache";
128 reg = <0x00a00000 0x1000>;
129 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
130 cache-unified;
131 cache-level = <2>;
132 };
133
134 ebi: ebi@10000000 {
135 compatible = "atmel,sama5d3-ebi";
136 #address-cells = <2>;
137 #size-cells = <1>;
138 atmel,smc = <&hsmc>;
139 reg = <0x10000000 0x10000000
140 0x60000000 0x28000000>;
141 ranges = <0x0 0x0 0x10000000 0x10000000
142 0x1 0x0 0x60000000 0x10000000
143 0x2 0x0 0x70000000 0x10000000
144 0x3 0x0 0x80000000 0x8000000>;
145 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
146 status = "disabled";
147
148 nand_controller: nand-controller {
149 compatible = "atmel,sama5d3-nand-controller";
150 atmel,nfc-sram = <&nfc_sram>;
151 atmel,nfc-io = <&nfc_io>;
152 ecc-engine = <&pmecc>;
153 #address-cells = <2>;
154 #size-cells = <1>;
155 ranges;
156 status = "disabled";
157 };
158 };
159
160 nfc_io: nfc-io@90000000 {
161 compatible = "atmel,sama5d3-nfc-io", "syscon";
162 reg = <0x90000000 0x8000000>;
163 };
164
165 apb {
166 compatible = "simple-bus";
167 #address-cells = <1>;
168 #size-cells = <1>;
169 ranges;
170
171 hlcdc: hlcdc@f0000000 {
172 compatible = "atmel,sama5d4-hlcdc";
173 reg = <0xf0000000 0x4000>;
174 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
175 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
176 clock-names = "periph_clk","sys_clk", "slow_clk";
177 status = "disabled";
178
179 hlcdc-display-controller {
180 compatible = "atmel,hlcdc-display-controller";
181 #address-cells = <1>;
182 #size-cells = <0>;
183
184 port@0 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 reg = <0>;
188 };
189 };
190
191 hlcdc_pwm: hlcdc-pwm {
192 compatible = "atmel,hlcdc-pwm";
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_lcd_pwm>;
195 #pwm-cells = <3>;
196 };
197 };
198
199 dma1: dma-controller@f0004000 {
200 compatible = "atmel,sama5d4-dma";
201 reg = <0xf0004000 0x200>;
202 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
203 #dma-cells = <1>;
204 clocks = <&pmc PMC_TYPE_PERIPHERAL 50>;
205 clock-names = "dma_clk";
206 };
207
208 isi: isi@f0008000 {
209 compatible = "atmel,at91sam9g45-isi";
210 reg = <0xf0008000 0x4000>;
211 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_isi_data_0_7>;
214 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
215 clock-names = "isi_clk";
216 status = "disabled";
217 port {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 };
221 };
222
223 ramc0: ramc@f0010000 {
224 compatible = "atmel,sama5d3-ddramc";
225 reg = <0xf0010000 0x200>;
226 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>;
227 clock-names = "ddrck", "mpddr";
228 };
229
230 dma0: dma-controller@f0014000 {
231 compatible = "atmel,sama5d4-dma";
232 reg = <0xf0014000 0x200>;
233 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
234 #dma-cells = <1>;
235 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
236 clock-names = "dma_clk";
237 };
238
239 pmc: pmc@f0018000 {
240 compatible = "atmel,sama5d4-pmc", "syscon";
241 reg = <0xf0018000 0x120>;
242 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
243 #clock-cells = <2>;
244 clocks = <&clk32k>, <&main_xtal>;
245 clock-names = "slow_clk", "main_xtal";
246 };
247
248 mmc0: mmc@f8000000 {
249 compatible = "atmel,hsmci";
250 reg = <0xf8000000 0x600>;
251 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
252 dmas = <&dma1
253 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
254 | AT91_XDMAC_DT_PERID(0))>;
255 dma-names = "rxtx";
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
258 status = "disabled";
259 #address-cells = <1>;
260 #size-cells = <0>;
261 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
262 clock-names = "mci_clk";
263 };
264
265 uart0: serial@f8004000 {
266 compatible = "atmel,at91sam9260-usart";
267 reg = <0xf8004000 0x100>;
268 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
269 dmas = <&dma0
270 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
271 | AT91_XDMAC_DT_PERID(22))>,
272 <&dma0
273 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
274 | AT91_XDMAC_DT_PERID(23))>;
275 dma-names = "tx", "rx";
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart0>;
278 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
279 clock-names = "usart";
280 status = "disabled";
281 };
282
283 ssc0: ssc@f8008000 {
284 compatible = "atmel,at91sam9g45-ssc";
285 reg = <0xf8008000 0x4000>;
286 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
289 dmas = <&dma1
290 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
291 | AT91_XDMAC_DT_PERID(26))>,
292 <&dma1
293 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
294 | AT91_XDMAC_DT_PERID(27))>;
295 dma-names = "tx", "rx";
296 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
297 clock-names = "pclk";
298 status = "disabled";
299 };
300
301 pwm0: pwm@f800c000 {
302 compatible = "atmel,sama5d3-pwm";
303 reg = <0xf800c000 0x300>;
304 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
305 #pwm-cells = <3>;
306 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
307 status = "disabled";
308 };
309
310 spi0: spi@f8010000 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 compatible = "atmel,at91rm9200-spi";
314 reg = <0xf8010000 0x100>;
315 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
316 dmas = <&dma1
317 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
318 | AT91_XDMAC_DT_PERID(10))>,
319 <&dma1
320 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
321 | AT91_XDMAC_DT_PERID(11))>;
322 dma-names = "tx", "rx";
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_spi0>;
325 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
326 clock-names = "spi_clk";
327 status = "disabled";
328 };
329
330 i2c0: i2c@f8014000 {
331 compatible = "atmel,sama5d4-i2c";
332 reg = <0xf8014000 0x4000>;
333 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
334 dmas = <&dma1
335 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
336 | AT91_XDMAC_DT_PERID(2))>,
337 <&dma1
338 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
339 | AT91_XDMAC_DT_PERID(3))>;
340 dma-names = "tx", "rx";
341 pinctrl-names = "default", "gpio";
342 pinctrl-0 = <&pinctrl_i2c0>;
343 pinctrl-1 = <&pinctrl_i2c0_gpio>;
344 sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
345 scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
349 status = "disabled";
350 };
351
352 i2c1: i2c@f8018000 {
353 compatible = "atmel,sama5d4-i2c";
354 reg = <0xf8018000 0x4000>;
355 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
356 dmas = <&dma0
357 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
358 | AT91_XDMAC_DT_PERID(4))>,
359 <&dma0
360 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
361 | AT91_XDMAC_DT_PERID(5))>;
362 dma-names = "tx", "rx";
363 pinctrl-names = "default", "gpio";
364 pinctrl-0 = <&pinctrl_i2c1>;
365 pinctrl-1 = <&pinctrl_i2c1_gpio>;
366 sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
367 scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
371 status = "disabled";
372 };
373
374 tcb0: timer@f801c000 {
375 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
376 #address-cells = <1>;
377 #size-cells = <0>;
378 reg = <0xf801c000 0x100>;
379 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
380 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>;
381 clock-names = "t0_clk", "slow_clk";
382 };
383
384 macb0: ethernet@f8020000 {
385 compatible = "atmel,sama5d4-gem";
386 reg = <0xf8020000 0x100>;
387 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_macb0_rmii>;
390 #address-cells = <1>;
391 #size-cells = <0>;
392 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>;
393 clock-names = "hclk", "pclk";
394 status = "disabled";
395 };
396
397 i2c2: i2c@f8024000 {
398 compatible = "atmel,sama5d4-i2c";
399 reg = <0xf8024000 0x4000>;
400 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
401 dmas = <&dma1
402 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
403 | AT91_XDMAC_DT_PERID(6))>,
404 <&dma1
405 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
406 | AT91_XDMAC_DT_PERID(7))>;
407 dma-names = "tx", "rx";
408 pinctrl-names = "default", "gpio";
409 pinctrl-0 = <&pinctrl_i2c2>;
410 pinctrl-1 = <&pinctrl_i2c2_gpio>;
411 sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>;
412 scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
416 status = "disabled";
417 };
418
419 sfr: sfr@f8028000 {
420 compatible = "atmel,sama5d4-sfr", "syscon";
421 reg = <0xf8028000 0x60>;
422 };
423
424 usart0: serial@f802c000 {
425 compatible = "atmel,at91sam9260-usart";
426 reg = <0xf802c000 0x100>;
427 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
428 dmas = <&dma0
429 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
430 | AT91_XDMAC_DT_PERID(36))>,
431 <&dma0
432 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
433 | AT91_XDMAC_DT_PERID(37))>;
434 dma-names = "tx", "rx";
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
437 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
438 clock-names = "usart";
439 status = "disabled";
440 };
441
442 usart1: serial@f8030000 {
443 compatible = "atmel,at91sam9260-usart";
444 reg = <0xf8030000 0x100>;
445 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
446 dmas = <&dma0
447 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
448 | AT91_XDMAC_DT_PERID(38))>,
449 <&dma0
450 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
451 | AT91_XDMAC_DT_PERID(39))>;
452 dma-names = "tx", "rx";
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
455 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
456 clock-names = "usart";
457 status = "disabled";
458 };
459
460 mmc1: mmc@fc000000 {
461 compatible = "atmel,hsmci";
462 reg = <0xfc000000 0x600>;
463 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
464 dmas = <&dma1
465 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
466 | AT91_XDMAC_DT_PERID(1))>;
467 dma-names = "rxtx";
468 pinctrl-names = "default";
469 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
470 status = "disabled";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
474 clock-names = "mci_clk";
475 };
476
477 uart1: serial@fc004000 {
478 compatible = "atmel,at91sam9260-usart";
479 reg = <0xfc004000 0x100>;
480 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
481 dmas = <&dma0
482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
483 | AT91_XDMAC_DT_PERID(24))>,
484 <&dma0
485 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
486 | AT91_XDMAC_DT_PERID(25))>;
487 dma-names = "tx", "rx";
488 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_uart1>;
490 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
491 clock-names = "usart";
492 status = "disabled";
493 };
494
495 usart2: serial@fc008000 {
496 compatible = "atmel,at91sam9260-usart";
497 reg = <0xfc008000 0x100>;
498 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
499 dmas = <&dma1
500 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
501 | AT91_XDMAC_DT_PERID(16))>,
502 <&dma1
503 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
504 | AT91_XDMAC_DT_PERID(17))>;
505 dma-names = "tx", "rx";
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
508 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
509 clock-names = "usart";
510 status = "disabled";
511 };
512
513 usart3: serial@fc00c000 {
514 compatible = "atmel,at91sam9260-usart";
515 reg = <0xfc00c000 0x100>;
516 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
517 dmas = <&dma1
518 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
519 | AT91_XDMAC_DT_PERID(18))>,
520 <&dma1
521 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
522 | AT91_XDMAC_DT_PERID(19))>;
523 dma-names = "tx", "rx";
524 pinctrl-names = "default";
525 pinctrl-0 = <&pinctrl_usart3>;
526 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
527 clock-names = "usart";
528 status = "disabled";
529 };
530
531 usart4: serial@fc010000 {
532 compatible = "atmel,at91sam9260-usart";
533 reg = <0xfc010000 0x100>;
534 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
535 dmas = <&dma1
536 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
537 | AT91_XDMAC_DT_PERID(20))>,
538 <&dma1
539 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
540 | AT91_XDMAC_DT_PERID(21))>;
541 dma-names = "tx", "rx";
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_usart4>;
544 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
545 clock-names = "usart";
546 status = "disabled";
547 };
548
549 ssc1: ssc@fc014000 {
550 compatible = "atmel,at91sam9g45-ssc";
551 reg = <0xfc014000 0x4000>;
552 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
555 dmas = <&dma1
556 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
557 | AT91_XDMAC_DT_PERID(28))>,
558 <&dma1
559 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
560 | AT91_XDMAC_DT_PERID(29))>;
561 dma-names = "tx", "rx";
562 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
563 clock-names = "pclk";
564 status = "disabled";
565 };
566
567 spi1: spi@fc018000 {
568 #address-cells = <1>;
569 #size-cells = <0>;
570 compatible = "atmel,at91rm9200-spi";
571 reg = <0xfc018000 0x100>;
572 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
573 dmas = <&dma1
574 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
575 | AT91_XDMAC_DT_PERID(12))>,
576 <&dma1
577 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
578 | AT91_XDMAC_DT_PERID(13))>;
579 dma-names = "tx", "rx";
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_spi1>;
582 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
583 clock-names = "spi_clk";
584 status = "disabled";
585 };
586
587 spi2: spi@fc01c000 {
588 #address-cells = <1>;
589 #size-cells = <0>;
590 compatible = "atmel,at91rm9200-spi";
591 reg = <0xfc01c000 0x100>;
592 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
593 dmas = <&dma0
594 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
595 | AT91_XDMAC_DT_PERID(14))>,
596 <&dma0
597 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
598 | AT91_XDMAC_DT_PERID(15))>;
599 dma-names = "tx", "rx";
600 pinctrl-names = "default";
601 pinctrl-0 = <&pinctrl_spi2>;
602 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
603 clock-names = "spi_clk";
604 status = "disabled";
605 };
606
607 tcb1: timer@fc020000 {
608 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
609 #address-cells = <1>;
610 #size-cells = <0>;
611 reg = <0xfc020000 0x100>;
612 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
613 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>;
614 clock-names = "t0_clk", "slow_clk";
615 };
616
617 tcb2: timer@fc024000 {
618 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 reg = <0xfc024000 0x100>;
622 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
623 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>;
624 clock-names = "t0_clk", "slow_clk";
625 };
626
627 macb1: ethernet@fc028000 {
628 compatible = "atmel,sama5d4-gem";
629 reg = <0xfc028000 0x100>;
630 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&pinctrl_macb1_rmii>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>;
636 clock-names = "hclk", "pclk";
637 status = "disabled";
638 };
639
640 trng@fc030000 {
641 compatible = "atmel,at91sam9g45-trng";
642 reg = <0xfc030000 0x100>;
643 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
644 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
645 };
646
647 adc0: adc@fc034000 {
648 compatible = "atmel,at91sam9x5-adc";
649 reg = <0xfc034000 0x100>;
650 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
651 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>,
652 <&adc_op_clk>;
653 clock-names = "adc_clk", "adc_op_clk";
654 atmel,adc-channels-used = <0x01f>;
655 atmel,adc-startup-time = <40>;
656 atmel,adc-use-external-triggers;
657 atmel,adc-vref = <3000>;
658 atmel,adc-res = <8 10>;
659 atmel,adc-sample-hold-time = <11>;
660 atmel,adc-res-names = "lowres", "highres";
661 atmel,adc-ts-pressure-threshold = <10000>;
662 status = "disabled";
663
664 trigger0 {
665 trigger-name = "external-rising";
666 trigger-value = <0x1>;
667 trigger-external;
668 };
669 trigger1 {
670 trigger-name = "external-falling";
671 trigger-value = <0x2>;
672 trigger-external;
673 };
674 trigger2 {
675 trigger-name = "external-any";
676 trigger-value = <0x3>;
677 trigger-external;
678 };
679 trigger3 {
680 trigger-name = "continuous";
681 trigger-value = <0x6>;
682 };
683 };
684
685 aes@fc044000 {
686 compatible = "atmel,at91sam9g46-aes";
687 reg = <0xfc044000 0x100>;
688 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
689 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
690 | AT91_XDMAC_DT_PERID(41))>,
691 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
692 | AT91_XDMAC_DT_PERID(40))>;
693 dma-names = "tx", "rx";
694 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
695 clock-names = "aes_clk";
696 status = "okay";
697 };
698
699 tdes@fc04c000 {
700 compatible = "atmel,at91sam9g46-tdes";
701 reg = <0xfc04c000 0x100>;
702 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
703 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
704 | AT91_XDMAC_DT_PERID(42))>,
705 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
706 | AT91_XDMAC_DT_PERID(43))>;
707 dma-names = "tx", "rx";
708 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
709 clock-names = "tdes_clk";
710 status = "okay";
711 };
712
713 sha@fc050000 {
714 compatible = "atmel,at91sam9g46-sha";
715 reg = <0xfc050000 0x100>;
716 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
717 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
718 | AT91_XDMAC_DT_PERID(44))>;
719 dma-names = "tx";
720 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
721 clock-names = "sha_clk";
722 status = "okay";
723 };
724
725 hsmc: smc@fc05c000 {
726 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
727 reg = <0xfc05c000 0x1000>;
728 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
729 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
730 #address-cells = <1>;
731 #size-cells = <1>;
732 ranges;
733
734 pmecc: ecc-engine@ffffc070 {
735 compatible = "atmel,sama5d4-pmecc";
736 reg = <0xfc05c070 0x490>,
737 <0xfc05c500 0x100>;
738 };
739 };
740
741 reset_controller: rstc@fc068600 {
742 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
743 reg = <0xfc068600 0x10>;
744 clocks = <&clk32k>;
745 };
746
747 shutdown_controller: shdwc@fc068610 {
748 compatible = "atmel,at91sam9x5-shdwc";
749 reg = <0xfc068610 0x10>;
750 clocks = <&clk32k>;
751 };
752
753 pit: timer@fc068630 {
754 compatible = "atmel,at91sam9260-pit";
755 reg = <0xfc068630 0x10>;
756 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
757 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
758 };
759
760 watchdog: watchdog@fc068640 {
761 compatible = "atmel,sama5d4-wdt";
762 reg = <0xfc068640 0x10>;
763 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
764 clocks = <&clk32k>;
765 status = "disabled";
766 };
767
768 clk32k: sckc@fc068650 {
769 compatible = "atmel,sama5d4-sckc";
770 reg = <0xfc068650 0x4>;
771 #clock-cells = <0>;
772 clocks = <&slow_xtal>;
773 };
774
775 rtc@fc0686b0 {
776 compatible = "atmel,sama5d4-rtc";
777 reg = <0xfc0686b0 0x30>;
778 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
779 clocks = <&clk32k>;
780 };
781
782 dbgu: serial@fc069000 {
783 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
784 reg = <0xfc069000 0x200>;
785 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
786 pinctrl-names = "default";
787 pinctrl-0 = <&pinctrl_dbgu>;
788 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
789 clock-names = "usart";
790 status = "disabled";
791 };
792
793
794 pinctrl: pinctrl@fc06a000 {
795 #address-cells = <1>;
796 #size-cells = <1>;
797 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
798 ranges = <0xfc068000 0xfc068000 0x100
799 0xfc06a000 0xfc06a000 0x4000>;
800 /* WARNING: revisit as pin spec has changed */
801 atmel,mux-mask = <
802 /* A B C */
803 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
804 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
805 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
806 0x0003ff00 0x8002a800 0x00000000 /* pioD */
807 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
808 >;
809
810 pioA: gpio@fc06a000 {
811 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
812 reg = <0xfc06a000 0x100>;
813 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
814 #gpio-cells = <2>;
815 gpio-controller;
816 interrupt-controller;
817 #interrupt-cells = <2>;
818 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
819 };
820
821 pioB: gpio@fc06b000 {
822 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
823 reg = <0xfc06b000 0x100>;
824 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
825 #gpio-cells = <2>;
826 gpio-controller;
827 interrupt-controller;
828 #interrupt-cells = <2>;
829 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
830 };
831
832 pioC: gpio@fc06c000 {
833 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
834 reg = <0xfc06c000 0x100>;
835 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
836 #gpio-cells = <2>;
837 gpio-controller;
838 interrupt-controller;
839 #interrupt-cells = <2>;
840 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
841 };
842
843 pioD: gpio@fc068000 {
844 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
845 reg = <0xfc068000 0x100>;
846 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
847 #gpio-cells = <2>;
848 gpio-controller;
849 interrupt-controller;
850 #interrupt-cells = <2>;
851 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
852 };
853
854 pioE: gpio@fc06d000 {
855 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
856 reg = <0xfc06d000 0x100>;
857 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
858 #gpio-cells = <2>;
859 gpio-controller;
860 interrupt-controller;
861 #interrupt-cells = <2>;
862 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
863 };
864
865 /* pinctrl pin settings */
866 adc0 {
867 pinctrl_adc0_adtrg: adc0_adtrg {
868 atmel,pins =
869 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
870 };
871 pinctrl_adc0_ad0: adc0_ad0 {
872 atmel,pins =
873 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
874 };
875 pinctrl_adc0_ad1: adc0_ad1 {
876 atmel,pins =
877 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
878 };
879 pinctrl_adc0_ad2: adc0_ad2 {
880 atmel,pins =
881 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
882 };
883 pinctrl_adc0_ad3: adc0_ad3 {
884 atmel,pins =
885 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
886 };
887 pinctrl_adc0_ad4: adc0_ad4 {
888 atmel,pins =
889 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
890 };
891 };
892
893 dbgu {
894 pinctrl_dbgu: dbgu-0 {
895 atmel,pins =
896 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */
897 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */
898 };
899 };
900
901 ebi {
902 pinctrl_ebi_addr: ebi-addr-0 {
903 atmel,pins =
904 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
905 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
906 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
907 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
908 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
909 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
910 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
911 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
912 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
913 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
914 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
915 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
916 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
917 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
918 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
919 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
920 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
921 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
922 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
923 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
924 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
925 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
926 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
927 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
928 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
929 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
930 };
931
932 pinctrl_ebi_nand_addr: ebi-addr-1 {
933 atmel,pins =
934 <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
935 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
936 };
937
938 pinctrl_ebi_cs0: ebi-cs0-0 {
939 atmel,pins =
940 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
941 };
942
943 pinctrl_ebi_cs1: ebi-cs1-0 {
944 atmel,pins =
945 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
946 };
947
948 pinctrl_ebi_cs2: ebi-cs2-0 {
949 atmel,pins =
950 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
951 };
952
953 pinctrl_ebi_cs3: ebi-cs3-0 {
954 atmel,pins =
955 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
956 };
957
958 pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
959 atmel,pins =
960 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
961 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
962 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
963 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
964 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
965 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
966 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
967 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
968 };
969
970 pinctrl_ebi_data_8_15: ebi-data-msb-0 {
971 atmel,pins =
972 <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
973 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
974 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
975 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
976 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
977 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
978 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
979 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
980 };
981
982 pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
983 atmel,pins =
984 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
985 };
986
987 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
988 atmel,pins =
989 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
990 };
991
992 pinctrl_ebi_nwait: ebi-nwait-0 {
993 atmel,pins =
994 <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
995 };
996
997 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
998 atmel,pins =
999 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1000 };
1001
1002 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
1003 atmel,pins =
1004 <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1005 };
1006 };
1007
1008 i2c0 {
1009 pinctrl_i2c0: i2c0-0 {
1010 atmel,pins =
1011 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1012 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1013 };
1014
1015 pinctrl_i2c0_gpio: i2c0-gpio {
1016 atmel,pins =
1017 <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
1018 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
1019 };
1020 };
1021
1022 i2c1 {
1023 pinctrl_i2c1: i2c1-0 {
1024 atmel,pins =
1025 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1026 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1027 };
1028
1029 pinctrl_i2c1_gpio: i2c1-gpio {
1030 atmel,pins =
1031 <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
1032 AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
1033 };
1034 };
1035
1036 i2c2 {
1037 pinctrl_i2c2: i2c2-0 {
1038 atmel,pins =
1039 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1040 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1041 };
1042
1043 pinctrl_i2c2_gpio: i2c2-gpio {
1044 atmel,pins =
1045 <AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
1046 AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
1047 };
1048 };
1049
1050 isi {
1051 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1052 atmel,pins =
1053 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1054 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1055 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1056 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1057 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1058 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1059 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1060 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1061 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1062 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1063 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1064 };
1065 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1066 atmel,pins =
1067 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1068 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1069 };
1070 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1071 atmel,pins =
1072 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1073 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1074 };
1075 };
1076
1077 lcd {
1078 pinctrl_lcd_base: lcd-base-0 {
1079 atmel,pins =
1080 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1081 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1082 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1083 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1084 };
1085 pinctrl_lcd_pwm: lcd-pwm-0 {
1086 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1087 };
1088 pinctrl_lcd_rgb444: lcd-rgb-0 {
1089 atmel,pins =
1090 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1091 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1092 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1093 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1094 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1095 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1096 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1097 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1098 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1099 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1100 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1101 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1102 };
1103 pinctrl_lcd_rgb565: lcd-rgb-1 {
1104 atmel,pins =
1105 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1106 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1107 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1108 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1109 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1110 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1111 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1112 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1113 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1114 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1115 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1116 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1117 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1118 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1119 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1120 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1121 };
1122 pinctrl_lcd_rgb666: lcd-rgb-2 {
1123 atmel,pins =
1124 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1125 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1126 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1127 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1128 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1129 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1130 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1131 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1132 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1133 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1134 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1135 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1136 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1137 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1138 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1139 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1140 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1141 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1142 };
1143 pinctrl_lcd_rgb777: lcd-rgb-3 {
1144 atmel,pins =
1145 /* LCDDAT0 conflicts with TMS */
1146 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1147 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1148 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1149 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1150 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1151 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1152 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1153 /* LCDDAT8 conflicts with TCK */
1154 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1155 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1156 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1157 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1158 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1159 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1160 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1161 /* LCDDAT16 conflicts with NTRST */
1162 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1163 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1164 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1165 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1166 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1167 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1168 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1169 };
1170 pinctrl_lcd_rgb888: lcd-rgb-4 {
1171 atmel,pins =
1172 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1173 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1174 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1175 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1176 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1177 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1178 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1179 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1180 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1181 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1182 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1183 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1184 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1185 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1186 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1187 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1188 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1189 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1190 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1191 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1192 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1193 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1194 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1195 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1196 };
1197 };
1198
1199 macb0 {
1200 pinctrl_macb0_rmii: macb0_rmii-0 {
1201 atmel,pins =
1202 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1203 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1204 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1205 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1206 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1207 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1208 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1209 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1210 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1211 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1212 >;
1213 };
1214 };
1215
1216 macb1 {
1217 pinctrl_macb1_rmii: macb1_rmii-0 {
1218 atmel,pins =
1219 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */
1220 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */
1221 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */
1222 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */
1223 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */
1224 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */
1225 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */
1226 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */
1227 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */
1228 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */
1229 >;
1230 };
1231 };
1232
1233 mmc0 {
1234 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1235 atmel,pins =
1236 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1237 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */
1238 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */
1239 >;
1240 };
1241 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1242 atmel,pins =
1243 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */
1244 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */
1245 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */
1246 >;
1247 };
1248 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
1249 atmel,pins =
1250 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */
1251 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */
1252 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */
1253 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */
1254 >;
1255 };
1256 };
1257
1258 mmc1 {
1259 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1260 atmel,pins =
1261 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1262 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1263 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1264 >;
1265 };
1266 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1267 atmel,pins =
1268 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1269 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1270 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1271 >;
1272 };
1273 };
1274
1275 nand0 {
1276 pinctrl_nand: nand-0 {
1277 atmel,pins =
1278 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1279 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1280
1281 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1282 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1283
1284 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1285 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1286 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1287 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1288 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1289 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1290 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1291 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1292 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1293 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1294 };
1295 };
1296
1297 spi0 {
1298 pinctrl_spi0: spi0-0 {
1299 atmel,pins =
1300 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1301 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1302 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1303 >;
1304 };
1305 };
1306
1307 ssc0 {
1308 pinctrl_ssc0_tx: ssc0_tx {
1309 atmel,pins =
1310 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1311 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1312 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1313 };
1314
1315 pinctrl_ssc0_rx: ssc0_rx {
1316 atmel,pins =
1317 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1318 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1319 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1320 };
1321 };
1322
1323 ssc1 {
1324 pinctrl_ssc1_tx: ssc1_tx {
1325 atmel,pins =
1326 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1327 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1328 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1329 };
1330
1331 pinctrl_ssc1_rx: ssc1_rx {
1332 atmel,pins =
1333 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1334 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1335 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1336 };
1337 };
1338
1339 spi1 {
1340 pinctrl_spi1: spi1-0 {
1341 atmel,pins =
1342 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
1343 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
1344 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
1345 >;
1346 };
1347 };
1348
1349 spi2 {
1350 pinctrl_spi2: spi2-0 {
1351 atmel,pins =
1352 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
1353 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
1354 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
1355 >;
1356 };
1357 };
1358
1359 uart0 {
1360 pinctrl_uart0: uart0-0 {
1361 atmel,pins =
1362 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1363 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1364 >;
1365 };
1366 };
1367
1368 uart1 {
1369 pinctrl_uart1: uart1-0 {
1370 atmel,pins =
1371 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */
1372 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */
1373 >;
1374 };
1375 };
1376
1377 usart0 {
1378 pinctrl_usart0: usart0-0 {
1379 atmel,pins =
1380 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1381 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1382 >;
1383 };
1384 pinctrl_usart0_rts: usart0_rts-0 {
1385 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1386 };
1387 pinctrl_usart0_cts: usart0_cts-0 {
1388 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1389 };
1390 };
1391
1392 usart1 {
1393 pinctrl_usart1: usart1-0 {
1394 atmel,pins =
1395 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1396 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1397 >;
1398 };
1399 pinctrl_usart1_rts: usart1_rts-0 {
1400 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1401 };
1402 pinctrl_usart1_cts: usart1_cts-0 {
1403 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1404 };
1405 };
1406
1407 usart2 {
1408 pinctrl_usart2: usart2-0 {
1409 atmel,pins =
1410 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1411 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */
1412 >;
1413 };
1414 pinctrl_usart2_rts: usart2_rts-0 {
1415 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1416 };
1417 pinctrl_usart2_cts: usart2_cts-0 {
1418 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1419 };
1420 };
1421
1422 usart3 {
1423 pinctrl_usart3: usart3-0 {
1424 atmel,pins =
1425 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1426 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1427 >;
1428 };
1429 };
1430
1431 usart4 {
1432 pinctrl_usart4: usart4-0 {
1433 atmel,pins =
1434 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1435 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1436 >;
1437 };
1438 pinctrl_usart4_rts: usart4_rts-0 {
1439 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1440 };
1441 pinctrl_usart4_cts: usart4_cts-0 {
1442 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1443 };
1444 };
1445 };
1446
1447 aic: interrupt-controller@fc06e000 {
1448 #interrupt-cells = <3>;
1449 compatible = "atmel,sama5d4-aic";
1450 interrupt-controller;
1451 reg = <0xfc06e000 0x200>;
1452 atmel,external-irqs = <56>;
1453 };
1454 };
1455 };
1456};