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1/*
2 * Device Tree Source for OMAP34xx/OMAP35xx SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/bus/ti-sysc.h>
12#include <dt-bindings/media/omap3-isp.h>
13
14#include "omap3.dtsi"
15
16/ {
17 cpus {
18 cpu: cpu@0 {
19 /* OMAP343x/OMAP35xx variants OPP1-6 */
20 operating-points-v2 = <&cpu0_opp_table>;
21
22 clock-latency = <300000>; /* From legacy driver */
23 #cooling-cells = <2>;
24 };
25 };
26
27 /* see Documentation/devicetree/bindings/opp/opp.txt */
28 cpu0_opp_table: opp-table {
29 compatible = "operating-points-v2-ti-cpu";
30 syscon = <&scm_conf>;
31
32 opp1-125000000 {
33 opp-hz = /bits/ 64 <125000000>;
34 /*
35 * we currently only select the max voltage from table
36 * Table 3-3 of the omap3530 Data sheet (SPRS507F).
37 * Format is: <target min max>
38 */
39 opp-microvolt = <975000 975000 975000>;
40 /*
41 * first value is silicon revision bit mask
42 * second one 720MHz Device Identification bit mask
43 */
44 opp-supported-hw = <0xffffffff 3>;
45 };
46
47 opp2-250000000 {
48 opp-hz = /bits/ 64 <250000000>;
49 opp-microvolt = <1075000 1075000 1075000>;
50 opp-supported-hw = <0xffffffff 3>;
51 opp-suspend;
52 };
53
54 opp3-500000000 {
55 opp-hz = /bits/ 64 <500000000>;
56 opp-microvolt = <1200000 1200000 1200000>;
57 opp-supported-hw = <0xffffffff 3>;
58 };
59
60 opp4-550000000 {
61 opp-hz = /bits/ 64 <550000000>;
62 opp-microvolt = <1275000 1275000 1275000>;
63 opp-supported-hw = <0xffffffff 3>;
64 };
65
66 opp5-600000000 {
67 opp-hz = /bits/ 64 <600000000>;
68 opp-microvolt = <1350000 1350000 1350000>;
69 opp-supported-hw = <0xffffffff 3>;
70 };
71
72 opp6-720000000 {
73 opp-hz = /bits/ 64 <720000000>;
74 opp-microvolt = <1350000 1350000 1350000>;
75 /* only high-speed grade omap3530 devices */
76 opp-supported-hw = <0xffffffff 2>;
77 turbo-mode;
78 };
79 };
80
81 ocp@68000000 {
82 omap3_pmx_core2: pinmux@480025d8 {
83 compatible = "ti,omap3-padconf", "pinctrl-single";
84 reg = <0x480025d8 0x24>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 #pinctrl-cells = <1>;
88 #interrupt-cells = <1>;
89 interrupt-controller;
90 pinctrl-single,register-width = <16>;
91 pinctrl-single,function-mask = <0xff1f>;
92 };
93
94 isp: isp@480bc000 {
95 compatible = "ti,omap3-isp";
96 reg = <0x480bc000 0x12fc
97 0x480bd800 0x017c>;
98 interrupts = <24>;
99 iommus = <&mmu_isp>;
100 syscon = <&scm_conf 0x6c>;
101 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
102 #clock-cells = <1>;
103 ports {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 };
107 };
108
109 bandgap: bandgap@48002524 {
110 reg = <0x48002524 0x4>;
111 compatible = "ti,omap34xx-bandgap";
112 #thermal-sensor-cells = <0>;
113 };
114
115 target-module@480cb000 {
116 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
117 ti,hwmods = "smartreflex_core";
118 reg = <0x480cb024 0x4>;
119 reg-names = "sysc";
120 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
121 clocks = <&sr2_fck>;
122 clock-names = "fck";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x480cb000 0x001000>;
126
127 smartreflex_core: smartreflex@0 {
128 compatible = "ti,omap3-smartreflex-core";
129 reg = <0 0x400>;
130 interrupts = <19>;
131 };
132 };
133
134 target-module@480c9000 {
135 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
136 ti,hwmods = "smartreflex_mpu_iva";
137 reg = <0x480c9024 0x4>;
138 reg-names = "sysc";
139 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
140 clocks = <&sr1_fck>;
141 clock-names = "fck";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges = <0 0x480c9000 0x001000>;
145
146 smartreflex_mpu_iva: smartreflex@480c9000 {
147 compatible = "ti,omap3-smartreflex-mpu-iva";
148 reg = <0 0x400>;
149 interrupts = <18>;
150 };
151 };
152
153 /*
154 * On omap34xx the OCP registers do not seem to be accessible
155 * at all unlike on 36xx. Maybe SGX is permanently set to
156 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
157 * write-only at 0x50000e10. We detect SGX based on the SGX
158 * revision register instead of the unreadable OCP revision
159 * register. Also note that on early 34xx es1 revision there
160 * are also different clocks, but we do not have any dts users
161 * for it.
162 */
163 sgx_module: target-module@50000000 {
164 compatible = "ti,sysc-omap2", "ti,sysc";
165 reg = <0x50000014 0x4>;
166 reg-names = "rev";
167 clocks = <&sgx_fck>, <&sgx_ick>;
168 clock-names = "fck", "ick";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0 0x50000000 0x4000>;
172
173 /*
174 * Closed source PowerVR driver, no child device
175 * binding or driver in mainline
176 */
177 };
178 };
179
180 thermal_zones: thermal-zones {
181 #include "omap3-cpu-thermal.dtsi"
182 };
183};
184
185&ssi {
186 status = "okay";
187
188 clocks = <&ssi_ssr_fck>,
189 <&ssi_sst_fck>,
190 <&ssi_ick>;
191 clock-names = "ssi_ssr_fck",
192 "ssi_sst_fck",
193 "ssi_ick";
194};
195
196/include/ "omap34xx-omap36xx-clocks.dtsi"
197/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
198/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
1/*
2 * Device Tree Source for OMAP34xx/OMAP35xx SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/bus/ti-sysc.h>
12#include <dt-bindings/media/omap3-isp.h>
13
14#include "omap3.dtsi"
15
16/ {
17 cpus {
18 cpu: cpu@0 {
19 /* OMAP343x/OMAP35xx variants OPP1-6 */
20 operating-points-v2 = <&cpu0_opp_table>;
21
22 clock-latency = <300000>; /* From legacy driver */
23 };
24 };
25
26 /* see Documentation/devicetree/bindings/opp/opp.txt */
27 cpu0_opp_table: opp-table {
28 compatible = "operating-points-v2-ti-cpu";
29 syscon = <&scm_conf>;
30
31 opp1-125000000 {
32 opp-hz = /bits/ 64 <125000000>;
33 /*
34 * we currently only select the max voltage from table
35 * Table 3-3 of the omap3530 Data sheet (SPRS507F).
36 * Format is: <target min max>
37 */
38 opp-microvolt = <975000 975000 975000>;
39 /*
40 * first value is silicon revision bit mask
41 * second one 720MHz Device Identification bit mask
42 */
43 opp-supported-hw = <0xffffffff 3>;
44 };
45
46 opp2-250000000 {
47 opp-hz = /bits/ 64 <250000000>;
48 opp-microvolt = <1075000 1075000 1075000>;
49 opp-supported-hw = <0xffffffff 3>;
50 opp-suspend;
51 };
52
53 opp3-500000000 {
54 opp-hz = /bits/ 64 <500000000>;
55 opp-microvolt = <1200000 1200000 1200000>;
56 opp-supported-hw = <0xffffffff 3>;
57 };
58
59 opp4-550000000 {
60 opp-hz = /bits/ 64 <550000000>;
61 opp-microvolt = <1275000 1275000 1275000>;
62 opp-supported-hw = <0xffffffff 3>;
63 };
64
65 opp5-600000000 {
66 opp-hz = /bits/ 64 <600000000>;
67 opp-microvolt = <1350000 1350000 1350000>;
68 opp-supported-hw = <0xffffffff 3>;
69 };
70
71 opp6-720000000 {
72 opp-hz = /bits/ 64 <720000000>;
73 opp-microvolt = <1350000 1350000 1350000>;
74 /* only high-speed grade omap3530 devices */
75 opp-supported-hw = <0xffffffff 2>;
76 turbo-mode;
77 };
78 };
79
80 ocp@68000000 {
81 omap3_pmx_core2: pinmux@480025d8 {
82 compatible = "ti,omap3-padconf", "pinctrl-single";
83 reg = <0x480025d8 0x24>;
84 #address-cells = <1>;
85 #size-cells = <0>;
86 #pinctrl-cells = <1>;
87 #interrupt-cells = <1>;
88 interrupt-controller;
89 pinctrl-single,register-width = <16>;
90 pinctrl-single,function-mask = <0xff1f>;
91 };
92
93 isp: isp@480bc000 {
94 compatible = "ti,omap3-isp";
95 reg = <0x480bc000 0x12fc
96 0x480bd800 0x017c>;
97 interrupts = <24>;
98 iommus = <&mmu_isp>;
99 syscon = <&scm_conf 0x6c>;
100 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
101 #clock-cells = <1>;
102 ports {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 };
106 };
107
108 bandgap: bandgap@48002524 {
109 reg = <0x48002524 0x4>;
110 compatible = "ti,omap34xx-bandgap";
111 #thermal-sensor-cells = <0>;
112 };
113
114 target-module@480cb000 {
115 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
116 ti,hwmods = "smartreflex_core";
117 reg = <0x480cb024 0x4>;
118 reg-names = "sysc";
119 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
120 clocks = <&sr2_fck>;
121 clock-names = "fck";
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges = <0 0x480cb000 0x001000>;
125
126 smartreflex_core: smartreflex@0 {
127 compatible = "ti,omap3-smartreflex-core";
128 reg = <0 0x400>;
129 interrupts = <19>;
130 };
131 };
132
133 target-module@480c9000 {
134 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
135 ti,hwmods = "smartreflex_mpu_iva";
136 reg = <0x480c9024 0x4>;
137 reg-names = "sysc";
138 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
139 clocks = <&sr1_fck>;
140 clock-names = "fck";
141 #address-cells = <1>;
142 #size-cells = <1>;
143 ranges = <0 0x480c9000 0x001000>;
144
145 smartreflex_mpu_iva: smartreflex@480c9000 {
146 compatible = "ti,omap3-smartreflex-mpu-iva";
147 reg = <0 0x400>;
148 interrupts = <18>;
149 };
150 };
151
152 /*
153 * On omap34xx the OCP registers do not seem to be accessible
154 * at all unlike on 36xx. Maybe SGX is permanently set to
155 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
156 * write-only at 0x50000e10. We detect SGX based on the SGX
157 * revision register instead of the unreadable OCP revision
158 * register. Also note that on early 34xx es1 revision there
159 * are also different clocks, but we do not have any dts users
160 * for it.
161 */
162 sgx_module: target-module@50000000 {
163 compatible = "ti,sysc-omap2", "ti,sysc";
164 reg = <0x50000014 0x4>;
165 reg-names = "rev";
166 clocks = <&sgx_fck>, <&sgx_ick>;
167 clock-names = "fck", "ick";
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges = <0 0x50000000 0x4000>;
171
172 /*
173 * Closed source PowerVR driver, no child device
174 * binding or driver in mainline
175 */
176 };
177 };
178
179 thermal_zones: thermal-zones {
180 #include "omap3-cpu-thermal.dtsi"
181 };
182};
183
184&ssi {
185 status = "ok";
186
187 clocks = <&ssi_ssr_fck>,
188 <&ssi_sst_fck>,
189 <&ssi_ick>;
190 clock-names = "ssi_ssr_fck",
191 "ssi_sst_fck",
192 "ssi_ick";
193};
194
195/include/ "omap34xx-omap36xx-clocks.dtsi"
196/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
197/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"