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1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Device Tree Include file for TQ Systems MBa7 carrier board.
4 *
5 * Copyright (C) 2016 TQ Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
8 *
9 * Note: This file does not include nodes for all peripheral devices.
10 * As device driver coverage increases additional nodes can be added.
11 */
12
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/net/ti-dp83867.h>
15
16/ {
17 aliases {
18 mmc0 = &usdhc3;
19 mmc1 = &usdhc1;
20 /delete-property/ mmc2;
21 };
22
23 beeper {
24 compatible = "gpio-beeper";
25 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
26 };
27
28 chosen {
29 stdout-path = &uart6;
30 };
31
32 gpio_buttons: gpio-keys {
33 compatible = "gpio-keys";
34
35 button-0 {
36 /* #SWITCH_A */
37 label = "S11";
38 linux,code = <KEY_1>;
39 gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
40 };
41
42 button-1 {
43 /* #SWITCH_B */
44 label = "S12";
45 linux,code = <KEY_2>;
46 gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
47 };
48
49 button-2 {
50 /* #SWITCH_C */
51 label = "S13";
52 linux,code = <KEY_3>;
53 gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
54 };
55 };
56
57 gpio-leds {
58 compatible = "gpio-leds";
59
60 led1 {
61 label = "led1";
62 gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "default-on";
64 };
65
66 led2 {
67 label = "led2";
68 gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
69 linux,default-trigger = "heartbeat";
70 };
71 };
72
73 reg_sd1_vmmc: regulator-sd1-vmmc {
74 compatible = "regulator-fixed";
75 regulator-name = "VCC3V3_SD1";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 };
80
81 reg_fec1_pwdn: regulator-fec1-pwdn {
82 compatible = "regulator-fixed";
83 regulator-name = "PWDN_FEC1";
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 regulator-always-on;
87 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
88 enable-active-high;
89 };
90
91 reg_fec2_pwdn: regulator-fec2-pwdn {
92 compatible = "regulator-fixed";
93 regulator-name = "PWDN_FEC2";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
96 regulator-always-on;
97 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
98 enable-active-high;
99 };
100
101 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
102 compatible = "regulator-fixed";
103 regulator-name = "VBUS_USBOTG1";
104 regulator-min-microvolt = <5000000>;
105 regulator-max-microvolt = <5000000>;
106 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
107 enable-active-high;
108 };
109
110 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
111 compatible = "regulator-fixed";
112 regulator-name = "VBUS_USBOTG2";
113 regulator-min-microvolt = <5000000>;
114 regulator-max-microvolt = <5000000>;
115 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
116 enable-active-high;
117 };
118
119 reg_mpcie_1v5: regulator-mpcie-1v5 {
120 compatible = "regulator-fixed";
121 regulator-name = "VCC1V5_MPCIE";
122 regulator-min-microvolt = <1500000>;
123 regulator-max-microvolt = <1500000>;
124 gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
125 enable-active-high;
126 regulator-always-on;
127 };
128
129 reg_mpcie_3v3: regulator-mpcie-3v3 {
130 compatible = "regulator-fixed";
131 regulator-name = "VCC3V3_MPCIE";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
135 enable-active-high;
136 regulator-always-on;
137 };
138
139 reg_mba_12v0: regulator-mba-12v0 {
140 compatible = "regulator-fixed";
141 regulator-name = "VCC12V0_MBA7";
142 regulator-min-microvolt = <12000000>;
143 regulator-max-microvolt = <12000000>;
144 gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
145 enable-active-high;
146 };
147
148 reg_lvds_transmitter: regulator-lvds-transmitter {
149 compatible = "regulator-fixed";
150 regulator-name = "#SHTDN_LVDS";
151 regulator-min-microvolt = <3300000>;
152 regulator-max-microvolt = <3300000>;
153 gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
154 enable-active-high;
155 };
156
157 reg_vref_1v8: regulator-vref-1v8 {
158 compatible = "regulator-fixed";
159 regulator-name = "VCC1V8_REF";
160 regulator-min-microvolt = <1800000>;
161 regulator-max-microvolt = <1800000>;
162 regulator-always-on;
163 vin-supply = <&sw2_reg>;
164 };
165
166 reg_audio_3v3: regulator-audio-3v3 {
167 compatible = "regulator-fixed";
168 regulator-name = "VCC3V3_AUDIO";
169 regulator-min-microvolt = <3300000>;
170 regulator-max-microvolt = <3300000>;
171 regulator-always-on;
172 };
173
174 sound {
175 compatible = "fsl,imx-audio-tlv320aic32x4";
176 model = "imx-audio-tlv320aic32x4";
177 ssi-controller = <&sai1>;
178 audio-codec = <&tlv320aic32x4>;
179 audio-routing =
180 "IN3_L", "Mic Jack",
181 "Mic Jack", "Mic Bias",
182 "IN1_L", "Line In Jack",
183 "IN1_R", "Line In Jack",
184 "Line Out Jack", "LOL",
185 "Line Out Jack", "LOR";
186 };
187};
188
189&adc1 {
190 vref-supply = <®_vref_1v8>;
191 status = "okay";
192};
193
194&adc2 {
195 vref-supply = <®_vref_1v8>;
196 status = "okay";
197};
198
199&ecspi1 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_ecspi1>;
202 cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
203 <&gpio4 2 GPIO_ACTIVE_LOW>;
204 status = "okay";
205};
206
207&ecspi2 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_ecspi2>;
210 status = "okay";
211};
212
213&fec1 {
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_enet1>;
216 phy-mode = "rgmii-id";
217 phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
218 phy-reset-duration = <1>;
219 phy-reset-delay = <1>;
220 phy-supply = <®_fec1_pwdn>;
221 phy-handle = <ðphy1_0>;
222 fsl,magic-packet;
223 status = "okay";
224
225 mdio {
226 #address-cells = <1>;
227 #size-cells = <0>;
228
229 ethphy1_0: ethernet-phy@0 {
230 compatible = "ethernet-phy-ieee802.3-c22";
231 reg = <0>;
232 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
233 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
234 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
235 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
236 };
237 };
238};
239
240&flexcan1 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_flexcan1>;
243 status = "okay";
244};
245
246&flexcan2 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_flexcan2>;
249 status = "okay";
250};
251
252&i2c1 {
253 lm75: temperature-sensor@49 {
254 compatible = "national,lm75";
255 reg = <0x49>;
256 };
257};
258
259&i2c2 {
260 clock-frequency = <100000>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_i2c2>;
263 status = "okay";
264
265 tlv320aic32x4: audio-codec@18 {
266 compatible = "ti,tlv320aic32x4";
267 reg = <0x18>;
268 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
269 clock-names = "mclk";
270 ldoin-supply = <®_audio_3v3>;
271 iov-supply = <®_audio_3v3>;
272 };
273
274 pca9555: gpio-expander@20 {
275 compatible = "nxp,pca9555";
276 reg = <0x20>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_pca9555>;
279 gpio-controller;
280 #gpio-cells = <2>;
281 interrupt-parent = <&gpio7>;
282 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 };
286};
287
288&i2c3 {
289 clock-frequency = <100000>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_i2c3>;
292 status = "okay";
293};
294
295&iomuxc {
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_hog_mba7_1>;
298
299 pinctrl_ecspi1: ecspi1grp {
300 fsl,pins = <
301 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c
302 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74
303 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74
304 MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74
305 MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74
306 MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74
307 >;
308 };
309
310 pinctrl_ecspi2: ecspi2grp {
311 fsl,pins = <
312 MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c
313 MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74
314 MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74
315 MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74
316 >;
317 };
318
319 pinctrl_enet1: enet1grp {
320 fsl,pins = <
321 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02
322 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00
323 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
324 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
325 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
326 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
327 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
328 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
329 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79
330 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79
331 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79
332 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79
333 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79
334 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
335 /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
336 MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070
337 /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
338 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078
339 >;
340 };
341
342 pinctrl_flexcan1: flexcan1grp {
343 fsl,pins = <
344 MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a
345 MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52
346 >;
347 };
348
349 pinctrl_flexcan2: flexcan2grp {
350 fsl,pins = <
351 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a
352 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52
353 >;
354 };
355
356 pinctrl_hog_mba7_1: hogmba71grp {
357 fsl,pins = <
358 /* Limitation: WDOG2_B / WDOG2_RESET not usable */
359 MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c
360 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074
361 /* #BOOT_EN */
362 MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010
363 >;
364 };
365
366 pinctrl_i2c2: i2c2grp {
367 fsl,pins = <
368 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078
369 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078
370 >;
371 };
372
373 pinctrl_i2c3: i2c3grp {
374 fsl,pins = <
375 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078
376 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078
377 >;
378 };
379
380 pinctrl_pca9555: pca95550grp {
381 fsl,pins = <
382 MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78
383 >;
384 };
385
386 pinctrl_sai1: sai1grp {
387 fsl,pins = <
388 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11
389 MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c
390 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c
391 MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c
392
393 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c
394 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14
395 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14
396 >;
397 };
398
399 pinctrl_uart3: uart3grp {
400 fsl,pins = <
401 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e
402 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76
403 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76
404 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e
405 >;
406 };
407
408 pinctrl_uart4: uart4grp {
409 fsl,pins = <
410 MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e
411 MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76
412 MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76
413 MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e
414 >;
415 };
416
417 pinctrl_uart5: uart5grp {
418 fsl,pins = <
419 MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e
420 MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76
421 >;
422 };
423
424 pinctrl_uart6: uart6grp {
425 fsl,pins = <
426 MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d
427 MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75
428 MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75
429 MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d
430 >;
431 };
432
433 pinctrl_uart7: uart7grp {
434 fsl,pins = <
435 MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e
436 MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76
437 MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76
438 /* Limitation: RTS is not connected */
439 MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e
440 >;
441 };
442
443 pinctrl_usdhc1_gpio: usdhc1grp_gpio {
444 fsl,pins = <
445 /* WP */
446 MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c
447 /* CD */
448 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c
449 /* VSELECT */
450 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59
451 >;
452 };
453
454 pinctrl_usdhc1: usdhc1grp {
455 fsl,pins = <
456 MX7D_PAD_SD1_CMD__SD1_CMD 0x5e
457 MX7D_PAD_SD1_CLK__SD1_CLK 0x57
458 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e
459 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e
460 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e
461 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e
462 >;
463 };
464
465 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
466 fsl,pins = <
467 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
468 MX7D_PAD_SD1_CLK__SD1_CLK 0x57
469 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
470 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
471 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
472 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
473 >;
474 };
475
476 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
477 fsl,pins = <
478 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
479 MX7D_PAD_SD1_CLK__SD1_CLK 0x57
480 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
481 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
482 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
483 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
484 >;
485 };
486};
487
488&iomuxc_lpsr {
489 pinctrl_pwm1: pwm1grp {
490 fsl,pins = <
491 /* LCD_CONTRAST */
492 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50
493 >;
494 };
495
496 pinctrl_usbotg1: usbotg1grp {
497 fsl,pins = <
498 MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c
499 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
500 >;
501 };
502
503 pinctrl_wdog1: wdog1grp {
504 fsl,pins = <
505 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
506 >;
507 };
508};
509
510&pwm1 {
511 pinctrl-names = "default";
512 pinctrl-0 = <&pinctrl_pwm1>;
513 status = "okay";
514};
515
516&sai1 {
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_sai1>;
519 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
520 <&clks IMX7D_SAI1_ROOT_CLK>;
521 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
522 assigned-clock-rates = <0>, <36864000>;
523 status = "okay";
524};
525
526&uart3 {
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_uart3>;
529 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
530 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
531 status = "okay";
532};
533
534&uart4 {
535 pinctrl-names = "default";
536 pinctrl-0 = <&pinctrl_uart4>;
537 assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
538 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
539 status = "okay";
540};
541
542&uart5 {
543 pinctrl-names = "default";
544 pinctrl-0 = <&pinctrl_uart5>;
545 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
546 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
547 status = "okay";
548};
549
550&uart6 {
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_uart6>;
553 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
554 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
555 status = "okay";
556};
557
558&uart7 {
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_uart7>;
561 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
562 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
563 uart-has-rtscts;
564 linux,rs485-enabled-at-boot-time;
565 rs485-rts-active-low;
566 rs485-rx-during-tx;
567 status = "okay";
568};
569
570&usbh {
571 status = "okay";
572};
573
574&usbotg1 {
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_usbotg1>;
577 vbus-supply = <®_usb_otg1_vbus>;
578 srp-disable;
579 hnp-disable;
580 adp-disable;
581 over-current-active-low;
582 dr_mode = "otg";
583 status = "okay";
584};
585
586&usdhc1 {
587 pinctrl-names = "default", "state_100mhz", "state_200mhz";
588 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
589 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
590 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
591 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
592 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
593 vmmc-supply = <®_sd1_vmmc>;
594 bus-width = <4>;
595 no-1-8-v;
596 status = "okay";
597};
598
599&wdog1 {
600 pinctrl-names = "default";
601 pinctrl-0 = <&pinctrl_wdog1>;
602 fsl,ext-reset-output;
603};
1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Device Tree Include file for TQ Systems MBa7 carrier board.
4 *
5 * Copyright (C) 2016 TQ Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
8 *
9 * Note: This file does not include nodes for all peripheral devices.
10 * As device driver coverage increases additional nodes can be added.
11 */
12
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/net/ti-dp83867.h>
15
16/ {
17 beeper {
18 compatible = "gpio-beeper";
19 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
20 };
21
22 chosen {
23 stdout-path = &uart6;
24 };
25
26 gpio_buttons: gpio-keys {
27 compatible = "gpio-keys";
28
29 button-0 {
30 /* #SWITCH_A */
31 label = "S11";
32 linux,code = <KEY_1>;
33 gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
34 };
35
36 button-1 {
37 /* #SWITCH_B */
38 label = "S12";
39 linux,code = <KEY_2>;
40 gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
41 };
42
43 button-2 {
44 /* #SWITCH_C */
45 label = "S13";
46 linux,code = <KEY_3>;
47 gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
48 };
49 };
50
51 gpio-leds {
52 compatible = "gpio-leds";
53
54 led1 {
55 label = "led1";
56 gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
57 linux,default-trigger = "default-on";
58 };
59
60 led2 {
61 label = "led2";
62 gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "heartbeat";
64 };
65 };
66
67 reg_sd1_vmmc: regulator-sd1-vmmc {
68 compatible = "regulator-fixed";
69 regulator-name = "VCC3V3_SD1";
70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
72 regulator-always-on;
73 };
74
75 reg_fec1_pwdn: regulator-fec1-pwdn {
76 compatible = "regulator-fixed";
77 regulator-name = "PWDN_FEC1";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 regulator-always-on;
81 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
82 enable-active-high;
83 };
84
85 reg_fec2_pwdn: regulator-fec2-pwdn {
86 compatible = "regulator-fixed";
87 regulator-name = "PWDN_FEC2";
88 regulator-min-microvolt = <3300000>;
89 regulator-max-microvolt = <3300000>;
90 regulator-always-on;
91 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
92 enable-active-high;
93 };
94
95 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
96 compatible = "regulator-fixed";
97 regulator-name = "VBUS_USBOTG1";
98 regulator-min-microvolt = <5000000>;
99 regulator-max-microvolt = <5000000>;
100 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
101 enable-active-high;
102 };
103
104 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
105 compatible = "regulator-fixed";
106 regulator-name = "VBUS_USBOTG2";
107 regulator-min-microvolt = <5000000>;
108 regulator-max-microvolt = <5000000>;
109 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
110 enable-active-high;
111 };
112
113 reg_mpcie_1v5: regulator-mpcie-1v5 {
114 compatible = "regulator-fixed";
115 regulator-name = "VCC1V5_MPCIE";
116 regulator-min-microvolt = <1500000>;
117 regulator-max-microvolt = <1500000>;
118 gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
119 enable-active-high;
120 regulator-always-on;
121 };
122
123 reg_mpcie_3v3: regulator-mpcie-3v3 {
124 compatible = "regulator-fixed";
125 regulator-name = "VCC3V3_MPCIE";
126 regulator-min-microvolt = <3300000>;
127 regulator-max-microvolt = <3300000>;
128 gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
129 enable-active-high;
130 regulator-always-on;
131 };
132
133 reg_mba_12v0: regulator-mba-12v0 {
134 compatible = "regulator-fixed";
135 regulator-name = "VCC12V0_MBA7";
136 regulator-min-microvolt = <12000000>;
137 regulator-max-microvolt = <12000000>;
138 gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
139 enable-active-high;
140 };
141
142 reg_lvds_transmitter: regulator-lvds-transmitter {
143 compatible = "regulator-fixed";
144 regulator-name = "#SHTDN_LVDS";
145 regulator-min-microvolt = <3300000>;
146 regulator-max-microvolt = <3300000>;
147 gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
148 enable-active-high;
149 };
150
151 reg_vref_1v8: regulator-vref-1v8 {
152 compatible = "regulator-fixed";
153 regulator-name = "VCC1V8_REF";
154 regulator-min-microvolt = <1800000>;
155 regulator-max-microvolt = <1800000>;
156 regulator-always-on;
157 vin-supply = <&sw2_reg>;
158 };
159
160 reg_audio_3v3: regulator-audio-3v3 {
161 compatible = "regulator-fixed";
162 regulator-name = "VCC3V3_AUDIO";
163 regulator-min-microvolt = <3300000>;
164 regulator-max-microvolt = <3300000>;
165 regulator-always-on;
166 };
167};
168
169&adc1 {
170 vref-supply = <®_vref_1v8>;
171 status = "okay";
172};
173
174&adc2 {
175 vref-supply = <®_vref_1v8>;
176 status = "okay";
177};
178
179&ecspi1 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_ecspi1>;
182 num-chipselects = <3>;
183 cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
184 <&gpio4 2 GPIO_ACTIVE_LOW>;
185 status = "okay";
186};
187
188&ecspi2 {
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_ecspi2>;
191 num-chipselects = <1>;
192 status = "okay";
193};
194
195&fec1 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_enet1>;
198 phy-mode = "rgmii-id";
199 phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
200 phy-reset-duration = <1>;
201 phy-reset-delay = <1>;
202 phy-supply = <®_fec1_pwdn>;
203 phy-handle = <ðphy1_0>;
204 fsl,magic-packet;
205 status = "okay";
206
207 mdio {
208 #address-cells = <1>;
209 #size-cells = <0>;
210
211 ethphy1_0: ethernet-phy@0 {
212 compatible = "ethernet-phy-ieee802.3-c22";
213 reg = <0>;
214 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
215 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
216 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
217 /* LED1: Link/Activity, LED2: Error */
218 ti,led-function = <0x0db0>;
219 /* Active low, LED1 and LED2 driven by phy */
220 ti,led-ctrl = <0x1001>;
221 };
222 };
223};
224
225&flexcan1 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_flexcan1>;
228 status = "okay";
229};
230
231&flexcan2 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_flexcan2>;
234 status = "okay";
235};
236
237&i2c1 {
238 lm75: temperature-sensor@49 {
239 compatible = "national,lm75";
240 reg = <0x49>;
241 };
242};
243
244&i2c2 {
245 clock-frequency = <100000>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_i2c2>;
248 status = "okay";
249
250 tlv320aic32x4: audio-codec@18 {
251 compatible = "ti,tlv320aic32x4";
252 reg = <0x18>;
253 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
254 clock-names = "mclk";
255 ldoin-supply = <®_audio_3v3>;
256 iov-supply = <®_audio_3v3>;
257 };
258
259 pca9555: gpio-expander@20 {
260 compatible = "nxp,pca9555";
261 reg = <0x20>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_pca9555>;
264 gpio-controller;
265 #gpio-cells = <2>;
266 interrupt-parent = <&gpio7>;
267 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 };
271};
272
273&i2c3 {
274 clock-frequency = <100000>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_i2c3>;
277 status = "okay";
278};
279
280&iomuxc {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_hog_mba7_1>;
283
284 pinctrl_ecspi1: ecspi1grp {
285 fsl,pins = <
286 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c
287 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74
288 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74
289 MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74
290 MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74
291 MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74
292 >;
293 };
294
295 pinctrl_ecspi2: ecspi2grp {
296 fsl,pins = <
297 MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c
298 MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74
299 MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74
300 MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74
301 >;
302 };
303
304 pinctrl_enet1: enet1grp {
305 fsl,pins = <
306 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02
307 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00
308 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
309 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
310 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
311 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
312 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
313 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
314 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79
315 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79
316 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79
317 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79
318 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79
319 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
320 /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
321 MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070
322 /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
323 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078
324 >;
325 };
326
327 pinctrl_flexcan1: flexcan1grp {
328 fsl,pins = <
329 MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a
330 MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52
331 >;
332 };
333
334 pinctrl_flexcan2: flexcan2grp {
335 fsl,pins = <
336 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a
337 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52
338 >;
339 };
340
341 pinctrl_hog_mba7_1: hogmba71grp {
342 fsl,pins = <
343 /* Limitation: WDOG2_B / WDOG2_RESET not usable */
344 MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c
345 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074
346 /* #BOOT_EN */
347 MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010
348 >;
349 };
350
351 pinctrl_i2c2: i2c2grp {
352 fsl,pins = <
353 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078
354 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078
355 >;
356 };
357
358 pinctrl_i2c3: i2c3grp {
359 fsl,pins = <
360 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078
361 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078
362 >;
363 };
364
365
366 pinctrl_pca9555: pca95550grp {
367 fsl,pins = <
368 MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78
369 >;
370 };
371
372 pinctrl_uart3: uart3grp {
373 fsl,pins = <
374 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e
375 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76
376 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76
377 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e
378 >;
379 };
380
381 pinctrl_uart4: uart4grp {
382 fsl,pins = <
383 MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e
384 MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76
385 MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76
386 MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e
387 >;
388 };
389
390 pinctrl_uart5: uart5grp {
391 fsl,pins = <
392 MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e
393 MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76
394 >;
395 };
396
397 pinctrl_uart6: uart6grp {
398 fsl,pins = <
399 MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d
400 MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75
401 MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75
402 MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d
403 >;
404 };
405
406 pinctrl_uart7: uart7grp {
407 fsl,pins = <
408 MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e
409 MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76
410 MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76
411 /* Limitation: RTS is not connected */
412 MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e
413 >;
414 };
415
416 pinctrl_usdhc1_gpio: usdhc1grp_gpio {
417 fsl,pins = <
418 /* WP */
419 MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c
420 /* CD */
421 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c
422 /* VSELECT */
423 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59
424 >;
425 };
426
427 pinctrl_usdhc1: usdhc1grp {
428 fsl,pins = <
429 MX7D_PAD_SD1_CMD__SD1_CMD 0x5e
430 MX7D_PAD_SD1_CLK__SD1_CLK 0x57
431 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e
432 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e
433 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e
434 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e
435 >;
436 };
437
438 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
439 fsl,pins = <
440 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
441 MX7D_PAD_SD1_CLK__SD1_CLK 0x57
442 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
443 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
444 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
445 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
446 >;
447 };
448
449 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
450 fsl,pins = <
451 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
452 MX7D_PAD_SD1_CLK__SD1_CLK 0x57
453 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
454 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
455 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
456 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
457 >;
458 };
459};
460
461&iomuxc_lpsr {
462 pinctrl_pwm1: pwm1grp {
463 fsl,pins = <
464 /* LCD_CONTRAST */
465 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50
466 >;
467 };
468
469 pinctrl_usbotg1: usbotg1grp {
470 fsl,pins = <
471 MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c
472 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
473 >;
474 };
475};
476
477&pwm1 {
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_pwm1>;
480 status = "okay";
481};
482
483&uart3 {
484 pinctrl-names = "default";
485 pinctrl-0 = <&pinctrl_uart3>;
486 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
487 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
488 status = "okay";
489};
490
491&uart4 {
492 pinctrl-names = "default";
493 pinctrl-0 = <&pinctrl_uart4>;
494 assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
495 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
496 status = "okay";
497};
498
499&uart5 {
500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_uart5>;
502 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
503 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
504 status = "okay";
505};
506
507&uart6 {
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_uart6>;
510 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
511 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
512 status = "okay";
513};
514
515&uart7 {
516 pinctrl-names = "default";
517 pinctrl-0 = <&pinctrl_uart7>;
518 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
519 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
520 uart-has-rtscts;
521 status = "okay";
522};
523
524&usbh {
525 status = "okay";
526};
527
528&usbotg1 {
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_usbotg1>;
531 vbus-supply = <®_usb_otg1_vbus>;
532 srp-disable;
533 hnp-disable;
534 adp-disable;
535 dr_mode = "host";
536 status = "okay";
537};
538
539&usdhc1 {
540 pinctrl-names = "default", "state_100mhz", "state_200mhz";
541 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
542 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
543 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
544 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
545 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
546 vmmc-supply = <®_sd1_vmmc>;
547 bus-width = <4>;
548 no-1-8-v;
549 status = "okay";
550};