1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2#ifndef _ASM_X86_INSN_H
  3#define _ASM_X86_INSN_H
  4/*
  5 * x86 instruction analysis
  6 *
  7 * Copyright (C) IBM Corporation, 2009
  8 */
  9
 10#include <asm/byteorder.h>
 11/* insn_attr_t is defined in inat.h */
 12#include "inat.h" /* __ignore_sync_check__ */
 13
 14#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __LITTLE_ENDIAN : defined(__LITTLE_ENDIAN)
 15
 16struct insn_field {
 17	union {
 18		insn_value_t value;
 19		insn_byte_t bytes[4];
 20	};
 21	/* !0 if we've run insn_get_xxx() for this field */
 22	unsigned char got;
 23	unsigned char nbytes;
 24};
 25
 26static inline void insn_field_set(struct insn_field *p, insn_value_t v,
 27				  unsigned char n)
 28{
 29	p->value = v;
 30	p->nbytes = n;
 31}
 32
 33static inline void insn_set_byte(struct insn_field *p, unsigned char n,
 34				 insn_byte_t v)
 35{
 36	p->bytes[n] = v;
 37}
 38
 39#else
 40
 41struct insn_field {
 42	insn_value_t value;
 43	union {
 44		insn_value_t little;
 45		insn_byte_t bytes[4];
 46	};
 47	/* !0 if we've run insn_get_xxx() for this field */
 48	unsigned char got;
 49	unsigned char nbytes;
 50};
 51
 52static inline void insn_field_set(struct insn_field *p, insn_value_t v,
 53				  unsigned char n)
 54{
 55	p->value = v;
 56	p->little = __cpu_to_le32(v);
 57	p->nbytes = n;
 58}
 59
 60static inline void insn_set_byte(struct insn_field *p, unsigned char n,
 61				 insn_byte_t v)
 62{
 63	p->bytes[n] = v;
 64	p->value = __le32_to_cpu(p->little);
 65}
 66#endif
 67
 68struct insn {
 69	struct insn_field prefixes;	/*
 70					 * Prefixes
 71					 * prefixes.bytes[3]: last prefix
 72					 */
 73	struct insn_field rex_prefix;	/* REX prefix */
 74	struct insn_field vex_prefix;	/* VEX prefix */
 75	struct insn_field opcode;	/*
 76					 * opcode.bytes[0]: opcode1
 77					 * opcode.bytes[1]: opcode2
 78					 * opcode.bytes[2]: opcode3
 79					 */
 80	struct insn_field modrm;
 81	struct insn_field sib;
 82	struct insn_field displacement;
 83	union {
 84		struct insn_field immediate;
 85		struct insn_field moffset1;	/* for 64bit MOV */
 86		struct insn_field immediate1;	/* for 64bit imm or off16/32 */
 87	};
 88	union {
 89		struct insn_field moffset2;	/* for 64bit MOV */
 90		struct insn_field immediate2;	/* for 64bit imm or seg16 */
 91	};
 92
 93	int	emulate_prefix_size;
 94	insn_attr_t attr;
 95	unsigned char opnd_bytes;
 96	unsigned char addr_bytes;
 97	unsigned char length;
 98	unsigned char x86_64;
 99
100	const insn_byte_t *kaddr;	/* kernel address of insn to analyze */
101	const insn_byte_t *end_kaddr;	/* kernel address of last insn in buffer */
102	const insn_byte_t *next_byte;
103};
104
105#define MAX_INSN_SIZE	15
106
107#define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
108#define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
109#define X86_MODRM_RM(modrm) ((modrm) & 0x07)
110
111#define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
112#define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
113#define X86_SIB_BASE(sib) ((sib) & 0x07)
114
115#define X86_REX_W(rex) ((rex) & 8)
116#define X86_REX_R(rex) ((rex) & 4)
117#define X86_REX_X(rex) ((rex) & 2)
118#define X86_REX_B(rex) ((rex) & 1)
119
120/* VEX bit flags  */
121#define X86_VEX_W(vex)	((vex) & 0x80)	/* VEX3 Byte2 */
122#define X86_VEX_R(vex)	((vex) & 0x80)	/* VEX2/3 Byte1 */
123#define X86_VEX_X(vex)	((vex) & 0x40)	/* VEX3 Byte1 */
124#define X86_VEX_B(vex)	((vex) & 0x20)	/* VEX3 Byte1 */
125#define X86_VEX_L(vex)	((vex) & 0x04)	/* VEX3 Byte2, VEX2 Byte1 */
126/* VEX bit fields */
127#define X86_EVEX_M(vex)	((vex) & 0x03)		/* EVEX Byte1 */
128#define X86_VEX3_M(vex)	((vex) & 0x1f)		/* VEX3 Byte1 */
129#define X86_VEX2_M	1			/* VEX2.M always 1 */
130#define X86_VEX_V(vex)	(((vex) & 0x78) >> 3)	/* VEX3 Byte2, VEX2 Byte1 */
131#define X86_VEX_P(vex)	((vex) & 0x03)		/* VEX3 Byte2, VEX2 Byte1 */
132#define X86_VEX_M_MAX	0x1f			/* VEX3.M Maximum value */
133
134extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
135extern int insn_get_prefixes(struct insn *insn);
136extern int insn_get_opcode(struct insn *insn);
137extern int insn_get_modrm(struct insn *insn);
138extern int insn_get_sib(struct insn *insn);
139extern int insn_get_displacement(struct insn *insn);
140extern int insn_get_immediate(struct insn *insn);
141extern int insn_get_length(struct insn *insn);
142
143enum insn_mode {
144	INSN_MODE_32,
145	INSN_MODE_64,
146	/* Mode is determined by the current kernel build. */
147	INSN_MODE_KERN,
148	INSN_NUM_MODES,
149};
150
151extern int insn_decode(struct insn *insn, const void *kaddr, int buf_len, enum insn_mode m);
152
153#define insn_decode_kernel(_insn, _ptr) insn_decode((_insn), (_ptr), MAX_INSN_SIZE, INSN_MODE_KERN)
154
155/* Attribute will be determined after getting ModRM (for opcode groups) */
156static inline void insn_get_attribute(struct insn *insn)
157{
158	insn_get_modrm(insn);
159}
160
161/* Instruction uses RIP-relative addressing */
162extern int insn_rip_relative(struct insn *insn);
163
 
 
 
 
 
 
 
 
 
 
 
164static inline int insn_is_avx(struct insn *insn)
165{
166	if (!insn->prefixes.got)
167		insn_get_prefixes(insn);
168	return (insn->vex_prefix.value != 0);
169}
170
171static inline int insn_is_evex(struct insn *insn)
172{
173	if (!insn->prefixes.got)
174		insn_get_prefixes(insn);
175	return (insn->vex_prefix.nbytes == 4);
176}
177
178static inline int insn_has_emulate_prefix(struct insn *insn)
179{
180	return !!insn->emulate_prefix_size;
181}
182
 
 
 
 
 
 
 
183static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
184{
185	if (insn->vex_prefix.nbytes == 2)	/* 2 bytes VEX */
186		return X86_VEX2_M;
187	else if (insn->vex_prefix.nbytes == 3)	/* 3 bytes VEX */
188		return X86_VEX3_M(insn->vex_prefix.bytes[1]);
189	else					/* EVEX */
190		return X86_EVEX_M(insn->vex_prefix.bytes[1]);
191}
192
193static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
194{
195	if (insn->vex_prefix.nbytes == 2)	/* 2 bytes VEX */
196		return X86_VEX_P(insn->vex_prefix.bytes[1]);
197	else
198		return X86_VEX_P(insn->vex_prefix.bytes[2]);
199}
200
201/* Get the last prefix id from last prefix or VEX prefix */
202static inline int insn_last_prefix_id(struct insn *insn)
203{
204	if (insn_is_avx(insn))
205		return insn_vex_p_bits(insn);	/* VEX_p is a SIMD prefix id */
206
207	if (insn->prefixes.bytes[3])
208		return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
209
210	return 0;
211}
212
213/* Offset of each field from kaddr */
214static inline int insn_offset_rex_prefix(struct insn *insn)
215{
216	return insn->prefixes.nbytes;
217}
218static inline int insn_offset_vex_prefix(struct insn *insn)
219{
220	return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
221}
222static inline int insn_offset_opcode(struct insn *insn)
223{
224	return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
225}
226static inline int insn_offset_modrm(struct insn *insn)
227{
228	return insn_offset_opcode(insn) + insn->opcode.nbytes;
229}
230static inline int insn_offset_sib(struct insn *insn)
231{
232	return insn_offset_modrm(insn) + insn->modrm.nbytes;
233}
234static inline int insn_offset_displacement(struct insn *insn)
235{
236	return insn_offset_sib(insn) + insn->sib.nbytes;
237}
238static inline int insn_offset_immediate(struct insn *insn)
239{
240	return insn_offset_displacement(insn) + insn->displacement.nbytes;
241}
242
243/**
244 * for_each_insn_prefix() -- Iterate prefixes in the instruction
245 * @insn: Pointer to struct insn.
246 * @idx:  Index storage.
247 * @prefix: Prefix byte.
248 *
249 * Iterate prefix bytes of given @insn. Each prefix byte is stored in @prefix
250 * and the index is stored in @idx (note that this @idx is just for a cursor,
251 * do not change it.)
252 * Since prefixes.nbytes can be bigger than 4 if some prefixes
253 * are repeated, it cannot be used for looping over the prefixes.
254 */
255#define for_each_insn_prefix(insn, idx, prefix)	\
256	for (idx = 0; idx < ARRAY_SIZE(insn->prefixes.bytes) && (prefix = insn->prefixes.bytes[idx]) != 0; idx++)
257
258#define POP_SS_OPCODE 0x1f
259#define MOV_SREG_OPCODE 0x8e
260
261/*
262 * Intel SDM Vol.3A 6.8.3 states;
263 * "Any single-step trap that would be delivered following the MOV to SS
264 * instruction or POP to SS instruction (because EFLAGS.TF is 1) is
265 * suppressed."
266 * This function returns true if @insn is MOV SS or POP SS. On these
267 * instructions, single stepping is suppressed.
268 */
269static inline int insn_masking_exception(struct insn *insn)
270{
271	return insn->opcode.bytes[0] == POP_SS_OPCODE ||
272		(insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
273		 X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
274}
275
276#endif /* _ASM_X86_INSN_H */

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2#ifndef _ASM_X86_INSN_H
  3#define _ASM_X86_INSN_H
  4/*
  5 * x86 instruction analysis
  6 *
  7 * Copyright (C) IBM Corporation, 2009
  8 */
  9
 
 10/* insn_attr_t is defined in inat.h */
 11#include "inat.h"
 
 
 12
 13struct insn_field {
 14	union {
 15		insn_value_t value;
 16		insn_byte_t bytes[4];
 17	};
 18	/* !0 if we've run insn_get_xxx() for this field */
 19	unsigned char got;
 20	unsigned char nbytes;
 21};
 22
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 23struct insn {
 24	struct insn_field prefixes;	/*
 25					 * Prefixes
 26					 * prefixes.bytes[3]: last prefix
 27					 */
 28	struct insn_field rex_prefix;	/* REX prefix */
 29	struct insn_field vex_prefix;	/* VEX prefix */
 30	struct insn_field opcode;	/*
 31					 * opcode.bytes[0]: opcode1
 32					 * opcode.bytes[1]: opcode2
 33					 * opcode.bytes[2]: opcode3
 34					 */
 35	struct insn_field modrm;
 36	struct insn_field sib;
 37	struct insn_field displacement;
 38	union {
 39		struct insn_field immediate;
 40		struct insn_field moffset1;	/* for 64bit MOV */
 41		struct insn_field immediate1;	/* for 64bit imm or off16/32 */
 42	};
 43	union {
 44		struct insn_field moffset2;	/* for 64bit MOV */
 45		struct insn_field immediate2;	/* for 64bit imm or seg16 */
 46	};
 47
 48	int	emulate_prefix_size;
 49	insn_attr_t attr;
 50	unsigned char opnd_bytes;
 51	unsigned char addr_bytes;
 52	unsigned char length;
 53	unsigned char x86_64;
 54
 55	const insn_byte_t *kaddr;	/* kernel address of insn to analyze */
 56	const insn_byte_t *end_kaddr;	/* kernel address of last insn in buffer */
 57	const insn_byte_t *next_byte;
 58};
 59
 60#define MAX_INSN_SIZE	15
 61
 62#define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
 63#define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
 64#define X86_MODRM_RM(modrm) ((modrm) & 0x07)
 65
 66#define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
 67#define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
 68#define X86_SIB_BASE(sib) ((sib) & 0x07)
 69
 70#define X86_REX_W(rex) ((rex) & 8)
 71#define X86_REX_R(rex) ((rex) & 4)
 72#define X86_REX_X(rex) ((rex) & 2)
 73#define X86_REX_B(rex) ((rex) & 1)
 74
 75/* VEX bit flags  */
 76#define X86_VEX_W(vex)	((vex) & 0x80)	/* VEX3 Byte2 */
 77#define X86_VEX_R(vex)	((vex) & 0x80)	/* VEX2/3 Byte1 */
 78#define X86_VEX_X(vex)	((vex) & 0x40)	/* VEX3 Byte1 */
 79#define X86_VEX_B(vex)	((vex) & 0x20)	/* VEX3 Byte1 */
 80#define X86_VEX_L(vex)	((vex) & 0x04)	/* VEX3 Byte2, VEX2 Byte1 */
 81/* VEX bit fields */
 82#define X86_EVEX_M(vex)	((vex) & 0x03)		/* EVEX Byte1 */
 83#define X86_VEX3_M(vex)	((vex) & 0x1f)		/* VEX3 Byte1 */
 84#define X86_VEX2_M	1			/* VEX2.M always 1 */
 85#define X86_VEX_V(vex)	(((vex) & 0x78) >> 3)	/* VEX3 Byte2, VEX2 Byte1 */
 86#define X86_VEX_P(vex)	((vex) & 0x03)		/* VEX3 Byte2, VEX2 Byte1 */
 87#define X86_VEX_M_MAX	0x1f			/* VEX3.M Maximum value */
 88
 89extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
 90extern void insn_get_prefixes(struct insn *insn);
 91extern void insn_get_opcode(struct insn *insn);
 92extern void insn_get_modrm(struct insn *insn);
 93extern void insn_get_sib(struct insn *insn);
 94extern void insn_get_displacement(struct insn *insn);
 95extern void insn_get_immediate(struct insn *insn);
 96extern void insn_get_length(struct insn *insn);
 
 
 
 
 
 
 
 
 
 
 
 
 97
 98/* Attribute will be determined after getting ModRM (for opcode groups) */
 99static inline void insn_get_attribute(struct insn *insn)
100{
101	insn_get_modrm(insn);
102}
103
104/* Instruction uses RIP-relative addressing */
105extern int insn_rip_relative(struct insn *insn);
106
107/* Init insn for kernel text */
108static inline void kernel_insn_init(struct insn *insn,
109				    const void *kaddr, int buf_len)
110{
111#ifdef CONFIG_X86_64
112	insn_init(insn, kaddr, buf_len, 1);
113#else /* CONFIG_X86_32 */
114	insn_init(insn, kaddr, buf_len, 0);
115#endif
116}
117
118static inline int insn_is_avx(struct insn *insn)
119{
120	if (!insn->prefixes.got)
121		insn_get_prefixes(insn);
122	return (insn->vex_prefix.value != 0);
123}
124
125static inline int insn_is_evex(struct insn *insn)
126{
127	if (!insn->prefixes.got)
128		insn_get_prefixes(insn);
129	return (insn->vex_prefix.nbytes == 4);
130}
131
132static inline int insn_has_emulate_prefix(struct insn *insn)
133{
134	return !!insn->emulate_prefix_size;
135}
136
137/* Ensure this instruction is decoded completely */
138static inline int insn_complete(struct insn *insn)
139{
140	return insn->opcode.got && insn->modrm.got && insn->sib.got &&
141		insn->displacement.got && insn->immediate.got;
142}
143
144static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
145{
146	if (insn->vex_prefix.nbytes == 2)	/* 2 bytes VEX */
147		return X86_VEX2_M;
148	else if (insn->vex_prefix.nbytes == 3)	/* 3 bytes VEX */
149		return X86_VEX3_M(insn->vex_prefix.bytes[1]);
150	else					/* EVEX */
151		return X86_EVEX_M(insn->vex_prefix.bytes[1]);
152}
153
154static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
155{
156	if (insn->vex_prefix.nbytes == 2)	/* 2 bytes VEX */
157		return X86_VEX_P(insn->vex_prefix.bytes[1]);
158	else
159		return X86_VEX_P(insn->vex_prefix.bytes[2]);
160}
161
162/* Get the last prefix id from last prefix or VEX prefix */
163static inline int insn_last_prefix_id(struct insn *insn)
164{
165	if (insn_is_avx(insn))
166		return insn_vex_p_bits(insn);	/* VEX_p is a SIMD prefix id */
167
168	if (insn->prefixes.bytes[3])
169		return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
170
171	return 0;
172}
173
174/* Offset of each field from kaddr */
175static inline int insn_offset_rex_prefix(struct insn *insn)
176{
177	return insn->prefixes.nbytes;
178}
179static inline int insn_offset_vex_prefix(struct insn *insn)
180{
181	return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
182}
183static inline int insn_offset_opcode(struct insn *insn)
184{
185	return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
186}
187static inline int insn_offset_modrm(struct insn *insn)
188{
189	return insn_offset_opcode(insn) + insn->opcode.nbytes;
190}
191static inline int insn_offset_sib(struct insn *insn)
192{
193	return insn_offset_modrm(insn) + insn->modrm.nbytes;
194}
195static inline int insn_offset_displacement(struct insn *insn)
196{
197	return insn_offset_sib(insn) + insn->sib.nbytes;
198}
199static inline int insn_offset_immediate(struct insn *insn)
200{
201	return insn_offset_displacement(insn) + insn->displacement.nbytes;
202}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
203
204#define POP_SS_OPCODE 0x1f
205#define MOV_SREG_OPCODE 0x8e
206
207/*
208 * Intel SDM Vol.3A 6.8.3 states;
209 * "Any single-step trap that would be delivered following the MOV to SS
210 * instruction or POP to SS instruction (because EFLAGS.TF is 1) is
211 * suppressed."
212 * This function returns true if @insn is MOV SS or POP SS. On these
213 * instructions, single stepping is suppressed.
214 */
215static inline int insn_masking_exception(struct insn *insn)
216{
217	return insn->opcode.bytes[0] == POP_SS_OPCODE ||
218		(insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
219		 X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
220}
221
222#endif /* _ASM_X86_INSN_H */