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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2020 Intel Corporation
4 *
5 * Please try to maintain the following order within this file unless it makes
6 * sense to do otherwise. From top to bottom:
7 * 1. typedefs
8 * 2. #defines, and macros
9 * 3. structure definitions
10 * 4. function prototypes
11 *
12 * Within each section, please try to order by generation in ascending order,
13 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
14 */
15
16#ifndef __INTEL_GTT_H__
17#define __INTEL_GTT_H__
18
19#include <linux/io-mapping.h>
20#include <linux/kref.h>
21#include <linux/mm.h>
22#include <linux/pagevec.h>
23#include <linux/scatterlist.h>
24#include <linux/workqueue.h>
25
26#include <drm/drm_mm.h>
27
28#include "gt/intel_reset.h"
29#include "i915_selftest.h"
30#include "i915_vma_types.h"
31
32#define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
33
34#if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT)
35#define DBG(...) trace_printk(__VA_ARGS__)
36#else
37#define DBG(...)
38#endif
39
40#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
41
42#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
43#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
44#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
45
46#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
47#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
48
49#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
50
51#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
52
53#define I915_FENCE_REG_NONE -1
54#define I915_MAX_NUM_FENCES 32
55/* 32 fences + sign bit for FENCE_REG_NONE */
56#define I915_MAX_NUM_FENCE_BITS 6
57
58typedef u32 gen6_pte_t;
59typedef u64 gen8_pte_t;
60
61#define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
62
63#define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
64#define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
65#define I915_PDES 512
66#define I915_PDE_MASK (I915_PDES - 1)
67
68/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
69#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
70#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
71#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
72#define GEN6_PTE_CACHE_LLC (2 << 1)
73#define GEN6_PTE_UNCACHED (1 << 1)
74#define GEN6_PTE_VALID REG_BIT(0)
75
76#define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
77#define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
78#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
79#define GEN6_PDE_SHIFT 22
80#define GEN6_PDE_VALID REG_BIT(0)
81#define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
82
83#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
84
85#define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
86#define BYT_PTE_WRITEABLE REG_BIT(1)
87
88#define GEN12_PPGTT_PTE_LM BIT_ULL(11)
89
90#define GEN12_GGTT_PTE_LM BIT_ULL(1)
91
92/*
93 * Cacheability Control is a 4-bit value. The low three bits are stored in bits
94 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
95 */
96#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
97 (((bits) & 0x8) << (11 - 3)))
98#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
99#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
100#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
101#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
102#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
103#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
104#define HSW_PTE_UNCACHED (0)
105#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
106#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
107
108/*
109 * GEN8 32b style address is defined as a 3 level page table:
110 * 31:30 | 29:21 | 20:12 | 11:0
111 * PDPE | PDE | PTE | offset
112 * The difference as compared to normal x86 3 level page table is the PDPEs are
113 * programmed via register.
114 *
115 * GEN8 48b style address is defined as a 4 level page table:
116 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
117 * PML4E | PDPE | PDE | PTE | offset
118 */
119#define GEN8_3LVL_PDPES 4
120
121#define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
122#define PPAT_CACHED_PDE 0 /* WB LLC */
123#define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
124#define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
125
126#define CHV_PPAT_SNOOP REG_BIT(6)
127#define GEN8_PPAT_AGE(x) ((x)<<4)
128#define GEN8_PPAT_LLCeLLC (3<<2)
129#define GEN8_PPAT_LLCELLC (2<<2)
130#define GEN8_PPAT_LLC (1<<2)
131#define GEN8_PPAT_WB (3<<0)
132#define GEN8_PPAT_WT (2<<0)
133#define GEN8_PPAT_WC (1<<0)
134#define GEN8_PPAT_UC (0<<0)
135#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
136#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
137
138#define GEN8_PDE_IPS_64K BIT(11)
139#define GEN8_PDE_PS_2M BIT(7)
140
141enum i915_cache_level;
142
143struct drm_i915_file_private;
144struct drm_i915_gem_object;
145struct i915_fence_reg;
146struct i915_vma;
147struct intel_gt;
148
149#define for_each_sgt_daddr(__dp, __iter, __sgt) \
150 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
151
152struct i915_page_table {
153 struct drm_i915_gem_object *base;
154 union {
155 atomic_t used;
156 struct i915_page_table *stash;
157 };
158};
159
160struct i915_page_directory {
161 struct i915_page_table pt;
162 spinlock_t lock;
163 void **entry;
164};
165
166#define __px_choose_expr(x, type, expr, other) \
167 __builtin_choose_expr( \
168 __builtin_types_compatible_p(typeof(x), type) || \
169 __builtin_types_compatible_p(typeof(x), const type), \
170 ({ type __x = (type)(x); expr; }), \
171 other)
172
173#define px_base(px) \
174 __px_choose_expr(px, struct drm_i915_gem_object *, __x, \
175 __px_choose_expr(px, struct i915_page_table *, __x->base, \
176 __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \
177 (void)0)))
178
179struct page *__px_page(struct drm_i915_gem_object *p);
180dma_addr_t __px_dma(struct drm_i915_gem_object *p);
181#define px_dma(px) (__px_dma(px_base(px)))
182
183void *__px_vaddr(struct drm_i915_gem_object *p);
184#define px_vaddr(px) (__px_vaddr(px_base(px)))
185
186#define px_pt(px) \
187 __px_choose_expr(px, struct i915_page_table *, __x, \
188 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
189 (void)0))
190#define px_used(px) (&px_pt(px)->used)
191
192struct i915_vm_pt_stash {
193 /* preallocated chains of page tables/directories */
194 struct i915_page_table *pt[2];
195};
196
197struct i915_vma_ops {
198 /* Map an object into an address space with the given cache flags. */
199 void (*bind_vma)(struct i915_address_space *vm,
200 struct i915_vm_pt_stash *stash,
201 struct i915_vma *vma,
202 enum i915_cache_level cache_level,
203 u32 flags);
204 /*
205 * Unmap an object from an address space. This usually consists of
206 * setting the valid PTE entries to a reserved scratch page.
207 */
208 void (*unbind_vma)(struct i915_address_space *vm,
209 struct i915_vma *vma);
210
211 int (*set_pages)(struct i915_vma *vma);
212 void (*clear_pages)(struct i915_vma *vma);
213};
214
215struct i915_address_space {
216 struct kref ref;
217 struct rcu_work rcu;
218
219 struct drm_mm mm;
220 struct intel_gt *gt;
221 struct drm_i915_private *i915;
222 struct device *dma;
223 /*
224 * Every address space belongs to a struct file - except for the global
225 * GTT that is owned by the driver (and so @file is set to NULL). In
226 * principle, no information should leak from one context to another
227 * (or between files/processes etc) unless explicitly shared by the
228 * owner. Tracking the owner is important in order to free up per-file
229 * objects along with the file, to aide resource tracking, and to
230 * assign blame.
231 */
232 struct drm_i915_file_private *file;
233 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
234 u64 reserved; /* size addr space reserved */
235
236 unsigned int bind_async_flags;
237
238 /*
239 * Each active user context has its own address space (in full-ppgtt).
240 * Since the vm may be shared between multiple contexts, we count how
241 * many contexts keep us "open". Once open hits zero, we are closed
242 * and do not allow any new attachments, and proceed to shutdown our
243 * vma and page directories.
244 */
245 atomic_t open;
246
247 struct mutex mutex; /* protects vma and our lists */
248
249 struct kref resv_ref; /* kref to keep the reservation lock alive. */
250 struct dma_resv _resv; /* reservation lock for all pd objects, and buffer pool */
251#define VM_CLASS_GGTT 0
252#define VM_CLASS_PPGTT 1
253#define VM_CLASS_DPT 2
254
255 struct drm_i915_gem_object *scratch[4];
256 /**
257 * List of vma currently bound.
258 */
259 struct list_head bound_list;
260
261 /* Global GTT */
262 bool is_ggtt:1;
263
264 /* Display page table */
265 bool is_dpt:1;
266
267 /* Some systems support read-only mappings for GGTT and/or PPGTT */
268 bool has_read_only:1;
269
270 u8 top;
271 u8 pd_shift;
272 u8 scratch_order;
273
274 struct drm_i915_gem_object *
275 (*alloc_pt_dma)(struct i915_address_space *vm, int sz);
276
277 u64 (*pte_encode)(dma_addr_t addr,
278 enum i915_cache_level level,
279 u32 flags); /* Create a valid PTE */
280#define PTE_READ_ONLY BIT(0)
281#define PTE_LM BIT(1)
282
283 void (*allocate_va_range)(struct i915_address_space *vm,
284 struct i915_vm_pt_stash *stash,
285 u64 start, u64 length);
286 void (*clear_range)(struct i915_address_space *vm,
287 u64 start, u64 length);
288 void (*insert_page)(struct i915_address_space *vm,
289 dma_addr_t addr,
290 u64 offset,
291 enum i915_cache_level cache_level,
292 u32 flags);
293 void (*insert_entries)(struct i915_address_space *vm,
294 struct i915_vma *vma,
295 enum i915_cache_level cache_level,
296 u32 flags);
297 void (*cleanup)(struct i915_address_space *vm);
298
299 struct i915_vma_ops vma_ops;
300
301 I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
302 I915_SELFTEST_DECLARE(bool scrub_64K);
303};
304
305/*
306 * The Graphics Translation Table is the way in which GEN hardware translates a
307 * Graphics Virtual Address into a Physical Address. In addition to the normal
308 * collateral associated with any va->pa translations GEN hardware also has a
309 * portion of the GTT which can be mapped by the CPU and remain both coherent
310 * and correct (in cases like swizzling). That region is referred to as GMADR in
311 * the spec.
312 */
313struct i915_ggtt {
314 struct i915_address_space vm;
315
316 struct io_mapping iomap; /* Mapping to our CPU mappable region */
317 struct resource gmadr; /* GMADR resource */
318 resource_size_t mappable_end; /* End offset that we can CPU map */
319
320 /** "Graphics Stolen Memory" holds the global PTEs */
321 void __iomem *gsm;
322 void (*invalidate)(struct i915_ggtt *ggtt);
323
324 /** PPGTT used for aliasing the PPGTT with the GTT */
325 struct i915_ppgtt *alias;
326
327 bool do_idle_maps;
328
329 int mtrr;
330
331 /** Bit 6 swizzling required for X tiling */
332 u32 bit_6_swizzle_x;
333 /** Bit 6 swizzling required for Y tiling */
334 u32 bit_6_swizzle_y;
335
336 u32 pin_bias;
337
338 unsigned int num_fences;
339 struct i915_fence_reg *fence_regs;
340 struct list_head fence_list;
341
342 /**
343 * List of all objects in gtt_space, currently mmaped by userspace.
344 * All objects within this list must also be on bound_list.
345 */
346 struct list_head userfault_list;
347
348 /* Manual runtime pm autosuspend delay for user GGTT mmaps */
349 struct intel_wakeref_auto userfault_wakeref;
350
351 struct mutex error_mutex;
352 struct drm_mm_node error_capture;
353 struct drm_mm_node uc_fw;
354};
355
356struct i915_ppgtt {
357 struct i915_address_space vm;
358
359 struct i915_page_directory *pd;
360};
361
362#define i915_is_ggtt(vm) ((vm)->is_ggtt)
363#define i915_is_dpt(vm) ((vm)->is_dpt)
364#define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm))
365
366int __must_check
367i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww);
368
369static inline bool
370i915_vm_is_4lvl(const struct i915_address_space *vm)
371{
372 return (vm->total - 1) >> 32;
373}
374
375static inline bool
376i915_vm_has_scratch_64K(struct i915_address_space *vm)
377{
378 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K);
379}
380
381static inline bool
382i915_vm_has_cache_coloring(struct i915_address_space *vm)
383{
384 return i915_is_ggtt(vm) && vm->mm.color_adjust;
385}
386
387static inline struct i915_ggtt *
388i915_vm_to_ggtt(struct i915_address_space *vm)
389{
390 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm));
391 GEM_BUG_ON(!i915_is_ggtt(vm));
392 return container_of(vm, struct i915_ggtt, vm);
393}
394
395static inline struct i915_ppgtt *
396i915_vm_to_ppgtt(struct i915_address_space *vm)
397{
398 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
399 GEM_BUG_ON(i915_is_ggtt_or_dpt(vm));
400 return container_of(vm, struct i915_ppgtt, vm);
401}
402
403static inline struct i915_address_space *
404i915_vm_get(struct i915_address_space *vm)
405{
406 kref_get(&vm->ref);
407 return vm;
408}
409
410/**
411 * i915_vm_resv_get - Obtain a reference on the vm's reservation lock
412 * @vm: The vm whose reservation lock we want to share.
413 *
414 * Return: A pointer to the vm's reservation lock.
415 */
416static inline struct dma_resv *i915_vm_resv_get(struct i915_address_space *vm)
417{
418 kref_get(&vm->resv_ref);
419 return &vm->_resv;
420}
421
422void i915_vm_release(struct kref *kref);
423
424void i915_vm_resv_release(struct kref *kref);
425
426static inline void i915_vm_put(struct i915_address_space *vm)
427{
428 kref_put(&vm->ref, i915_vm_release);
429}
430
431/**
432 * i915_vm_resv_put - Release a reference on the vm's reservation lock
433 * @resv: Pointer to a reservation lock obtained from i915_vm_resv_get()
434 */
435static inline void i915_vm_resv_put(struct i915_address_space *vm)
436{
437 kref_put(&vm->resv_ref, i915_vm_resv_release);
438}
439
440static inline struct i915_address_space *
441i915_vm_open(struct i915_address_space *vm)
442{
443 GEM_BUG_ON(!atomic_read(&vm->open));
444 atomic_inc(&vm->open);
445 return i915_vm_get(vm);
446}
447
448static inline bool
449i915_vm_tryopen(struct i915_address_space *vm)
450{
451 if (atomic_add_unless(&vm->open, 1, 0))
452 return i915_vm_get(vm);
453
454 return false;
455}
456
457void __i915_vm_close(struct i915_address_space *vm);
458
459static inline void
460i915_vm_close(struct i915_address_space *vm)
461{
462 GEM_BUG_ON(!atomic_read(&vm->open));
463 __i915_vm_close(vm);
464
465 i915_vm_put(vm);
466}
467
468void i915_address_space_init(struct i915_address_space *vm, int subclass);
469void i915_address_space_fini(struct i915_address_space *vm);
470
471static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
472{
473 const u32 mask = NUM_PTE(pde_shift) - 1;
474
475 return (address >> PAGE_SHIFT) & mask;
476}
477
478/*
479 * Helper to counts the number of PTEs within the given length. This count
480 * does not cross a page table boundary, so the max value would be
481 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
482 */
483static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
484{
485 const u64 mask = ~((1ULL << pde_shift) - 1);
486 u64 end;
487
488 GEM_BUG_ON(length == 0);
489 GEM_BUG_ON(offset_in_page(addr | length));
490
491 end = addr + length;
492
493 if ((addr & mask) != (end & mask))
494 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
495
496 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
497}
498
499static inline u32 i915_pde_index(u64 addr, u32 shift)
500{
501 return (addr >> shift) & I915_PDE_MASK;
502}
503
504static inline struct i915_page_table *
505i915_pt_entry(const struct i915_page_directory * const pd,
506 const unsigned short n)
507{
508 return pd->entry[n];
509}
510
511static inline struct i915_page_directory *
512i915_pd_entry(const struct i915_page_directory * const pdp,
513 const unsigned short n)
514{
515 return pdp->entry[n];
516}
517
518static inline dma_addr_t
519i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
520{
521 struct i915_page_table *pt = ppgtt->pd->entry[n];
522
523 return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
524}
525
526void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
527
528int i915_ggtt_probe_hw(struct drm_i915_private *i915);
529int i915_ggtt_init_hw(struct drm_i915_private *i915);
530int i915_ggtt_enable_hw(struct drm_i915_private *i915);
531void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
532void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
533int i915_init_ggtt(struct drm_i915_private *i915);
534void i915_ggtt_driver_release(struct drm_i915_private *i915);
535void i915_ggtt_driver_late_release(struct drm_i915_private *i915);
536
537static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
538{
539 return ggtt->mappable_end > 0;
540}
541
542int i915_ppgtt_init_hw(struct intel_gt *gt);
543
544struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
545
546void i915_ggtt_suspend(struct i915_ggtt *gtt);
547void i915_ggtt_resume(struct i915_ggtt *ggtt);
548
549void
550fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count);
551
552#define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))
553#define fill32_px(px, v) do { \
554 u64 v__ = lower_32_bits(v); \
555 fill_px((px), v__ << 32 | v__); \
556} while (0)
557
558int setup_scratch_page(struct i915_address_space *vm);
559void free_scratch(struct i915_address_space *vm);
560
561struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz);
562struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz);
563struct i915_page_table *alloc_pt(struct i915_address_space *vm);
564struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
565struct i915_page_directory *__alloc_pd(int npde);
566
567int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
568int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
569
570void free_px(struct i915_address_space *vm,
571 struct i915_page_table *pt, int lvl);
572#define free_pt(vm, px) free_px(vm, px, 0)
573#define free_pd(vm, px) free_px(vm, px_pt(px), 1)
574
575void
576__set_pd_entry(struct i915_page_directory * const pd,
577 const unsigned short idx,
578 struct i915_page_table *pt,
579 u64 (*encode)(const dma_addr_t, const enum i915_cache_level));
580
581#define set_pd_entry(pd, idx, to) \
582 __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode)
583
584void
585clear_pd_entry(struct i915_page_directory * const pd,
586 const unsigned short idx,
587 const struct drm_i915_gem_object * const scratch);
588
589bool
590release_pd_entry(struct i915_page_directory * const pd,
591 const unsigned short idx,
592 struct i915_page_table * const pt,
593 const struct drm_i915_gem_object * const scratch);
594void gen6_ggtt_invalidate(struct i915_ggtt *ggtt);
595
596int ggtt_set_pages(struct i915_vma *vma);
597int ppgtt_set_pages(struct i915_vma *vma);
598void clear_pages(struct i915_vma *vma);
599
600void ppgtt_bind_vma(struct i915_address_space *vm,
601 struct i915_vm_pt_stash *stash,
602 struct i915_vma *vma,
603 enum i915_cache_level cache_level,
604 u32 flags);
605void ppgtt_unbind_vma(struct i915_address_space *vm,
606 struct i915_vma *vma);
607
608void gtt_write_workarounds(struct intel_gt *gt);
609
610void setup_private_pat(struct intel_uncore *uncore);
611
612int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
613 struct i915_vm_pt_stash *stash,
614 u64 size);
615int i915_vm_map_pt_stash(struct i915_address_space *vm,
616 struct i915_vm_pt_stash *stash);
617void i915_vm_free_pt_stash(struct i915_address_space *vm,
618 struct i915_vm_pt_stash *stash);
619
620struct i915_vma *
621__vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size);
622
623struct i915_vma *
624__vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size);
625
626static inline struct sgt_dma {
627 struct scatterlist *sg;
628 dma_addr_t dma, max;
629} sgt_dma(struct i915_vma *vma) {
630 struct scatterlist *sg = vma->pages->sgl;
631 dma_addr_t addr = sg_dma_address(sg);
632
633 return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
634}
635
636#endif
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2020 Intel Corporation
4 *
5 * Please try to maintain the following order within this file unless it makes
6 * sense to do otherwise. From top to bottom:
7 * 1. typedefs
8 * 2. #defines, and macros
9 * 3. structure definitions
10 * 4. function prototypes
11 *
12 * Within each section, please try to order by generation in ascending order,
13 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
14 */
15
16#ifndef __INTEL_GTT_H__
17#define __INTEL_GTT_H__
18
19#include <linux/io-mapping.h>
20#include <linux/kref.h>
21#include <linux/mm.h>
22#include <linux/pagevec.h>
23#include <linux/scatterlist.h>
24#include <linux/workqueue.h>
25
26#include <drm/drm_mm.h>
27
28#include "gt/intel_reset.h"
29#include "i915_selftest.h"
30#include "i915_vma_types.h"
31
32#define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
33
34#if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT)
35#define DBG(...) trace_printk(__VA_ARGS__)
36#else
37#define DBG(...)
38#endif
39
40#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
41
42#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
43#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
44#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
45
46#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
47#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
48
49#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
50
51#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
52
53#define I915_FENCE_REG_NONE -1
54#define I915_MAX_NUM_FENCES 32
55/* 32 fences + sign bit for FENCE_REG_NONE */
56#define I915_MAX_NUM_FENCE_BITS 6
57
58typedef u32 gen6_pte_t;
59typedef u64 gen8_pte_t;
60
61#define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
62
63#define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
64#define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
65#define I915_PDES 512
66#define I915_PDE_MASK (I915_PDES - 1)
67
68/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
69#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
70#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
71#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
72#define GEN6_PTE_CACHE_LLC (2 << 1)
73#define GEN6_PTE_UNCACHED (1 << 1)
74#define GEN6_PTE_VALID REG_BIT(0)
75
76#define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
77#define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
78#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
79#define GEN6_PDE_SHIFT 22
80#define GEN6_PDE_VALID REG_BIT(0)
81#define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
82
83#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
84
85#define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
86#define BYT_PTE_WRITEABLE REG_BIT(1)
87
88/*
89 * Cacheability Control is a 4-bit value. The low three bits are stored in bits
90 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
91 */
92#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
93 (((bits) & 0x8) << (11 - 3)))
94#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
95#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
96#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
97#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
98#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
99#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
100#define HSW_PTE_UNCACHED (0)
101#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
102#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
103
104/*
105 * GEN8 32b style address is defined as a 3 level page table:
106 * 31:30 | 29:21 | 20:12 | 11:0
107 * PDPE | PDE | PTE | offset
108 * The difference as compared to normal x86 3 level page table is the PDPEs are
109 * programmed via register.
110 *
111 * GEN8 48b style address is defined as a 4 level page table:
112 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
113 * PML4E | PDPE | PDE | PTE | offset
114 */
115#define GEN8_3LVL_PDPES 4
116
117#define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
118#define PPAT_CACHED_PDE 0 /* WB LLC */
119#define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
120#define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
121
122#define CHV_PPAT_SNOOP REG_BIT(6)
123#define GEN8_PPAT_AGE(x) ((x)<<4)
124#define GEN8_PPAT_LLCeLLC (3<<2)
125#define GEN8_PPAT_LLCELLC (2<<2)
126#define GEN8_PPAT_LLC (1<<2)
127#define GEN8_PPAT_WB (3<<0)
128#define GEN8_PPAT_WT (2<<0)
129#define GEN8_PPAT_WC (1<<0)
130#define GEN8_PPAT_UC (0<<0)
131#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
132#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
133
134#define GEN8_PDE_IPS_64K BIT(11)
135#define GEN8_PDE_PS_2M BIT(7)
136
137struct i915_fence_reg;
138
139#define for_each_sgt_daddr(__dp, __iter, __sgt) \
140 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
141
142struct i915_page_dma {
143 struct page *page;
144 union {
145 dma_addr_t daddr;
146
147 /*
148 * For gen6/gen7 only. This is the offset in the GGTT
149 * where the page directory entries for PPGTT begin
150 */
151 u32 ggtt_offset;
152 };
153};
154
155struct i915_page_scratch {
156 struct i915_page_dma base;
157 u64 encode;
158};
159
160struct i915_page_table {
161 struct i915_page_dma base;
162 atomic_t used;
163};
164
165struct i915_page_directory {
166 struct i915_page_table pt;
167 spinlock_t lock;
168 void *entry[512];
169};
170
171#define __px_choose_expr(x, type, expr, other) \
172 __builtin_choose_expr( \
173 __builtin_types_compatible_p(typeof(x), type) || \
174 __builtin_types_compatible_p(typeof(x), const type), \
175 ({ type __x = (type)(x); expr; }), \
176 other)
177
178#define px_base(px) \
179 __px_choose_expr(px, struct i915_page_dma *, __x, \
180 __px_choose_expr(px, struct i915_page_scratch *, &__x->base, \
181 __px_choose_expr(px, struct i915_page_table *, &__x->base, \
182 __px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \
183 (void)0))))
184#define px_dma(px) (px_base(px)->daddr)
185
186#define px_pt(px) \
187 __px_choose_expr(px, struct i915_page_table *, __x, \
188 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
189 (void)0))
190#define px_used(px) (&px_pt(px)->used)
191
192enum i915_cache_level;
193
194struct drm_i915_file_private;
195struct drm_i915_gem_object;
196struct i915_vma;
197struct intel_gt;
198
199struct i915_vma_ops {
200 /* Map an object into an address space with the given cache flags. */
201 int (*bind_vma)(struct i915_address_space *vm,
202 struct i915_vma *vma,
203 enum i915_cache_level cache_level,
204 u32 flags);
205 /*
206 * Unmap an object from an address space. This usually consists of
207 * setting the valid PTE entries to a reserved scratch page.
208 */
209 void (*unbind_vma)(struct i915_address_space *vm,
210 struct i915_vma *vma);
211
212 int (*set_pages)(struct i915_vma *vma);
213 void (*clear_pages)(struct i915_vma *vma);
214};
215
216struct pagestash {
217 spinlock_t lock;
218 struct pagevec pvec;
219};
220
221void stash_init(struct pagestash *stash);
222
223struct i915_address_space {
224 struct kref ref;
225 struct rcu_work rcu;
226
227 struct drm_mm mm;
228 struct intel_gt *gt;
229 struct drm_i915_private *i915;
230 struct device *dma;
231 /*
232 * Every address space belongs to a struct file - except for the global
233 * GTT that is owned by the driver (and so @file is set to NULL). In
234 * principle, no information should leak from one context to another
235 * (or between files/processes etc) unless explicitly shared by the
236 * owner. Tracking the owner is important in order to free up per-file
237 * objects along with the file, to aide resource tracking, and to
238 * assign blame.
239 */
240 struct drm_i915_file_private *file;
241 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
242 u64 reserved; /* size addr space reserved */
243
244 unsigned int bind_async_flags;
245
246 /*
247 * Each active user context has its own address space (in full-ppgtt).
248 * Since the vm may be shared between multiple contexts, we count how
249 * many contexts keep us "open". Once open hits zero, we are closed
250 * and do not allow any new attachments, and proceed to shutdown our
251 * vma and page directories.
252 */
253 atomic_t open;
254
255 struct mutex mutex; /* protects vma and our lists */
256#define VM_CLASS_GGTT 0
257#define VM_CLASS_PPGTT 1
258
259 struct i915_page_scratch scratch[4];
260 unsigned int scratch_order;
261 unsigned int top;
262
263 /**
264 * List of vma currently bound.
265 */
266 struct list_head bound_list;
267
268 struct pagestash free_pages;
269
270 /* Global GTT */
271 bool is_ggtt:1;
272
273 /* Some systems require uncached updates of the page directories */
274 bool pt_kmap_wc:1;
275
276 /* Some systems support read-only mappings for GGTT and/or PPGTT */
277 bool has_read_only:1;
278
279 u64 (*pte_encode)(dma_addr_t addr,
280 enum i915_cache_level level,
281 u32 flags); /* Create a valid PTE */
282#define PTE_READ_ONLY BIT(0)
283
284 int (*allocate_va_range)(struct i915_address_space *vm,
285 u64 start, u64 length);
286 void (*clear_range)(struct i915_address_space *vm,
287 u64 start, u64 length);
288 void (*insert_page)(struct i915_address_space *vm,
289 dma_addr_t addr,
290 u64 offset,
291 enum i915_cache_level cache_level,
292 u32 flags);
293 void (*insert_entries)(struct i915_address_space *vm,
294 struct i915_vma *vma,
295 enum i915_cache_level cache_level,
296 u32 flags);
297 void (*cleanup)(struct i915_address_space *vm);
298
299 struct i915_vma_ops vma_ops;
300
301 I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
302 I915_SELFTEST_DECLARE(bool scrub_64K);
303};
304
305/*
306 * The Graphics Translation Table is the way in which GEN hardware translates a
307 * Graphics Virtual Address into a Physical Address. In addition to the normal
308 * collateral associated with any va->pa translations GEN hardware also has a
309 * portion of the GTT which can be mapped by the CPU and remain both coherent
310 * and correct (in cases like swizzling). That region is referred to as GMADR in
311 * the spec.
312 */
313struct i915_ggtt {
314 struct i915_address_space vm;
315
316 struct io_mapping iomap; /* Mapping to our CPU mappable region */
317 struct resource gmadr; /* GMADR resource */
318 resource_size_t mappable_end; /* End offset that we can CPU map */
319
320 /** "Graphics Stolen Memory" holds the global PTEs */
321 void __iomem *gsm;
322 void (*invalidate)(struct i915_ggtt *ggtt);
323
324 /** PPGTT used for aliasing the PPGTT with the GTT */
325 struct i915_ppgtt *alias;
326
327 bool do_idle_maps;
328
329 int mtrr;
330
331 /** Bit 6 swizzling required for X tiling */
332 u32 bit_6_swizzle_x;
333 /** Bit 6 swizzling required for Y tiling */
334 u32 bit_6_swizzle_y;
335
336 u32 pin_bias;
337
338 unsigned int num_fences;
339 struct i915_fence_reg *fence_regs;
340 struct list_head fence_list;
341
342 /**
343 * List of all objects in gtt_space, currently mmaped by userspace.
344 * All objects within this list must also be on bound_list.
345 */
346 struct list_head userfault_list;
347
348 /* Manual runtime pm autosuspend delay for user GGTT mmaps */
349 struct intel_wakeref_auto userfault_wakeref;
350
351 struct mutex error_mutex;
352 struct drm_mm_node error_capture;
353 struct drm_mm_node uc_fw;
354};
355
356struct i915_ppgtt {
357 struct i915_address_space vm;
358
359 struct i915_page_directory *pd;
360};
361
362#define i915_is_ggtt(vm) ((vm)->is_ggtt)
363
364static inline bool
365i915_vm_is_4lvl(const struct i915_address_space *vm)
366{
367 return (vm->total - 1) >> 32;
368}
369
370static inline bool
371i915_vm_has_scratch_64K(struct i915_address_space *vm)
372{
373 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K);
374}
375
376static inline bool
377i915_vm_has_cache_coloring(struct i915_address_space *vm)
378{
379 return i915_is_ggtt(vm) && vm->mm.color_adjust;
380}
381
382static inline struct i915_ggtt *
383i915_vm_to_ggtt(struct i915_address_space *vm)
384{
385 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm));
386 GEM_BUG_ON(!i915_is_ggtt(vm));
387 return container_of(vm, struct i915_ggtt, vm);
388}
389
390static inline struct i915_ppgtt *
391i915_vm_to_ppgtt(struct i915_address_space *vm)
392{
393 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
394 GEM_BUG_ON(i915_is_ggtt(vm));
395 return container_of(vm, struct i915_ppgtt, vm);
396}
397
398static inline struct i915_address_space *
399i915_vm_get(struct i915_address_space *vm)
400{
401 kref_get(&vm->ref);
402 return vm;
403}
404
405void i915_vm_release(struct kref *kref);
406
407static inline void i915_vm_put(struct i915_address_space *vm)
408{
409 kref_put(&vm->ref, i915_vm_release);
410}
411
412static inline struct i915_address_space *
413i915_vm_open(struct i915_address_space *vm)
414{
415 GEM_BUG_ON(!atomic_read(&vm->open));
416 atomic_inc(&vm->open);
417 return i915_vm_get(vm);
418}
419
420static inline bool
421i915_vm_tryopen(struct i915_address_space *vm)
422{
423 if (atomic_add_unless(&vm->open, 1, 0))
424 return i915_vm_get(vm);
425
426 return false;
427}
428
429void __i915_vm_close(struct i915_address_space *vm);
430
431static inline void
432i915_vm_close(struct i915_address_space *vm)
433{
434 GEM_BUG_ON(!atomic_read(&vm->open));
435 __i915_vm_close(vm);
436
437 i915_vm_put(vm);
438}
439
440void i915_address_space_init(struct i915_address_space *vm, int subclass);
441void i915_address_space_fini(struct i915_address_space *vm);
442
443static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
444{
445 const u32 mask = NUM_PTE(pde_shift) - 1;
446
447 return (address >> PAGE_SHIFT) & mask;
448}
449
450/*
451 * Helper to counts the number of PTEs within the given length. This count
452 * does not cross a page table boundary, so the max value would be
453 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
454 */
455static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
456{
457 const u64 mask = ~((1ULL << pde_shift) - 1);
458 u64 end;
459
460 GEM_BUG_ON(length == 0);
461 GEM_BUG_ON(offset_in_page(addr | length));
462
463 end = addr + length;
464
465 if ((addr & mask) != (end & mask))
466 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
467
468 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
469}
470
471static inline u32 i915_pde_index(u64 addr, u32 shift)
472{
473 return (addr >> shift) & I915_PDE_MASK;
474}
475
476static inline struct i915_page_table *
477i915_pt_entry(const struct i915_page_directory * const pd,
478 const unsigned short n)
479{
480 return pd->entry[n];
481}
482
483static inline struct i915_page_directory *
484i915_pd_entry(const struct i915_page_directory * const pdp,
485 const unsigned short n)
486{
487 return pdp->entry[n];
488}
489
490static inline dma_addr_t
491i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
492{
493 struct i915_page_dma *pt = ppgtt->pd->entry[n];
494
495 return px_dma(pt ?: px_base(&ppgtt->vm.scratch[ppgtt->vm.top]));
496}
497
498void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
499
500int i915_ggtt_probe_hw(struct drm_i915_private *i915);
501int i915_ggtt_init_hw(struct drm_i915_private *i915);
502int i915_ggtt_enable_hw(struct drm_i915_private *i915);
503void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
504void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
505int i915_init_ggtt(struct drm_i915_private *i915);
506void i915_ggtt_driver_release(struct drm_i915_private *i915);
507
508static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
509{
510 return ggtt->mappable_end > 0;
511}
512
513int i915_ppgtt_init_hw(struct intel_gt *gt);
514
515struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
516
517void i915_ggtt_suspend(struct i915_ggtt *gtt);
518void i915_ggtt_resume(struct i915_ggtt *ggtt);
519
520int setup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p);
521void cleanup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p);
522
523#define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
524
525void
526fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count);
527
528#define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))
529#define fill32_px(px, v) do { \
530 u64 v__ = lower_32_bits(v); \
531 fill_px((px), v__ << 32 | v__); \
532} while (0)
533
534int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp);
535void cleanup_scratch_page(struct i915_address_space *vm);
536void free_scratch(struct i915_address_space *vm);
537
538struct i915_page_table *alloc_pt(struct i915_address_space *vm);
539struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
540struct i915_page_directory *__alloc_pd(size_t sz);
541
542void free_pd(struct i915_address_space *vm, struct i915_page_dma *pd);
543
544#define free_px(vm, px) free_pd(vm, px_base(px))
545
546void
547__set_pd_entry(struct i915_page_directory * const pd,
548 const unsigned short idx,
549 struct i915_page_dma * const to,
550 u64 (*encode)(const dma_addr_t, const enum i915_cache_level));
551
552#define set_pd_entry(pd, idx, to) \
553 __set_pd_entry((pd), (idx), px_base(to), gen8_pde_encode)
554
555void
556clear_pd_entry(struct i915_page_directory * const pd,
557 const unsigned short idx,
558 const struct i915_page_scratch * const scratch);
559
560bool
561release_pd_entry(struct i915_page_directory * const pd,
562 const unsigned short idx,
563 struct i915_page_table * const pt,
564 const struct i915_page_scratch * const scratch);
565void gen6_ggtt_invalidate(struct i915_ggtt *ggtt);
566
567int ggtt_set_pages(struct i915_vma *vma);
568int ppgtt_set_pages(struct i915_vma *vma);
569void clear_pages(struct i915_vma *vma);
570
571int ppgtt_bind_vma(struct i915_address_space *vm,
572 struct i915_vma *vma,
573 enum i915_cache_level cache_level,
574 u32 flags);
575void ppgtt_unbind_vma(struct i915_address_space *vm,
576 struct i915_vma *vma);
577
578void gtt_write_workarounds(struct intel_gt *gt);
579
580void setup_private_pat(struct intel_uncore *uncore);
581
582static inline struct sgt_dma {
583 struct scatterlist *sg;
584 dma_addr_t dma, max;
585} sgt_dma(struct i915_vma *vma) {
586 struct scatterlist *sg = vma->pages->sgl;
587 dma_addr_t addr = sg_dma_address(sg);
588
589 return (struct sgt_dma){ sg, addr, addr + sg->length };
590}
591
592#endif