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1&l4_cfg { /* 0x4a000000 */
2 compatible = "ti,dra7-l4-cfg", "simple-pm-bus";
3 power-domains = <&prm_coreaon>;
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
5 clock-names = "fck";
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
9 reg-names = "ap", "la", "ia0";
10 #address-cells = <1>;
11 #size-cells = <1>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
15
16 segment@0 { /* 0x4a000000 */
17 compatible = "simple-pm-bus";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
21 <0x00000800 0x00000800 0x000800>, /* ap 1 */
22 <0x00001000 0x00001000 0x001000>, /* ap 2 */
23 <0x00002000 0x00002000 0x002000>, /* ap 3 */
24 <0x00004000 0x00004000 0x001000>, /* ap 4 */
25 <0x00005000 0x00005000 0x001000>, /* ap 5 */
26 <0x00006000 0x00006000 0x001000>, /* ap 6 */
27 <0x00008000 0x00008000 0x002000>, /* ap 7 */
28 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
29 <0x00056000 0x00056000 0x001000>, /* ap 9 */
30 <0x00057000 0x00057000 0x001000>, /* ap 10 */
31 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
32 <0x00060000 0x00060000 0x001000>, /* ap 12 */
33 <0x00080000 0x00080000 0x008000>, /* ap 13 */
34 <0x00088000 0x00088000 0x001000>, /* ap 14 */
35 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
36 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
37 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
38 <0x000da000 0x000da000 0x001000>, /* ap 18 */
39 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
40 <0x000de000 0x000de000 0x001000>, /* ap 20 */
41 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
42 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
43 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
44 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
45 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
46 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
47 <0x00090000 0x00090000 0x008000>, /* ap 59 */
48 <0x00098000 0x00098000 0x001000>; /* ap 60 */
49
50 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
51 compatible = "ti,sysc-omap4", "ti,sysc";
52 reg = <0x2000 0x4>;
53 reg-names = "rev";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges = <0x0 0x2000 0x2000>;
57
58 scm: scm@0 {
59 compatible = "ti,dra7-scm-core", "simple-bus";
60 reg = <0 0x2000>;
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges = <0 0 0x2000>;
64
65 scm_conf: scm_conf@0 {
66 compatible = "syscon", "simple-bus";
67 reg = <0x0 0x1400>;
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges = <0 0x0 0x1400>;
71
72 pbias_regulator: pbias_regulator@e00 {
73 compatible = "ti,pbias-dra7", "ti,pbias-omap";
74 reg = <0xe00 0x4>;
75 syscon = <&scm_conf>;
76 pbias_mmc_reg: pbias_mmc_omap5 {
77 regulator-name = "pbias_mmc_omap5";
78 regulator-min-microvolt = <1800000>;
79 regulator-max-microvolt = <3300000>;
80 };
81 };
82
83 phy_gmii_sel: phy-gmii-sel {
84 compatible = "ti,dra7xx-phy-gmii-sel";
85 reg = <0x554 0x4>;
86 #phy-cells = <1>;
87 };
88
89 scm_conf_clocks: clocks {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 };
93 };
94
95 dra7_pmx_core: pinmux@1400 {
96 compatible = "ti,dra7-padconf",
97 "pinctrl-single";
98 reg = <0x1400 0x0468>;
99 #address-cells = <1>;
100 #size-cells = <0>;
101 #pinctrl-cells = <1>;
102 #interrupt-cells = <1>;
103 interrupt-controller;
104 pinctrl-single,register-width = <32>;
105 pinctrl-single,function-mask = <0x3fffffff>;
106 };
107
108 scm_conf1: scm_conf@1c04 {
109 compatible = "syscon";
110 reg = <0x1c04 0x0020>;
111 #syscon-cells = <2>;
112 };
113
114 scm_conf_pcie: scm_conf@1c24 {
115 compatible = "syscon";
116 reg = <0x1c24 0x0024>;
117 };
118
119 sdma_xbar: dma-router@b78 {
120 compatible = "ti,dra7-dma-crossbar";
121 reg = <0xb78 0xfc>;
122 #dma-cells = <1>;
123 dma-requests = <205>;
124 ti,dma-safe-map = <0>;
125 dma-masters = <&sdma>;
126 };
127
128 edma_xbar: dma-router@c78 {
129 compatible = "ti,dra7-dma-crossbar";
130 reg = <0xc78 0x7c>;
131 #dma-cells = <2>;
132 dma-requests = <204>;
133 ti,dma-safe-map = <0>;
134 dma-masters = <&edma>;
135 };
136 };
137 };
138
139 target-module@5000 { /* 0x4a005000, ap 5 10.0 */
140 compatible = "ti,sysc-omap4", "ti,sysc";
141 reg = <0x5000 0x4>;
142 reg-names = "rev";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0x0 0x5000 0x1000>;
146
147 cm_core_aon: cm_core_aon@0 {
148 compatible = "ti,dra7-cm-core-aon",
149 "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0 0x2000>;
153 ranges = <0 0 0x2000>;
154
155 cm_core_aon_clocks: clocks {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 };
159
160 cm_core_aon_clockdomains: clockdomains {
161 };
162 };
163 };
164
165 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
166 compatible = "ti,sysc-omap4", "ti,sysc";
167 reg = <0x8000 0x4>;
168 reg-names = "rev";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0x8000 0x2000>;
172
173 cm_core: cm_core@0 {
174 compatible = "ti,dra7-cm-core", "simple-bus";
175 #address-cells = <1>;
176 #size-cells = <1>;
177 reg = <0 0x3000>;
178 ranges = <0 0 0x3000>;
179
180 cm_core_clocks: clocks {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 };
184
185 cm_core_clockdomains: clockdomains {
186 };
187 };
188 };
189
190 target-module@56000 { /* 0x4a056000, ap 9 02.0 */
191 compatible = "ti,sysc-omap2", "ti,sysc";
192 reg = <0x56000 0x4>,
193 <0x5602c 0x4>,
194 <0x56028 0x4>;
195 reg-names = "rev", "sysc", "syss";
196 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
197 SYSC_OMAP2_EMUFREE |
198 SYSC_OMAP2_SOFTRESET |
199 SYSC_OMAP2_AUTOIDLE)>;
200 ti,sysc-midle = <SYSC_IDLE_FORCE>,
201 <SYSC_IDLE_NO>,
202 <SYSC_IDLE_SMART>,
203 <SYSC_IDLE_SMART_WKUP>;
204 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
205 <SYSC_IDLE_NO>,
206 <SYSC_IDLE_SMART>,
207 <SYSC_IDLE_SMART_WKUP>;
208 ti,syss-mask = <1>;
209 /* Domains (P, C): core_pwrdm, dma_clkdm */
210 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
211 clock-names = "fck";
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges = <0x0 0x56000 0x1000>;
215
216 sdma: dma-controller@0 {
217 compatible = "ti,omap4430-sdma", "ti,omap-sdma";
218 reg = <0x0 0x1000>;
219 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
223 #dma-cells = <1>;
224 dma-channels = <32>;
225 dma-requests = <127>;
226 };
227 };
228
229 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
230 compatible = "ti,sysc";
231 status = "disabled";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges = <0x0 0x5e000 0x2000>;
235 };
236
237 target-module@80000 { /* 0x4a080000, ap 13 20.0 */
238 compatible = "ti,sysc-omap2", "ti,sysc";
239 reg = <0x80000 0x4>,
240 <0x80010 0x4>,
241 <0x80014 0x4>;
242 reg-names = "rev", "sysc", "syss";
243 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
244 SYSC_OMAP2_AUTOIDLE)>;
245 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
246 <SYSC_IDLE_NO>,
247 <SYSC_IDLE_SMART>;
248 ti,syss-mask = <1>;
249 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
250 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
251 clock-names = "fck";
252 #address-cells = <1>;
253 #size-cells = <1>;
254 ranges = <0x0 0x80000 0x8000>;
255
256 ocp2scp@0 {
257 compatible = "ti,omap-ocp2scp";
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges = <0 0 0x8000>;
261 reg = <0x0 0x20>;
262
263 usb2_phy1: phy@4000 {
264 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
265 reg = <0x4000 0x400>;
266 syscon-phy-power = <&scm_conf 0x300>;
267 clocks = <&usb_phy1_always_on_clk32k>,
268 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
269 clock-names = "wkupclk",
270 "refclk";
271 #phy-cells = <0>;
272 };
273
274 usb2_phy2: phy@5000 {
275 compatible = "ti,dra7x-usb2-phy2",
276 "ti,omap-usb2";
277 reg = <0x5000 0x400>;
278 syscon-phy-power = <&scm_conf 0xe74>;
279 clocks = <&usb_phy2_always_on_clk32k>,
280 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
281 clock-names = "wkupclk",
282 "refclk";
283 #phy-cells = <0>;
284 };
285
286 usb3_phy1: phy@4400 {
287 compatible = "ti,omap-usb3";
288 reg = <0x4400 0x80>,
289 <0x4800 0x64>,
290 <0x4c00 0x40>;
291 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
292 syscon-phy-power = <&scm_conf 0x370>;
293 clocks = <&usb_phy3_always_on_clk32k>,
294 <&sys_clkin1>,
295 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
296 clock-names = "wkupclk",
297 "sysclk",
298 "refclk";
299 #phy-cells = <0>;
300 };
301 };
302 };
303
304 target-module@90000 { /* 0x4a090000, ap 59 42.0 */
305 compatible = "ti,sysc-omap2", "ti,sysc";
306 reg = <0x90000 0x4>,
307 <0x90010 0x4>,
308 <0x90014 0x4>;
309 reg-names = "rev", "sysc", "syss";
310 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
311 SYSC_OMAP2_AUTOIDLE)>;
312 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
313 <SYSC_IDLE_NO>,
314 <SYSC_IDLE_SMART>;
315 ti,syss-mask = <1>;
316 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
317 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
318 clock-names = "fck";
319 #address-cells = <1>;
320 #size-cells = <1>;
321 ranges = <0x0 0x90000 0x8000>;
322
323 ocp2scp@0 {
324 compatible = "ti,omap-ocp2scp";
325 #address-cells = <1>;
326 #size-cells = <1>;
327 ranges = <0 0 0x8000>;
328 reg = <0x0 0x20>;
329
330 pcie1_phy: pciephy@4000 {
331 compatible = "ti,phy-pipe3-pcie";
332 reg = <0x4000 0x80>, /* phy_rx */
333 <0x4400 0x64>; /* phy_tx */
334 reg-names = "phy_rx", "phy_tx";
335 syscon-phy-power = <&scm_conf_pcie 0x1c>;
336 syscon-pcs = <&scm_conf_pcie 0x10>;
337 clocks = <&dpll_pcie_ref_ck>,
338 <&dpll_pcie_ref_m2ldo_ck>,
339 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
340 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
341 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
342 <&optfclk_pciephy_div>,
343 <&sys_clkin1>;
344 clock-names = "dpll_ref", "dpll_ref_m2",
345 "wkupclk", "refclk",
346 "div-clk", "phy-div", "sysclk";
347 #phy-cells = <0>;
348 };
349
350 pcie2_phy: pciephy@5000 {
351 compatible = "ti,phy-pipe3-pcie";
352 reg = <0x5000 0x80>, /* phy_rx */
353 <0x5400 0x64>; /* phy_tx */
354 reg-names = "phy_rx", "phy_tx";
355 syscon-phy-power = <&scm_conf_pcie 0x20>;
356 syscon-pcs = <&scm_conf_pcie 0x10>;
357 clocks = <&dpll_pcie_ref_ck>,
358 <&dpll_pcie_ref_m2ldo_ck>,
359 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
360 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
361 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
362 <&optfclk_pciephy_div>,
363 <&sys_clkin1>;
364 clock-names = "dpll_ref", "dpll_ref_m2",
365 "wkupclk", "refclk",
366 "div-clk", "phy-div", "sysclk";
367 #phy-cells = <0>;
368 status = "disabled";
369 };
370
371 sata_phy: phy@6000 {
372 compatible = "ti,phy-pipe3-sata";
373 reg = <0x6000 0x80>, /* phy_rx */
374 <0x6400 0x64>, /* phy_tx */
375 <0x6800 0x40>; /* pll_ctrl */
376 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
377 syscon-phy-power = <&scm_conf 0x374>;
378 clocks = <&sys_clkin1>,
379 <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
380 clock-names = "sysclk", "refclk";
381 syscon-pllreset = <&scm_conf 0x3fc>;
382 #phy-cells = <0>;
383 };
384 };
385 };
386
387 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
388 compatible = "ti,sysc";
389 status = "disabled";
390 #address-cells = <1>;
391 #size-cells = <1>;
392 ranges = <0x0 0xa0000 0x8000>;
393 };
394
395 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
396 compatible = "ti,sysc-omap4-sr", "ti,sysc";
397 reg = <0xd9038 0x4>;
398 reg-names = "sysc";
399 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
400 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
401 <SYSC_IDLE_NO>,
402 <SYSC_IDLE_SMART>,
403 <SYSC_IDLE_SMART_WKUP>;
404 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
405 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
406 clock-names = "fck";
407 #address-cells = <1>;
408 #size-cells = <1>;
409 ranges = <0x0 0xd9000 0x1000>;
410
411 /* SmartReflex child device marked reserved in TRM */
412 };
413
414 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
415 compatible = "ti,sysc-omap4-sr", "ti,sysc";
416 reg = <0xdd038 0x4>;
417 reg-names = "sysc";
418 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
419 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
420 <SYSC_IDLE_NO>,
421 <SYSC_IDLE_SMART>,
422 <SYSC_IDLE_SMART_WKUP>;
423 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
424 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
425 clock-names = "fck";
426 #address-cells = <1>;
427 #size-cells = <1>;
428 ranges = <0x0 0xdd000 0x1000>;
429
430 /* SmartReflex child device marked reserved in TRM */
431 };
432
433 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
434 compatible = "ti,sysc";
435 status = "disabled";
436 #address-cells = <1>;
437 #size-cells = <1>;
438 ranges = <0x0 0xe0000 0x1000>;
439 };
440
441 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
442 compatible = "ti,sysc-omap4", "ti,sysc";
443 reg = <0xf4000 0x4>,
444 <0xf4010 0x4>;
445 reg-names = "rev", "sysc";
446 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
447 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
448 <SYSC_IDLE_NO>,
449 <SYSC_IDLE_SMART>;
450 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
451 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
452 clock-names = "fck";
453 #address-cells = <1>;
454 #size-cells = <1>;
455 ranges = <0x0 0xf4000 0x1000>;
456
457 mailbox1: mailbox@0 {
458 compatible = "ti,omap4-mailbox";
459 reg = <0x0 0x200>;
460 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
463 #mbox-cells = <1>;
464 ti,mbox-num-users = <3>;
465 ti,mbox-num-fifos = <8>;
466 status = "disabled";
467 };
468 };
469
470 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
471 compatible = "ti,sysc-omap2", "ti,sysc";
472 reg = <0xf6000 0x4>,
473 <0xf6010 0x4>,
474 <0xf6014 0x4>;
475 reg-names = "rev", "sysc", "syss";
476 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
477 SYSC_OMAP2_SOFTRESET |
478 SYSC_OMAP2_AUTOIDLE)>;
479 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
480 <SYSC_IDLE_NO>,
481 <SYSC_IDLE_SMART>;
482 ti,syss-mask = <1>;
483 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
484 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
485 clock-names = "fck";
486 #address-cells = <1>;
487 #size-cells = <1>;
488 ranges = <0x0 0xf6000 0x1000>;
489
490 hwspinlock: spinlock@0 {
491 compatible = "ti,omap4-hwspinlock";
492 reg = <0x0 0x1000>;
493 #hwlock-cells = <1>;
494 };
495 };
496 };
497
498 segment@100000 { /* 0x4a100000 */
499 compatible = "simple-pm-bus";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
503 <0x00003000 0x00103000 0x001000>, /* ap 28 */
504 <0x00008000 0x00108000 0x001000>, /* ap 29 */
505 <0x00009000 0x00109000 0x001000>, /* ap 30 */
506 <0x00040000 0x00140000 0x010000>, /* ap 31 */
507 <0x00050000 0x00150000 0x001000>, /* ap 32 */
508 <0x00051000 0x00151000 0x001000>, /* ap 33 */
509 <0x00052000 0x00152000 0x001000>, /* ap 34 */
510 <0x00053000 0x00153000 0x001000>, /* ap 35 */
511 <0x00054000 0x00154000 0x001000>, /* ap 36 */
512 <0x00055000 0x00155000 0x001000>, /* ap 37 */
513 <0x00056000 0x00156000 0x001000>, /* ap 38 */
514 <0x00057000 0x00157000 0x001000>, /* ap 39 */
515 <0x00058000 0x00158000 0x001000>, /* ap 40 */
516 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
517 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
518 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
519 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
520 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
521 <0x00060000 0x00160000 0x001000>, /* ap 48 */
522 <0x00061000 0x00161000 0x001000>, /* ap 49 */
523 <0x00062000 0x00162000 0x001000>, /* ap 50 */
524 <0x00063000 0x00163000 0x001000>, /* ap 51 */
525 <0x00064000 0x00164000 0x001000>, /* ap 52 */
526 <0x00065000 0x00165000 0x001000>, /* ap 53 */
527 <0x00066000 0x00166000 0x001000>, /* ap 54 */
528 <0x00067000 0x00167000 0x001000>, /* ap 55 */
529 <0x00068000 0x00168000 0x001000>, /* ap 56 */
530 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
531 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
532 <0x00071000 0x00171000 0x001000>, /* ap 61 */
533 <0x00072000 0x00172000 0x001000>, /* ap 62 */
534 <0x00073000 0x00173000 0x001000>, /* ap 63 */
535 <0x00074000 0x00174000 0x001000>, /* ap 64 */
536 <0x00075000 0x00175000 0x001000>, /* ap 65 */
537 <0x00076000 0x00176000 0x001000>, /* ap 66 */
538 <0x00077000 0x00177000 0x001000>, /* ap 67 */
539 <0x00078000 0x00178000 0x001000>, /* ap 68 */
540 <0x00081000 0x00181000 0x001000>, /* ap 69 */
541 <0x00082000 0x00182000 0x001000>, /* ap 70 */
542 <0x00083000 0x00183000 0x001000>, /* ap 71 */
543 <0x00084000 0x00184000 0x001000>, /* ap 72 */
544 <0x00085000 0x00185000 0x001000>, /* ap 73 */
545 <0x00086000 0x00186000 0x001000>, /* ap 74 */
546 <0x00087000 0x00187000 0x001000>, /* ap 75 */
547 <0x00088000 0x00188000 0x001000>, /* ap 76 */
548 <0x00069000 0x00169000 0x001000>, /* ap 103 */
549 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
550 <0x00079000 0x00179000 0x001000>, /* ap 105 */
551 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
552 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
553 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
554 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
555 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
556 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
557 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
558 <0x00059000 0x00159000 0x001000>, /* ap 125 */
559 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
560
561 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
562 compatible = "ti,sysc";
563 status = "disabled";
564 #address-cells = <1>;
565 #size-cells = <1>;
566 ranges = <0x0 0x2000 0x1000>;
567 };
568
569 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
570 compatible = "ti,sysc";
571 status = "disabled";
572 #address-cells = <1>;
573 #size-cells = <1>;
574 ranges = <0x0 0x8000 0x1000>;
575 };
576
577 target-module@40000 { /* 0x4a140000, ap 31 06.0 */
578 compatible = "ti,sysc-omap4", "ti,sysc";
579 reg = <0x400fc 4>,
580 <0x41100 4>;
581 reg-names = "rev", "sysc";
582 ti,sysc-midle = <SYSC_IDLE_FORCE>,
583 <SYSC_IDLE_NO>,
584 <SYSC_IDLE_SMART>;
585 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
586 <SYSC_IDLE_NO>,
587 <SYSC_IDLE_SMART>,
588 <SYSC_IDLE_SMART_WKUP>;
589 power-domains = <&prm_l3init>;
590 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>;
591 clock-names = "fck";
592 #size-cells = <1>;
593 #address-cells = <1>;
594 ranges = <0x0 0x40000 0x10000>;
595
596 sata: sata@0 {
597 compatible = "snps,dwc-ahci";
598 reg = <0 0x1100>, <0x1100 0x8>;
599 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
600 phys = <&sata_phy>;
601 phy-names = "sata-phy";
602 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
603 ports-implemented = <0x1>;
604 };
605 };
606
607 target-module@51000 { /* 0x4a151000, ap 33 50.0 */
608 compatible = "ti,sysc";
609 status = "disabled";
610 #address-cells = <1>;
611 #size-cells = <1>;
612 ranges = <0x0 0x51000 0x1000>;
613 };
614
615 target-module@53000 { /* 0x4a153000, ap 35 54.0 */
616 compatible = "ti,sysc";
617 status = "disabled";
618 #address-cells = <1>;
619 #size-cells = <1>;
620 ranges = <0x0 0x53000 0x1000>;
621 };
622
623 target-module@55000 { /* 0x4a155000, ap 37 46.0 */
624 compatible = "ti,sysc";
625 status = "disabled";
626 #address-cells = <1>;
627 #size-cells = <1>;
628 ranges = <0x0 0x55000 0x1000>;
629 };
630
631 target-module@57000 { /* 0x4a157000, ap 39 58.0 */
632 compatible = "ti,sysc";
633 status = "disabled";
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges = <0x0 0x57000 0x1000>;
637 };
638
639 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
640 compatible = "ti,sysc";
641 status = "disabled";
642 #address-cells = <1>;
643 #size-cells = <1>;
644 ranges = <0x0 0x59000 0x1000>;
645 };
646
647 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
648 compatible = "ti,sysc";
649 status = "disabled";
650 #address-cells = <1>;
651 #size-cells = <1>;
652 ranges = <0x0 0x5b000 0x1000>;
653 };
654
655 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
656 compatible = "ti,sysc";
657 status = "disabled";
658 #address-cells = <1>;
659 #size-cells = <1>;
660 ranges = <0x0 0x5d000 0x1000>;
661 };
662
663 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
664 compatible = "ti,sysc";
665 status = "disabled";
666 #address-cells = <1>;
667 #size-cells = <1>;
668 ranges = <0x0 0x5f000 0x1000>;
669 };
670
671 target-module@61000 { /* 0x4a161000, ap 49 32.0 */
672 compatible = "ti,sysc";
673 status = "disabled";
674 #address-cells = <1>;
675 #size-cells = <1>;
676 ranges = <0x0 0x61000 0x1000>;
677 };
678
679 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
680 compatible = "ti,sysc";
681 status = "disabled";
682 #address-cells = <1>;
683 #size-cells = <1>;
684 ranges = <0x0 0x63000 0x1000>;
685 };
686
687 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
688 compatible = "ti,sysc";
689 status = "disabled";
690 #address-cells = <1>;
691 #size-cells = <1>;
692 ranges = <0x0 0x65000 0x1000>;
693 };
694
695 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
696 compatible = "ti,sysc";
697 status = "disabled";
698 #address-cells = <1>;
699 #size-cells = <1>;
700 ranges = <0x0 0x67000 0x1000>;
701 };
702
703 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
704 compatible = "ti,sysc";
705 status = "disabled";
706 #address-cells = <1>;
707 #size-cells = <1>;
708 ranges = <0x0 0x69000 0x1000>;
709 };
710
711 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
712 compatible = "ti,sysc";
713 status = "disabled";
714 #address-cells = <1>;
715 #size-cells = <1>;
716 ranges = <0x0 0x6b000 0x1000>;
717 };
718
719 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
720 compatible = "ti,sysc";
721 status = "disabled";
722 #address-cells = <1>;
723 #size-cells = <1>;
724 ranges = <0x0 0x6d000 0x1000>;
725 };
726
727 target-module@71000 { /* 0x4a171000, ap 61 48.0 */
728 compatible = "ti,sysc";
729 status = "disabled";
730 #address-cells = <1>;
731 #size-cells = <1>;
732 ranges = <0x0 0x71000 0x1000>;
733 };
734
735 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
736 compatible = "ti,sysc";
737 status = "disabled";
738 #address-cells = <1>;
739 #size-cells = <1>;
740 ranges = <0x0 0x73000 0x1000>;
741 };
742
743 target-module@75000 { /* 0x4a175000, ap 65 64.0 */
744 compatible = "ti,sysc";
745 status = "disabled";
746 #address-cells = <1>;
747 #size-cells = <1>;
748 ranges = <0x0 0x75000 0x1000>;
749 };
750
751 target-module@77000 { /* 0x4a177000, ap 67 66.0 */
752 compatible = "ti,sysc";
753 status = "disabled";
754 #address-cells = <1>;
755 #size-cells = <1>;
756 ranges = <0x0 0x77000 0x1000>;
757 };
758
759 target-module@79000 { /* 0x4a179000, ap 105 34.0 */
760 compatible = "ti,sysc";
761 status = "disabled";
762 #address-cells = <1>;
763 #size-cells = <1>;
764 ranges = <0x0 0x79000 0x1000>;
765 };
766
767 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
768 compatible = "ti,sysc";
769 status = "disabled";
770 #address-cells = <1>;
771 #size-cells = <1>;
772 ranges = <0x0 0x7b000 0x1000>;
773 };
774
775 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
776 compatible = "ti,sysc";
777 status = "disabled";
778 #address-cells = <1>;
779 #size-cells = <1>;
780 ranges = <0x0 0x7d000 0x1000>;
781 };
782
783 target-module@81000 { /* 0x4a181000, ap 69 26.0 */
784 compatible = "ti,sysc";
785 status = "disabled";
786 #address-cells = <1>;
787 #size-cells = <1>;
788 ranges = <0x0 0x81000 0x1000>;
789 };
790
791 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
792 compatible = "ti,sysc";
793 status = "disabled";
794 #address-cells = <1>;
795 #size-cells = <1>;
796 ranges = <0x0 0x83000 0x1000>;
797 };
798
799 target-module@85000 { /* 0x4a185000, ap 73 36.0 */
800 compatible = "ti,sysc";
801 status = "disabled";
802 #address-cells = <1>;
803 #size-cells = <1>;
804 ranges = <0x0 0x85000 0x1000>;
805 };
806
807 target-module@87000 { /* 0x4a187000, ap 75 74.0 */
808 compatible = "ti,sysc";
809 status = "disabled";
810 #address-cells = <1>;
811 #size-cells = <1>;
812 ranges = <0x0 0x87000 0x1000>;
813 };
814 };
815
816 segment@200000 { /* 0x4a200000 */
817 compatible = "simple-pm-bus";
818 #address-cells = <1>;
819 #size-cells = <1>;
820 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
821 <0x00019000 0x00219000 0x001000>, /* ap 44 */
822 <0x00000000 0x00200000 0x001000>, /* ap 77 */
823 <0x00001000 0x00201000 0x001000>, /* ap 78 */
824 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
825 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
826 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
827 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
828 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
829 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
830 <0x00010000 0x00210000 0x001000>, /* ap 85 */
831 <0x00011000 0x00211000 0x001000>, /* ap 86 */
832 <0x00012000 0x00212000 0x001000>, /* ap 87 */
833 <0x00013000 0x00213000 0x001000>, /* ap 88 */
834 <0x00014000 0x00214000 0x001000>, /* ap 89 */
835 <0x00015000 0x00215000 0x001000>, /* ap 90 */
836 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
837 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
838 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
839 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
840 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
841 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
842 <0x00020000 0x00220000 0x001000>, /* ap 97 */
843 <0x00021000 0x00221000 0x001000>, /* ap 98 */
844 <0x00024000 0x00224000 0x001000>, /* ap 99 */
845 <0x00025000 0x00225000 0x001000>, /* ap 100 */
846 <0x00026000 0x00226000 0x001000>, /* ap 101 */
847 <0x00027000 0x00227000 0x001000>, /* ap 102 */
848 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
849 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
850 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
851 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
852 <0x00030000 0x00230000 0x001000>, /* ap 113 */
853 <0x00031000 0x00231000 0x001000>, /* ap 114 */
854 <0x00032000 0x00232000 0x001000>, /* ap 115 */
855 <0x00033000 0x00233000 0x001000>, /* ap 116 */
856 <0x00034000 0x00234000 0x001000>, /* ap 117 */
857 <0x00035000 0x00235000 0x001000>, /* ap 118 */
858 <0x00036000 0x00236000 0x001000>, /* ap 119 */
859 <0x00037000 0x00237000 0x001000>, /* ap 120 */
860 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
861 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
862
863 target-module@0 { /* 0x4a200000, ap 77 3e.0 */
864 compatible = "ti,sysc";
865 status = "disabled";
866 #address-cells = <1>;
867 #size-cells = <1>;
868 ranges = <0x0 0x0 0x1000>;
869 };
870
871 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
872 compatible = "ti,sysc";
873 status = "disabled";
874 #address-cells = <1>;
875 #size-cells = <1>;
876 ranges = <0x0 0xa000 0x1000>;
877 };
878
879 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
880 compatible = "ti,sysc";
881 status = "disabled";
882 #address-cells = <1>;
883 #size-cells = <1>;
884 ranges = <0x0 0xc000 0x1000>;
885 };
886
887 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
888 compatible = "ti,sysc";
889 status = "disabled";
890 #address-cells = <1>;
891 #size-cells = <1>;
892 ranges = <0x0 0xe000 0x1000>;
893 };
894
895 target-module@10000 { /* 0x4a210000, ap 85 14.0 */
896 compatible = "ti,sysc";
897 status = "disabled";
898 #address-cells = <1>;
899 #size-cells = <1>;
900 ranges = <0x0 0x10000 0x1000>;
901 };
902
903 target-module@12000 { /* 0x4a212000, ap 87 16.0 */
904 compatible = "ti,sysc";
905 status = "disabled";
906 #address-cells = <1>;
907 #size-cells = <1>;
908 ranges = <0x0 0x12000 0x1000>;
909 };
910
911 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
912 compatible = "ti,sysc";
913 status = "disabled";
914 #address-cells = <1>;
915 #size-cells = <1>;
916 ranges = <0x0 0x14000 0x1000>;
917 };
918
919 target-module@18000 { /* 0x4a218000, ap 43 12.0 */
920 compatible = "ti,sysc";
921 status = "disabled";
922 #address-cells = <1>;
923 #size-cells = <1>;
924 ranges = <0x0 0x18000 0x1000>;
925 };
926
927 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
928 compatible = "ti,sysc";
929 status = "disabled";
930 #address-cells = <1>;
931 #size-cells = <1>;
932 ranges = <0x0 0x1a000 0x1000>;
933 };
934
935 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
936 compatible = "ti,sysc";
937 status = "disabled";
938 #address-cells = <1>;
939 #size-cells = <1>;
940 ranges = <0x0 0x1c000 0x1000>;
941 };
942
943 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
944 compatible = "ti,sysc";
945 status = "disabled";
946 #address-cells = <1>;
947 #size-cells = <1>;
948 ranges = <0x0 0x1e000 0x1000>;
949 };
950
951 target-module@20000 { /* 0x4a220000, ap 97 24.0 */
952 compatible = "ti,sysc";
953 status = "disabled";
954 #address-cells = <1>;
955 #size-cells = <1>;
956 ranges = <0x0 0x20000 0x1000>;
957 };
958
959 target-module@24000 { /* 0x4a224000, ap 99 44.0 */
960 compatible = "ti,sysc";
961 status = "disabled";
962 #address-cells = <1>;
963 #size-cells = <1>;
964 ranges = <0x0 0x24000 0x1000>;
965 };
966
967 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
968 compatible = "ti,sysc";
969 status = "disabled";
970 #address-cells = <1>;
971 #size-cells = <1>;
972 ranges = <0x0 0x26000 0x1000>;
973 };
974
975 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
976 compatible = "ti,sysc";
977 status = "disabled";
978 #address-cells = <1>;
979 #size-cells = <1>;
980 ranges = <0x0 0x2a000 0x1000>;
981 };
982
983 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
984 compatible = "ti,sysc";
985 status = "disabled";
986 #address-cells = <1>;
987 #size-cells = <1>;
988 ranges = <0x0 0x2c000 0x1000>;
989 };
990
991 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
992 compatible = "ti,sysc";
993 status = "disabled";
994 #address-cells = <1>;
995 #size-cells = <1>;
996 ranges = <0x0 0x2e000 0x1000>;
997 };
998
999 target-module@30000 { /* 0x4a230000, ap 113 70.0 */
1000 compatible = "ti,sysc";
1001 status = "disabled";
1002 #address-cells = <1>;
1003 #size-cells = <1>;
1004 ranges = <0x0 0x30000 0x1000>;
1005 };
1006
1007 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
1008 compatible = "ti,sysc";
1009 status = "disabled";
1010 #address-cells = <1>;
1011 #size-cells = <1>;
1012 ranges = <0x0 0x32000 0x1000>;
1013 };
1014
1015 target-module@34000 { /* 0x4a234000, ap 117 76.1 */
1016 compatible = "ti,sysc";
1017 status = "disabled";
1018 #address-cells = <1>;
1019 #size-cells = <1>;
1020 ranges = <0x0 0x34000 0x1000>;
1021 };
1022
1023 target-module@36000 { /* 0x4a236000, ap 119 62.0 */
1024 compatible = "ti,sysc";
1025 status = "disabled";
1026 #address-cells = <1>;
1027 #size-cells = <1>;
1028 ranges = <0x0 0x36000 0x1000>;
1029 };
1030 };
1031};
1032
1033&l4_per1 { /* 0x48000000 */
1034 compatible = "ti,dra7-l4-per1", "simple-pm-bus";
1035 power-domains = <&prm_l4per>;
1036 clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>;
1037 clock-names = "fck";
1038 reg = <0x48000000 0x800>,
1039 <0x48000800 0x800>,
1040 <0x48001000 0x400>,
1041 <0x48001400 0x400>,
1042 <0x48001800 0x400>,
1043 <0x48001c00 0x400>;
1044 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1045 #address-cells = <1>;
1046 #size-cells = <1>;
1047 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1048 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1049
1050 segment@0 { /* 0x48000000 */
1051 compatible = "simple-pm-bus";
1052 #address-cells = <1>;
1053 #size-cells = <1>;
1054 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1055 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1056 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1057 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1058 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1059 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1060 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1061 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1062 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1063 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1064 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1065 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1066 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1067 <0x00055000 0x00055000 0x001000>, /* ap 13 */
1068 <0x00056000 0x00056000 0x001000>, /* ap 14 */
1069 <0x00057000 0x00057000 0x001000>, /* ap 15 */
1070 <0x00058000 0x00058000 0x001000>, /* ap 16 */
1071 <0x00059000 0x00059000 0x001000>, /* ap 17 */
1072 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
1073 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
1074 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
1075 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
1076 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
1077 <0x00060000 0x00060000 0x001000>, /* ap 23 */
1078 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
1079 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
1080 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1081 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1082 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1083 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1084 <0x00070000 0x00070000 0x001000>, /* ap 30 */
1085 <0x00071000 0x00071000 0x001000>, /* ap 31 */
1086 <0x00072000 0x00072000 0x001000>, /* ap 32 */
1087 <0x00073000 0x00073000 0x001000>, /* ap 33 */
1088 <0x00061000 0x00061000 0x001000>, /* ap 34 */
1089 <0x00053000 0x00053000 0x001000>, /* ap 35 */
1090 <0x00054000 0x00054000 0x001000>, /* ap 36 */
1091 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1092 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1093 <0x00078000 0x00078000 0x001000>, /* ap 39 */
1094 <0x00079000 0x00079000 0x001000>, /* ap 40 */
1095 <0x00086000 0x00086000 0x001000>, /* ap 41 */
1096 <0x00087000 0x00087000 0x001000>, /* ap 42 */
1097 <0x00088000 0x00088000 0x001000>, /* ap 43 */
1098 <0x00089000 0x00089000 0x001000>, /* ap 44 */
1099 <0x00051000 0x00051000 0x001000>, /* ap 45 */
1100 <0x00052000 0x00052000 0x001000>, /* ap 46 */
1101 <0x00098000 0x00098000 0x001000>, /* ap 47 */
1102 <0x00099000 0x00099000 0x001000>, /* ap 48 */
1103 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1104 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1105 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1106 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1107 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1108 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1109 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1110 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1111 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1112 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1113 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1114 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1115 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1116 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1117 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1118 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1119 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1120 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1121 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1122 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1123 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1124 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1125 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1126 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1127 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1128 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1129 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1130 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1131 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1132 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1133 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1134 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1135 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1136 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1137 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1138 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1139
1140 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1141 compatible = "ti,sysc-omap2", "ti,sysc";
1142 reg = <0x20050 0x4>,
1143 <0x20054 0x4>,
1144 <0x20058 0x4>;
1145 reg-names = "rev", "sysc", "syss";
1146 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1147 SYSC_OMAP2_SOFTRESET |
1148 SYSC_OMAP2_AUTOIDLE)>;
1149 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1150 <SYSC_IDLE_NO>,
1151 <SYSC_IDLE_SMART>,
1152 <SYSC_IDLE_SMART_WKUP>;
1153 ti,syss-mask = <1>;
1154 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1155 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1156 clock-names = "fck";
1157 #address-cells = <1>;
1158 #size-cells = <1>;
1159 ranges = <0x0 0x20000 0x1000>;
1160
1161 uart3: serial@0 {
1162 compatible = "ti,dra742-uart";
1163 reg = <0x0 0x100>;
1164 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1165 clock-frequency = <48000000>;
1166 status = "disabled";
1167 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1168 dma-names = "tx", "rx";
1169 };
1170 };
1171
1172 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1173 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1174 reg = <0x32000 0x4>,
1175 <0x32010 0x4>;
1176 reg-names = "rev", "sysc";
1177 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1178 SYSC_OMAP4_SOFTRESET)>;
1179 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1180 <SYSC_IDLE_NO>,
1181 <SYSC_IDLE_SMART>,
1182 <SYSC_IDLE_SMART_WKUP>;
1183 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1184 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1185 clock-names = "fck";
1186 #address-cells = <1>;
1187 #size-cells = <1>;
1188 ranges = <0x0 0x32000 0x1000>;
1189
1190 timer2: timer@0 {
1191 compatible = "ti,omap5430-timer";
1192 reg = <0x0 0x80>;
1193 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>;
1194 clock-names = "fck", "timer_sys_ck";
1195 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1196 };
1197 };
1198
1199 timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */
1200 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1201 reg = <0x34000 0x4>,
1202 <0x34010 0x4>;
1203 reg-names = "rev", "sysc";
1204 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1205 SYSC_OMAP4_SOFTRESET)>;
1206 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1207 <SYSC_IDLE_NO>,
1208 <SYSC_IDLE_SMART>,
1209 <SYSC_IDLE_SMART_WKUP>;
1210 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1211 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1212 clock-names = "fck";
1213 #address-cells = <1>;
1214 #size-cells = <1>;
1215 ranges = <0x0 0x34000 0x1000>;
1216
1217 timer3: timer@0 {
1218 compatible = "ti,omap5430-timer";
1219 reg = <0x0 0x80>;
1220 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>;
1221 clock-names = "fck", "timer_sys_ck";
1222 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1223 };
1224 };
1225
1226 timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1227 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1228 reg = <0x36000 0x4>,
1229 <0x36010 0x4>;
1230 reg-names = "rev", "sysc";
1231 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1232 SYSC_OMAP4_SOFTRESET)>;
1233 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1234 <SYSC_IDLE_NO>,
1235 <SYSC_IDLE_SMART>,
1236 <SYSC_IDLE_SMART_WKUP>;
1237 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1238 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1239 clock-names = "fck";
1240 #address-cells = <1>;
1241 #size-cells = <1>;
1242 ranges = <0x0 0x36000 0x1000>;
1243
1244 timer4: timer@0 {
1245 compatible = "ti,omap5430-timer";
1246 reg = <0x0 0x80>;
1247 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>;
1248 clock-names = "fck", "timer_sys_ck";
1249 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1250 };
1251 };
1252
1253 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1254 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1255 reg = <0x3e000 0x4>,
1256 <0x3e010 0x4>;
1257 reg-names = "rev", "sysc";
1258 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1259 SYSC_OMAP4_SOFTRESET)>;
1260 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1261 <SYSC_IDLE_NO>,
1262 <SYSC_IDLE_SMART>,
1263 <SYSC_IDLE_SMART_WKUP>;
1264 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1265 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1266 clock-names = "fck";
1267 #address-cells = <1>;
1268 #size-cells = <1>;
1269 ranges = <0x0 0x3e000 0x1000>;
1270
1271 timer9: timer@0 {
1272 compatible = "ti,omap5430-timer";
1273 reg = <0x0 0x80>;
1274 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>;
1275 clock-names = "fck", "timer_sys_ck";
1276 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1277 };
1278 };
1279
1280 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1281 compatible = "ti,sysc-omap2", "ti,sysc";
1282 reg = <0x51000 0x4>,
1283 <0x51010 0x4>,
1284 <0x51114 0x4>;
1285 reg-names = "rev", "sysc", "syss";
1286 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1287 SYSC_OMAP2_SOFTRESET |
1288 SYSC_OMAP2_AUTOIDLE)>;
1289 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1290 <SYSC_IDLE_NO>,
1291 <SYSC_IDLE_SMART>,
1292 <SYSC_IDLE_SMART_WKUP>;
1293 ti,syss-mask = <1>;
1294 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1295 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1296 <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1297 clock-names = "fck", "dbclk";
1298 #address-cells = <1>;
1299 #size-cells = <1>;
1300 ranges = <0x0 0x51000 0x1000>;
1301
1302 gpio7: gpio@0 {
1303 compatible = "ti,omap4-gpio";
1304 reg = <0x0 0x200>;
1305 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1306 gpio-controller;
1307 #gpio-cells = <2>;
1308 interrupt-controller;
1309 #interrupt-cells = <2>;
1310 };
1311 };
1312
1313 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1314 compatible = "ti,sysc-omap2", "ti,sysc";
1315 reg = <0x53000 0x4>,
1316 <0x53010 0x4>,
1317 <0x53114 0x4>;
1318 reg-names = "rev", "sysc", "syss";
1319 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1320 SYSC_OMAP2_SOFTRESET |
1321 SYSC_OMAP2_AUTOIDLE)>;
1322 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1323 <SYSC_IDLE_NO>,
1324 <SYSC_IDLE_SMART>,
1325 <SYSC_IDLE_SMART_WKUP>;
1326 ti,syss-mask = <1>;
1327 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1328 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1329 <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1330 clock-names = "fck", "dbclk";
1331 #address-cells = <1>;
1332 #size-cells = <1>;
1333 ranges = <0x0 0x53000 0x1000>;
1334
1335 gpio8: gpio@0 {
1336 compatible = "ti,omap4-gpio";
1337 reg = <0x0 0x200>;
1338 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1339 gpio-controller;
1340 #gpio-cells = <2>;
1341 interrupt-controller;
1342 #interrupt-cells = <2>;
1343 };
1344 };
1345
1346 gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1347 compatible = "ti,sysc-omap2", "ti,sysc";
1348 reg = <0x55000 0x4>,
1349 <0x55010 0x4>,
1350 <0x55114 0x4>;
1351 reg-names = "rev", "sysc", "syss";
1352 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1353 SYSC_OMAP2_SOFTRESET |
1354 SYSC_OMAP2_AUTOIDLE)>;
1355 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1356 <SYSC_IDLE_NO>,
1357 <SYSC_IDLE_SMART>,
1358 <SYSC_IDLE_SMART_WKUP>;
1359 ti,syss-mask = <1>;
1360 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1361 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1362 <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1363 clock-names = "fck", "dbclk";
1364 #address-cells = <1>;
1365 #size-cells = <1>;
1366 ranges = <0x0 0x55000 0x1000>;
1367
1368 gpio2: gpio@0 {
1369 compatible = "ti,omap4-gpio";
1370 reg = <0x0 0x200>;
1371 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1372 gpio-controller;
1373 #gpio-cells = <2>;
1374 interrupt-controller;
1375 #interrupt-cells = <2>;
1376 };
1377 };
1378
1379 gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */
1380 compatible = "ti,sysc-omap2", "ti,sysc";
1381 reg = <0x57000 0x4>,
1382 <0x57010 0x4>,
1383 <0x57114 0x4>;
1384 reg-names = "rev", "sysc", "syss";
1385 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1386 SYSC_OMAP2_SOFTRESET |
1387 SYSC_OMAP2_AUTOIDLE)>;
1388 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1389 <SYSC_IDLE_NO>,
1390 <SYSC_IDLE_SMART>,
1391 <SYSC_IDLE_SMART_WKUP>;
1392 ti,syss-mask = <1>;
1393 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1394 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1395 <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1396 clock-names = "fck", "dbclk";
1397 #address-cells = <1>;
1398 #size-cells = <1>;
1399 ranges = <0x0 0x57000 0x1000>;
1400
1401 gpio3: gpio@0 {
1402 compatible = "ti,omap4-gpio";
1403 reg = <0x0 0x200>;
1404 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1405 gpio-controller;
1406 #gpio-cells = <2>;
1407 interrupt-controller;
1408 #interrupt-cells = <2>;
1409 };
1410 };
1411
1412 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1413 compatible = "ti,sysc-omap2", "ti,sysc";
1414 reg = <0x59000 0x4>,
1415 <0x59010 0x4>,
1416 <0x59114 0x4>;
1417 reg-names = "rev", "sysc", "syss";
1418 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1419 SYSC_OMAP2_SOFTRESET |
1420 SYSC_OMAP2_AUTOIDLE)>;
1421 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1422 <SYSC_IDLE_NO>,
1423 <SYSC_IDLE_SMART>,
1424 <SYSC_IDLE_SMART_WKUP>;
1425 ti,syss-mask = <1>;
1426 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1427 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1428 <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1429 clock-names = "fck", "dbclk";
1430 #address-cells = <1>;
1431 #size-cells = <1>;
1432 ranges = <0x0 0x59000 0x1000>;
1433
1434 gpio4: gpio@0 {
1435 compatible = "ti,omap4-gpio";
1436 reg = <0x0 0x200>;
1437 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1438 gpio-controller;
1439 #gpio-cells = <2>;
1440 interrupt-controller;
1441 #interrupt-cells = <2>;
1442 };
1443 };
1444
1445 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1446 compatible = "ti,sysc-omap2", "ti,sysc";
1447 reg = <0x5b000 0x4>,
1448 <0x5b010 0x4>,
1449 <0x5b114 0x4>;
1450 reg-names = "rev", "sysc", "syss";
1451 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1452 SYSC_OMAP2_SOFTRESET |
1453 SYSC_OMAP2_AUTOIDLE)>;
1454 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1455 <SYSC_IDLE_NO>,
1456 <SYSC_IDLE_SMART>,
1457 <SYSC_IDLE_SMART_WKUP>;
1458 ti,syss-mask = <1>;
1459 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1460 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1461 <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1462 clock-names = "fck", "dbclk";
1463 #address-cells = <1>;
1464 #size-cells = <1>;
1465 ranges = <0x0 0x5b000 0x1000>;
1466
1467 gpio5: gpio@0 {
1468 compatible = "ti,omap4-gpio";
1469 reg = <0x0 0x200>;
1470 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1471 gpio-controller;
1472 #gpio-cells = <2>;
1473 interrupt-controller;
1474 #interrupt-cells = <2>;
1475 };
1476 };
1477
1478 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1479 compatible = "ti,sysc-omap2", "ti,sysc";
1480 reg = <0x5d000 0x4>,
1481 <0x5d010 0x4>,
1482 <0x5d114 0x4>;
1483 reg-names = "rev", "sysc", "syss";
1484 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1485 SYSC_OMAP2_SOFTRESET |
1486 SYSC_OMAP2_AUTOIDLE)>;
1487 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1488 <SYSC_IDLE_NO>,
1489 <SYSC_IDLE_SMART>,
1490 <SYSC_IDLE_SMART_WKUP>;
1491 ti,syss-mask = <1>;
1492 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1493 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1494 <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1495 clock-names = "fck", "dbclk";
1496 #address-cells = <1>;
1497 #size-cells = <1>;
1498 ranges = <0x0 0x5d000 0x1000>;
1499
1500 gpio6: gpio@0 {
1501 compatible = "ti,omap4-gpio";
1502 reg = <0x0 0x200>;
1503 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1504 gpio-controller;
1505 #gpio-cells = <2>;
1506 interrupt-controller;
1507 #interrupt-cells = <2>;
1508 };
1509 };
1510
1511 target-module@60000 { /* 0x48060000, ap 23 32.0 */
1512 compatible = "ti,sysc-omap2", "ti,sysc";
1513 reg = <0x60000 0x8>,
1514 <0x60010 0x8>,
1515 <0x60090 0x8>;
1516 reg-names = "rev", "sysc", "syss";
1517 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1518 SYSC_OMAP2_ENAWAKEUP |
1519 SYSC_OMAP2_SOFTRESET |
1520 SYSC_OMAP2_AUTOIDLE)>;
1521 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1522 <SYSC_IDLE_NO>,
1523 <SYSC_IDLE_SMART>,
1524 <SYSC_IDLE_SMART_WKUP>;
1525 ti,syss-mask = <1>;
1526 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1527 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1528 clock-names = "fck";
1529 #address-cells = <1>;
1530 #size-cells = <1>;
1531 ranges = <0x0 0x60000 0x1000>;
1532
1533 i2c3: i2c@0 {
1534 compatible = "ti,omap4-i2c";
1535 reg = <0x0 0x100>;
1536 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1537 #address-cells = <1>;
1538 #size-cells = <0>;
1539 status = "disabled";
1540 };
1541 };
1542
1543 target-module@66000 { /* 0x48066000, ap 63 14.0 */
1544 compatible = "ti,sysc-omap2", "ti,sysc";
1545 reg = <0x66050 0x4>,
1546 <0x66054 0x4>,
1547 <0x66058 0x4>;
1548 reg-names = "rev", "sysc", "syss";
1549 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1550 SYSC_OMAP2_SOFTRESET |
1551 SYSC_OMAP2_AUTOIDLE)>;
1552 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1553 <SYSC_IDLE_NO>,
1554 <SYSC_IDLE_SMART>,
1555 <SYSC_IDLE_SMART_WKUP>;
1556 ti,syss-mask = <1>;
1557 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1558 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1559 clock-names = "fck";
1560 #address-cells = <1>;
1561 #size-cells = <1>;
1562 ranges = <0x0 0x66000 0x1000>;
1563
1564 uart5: serial@0 {
1565 compatible = "ti,dra742-uart";
1566 reg = <0x0 0x100>;
1567 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1568 clock-frequency = <48000000>;
1569 status = "disabled";
1570 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1571 dma-names = "tx", "rx";
1572 };
1573 };
1574
1575 target-module@68000 { /* 0x48068000, ap 53 1c.0 */
1576 compatible = "ti,sysc-omap2", "ti,sysc";
1577 reg = <0x68050 0x4>,
1578 <0x68054 0x4>,
1579 <0x68058 0x4>;
1580 reg-names = "rev", "sysc", "syss";
1581 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1582 SYSC_OMAP2_SOFTRESET |
1583 SYSC_OMAP2_AUTOIDLE)>;
1584 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1585 <SYSC_IDLE_NO>,
1586 <SYSC_IDLE_SMART>,
1587 <SYSC_IDLE_SMART_WKUP>;
1588 ti,syss-mask = <1>;
1589 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1590 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1591 clock-names = "fck";
1592 #address-cells = <1>;
1593 #size-cells = <1>;
1594 ranges = <0x0 0x68000 0x1000>;
1595
1596 uart6: serial@0 {
1597 compatible = "ti,dra742-uart";
1598 reg = <0x0 0x100>;
1599 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1600 clock-frequency = <48000000>;
1601 status = "disabled";
1602 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1603 dma-names = "tx", "rx";
1604 };
1605 };
1606
1607 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
1608 compatible = "ti,sysc-omap2", "ti,sysc";
1609 reg = <0x6a050 0x4>,
1610 <0x6a054 0x4>,
1611 <0x6a058 0x4>;
1612 reg-names = "rev", "sysc", "syss";
1613 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1614 SYSC_OMAP2_SOFTRESET |
1615 SYSC_OMAP2_AUTOIDLE)>;
1616 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1617 <SYSC_IDLE_NO>,
1618 <SYSC_IDLE_SMART>,
1619 <SYSC_IDLE_SMART_WKUP>;
1620 ti,syss-mask = <1>;
1621 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1622 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1623 clock-names = "fck";
1624 #address-cells = <1>;
1625 #size-cells = <1>;
1626 ranges = <0x0 0x6a000 0x1000>;
1627
1628 uart1: serial@0 {
1629 compatible = "ti,dra742-uart";
1630 reg = <0x0 0x100>;
1631 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1632 clock-frequency = <48000000>;
1633 status = "disabled";
1634 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1635 dma-names = "tx", "rx";
1636 };
1637 };
1638
1639 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
1640 compatible = "ti,sysc-omap2", "ti,sysc";
1641 reg = <0x6c050 0x4>,
1642 <0x6c054 0x4>,
1643 <0x6c058 0x4>;
1644 reg-names = "rev", "sysc", "syss";
1645 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1646 SYSC_OMAP2_SOFTRESET |
1647 SYSC_OMAP2_AUTOIDLE)>;
1648 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1649 <SYSC_IDLE_NO>,
1650 <SYSC_IDLE_SMART>,
1651 <SYSC_IDLE_SMART_WKUP>;
1652 ti,syss-mask = <1>;
1653 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1654 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1655 clock-names = "fck";
1656 #address-cells = <1>;
1657 #size-cells = <1>;
1658 ranges = <0x0 0x6c000 0x1000>;
1659
1660 uart2: serial@0 {
1661 compatible = "ti,dra742-uart";
1662 reg = <0x0 0x100>;
1663 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1664 clock-frequency = <48000000>;
1665 status = "disabled";
1666 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1667 dma-names = "tx", "rx";
1668 };
1669 };
1670
1671 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
1672 compatible = "ti,sysc-omap2", "ti,sysc";
1673 reg = <0x6e050 0x4>,
1674 <0x6e054 0x4>,
1675 <0x6e058 0x4>;
1676 reg-names = "rev", "sysc", "syss";
1677 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1678 SYSC_OMAP2_SOFTRESET |
1679 SYSC_OMAP2_AUTOIDLE)>;
1680 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1681 <SYSC_IDLE_NO>,
1682 <SYSC_IDLE_SMART>,
1683 <SYSC_IDLE_SMART_WKUP>;
1684 ti,syss-mask = <1>;
1685 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1686 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1687 clock-names = "fck";
1688 #address-cells = <1>;
1689 #size-cells = <1>;
1690 ranges = <0x0 0x6e000 0x1000>;
1691
1692 uart4: serial@0 {
1693 compatible = "ti,dra742-uart";
1694 reg = <0x0 0x100>;
1695 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1696 clock-frequency = <48000000>;
1697 status = "disabled";
1698 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1699 dma-names = "tx", "rx";
1700 };
1701 };
1702
1703 target-module@70000 { /* 0x48070000, ap 30 22.0 */
1704 compatible = "ti,sysc-omap2", "ti,sysc";
1705 reg = <0x70000 0x8>,
1706 <0x70010 0x8>,
1707 <0x70090 0x8>;
1708 reg-names = "rev", "sysc", "syss";
1709 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1710 SYSC_OMAP2_ENAWAKEUP |
1711 SYSC_OMAP2_SOFTRESET |
1712 SYSC_OMAP2_AUTOIDLE)>;
1713 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1714 <SYSC_IDLE_NO>,
1715 <SYSC_IDLE_SMART>,
1716 <SYSC_IDLE_SMART_WKUP>;
1717 ti,syss-mask = <1>;
1718 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1719 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1720 clock-names = "fck";
1721 #address-cells = <1>;
1722 #size-cells = <1>;
1723 ranges = <0x0 0x70000 0x1000>;
1724
1725 i2c1: i2c@0 {
1726 compatible = "ti,omap4-i2c";
1727 reg = <0x0 0x100>;
1728 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1729 #address-cells = <1>;
1730 #size-cells = <0>;
1731 status = "disabled";
1732 };
1733 };
1734
1735 target-module@72000 { /* 0x48072000, ap 32 2a.0 */
1736 compatible = "ti,sysc-omap2", "ti,sysc";
1737 reg = <0x72000 0x8>,
1738 <0x72010 0x8>,
1739 <0x72090 0x8>;
1740 reg-names = "rev", "sysc", "syss";
1741 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1742 SYSC_OMAP2_ENAWAKEUP |
1743 SYSC_OMAP2_SOFTRESET |
1744 SYSC_OMAP2_AUTOIDLE)>;
1745 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1746 <SYSC_IDLE_NO>,
1747 <SYSC_IDLE_SMART>,
1748 <SYSC_IDLE_SMART_WKUP>;
1749 ti,syss-mask = <1>;
1750 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1751 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1752 clock-names = "fck";
1753 #address-cells = <1>;
1754 #size-cells = <1>;
1755 ranges = <0x0 0x72000 0x1000>;
1756
1757 i2c2: i2c@0 {
1758 compatible = "ti,omap4-i2c";
1759 reg = <0x0 0x100>;
1760 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1761 #address-cells = <1>;
1762 #size-cells = <0>;
1763 status = "disabled";
1764 };
1765 };
1766
1767 target-module@78000 { /* 0x48078000, ap 39 0a.0 */
1768 compatible = "ti,sysc-omap2", "ti,sysc";
1769 reg = <0x78000 0x4>,
1770 <0x78010 0x4>,
1771 <0x78014 0x4>;
1772 reg-names = "rev", "sysc", "syss";
1773 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1774 SYSC_OMAP2_SOFTRESET |
1775 SYSC_OMAP2_AUTOIDLE)>;
1776 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1777 <SYSC_IDLE_NO>,
1778 <SYSC_IDLE_SMART>,
1779 <SYSC_IDLE_SMART_WKUP>;
1780 ti,syss-mask = <1>;
1781 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1782 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1783 clock-names = "fck";
1784 #address-cells = <1>;
1785 #size-cells = <1>;
1786 ranges = <0x0 0x78000 0x1000>;
1787
1788 elm: elm@0 {
1789 compatible = "ti,am3352-elm";
1790 reg = <0x0 0xfc0>; /* device IO registers */
1791 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1792 status = "disabled";
1793 };
1794 };
1795
1796 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
1797 compatible = "ti,sysc-omap2", "ti,sysc";
1798 reg = <0x7a000 0x8>,
1799 <0x7a010 0x8>,
1800 <0x7a090 0x8>;
1801 reg-names = "rev", "sysc", "syss";
1802 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1803 SYSC_OMAP2_ENAWAKEUP |
1804 SYSC_OMAP2_SOFTRESET |
1805 SYSC_OMAP2_AUTOIDLE)>;
1806 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1807 <SYSC_IDLE_NO>,
1808 <SYSC_IDLE_SMART>,
1809 <SYSC_IDLE_SMART_WKUP>;
1810 ti,syss-mask = <1>;
1811 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1812 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1813 clock-names = "fck";
1814 #address-cells = <1>;
1815 #size-cells = <1>;
1816 ranges = <0x0 0x7a000 0x1000>;
1817
1818 i2c4: i2c@0 {
1819 compatible = "ti,omap4-i2c";
1820 reg = <0x0 0x100>;
1821 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1822 #address-cells = <1>;
1823 #size-cells = <0>;
1824 status = "disabled";
1825 };
1826 };
1827
1828 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
1829 compatible = "ti,sysc-omap2", "ti,sysc";
1830 reg = <0x7c000 0x8>,
1831 <0x7c010 0x8>,
1832 <0x7c090 0x8>;
1833 reg-names = "rev", "sysc", "syss";
1834 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1835 SYSC_OMAP2_ENAWAKEUP |
1836 SYSC_OMAP2_SOFTRESET |
1837 SYSC_OMAP2_AUTOIDLE)>;
1838 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1839 <SYSC_IDLE_NO>,
1840 <SYSC_IDLE_SMART>,
1841 <SYSC_IDLE_SMART_WKUP>;
1842 ti,syss-mask = <1>;
1843 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1844 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1845 clock-names = "fck";
1846 #address-cells = <1>;
1847 #size-cells = <1>;
1848 ranges = <0x0 0x7c000 0x1000>;
1849
1850 i2c5: i2c@0 {
1851 compatible = "ti,omap4-i2c";
1852 reg = <0x0 0x100>;
1853 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1854 #address-cells = <1>;
1855 #size-cells = <0>;
1856 status = "disabled";
1857 };
1858 };
1859
1860 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1861 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1862 reg = <0x86000 0x4>,
1863 <0x86010 0x4>;
1864 reg-names = "rev", "sysc";
1865 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1866 SYSC_OMAP4_SOFTRESET)>;
1867 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1868 <SYSC_IDLE_NO>,
1869 <SYSC_IDLE_SMART>,
1870 <SYSC_IDLE_SMART_WKUP>;
1871 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1872 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1873 clock-names = "fck";
1874 #address-cells = <1>;
1875 #size-cells = <1>;
1876 ranges = <0x0 0x86000 0x1000>;
1877
1878 timer10: timer@0 {
1879 compatible = "ti,omap5430-timer";
1880 reg = <0x0 0x80>;
1881 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>;
1882 clock-names = "fck", "timer_sys_ck";
1883 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1884 };
1885 };
1886
1887 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1888 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1889 reg = <0x88000 0x4>,
1890 <0x88010 0x4>;
1891 reg-names = "rev", "sysc";
1892 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1893 SYSC_OMAP4_SOFTRESET)>;
1894 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1895 <SYSC_IDLE_NO>,
1896 <SYSC_IDLE_SMART>,
1897 <SYSC_IDLE_SMART_WKUP>;
1898 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1899 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1900 clock-names = "fck";
1901 #address-cells = <1>;
1902 #size-cells = <1>;
1903 ranges = <0x0 0x88000 0x1000>;
1904
1905 timer11: timer@0 {
1906 compatible = "ti,omap5430-timer";
1907 reg = <0x0 0x80>;
1908 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>;
1909 clock-names = "fck", "timer_sys_ck";
1910 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1911 };
1912 };
1913
1914 target-module@90000 { /* 0x48090000, ap 55 12.0 */
1915 compatible = "ti,sysc-omap2", "ti,sysc";
1916 reg = <0x91fe0 0x4>,
1917 <0x91fe4 0x4>;
1918 reg-names = "rev", "sysc";
1919 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1920 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1921 <SYSC_IDLE_NO>;
1922 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1923 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1924 clock-names = "fck";
1925 #address-cells = <1>;
1926 #size-cells = <1>;
1927 ranges = <0x0 0x90000 0x2000>;
1928
1929 rng: rng@0 {
1930 compatible = "ti,omap4-rng";
1931 reg = <0x0 0x2000>;
1932 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1933 clocks = <&l3_iclk_div>;
1934 clock-names = "fck";
1935 };
1936 };
1937
1938 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1939 compatible = "ti,sysc-omap4", "ti,sysc";
1940 reg = <0x98000 0x4>,
1941 <0x98010 0x4>;
1942 reg-names = "rev", "sysc";
1943 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1944 SYSC_OMAP4_SOFTRESET)>;
1945 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1946 <SYSC_IDLE_NO>,
1947 <SYSC_IDLE_SMART>,
1948 <SYSC_IDLE_SMART_WKUP>;
1949 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1950 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1951 clock-names = "fck";
1952 #address-cells = <1>;
1953 #size-cells = <1>;
1954 ranges = <0x0 0x98000 0x1000>;
1955
1956 mcspi1: spi@0 {
1957 compatible = "ti,omap4-mcspi";
1958 reg = <0x0 0x200>;
1959 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1960 #address-cells = <1>;
1961 #size-cells = <0>;
1962 ti,spi-num-cs = <4>;
1963 dmas = <&sdma_xbar 35>,
1964 <&sdma_xbar 36>,
1965 <&sdma_xbar 37>,
1966 <&sdma_xbar 38>,
1967 <&sdma_xbar 39>,
1968 <&sdma_xbar 40>,
1969 <&sdma_xbar 41>,
1970 <&sdma_xbar 42>;
1971 dma-names = "tx0", "rx0", "tx1", "rx1",
1972 "tx2", "rx2", "tx3", "rx3";
1973 status = "disabled";
1974 };
1975 };
1976
1977 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1978 compatible = "ti,sysc-omap4", "ti,sysc";
1979 reg = <0x9a000 0x4>,
1980 <0x9a010 0x4>;
1981 reg-names = "rev", "sysc";
1982 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1983 SYSC_OMAP4_SOFTRESET)>;
1984 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1985 <SYSC_IDLE_NO>,
1986 <SYSC_IDLE_SMART>,
1987 <SYSC_IDLE_SMART_WKUP>;
1988 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1989 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1990 clock-names = "fck";
1991 #address-cells = <1>;
1992 #size-cells = <1>;
1993 ranges = <0x0 0x9a000 0x1000>;
1994
1995 mcspi2: spi@0 {
1996 compatible = "ti,omap4-mcspi";
1997 reg = <0x0 0x200>;
1998 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cells = <1>;
2000 #size-cells = <0>;
2001 ti,spi-num-cs = <2>;
2002 dmas = <&sdma_xbar 43>,
2003 <&sdma_xbar 44>,
2004 <&sdma_xbar 45>,
2005 <&sdma_xbar 46>;
2006 dma-names = "tx0", "rx0", "tx1", "rx1";
2007 status = "disabled";
2008 };
2009 };
2010
2011 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
2012 compatible = "ti,sysc-omap4", "ti,sysc";
2013 reg = <0x9c000 0x4>,
2014 <0x9c010 0x4>;
2015 reg-names = "rev", "sysc";
2016 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2017 SYSC_OMAP4_SOFTRESET)>;
2018 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2019 <SYSC_IDLE_NO>,
2020 <SYSC_IDLE_SMART>,
2021 <SYSC_IDLE_SMART_WKUP>;
2022 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2023 <SYSC_IDLE_NO>,
2024 <SYSC_IDLE_SMART>,
2025 <SYSC_IDLE_SMART_WKUP>;
2026 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2027 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2028 clock-names = "fck";
2029 #address-cells = <1>;
2030 #size-cells = <1>;
2031 ranges = <0x0 0x9c000 0x1000>;
2032
2033 mmc1: mmc@0 {
2034 compatible = "ti,dra7-sdhci";
2035 reg = <0x0 0x400>;
2036 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2037 status = "disabled";
2038 pbias-supply = <&pbias_mmc_reg>;
2039 max-frequency = <192000000>;
2040 mmc-ddr-1_8v;
2041 mmc-ddr-3_3v;
2042 };
2043 };
2044
2045 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
2046 compatible = "ti,sysc";
2047 status = "disabled";
2048 #address-cells = <1>;
2049 #size-cells = <1>;
2050 ranges = <0x0 0xa2000 0x1000>;
2051 };
2052
2053 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
2054 compatible = "ti,sysc";
2055 status = "disabled";
2056 #address-cells = <1>;
2057 #size-cells = <1>;
2058 ranges = <0x00000000 0x000a4000 0x00001000>,
2059 <0x00001000 0x000a5000 0x00001000>;
2060 };
2061
2062 des_target: target-module@a5000 { /* 0x480a5000 */
2063 compatible = "ti,sysc-omap2", "ti,sysc";
2064 reg = <0xa5030 0x4>,
2065 <0xa5034 0x4>,
2066 <0xa5038 0x4>;
2067 reg-names = "rev", "sysc", "syss";
2068 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2069 SYSC_OMAP2_AUTOIDLE)>;
2070 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2071 <SYSC_IDLE_NO>,
2072 <SYSC_IDLE_SMART>,
2073 <SYSC_IDLE_SMART_WKUP>;
2074 ti,syss-mask = <1>;
2075 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
2076 clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
2077 clock-names = "fck";
2078 #address-cells = <1>;
2079 #size-cells = <1>;
2080 ranges = <0 0xa5000 0x00001000>;
2081
2082 des: des@0 {
2083 compatible = "ti,omap4-des";
2084 reg = <0 0xa0>;
2085 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2086 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2087 dma-names = "tx", "rx";
2088 clocks = <&l3_iclk_div>;
2089 clock-names = "fck";
2090 };
2091 };
2092
2093 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
2094 compatible = "ti,sysc";
2095 status = "disabled";
2096 #address-cells = <1>;
2097 #size-cells = <1>;
2098 ranges = <0x0 0xa8000 0x4000>;
2099 };
2100
2101 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
2102 compatible = "ti,sysc-omap4", "ti,sysc";
2103 reg = <0xad000 0x4>,
2104 <0xad010 0x4>;
2105 reg-names = "rev", "sysc";
2106 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2107 SYSC_OMAP4_SOFTRESET)>;
2108 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2109 <SYSC_IDLE_NO>,
2110 <SYSC_IDLE_SMART>,
2111 <SYSC_IDLE_SMART_WKUP>;
2112 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2113 <SYSC_IDLE_NO>,
2114 <SYSC_IDLE_SMART>,
2115 <SYSC_IDLE_SMART_WKUP>;
2116 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2117 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2118 clock-names = "fck";
2119 #address-cells = <1>;
2120 #size-cells = <1>;
2121 ranges = <0x0 0xad000 0x1000>;
2122
2123 mmc3: mmc@0 {
2124 compatible = "ti,dra7-sdhci";
2125 reg = <0x0 0x400>;
2126 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2127 status = "disabled";
2128 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2129 max-frequency = <64000000>;
2130 /* SDMA is not supported */
2131 sdhci-caps-mask = <0x0 0x400000>;
2132 };
2133 };
2134
2135 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
2136 compatible = "ti,sysc-omap2", "ti,sysc";
2137 reg = <0xb2000 0x4>,
2138 <0xb2014 0x4>,
2139 <0xb2018 0x4>;
2140 reg-names = "rev", "sysc", "syss";
2141 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2142 SYSC_OMAP2_AUTOIDLE)>;
2143 ti,syss-mask = <1>;
2144 ti,no-reset-on-init;
2145 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2146 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2147 clock-names = "fck";
2148 #address-cells = <1>;
2149 #size-cells = <1>;
2150 ranges = <0x0 0xb2000 0x1000>;
2151
2152 hdqw1w: 1w@0 {
2153 compatible = "ti,omap3-1w";
2154 reg = <0x0 0x1000>;
2155 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2156 };
2157 };
2158
2159 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
2160 compatible = "ti,sysc-omap4", "ti,sysc";
2161 reg = <0xb4000 0x4>,
2162 <0xb4010 0x4>;
2163 reg-names = "rev", "sysc";
2164 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2165 SYSC_OMAP4_SOFTRESET)>;
2166 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2167 <SYSC_IDLE_NO>,
2168 <SYSC_IDLE_SMART>,
2169 <SYSC_IDLE_SMART_WKUP>;
2170 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2171 <SYSC_IDLE_NO>,
2172 <SYSC_IDLE_SMART>,
2173 <SYSC_IDLE_SMART_WKUP>;
2174 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2175 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2176 clock-names = "fck";
2177 #address-cells = <1>;
2178 #size-cells = <1>;
2179 ranges = <0x0 0xb4000 0x1000>;
2180
2181 mmc2: mmc@0 {
2182 compatible = "ti,dra7-sdhci";
2183 reg = <0x0 0x400>;
2184 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2185 status = "disabled";
2186 max-frequency = <192000000>;
2187 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2188 sdhci-caps-mask = <0x7 0x0>;
2189 mmc-hs200-1_8v;
2190 mmc-ddr-1_8v;
2191 mmc-ddr-3_3v;
2192 };
2193 };
2194
2195 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
2196 compatible = "ti,sysc-omap4", "ti,sysc";
2197 reg = <0xb8000 0x4>,
2198 <0xb8010 0x4>;
2199 reg-names = "rev", "sysc";
2200 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2201 SYSC_OMAP4_SOFTRESET)>;
2202 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2203 <SYSC_IDLE_NO>,
2204 <SYSC_IDLE_SMART>,
2205 <SYSC_IDLE_SMART_WKUP>;
2206 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2207 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2208 clock-names = "fck";
2209 #address-cells = <1>;
2210 #size-cells = <1>;
2211 ranges = <0x0 0xb8000 0x1000>;
2212
2213 mcspi3: spi@0 {
2214 compatible = "ti,omap4-mcspi";
2215 reg = <0x0 0x200>;
2216 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2217 #address-cells = <1>;
2218 #size-cells = <0>;
2219 ti,spi-num-cs = <2>;
2220 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2221 dma-names = "tx0", "rx0";
2222 status = "disabled";
2223 };
2224 };
2225
2226 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2227 compatible = "ti,sysc-omap4", "ti,sysc";
2228 reg = <0xba000 0x4>,
2229 <0xba010 0x4>;
2230 reg-names = "rev", "sysc";
2231 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2232 SYSC_OMAP4_SOFTRESET)>;
2233 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2234 <SYSC_IDLE_NO>,
2235 <SYSC_IDLE_SMART>,
2236 <SYSC_IDLE_SMART_WKUP>;
2237 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2238 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2239 clock-names = "fck";
2240 #address-cells = <1>;
2241 #size-cells = <1>;
2242 ranges = <0x0 0xba000 0x1000>;
2243
2244 mcspi4: spi@0 {
2245 compatible = "ti,omap4-mcspi";
2246 reg = <0x0 0x200>;
2247 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2248 #address-cells = <1>;
2249 #size-cells = <0>;
2250 ti,spi-num-cs = <1>;
2251 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2252 dma-names = "tx0", "rx0";
2253 status = "disabled";
2254 };
2255 };
2256
2257 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2258 compatible = "ti,sysc-omap4", "ti,sysc";
2259 reg = <0xd1000 0x4>,
2260 <0xd1010 0x4>;
2261 reg-names = "rev", "sysc";
2262 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2263 SYSC_OMAP4_SOFTRESET)>;
2264 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2265 <SYSC_IDLE_NO>,
2266 <SYSC_IDLE_SMART>,
2267 <SYSC_IDLE_SMART_WKUP>;
2268 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2269 <SYSC_IDLE_NO>,
2270 <SYSC_IDLE_SMART>,
2271 <SYSC_IDLE_SMART_WKUP>;
2272 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2273 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2274 clock-names = "fck";
2275 #address-cells = <1>;
2276 #size-cells = <1>;
2277 ranges = <0x0 0xd1000 0x1000>;
2278
2279 mmc4: mmc@0 {
2280 compatible = "ti,dra7-sdhci";
2281 reg = <0x0 0x400>;
2282 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2283 status = "disabled";
2284 max-frequency = <192000000>;
2285 /* SDMA is not supported */
2286 sdhci-caps-mask = <0x0 0x400000>;
2287 };
2288 };
2289
2290 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2291 compatible = "ti,sysc";
2292 status = "disabled";
2293 #address-cells = <1>;
2294 #size-cells = <1>;
2295 ranges = <0x0 0xd5000 0x1000>;
2296 };
2297 };
2298
2299 segment@200000 { /* 0x48200000 */
2300 compatible = "simple-pm-bus";
2301 #address-cells = <1>;
2302 #size-cells = <1>;
2303 };
2304};
2305
2306&l4_per2 { /* 0x48400000 */
2307 compatible = "ti,dra7-l4-per2", "simple-pm-bus";
2308 power-domains = <&prm_l4per>;
2309 clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>;
2310 clock-names = "fck";
2311 reg = <0x48400000 0x800>,
2312 <0x48400800 0x800>,
2313 <0x48401000 0x400>,
2314 <0x48401400 0x400>,
2315 <0x48401800 0x400>;
2316 reg-names = "ap", "la", "ia0", "ia1", "ia2";
2317 #address-cells = <1>;
2318 #size-cells = <1>;
2319 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
2320 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2321 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2322 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2323 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2324 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2325 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2326 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2327 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2328
2329 segment@0 { /* 0x48400000 */
2330 compatible = "simple-pm-bus";
2331 #address-cells = <1>;
2332 #size-cells = <1>;
2333 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2334 <0x00001000 0x00001000 0x000400>, /* ap 1 */
2335 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2336 <0x00084000 0x00084000 0x004000>, /* ap 3 */
2337 <0x00001400 0x00001400 0x000400>, /* ap 4 */
2338 <0x00001800 0x00001800 0x000400>, /* ap 5 */
2339 <0x00088000 0x00088000 0x001000>, /* ap 6 */
2340 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */
2341 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */
2342 <0x00060000 0x00060000 0x002000>, /* ap 9 */
2343 <0x00062000 0x00062000 0x001000>, /* ap 10 */
2344 <0x00064000 0x00064000 0x002000>, /* ap 11 */
2345 <0x00066000 0x00066000 0x001000>, /* ap 12 */
2346 <0x00068000 0x00068000 0x002000>, /* ap 13 */
2347 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */
2348 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */
2349 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */
2350 <0x00036000 0x00036000 0x001000>, /* ap 17 */
2351 <0x00037000 0x00037000 0x001000>, /* ap 18 */
2352 <0x00070000 0x00070000 0x002000>, /* ap 19 */
2353 <0x00072000 0x00072000 0x001000>, /* ap 20 */
2354 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */
2355 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */
2356 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
2357 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */
2358 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */
2359 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */
2360 <0x00040000 0x00040000 0x001000>, /* ap 27 */
2361 <0x00041000 0x00041000 0x001000>, /* ap 28 */
2362 <0x00042000 0x00042000 0x001000>, /* ap 29 */
2363 <0x00043000 0x00043000 0x001000>, /* ap 30 */
2364 <0x00080000 0x00080000 0x002000>, /* ap 31 */
2365 <0x00082000 0x00082000 0x001000>, /* ap 32 */
2366 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */
2367 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */
2368 <0x00074000 0x00074000 0x002000>, /* ap 35 */
2369 <0x00076000 0x00076000 0x001000>, /* ap 36 */
2370 <0x00050000 0x00050000 0x001000>, /* ap 37 */
2371 <0x00051000 0x00051000 0x001000>, /* ap 38 */
2372 <0x00078000 0x00078000 0x002000>, /* ap 39 */
2373 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */
2374 <0x00054000 0x00054000 0x001000>, /* ap 41 */
2375 <0x00055000 0x00055000 0x001000>, /* ap 42 */
2376 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */
2377 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */
2378 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */
2379 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */
2380 <0x00020000 0x00020000 0x001000>, /* ap 47 */
2381 <0x00021000 0x00021000 0x001000>, /* ap 48 */
2382 <0x00022000 0x00022000 0x001000>, /* ap 49 */
2383 <0x00023000 0x00023000 0x001000>, /* ap 50 */
2384 <0x00024000 0x00024000 0x001000>, /* ap 51 */
2385 <0x00025000 0x00025000 0x001000>, /* ap 52 */
2386 <0x00046000 0x00046000 0x001000>, /* ap 53 */
2387 <0x00047000 0x00047000 0x001000>, /* ap 54 */
2388 <0x00048000 0x00048000 0x001000>, /* ap 55 */
2389 <0x00049000 0x00049000 0x001000>, /* ap 56 */
2390 <0x00058000 0x00058000 0x002000>, /* ap 57 */
2391 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */
2392 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */
2393 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */
2394 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */
2395 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */
2396 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2397 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2398 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2399 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2400 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2401 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2402 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2403 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2404
2405 target-module@20000 { /* 0x48420000, ap 47 02.0 */
2406 compatible = "ti,sysc-omap2", "ti,sysc";
2407 reg = <0x20050 0x4>,
2408 <0x20054 0x4>,
2409 <0x20058 0x4>;
2410 reg-names = "rev", "sysc", "syss";
2411 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2412 SYSC_OMAP2_SOFTRESET |
2413 SYSC_OMAP2_AUTOIDLE)>;
2414 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2415 <SYSC_IDLE_NO>,
2416 <SYSC_IDLE_SMART>,
2417 <SYSC_IDLE_SMART_WKUP>;
2418 ti,syss-mask = <1>;
2419 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2420 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2421 clock-names = "fck";
2422 #address-cells = <1>;
2423 #size-cells = <1>;
2424 ranges = <0x0 0x20000 0x1000>;
2425
2426 uart7: serial@0 {
2427 compatible = "ti,dra742-uart";
2428 reg = <0x0 0x100>;
2429 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2430 clock-frequency = <48000000>;
2431 status = "disabled";
2432 };
2433 };
2434
2435 target-module@22000 { /* 0x48422000, ap 49 0a.0 */
2436 compatible = "ti,sysc-omap2", "ti,sysc";
2437 reg = <0x22050 0x4>,
2438 <0x22054 0x4>,
2439 <0x22058 0x4>;
2440 reg-names = "rev", "sysc", "syss";
2441 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2442 SYSC_OMAP2_SOFTRESET |
2443 SYSC_OMAP2_AUTOIDLE)>;
2444 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2445 <SYSC_IDLE_NO>,
2446 <SYSC_IDLE_SMART>,
2447 <SYSC_IDLE_SMART_WKUP>;
2448 ti,syss-mask = <1>;
2449 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2450 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2451 clock-names = "fck";
2452 #address-cells = <1>;
2453 #size-cells = <1>;
2454 ranges = <0x0 0x22000 0x1000>;
2455
2456 uart8: serial@0 {
2457 compatible = "ti,dra742-uart";
2458 reg = <0x0 0x100>;
2459 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2460 clock-frequency = <48000000>;
2461 status = "disabled";
2462 };
2463 };
2464
2465 target-module@24000 { /* 0x48424000, ap 51 12.0 */
2466 compatible = "ti,sysc-omap2", "ti,sysc";
2467 reg = <0x24050 0x4>,
2468 <0x24054 0x4>,
2469 <0x24058 0x4>;
2470 reg-names = "rev", "sysc", "syss";
2471 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2472 SYSC_OMAP2_SOFTRESET |
2473 SYSC_OMAP2_AUTOIDLE)>;
2474 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2475 <SYSC_IDLE_NO>,
2476 <SYSC_IDLE_SMART>,
2477 <SYSC_IDLE_SMART_WKUP>;
2478 ti,syss-mask = <1>;
2479 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2480 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2481 clock-names = "fck";
2482 #address-cells = <1>;
2483 #size-cells = <1>;
2484 ranges = <0x0 0x24000 0x1000>;
2485
2486 uart9: serial@0 {
2487 compatible = "ti,dra742-uart";
2488 reg = <0x0 0x100>;
2489 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2490 clock-frequency = <48000000>;
2491 status = "disabled";
2492 };
2493 };
2494
2495 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
2496 compatible = "ti,sysc";
2497 status = "disabled";
2498 #address-cells = <1>;
2499 #size-cells = <1>;
2500 ranges = <0x0 0x2c000 0x1000>;
2501 };
2502
2503 target-module@36000 { /* 0x48436000, ap 17 06.0 */
2504 compatible = "ti,sysc";
2505 status = "disabled";
2506 #address-cells = <1>;
2507 #size-cells = <1>;
2508 ranges = <0x0 0x36000 0x1000>;
2509 };
2510
2511 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
2512 compatible = "ti,sysc";
2513 status = "disabled";
2514 #address-cells = <1>;
2515 #size-cells = <1>;
2516 ranges = <0x0 0x3a000 0x1000>;
2517 };
2518
2519 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
2520 compatible = "ti,sysc-omap4", "ti,sysc";
2521 reg = <0x3c000 0x4>;
2522 reg-names = "rev";
2523 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2524 clock-names = "fck";
2525 #address-cells = <1>;
2526 #size-cells = <1>;
2527 ranges = <0x0 0x3c000 0x1000>;
2528
2529 atl: atl@0 {
2530 compatible = "ti,dra7-atl";
2531 reg = <0x0 0x3ff>;
2532 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2533 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2534 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2535 clock-names = "fck";
2536 status = "disabled";
2537 };
2538 };
2539
2540 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
2541 compatible = "ti,sysc-omap4", "ti,sysc";
2542 reg = <0x3e000 0x4>,
2543 <0x3e004 0x4>;
2544 reg-names = "rev", "sysc";
2545 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2546 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2547 <SYSC_IDLE_NO>,
2548 <SYSC_IDLE_SMART>;
2549 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2550 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2551 clock-names = "fck";
2552 #address-cells = <1>;
2553 #size-cells = <1>;
2554 ranges = <0x0 0x3e000 0x1000>;
2555
2556 epwmss0: epwmss@0 {
2557 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2558 reg = <0x0 0x30>;
2559 #address-cells = <1>;
2560 #size-cells = <1>;
2561 status = "disabled";
2562 ranges = <0 0 0x1000>;
2563
2564 ecap0: pwm@100 {
2565 compatible = "ti,dra746-ecap",
2566 "ti,am3352-ecap";
2567 #pwm-cells = <3>;
2568 reg = <0x100 0x80>;
2569 clocks = <&l4_root_clk_div>;
2570 clock-names = "fck";
2571 status = "disabled";
2572 };
2573
2574 ehrpwm0: pwm@200 {
2575 compatible = "ti,dra746-ehrpwm",
2576 "ti,am3352-ehrpwm";
2577 #pwm-cells = <3>;
2578 reg = <0x200 0x80>;
2579 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2580 clock-names = "tbclk", "fck";
2581 status = "disabled";
2582 };
2583 };
2584 };
2585
2586 target-module@40000 { /* 0x48440000, ap 27 38.0 */
2587 compatible = "ti,sysc-omap4", "ti,sysc";
2588 reg = <0x40000 0x4>,
2589 <0x40004 0x4>;
2590 reg-names = "rev", "sysc";
2591 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2592 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2593 <SYSC_IDLE_NO>,
2594 <SYSC_IDLE_SMART>;
2595 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2596 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2597 clock-names = "fck";
2598 #address-cells = <1>;
2599 #size-cells = <1>;
2600 ranges = <0x0 0x40000 0x1000>;
2601
2602 epwmss1: epwmss@0 {
2603 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2604 reg = <0x0 0x30>;
2605 #address-cells = <1>;
2606 #size-cells = <1>;
2607 status = "disabled";
2608 ranges = <0 0 0x1000>;
2609
2610 ecap1: pwm@100 {
2611 compatible = "ti,dra746-ecap",
2612 "ti,am3352-ecap";
2613 #pwm-cells = <3>;
2614 reg = <0x100 0x80>;
2615 clocks = <&l4_root_clk_div>;
2616 clock-names = "fck";
2617 status = "disabled";
2618 };
2619
2620 ehrpwm1: pwm@200 {
2621 compatible = "ti,dra746-ehrpwm",
2622 "ti,am3352-ehrpwm";
2623 #pwm-cells = <3>;
2624 reg = <0x200 0x80>;
2625 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2626 clock-names = "tbclk", "fck";
2627 status = "disabled";
2628 };
2629 };
2630 };
2631
2632 target-module@42000 { /* 0x48442000, ap 29 20.0 */
2633 compatible = "ti,sysc-omap4", "ti,sysc";
2634 reg = <0x42000 0x4>,
2635 <0x42004 0x4>;
2636 reg-names = "rev", "sysc";
2637 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2638 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2639 <SYSC_IDLE_NO>,
2640 <SYSC_IDLE_SMART>;
2641 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2642 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2643 clock-names = "fck";
2644 #address-cells = <1>;
2645 #size-cells = <1>;
2646 ranges = <0x0 0x42000 0x1000>;
2647
2648 epwmss2: epwmss@0 {
2649 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2650 reg = <0x0 0x30>;
2651 #address-cells = <1>;
2652 #size-cells = <1>;
2653 status = "disabled";
2654 ranges = <0 0 0x1000>;
2655
2656 ecap2: pwm@100 {
2657 compatible = "ti,dra746-ecap",
2658 "ti,am3352-ecap";
2659 #pwm-cells = <3>;
2660 reg = <0x100 0x80>;
2661 clocks = <&l4_root_clk_div>;
2662 clock-names = "fck";
2663 status = "disabled";
2664 };
2665
2666 ehrpwm2: pwm@200 {
2667 compatible = "ti,dra746-ehrpwm",
2668 "ti,am3352-ehrpwm";
2669 #pwm-cells = <3>;
2670 reg = <0x200 0x80>;
2671 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2672 clock-names = "tbclk", "fck";
2673 status = "disabled";
2674 };
2675 };
2676 };
2677
2678 target-module@46000 { /* 0x48446000, ap 53 40.0 */
2679 compatible = "ti,sysc";
2680 status = "disabled";
2681 #address-cells = <1>;
2682 #size-cells = <1>;
2683 ranges = <0x0 0x46000 0x1000>;
2684 };
2685
2686 target-module@48000 { /* 0x48448000, ap 55 48.0 */
2687 compatible = "ti,sysc";
2688 status = "disabled";
2689 #address-cells = <1>;
2690 #size-cells = <1>;
2691 ranges = <0x0 0x48000 0x1000>;
2692 };
2693
2694 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
2695 compatible = "ti,sysc";
2696 status = "disabled";
2697 #address-cells = <1>;
2698 #size-cells = <1>;
2699 ranges = <0x0 0x4a000 0x1000>;
2700 };
2701
2702 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
2703 compatible = "ti,sysc";
2704 status = "disabled";
2705 #address-cells = <1>;
2706 #size-cells = <1>;
2707 ranges = <0x0 0x4c000 0x1000>;
2708 };
2709
2710 target-module@50000 { /* 0x48450000, ap 37 24.0 */
2711 compatible = "ti,sysc";
2712 status = "disabled";
2713 #address-cells = <1>;
2714 #size-cells = <1>;
2715 ranges = <0x0 0x50000 0x1000>;
2716 };
2717
2718 target-module@54000 { /* 0x48454000, ap 41 2c.0 */
2719 compatible = "ti,sysc";
2720 status = "disabled";
2721 #address-cells = <1>;
2722 #size-cells = <1>;
2723 ranges = <0x0 0x54000 0x1000>;
2724 };
2725
2726 target-module@58000 { /* 0x48458000, ap 57 28.0 */
2727 compatible = "ti,sysc";
2728 status = "disabled";
2729 #address-cells = <1>;
2730 #size-cells = <1>;
2731 ranges = <0x0 0x58000 0x2000>;
2732 };
2733
2734 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
2735 compatible = "ti,sysc";
2736 status = "disabled";
2737 #address-cells = <1>;
2738 #size-cells = <1>;
2739 ranges = <0x0 0x5b000 0x1000>;
2740 };
2741
2742 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
2743 compatible = "ti,sysc";
2744 status = "disabled";
2745 #address-cells = <1>;
2746 #size-cells = <1>;
2747 ranges = <0x0 0x5d000 0x1000>;
2748 };
2749
2750 target-module@60000 { /* 0x48460000, ap 9 0e.0 */
2751 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2752 reg = <0x60000 0x4>,
2753 <0x60004 0x4>;
2754 reg-names = "rev", "sysc";
2755 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2756 <SYSC_IDLE_NO>,
2757 <SYSC_IDLE_SMART>;
2758 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2759 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2760 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2761 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2762 clock-names = "fck", "ahclkx", "ahclkr";
2763 #address-cells = <1>;
2764 #size-cells = <1>;
2765 ranges = <0x0 0x60000 0x2000>,
2766 <0x45800000 0x45800000 0x400000>;
2767
2768 mcasp1: mcasp@0 {
2769 compatible = "ti,dra7-mcasp-audio";
2770 reg = <0x0 0x2000>,
2771 <0x45800000 0x1000>; /* L3 data port */
2772 reg-names = "mpu","dat";
2773 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2774 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2775 interrupt-names = "tx", "rx";
2776 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2777 dma-names = "tx", "rx";
2778 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2779 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2780 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2781 clock-names = "fck", "ahclkx", "ahclkr";
2782 status = "disabled";
2783 };
2784 };
2785
2786 target-module@64000 { /* 0x48464000, ap 11 1e.0 */
2787 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2788 reg = <0x64000 0x4>,
2789 <0x64004 0x4>;
2790 reg-names = "rev", "sysc";
2791 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2792 <SYSC_IDLE_NO>,
2793 <SYSC_IDLE_SMART>;
2794 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2795 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2796 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2797 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2798 clock-names = "fck", "ahclkx", "ahclkr";
2799 #address-cells = <1>;
2800 #size-cells = <1>;
2801 ranges = <0x0 0x64000 0x2000>,
2802 <0x45c00000 0x45c00000 0x400000>;
2803
2804 mcasp2: mcasp@0 {
2805 compatible = "ti,dra7-mcasp-audio";
2806 reg = <0x0 0x2000>,
2807 <0x45c00000 0x1000>; /* L3 data port */
2808 reg-names = "mpu","dat";
2809 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2810 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2811 interrupt-names = "tx", "rx";
2812 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2813 dma-names = "tx", "rx";
2814 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2815 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2816 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2817 clock-names = "fck", "ahclkx", "ahclkr";
2818 status = "disabled";
2819 };
2820 };
2821
2822 target-module@68000 { /* 0x48468000, ap 13 26.0 */
2823 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2824 reg = <0x68000 0x4>,
2825 <0x68004 0x4>;
2826 reg-names = "rev", "sysc";
2827 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2828 <SYSC_IDLE_NO>,
2829 <SYSC_IDLE_SMART>;
2830 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2831 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2832 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2833 clock-names = "fck", "ahclkx";
2834 #address-cells = <1>;
2835 #size-cells = <1>;
2836 ranges = <0x0 0x68000 0x2000>,
2837 <0x46000000 0x46000000 0x400000>;
2838
2839 mcasp3: mcasp@0 {
2840 compatible = "ti,dra7-mcasp-audio";
2841 reg = <0x0 0x2000>,
2842 <0x46000000 0x1000>; /* L3 data port */
2843 reg-names = "mpu","dat";
2844 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2845 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2846 interrupt-names = "tx", "rx";
2847 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2848 dma-names = "tx", "rx";
2849 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2850 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2851 clock-names = "fck", "ahclkx";
2852 status = "disabled";
2853 };
2854 };
2855
2856 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
2857 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2858 reg = <0x6c000 0x4>,
2859 <0x6c004 0x4>;
2860 reg-names = "rev", "sysc";
2861 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2862 <SYSC_IDLE_NO>,
2863 <SYSC_IDLE_SMART>;
2864 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2865 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2866 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2867 clock-names = "fck", "ahclkx";
2868 #address-cells = <1>;
2869 #size-cells = <1>;
2870 ranges = <0x0 0x6c000 0x2000>,
2871 <0x48436000 0x48436000 0x400000>;
2872
2873 mcasp4: mcasp@0 {
2874 compatible = "ti,dra7-mcasp-audio";
2875 reg = <0x0 0x2000>,
2876 <0x48436000 0x1000>; /* L3 data port */
2877 reg-names = "mpu","dat";
2878 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2879 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2880 interrupt-names = "tx", "rx";
2881 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2882 dma-names = "tx", "rx";
2883 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2884 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2885 clock-names = "fck", "ahclkx";
2886 status = "disabled";
2887 };
2888 };
2889
2890 target-module@70000 { /* 0x48470000, ap 19 36.0 */
2891 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2892 reg = <0x70000 0x4>,
2893 <0x70004 0x4>;
2894 reg-names = "rev", "sysc";
2895 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2896 <SYSC_IDLE_NO>,
2897 <SYSC_IDLE_SMART>;
2898 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2899 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2900 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2901 clock-names = "fck", "ahclkx";
2902 #address-cells = <1>;
2903 #size-cells = <1>;
2904 ranges = <0x0 0x70000 0x2000>,
2905 <0x4843a000 0x4843a000 0x400000>;
2906
2907 mcasp5: mcasp@0 {
2908 compatible = "ti,dra7-mcasp-audio";
2909 reg = <0x0 0x2000>,
2910 <0x4843a000 0x1000>; /* L3 data port */
2911 reg-names = "mpu","dat";
2912 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2913 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2914 interrupt-names = "tx", "rx";
2915 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2916 dma-names = "tx", "rx";
2917 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2918 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2919 clock-names = "fck", "ahclkx";
2920 status = "disabled";
2921 };
2922 };
2923
2924 target-module@74000 { /* 0x48474000, ap 35 14.0 */
2925 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2926 reg = <0x74000 0x4>,
2927 <0x74004 0x4>;
2928 reg-names = "rev", "sysc";
2929 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2930 <SYSC_IDLE_NO>,
2931 <SYSC_IDLE_SMART>;
2932 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2933 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2934 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2935 clock-names = "fck", "ahclkx";
2936 #address-cells = <1>;
2937 #size-cells = <1>;
2938 ranges = <0x0 0x74000 0x2000>,
2939 <0x4844c000 0x4844c000 0x400000>;
2940
2941 mcasp6: mcasp@0 {
2942 compatible = "ti,dra7-mcasp-audio";
2943 reg = <0x0 0x2000>,
2944 <0x4844c000 0x1000>; /* L3 data port */
2945 reg-names = "mpu","dat";
2946 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2947 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2948 interrupt-names = "tx", "rx";
2949 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2950 dma-names = "tx", "rx";
2951 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2952 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2953 clock-names = "fck", "ahclkx";
2954 status = "disabled";
2955 };
2956 };
2957
2958 target-module@78000 { /* 0x48478000, ap 39 0c.0 */
2959 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2960 reg = <0x78000 0x4>,
2961 <0x78004 0x4>;
2962 reg-names = "rev", "sysc";
2963 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2964 <SYSC_IDLE_NO>,
2965 <SYSC_IDLE_SMART>;
2966 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2967 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2968 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2969 clock-names = "fck", "ahclkx";
2970 #address-cells = <1>;
2971 #size-cells = <1>;
2972 ranges = <0x0 0x78000 0x2000>,
2973 <0x48450000 0x48450000 0x400000>;
2974
2975 mcasp7: mcasp@0 {
2976 compatible = "ti,dra7-mcasp-audio";
2977 reg = <0x0 0x2000>,
2978 <0x48450000 0x1000>; /* L3 data port */
2979 reg-names = "mpu","dat";
2980 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2981 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2982 interrupt-names = "tx", "rx";
2983 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2984 dma-names = "tx", "rx";
2985 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2986 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2987 clock-names = "fck", "ahclkx";
2988 status = "disabled";
2989 };
2990 };
2991
2992 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
2993 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2994 reg = <0x7c000 0x4>,
2995 <0x7c004 0x4>;
2996 reg-names = "rev", "sysc";
2997 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2998 <SYSC_IDLE_NO>,
2999 <SYSC_IDLE_SMART>;
3000 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
3001 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3002 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
3003 clock-names = "fck", "ahclkx";
3004 #address-cells = <1>;
3005 #size-cells = <1>;
3006 ranges = <0x0 0x7c000 0x2000>,
3007 <0x48454000 0x48454000 0x400000>;
3008
3009 mcasp8: mcasp@0 {
3010 compatible = "ti,dra7-mcasp-audio";
3011 reg = <0x0 0x2000>,
3012 <0x48454000 0x1000>; /* L3 data port */
3013 reg-names = "mpu","dat";
3014 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
3015 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
3016 interrupt-names = "tx", "rx";
3017 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
3018 dma-names = "tx", "rx";
3019 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3020 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
3021 clock-names = "fck", "ahclkx";
3022 status = "disabled";
3023 };
3024 };
3025
3026 target-module@80000 { /* 0x48480000, ap 31 16.0 */
3027 compatible = "ti,sysc-omap4", "ti,sysc";
3028 reg = <0x80020 0x4>;
3029 reg-names = "rev";
3030 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
3031 clock-names = "fck";
3032 #address-cells = <1>;
3033 #size-cells = <1>;
3034 ranges = <0x0 0x80000 0x2000>;
3035
3036 dcan2: can@0 {
3037 compatible = "ti,dra7-d_can";
3038 reg = <0x0 0x2000>;
3039 syscon-raminit = <&scm_conf 0x558 1>;
3040 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
3041 clocks = <&sys_clkin1>;
3042 status = "disabled";
3043 };
3044 };
3045
3046 target-module@84000 { /* 0x48484000, ap 3 10.0 */
3047 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3048 reg = <0x85200 0x4>,
3049 <0x85208 0x4>,
3050 <0x85204 0x4>;
3051 reg-names = "rev", "sysc", "syss";
3052 ti,sysc-mask = <0>;
3053 ti,sysc-midle = <SYSC_IDLE_FORCE>,
3054 <SYSC_IDLE_NO>;
3055 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3056 <SYSC_IDLE_NO>;
3057 ti,syss-mask = <1>;
3058 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3059 clock-names = "fck";
3060 #address-cells = <1>;
3061 #size-cells = <1>;
3062 ranges = <0x0 0x84000 0x4000>;
3063 /*
3064 * Do not allow gating of cpsw clock as workaround
3065 * for errata i877. Keeping internal clock disabled
3066 * causes the device switching characteristics
3067 * to degrade over time and eventually fail to meet
3068 * the data manual delay time/skew specs.
3069 */
3070 ti,no-idle;
3071
3072 mac_sw: switch@0 {
3073 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
3074 reg = <0x0 0x4000>;
3075 ranges = <0 0 0x4000>;
3076 clocks = <&gmac_main_clk>;
3077 clock-names = "fck";
3078 #address-cells = <1>;
3079 #size-cells = <1>;
3080 syscon = <&scm_conf>;
3081 status = "disabled";
3082
3083 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3084 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3085 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3086 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3087 interrupt-names = "rx_thresh", "rx", "tx", "misc";
3088
3089 ethernet-ports {
3090 #address-cells = <1>;
3091 #size-cells = <0>;
3092
3093 cpsw_port1: port@1 {
3094 reg = <1>;
3095 label = "port1";
3096 mac-address = [ 00 00 00 00 00 00 ];
3097 phys = <&phy_gmii_sel 1>;
3098 };
3099
3100 cpsw_port2: port@2 {
3101 reg = <2>;
3102 label = "port2";
3103 mac-address = [ 00 00 00 00 00 00 ];
3104 phys = <&phy_gmii_sel 2>;
3105 };
3106 };
3107
3108 davinci_mdio_sw: mdio@1000 {
3109 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3110 clocks = <&gmac_main_clk>;
3111 clock-names = "fck";
3112 #address-cells = <1>;
3113 #size-cells = <0>;
3114 bus_freq = <1000000>;
3115 reg = <0x1000 0x100>;
3116 };
3117
3118 cpts {
3119 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3120 clock-names = "cpts";
3121 };
3122 };
3123 };
3124 };
3125};
3126
3127&l4_per3 { /* 0x48800000 */
3128 compatible = "ti,dra7-l4-per3", "simple-pm-bus";
3129 power-domains = <&prm_l4per>;
3130 clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>;
3131 clock-names = "fck";
3132 reg = <0x48800000 0x800>,
3133 <0x48800800 0x800>,
3134 <0x48801000 0x400>,
3135 <0x48801400 0x400>,
3136 <0x48801800 0x400>;
3137 reg-names = "ap", "la", "ia0", "ia1", "ia2";
3138 #address-cells = <1>;
3139 #size-cells = <1>;
3140 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
3141
3142 segment@0 { /* 0x48800000 */
3143 compatible = "simple-pm-bus";
3144 #address-cells = <1>;
3145 #size-cells = <1>;
3146 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
3147 <0x00000800 0x00000800 0x000800>, /* ap 1 */
3148 <0x00001000 0x00001000 0x000400>, /* ap 2 */
3149 <0x00001400 0x00001400 0x000400>, /* ap 3 */
3150 <0x00001800 0x00001800 0x000400>, /* ap 4 */
3151 <0x00020000 0x00020000 0x001000>, /* ap 5 */
3152 <0x00021000 0x00021000 0x001000>, /* ap 6 */
3153 <0x00022000 0x00022000 0x001000>, /* ap 7 */
3154 <0x00023000 0x00023000 0x001000>, /* ap 8 */
3155 <0x00024000 0x00024000 0x001000>, /* ap 9 */
3156 <0x00025000 0x00025000 0x001000>, /* ap 10 */
3157 <0x00026000 0x00026000 0x001000>, /* ap 11 */
3158 <0x00027000 0x00027000 0x001000>, /* ap 12 */
3159 <0x00028000 0x00028000 0x001000>, /* ap 13 */
3160 <0x00029000 0x00029000 0x001000>, /* ap 14 */
3161 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */
3162 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */
3163 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */
3164 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */
3165 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */
3166 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */
3167 <0x00170000 0x00170000 0x010000>, /* ap 21 */
3168 <0x00180000 0x00180000 0x001000>, /* ap 22 */
3169 <0x00190000 0x00190000 0x010000>, /* ap 23 */
3170 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */
3171 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */
3172 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */
3173 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */
3174 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */
3175 <0x00038000 0x00038000 0x001000>, /* ap 29 */
3176 <0x00039000 0x00039000 0x001000>, /* ap 30 */
3177 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */
3178 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */
3179 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */
3180 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */
3181 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */
3182 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */
3183 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */
3184 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */
3185 <0x00040000 0x00040000 0x001000>, /* ap 39 */
3186 <0x00041000 0x00041000 0x001000>, /* ap 40 */
3187 <0x00042000 0x00042000 0x001000>, /* ap 41 */
3188 <0x00043000 0x00043000 0x001000>, /* ap 42 */
3189 <0x00044000 0x00044000 0x001000>, /* ap 43 */
3190 <0x00045000 0x00045000 0x001000>, /* ap 44 */
3191 <0x00046000 0x00046000 0x001000>, /* ap 45 */
3192 <0x00047000 0x00047000 0x001000>, /* ap 46 */
3193 <0x00048000 0x00048000 0x001000>, /* ap 47 */
3194 <0x00049000 0x00049000 0x001000>, /* ap 48 */
3195 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */
3196 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */
3197 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */
3198 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */
3199 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */
3200 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */
3201 <0x00050000 0x00050000 0x001000>, /* ap 55 */
3202 <0x00051000 0x00051000 0x001000>, /* ap 56 */
3203 <0x00052000 0x00052000 0x001000>, /* ap 57 */
3204 <0x00053000 0x00053000 0x001000>, /* ap 58 */
3205 <0x00054000 0x00054000 0x001000>, /* ap 59 */
3206 <0x00055000 0x00055000 0x001000>, /* ap 60 */
3207 <0x00056000 0x00056000 0x001000>, /* ap 61 */
3208 <0x00057000 0x00057000 0x001000>, /* ap 62 */
3209 <0x00058000 0x00058000 0x001000>, /* ap 63 */
3210 <0x00059000 0x00059000 0x001000>, /* ap 64 */
3211 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */
3212 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */
3213 <0x00064000 0x00064000 0x001000>, /* ap 67 */
3214 <0x00065000 0x00065000 0x001000>, /* ap 68 */
3215 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */
3216 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */
3217 <0x00060000 0x00060000 0x001000>, /* ap 71 */
3218 <0x00061000 0x00061000 0x001000>, /* ap 72 */
3219 <0x00062000 0x00062000 0x001000>, /* ap 73 */
3220 <0x00063000 0x00063000 0x001000>, /* ap 74 */
3221 <0x00140000 0x00140000 0x020000>, /* ap 75 */
3222 <0x00160000 0x00160000 0x001000>, /* ap 76 */
3223 <0x00016000 0x00016000 0x001000>, /* ap 77 */
3224 <0x00017000 0x00017000 0x001000>, /* ap 78 */
3225 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */
3226 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */
3227 <0x00004000 0x00004000 0x001000>, /* ap 81 */
3228 <0x00005000 0x00005000 0x001000>, /* ap 82 */
3229 <0x00080000 0x00080000 0x020000>, /* ap 83 */
3230 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */
3231 <0x00100000 0x00100000 0x020000>, /* ap 85 */
3232 <0x00120000 0x00120000 0x001000>, /* ap 86 */
3233 <0x00010000 0x00010000 0x001000>, /* ap 87 */
3234 <0x00011000 0x00011000 0x001000>, /* ap 88 */
3235 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */
3236 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */
3237 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */
3238 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */
3239 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */
3240 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */
3241 <0x00002000 0x00002000 0x001000>, /* ap 95 */
3242 <0x00003000 0x00003000 0x001000>; /* ap 96 */
3243
3244 target-module@2000 { /* 0x48802000, ap 95 7c.0 */
3245 compatible = "ti,sysc-omap4", "ti,sysc";
3246 reg = <0x2000 0x4>,
3247 <0x2010 0x4>;
3248 reg-names = "rev", "sysc";
3249 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3250 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3251 <SYSC_IDLE_NO>,
3252 <SYSC_IDLE_SMART>;
3253 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3254 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3255 clock-names = "fck";
3256 #address-cells = <1>;
3257 #size-cells = <1>;
3258 ranges = <0x0 0x2000 0x1000>;
3259
3260 mailbox13: mailbox@0 {
3261 compatible = "ti,omap4-mailbox";
3262 reg = <0x0 0x200>;
3263 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
3264 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3265 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
3266 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
3267 #mbox-cells = <1>;
3268 ti,mbox-num-users = <4>;
3269 ti,mbox-num-fifos = <12>;
3270 status = "disabled";
3271 };
3272 };
3273
3274 target-module@4000 { /* 0x48804000, ap 81 20.0 */
3275 compatible = "ti,sysc";
3276 status = "disabled";
3277 #address-cells = <1>;
3278 #size-cells = <1>;
3279 ranges = <0x0 0x4000 0x1000>;
3280 };
3281
3282 target-module@a000 { /* 0x4880a000, ap 89 18.0 */
3283 compatible = "ti,sysc";
3284 status = "disabled";
3285 #address-cells = <1>;
3286 #size-cells = <1>;
3287 ranges = <0x0 0xa000 0x1000>;
3288 };
3289
3290 target-module@10000 { /* 0x48810000, ap 87 28.0 */
3291 compatible = "ti,sysc";
3292 status = "disabled";
3293 #address-cells = <1>;
3294 #size-cells = <1>;
3295 ranges = <0x0 0x10000 0x1000>;
3296 };
3297
3298 target-module@16000 { /* 0x48816000, ap 77 1e.0 */
3299 compatible = "ti,sysc";
3300 status = "disabled";
3301 #address-cells = <1>;
3302 #size-cells = <1>;
3303 ranges = <0x0 0x16000 0x1000>;
3304 };
3305
3306 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */
3307 compatible = "ti,sysc";
3308 status = "disabled";
3309 #address-cells = <1>;
3310 #size-cells = <1>;
3311 ranges = <0x0 0x1c000 0x1000>;
3312 };
3313
3314 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
3315 compatible = "ti,sysc";
3316 status = "disabled";
3317 #address-cells = <1>;
3318 #size-cells = <1>;
3319 ranges = <0x0 0x1e000 0x1000>;
3320 };
3321
3322 target-module@20000 { /* 0x48820000, ap 5 08.0 */
3323 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3324 reg = <0x20000 0x4>,
3325 <0x20010 0x4>;
3326 reg-names = "rev", "sysc";
3327 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3328 SYSC_OMAP4_SOFTRESET)>;
3329 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3330 <SYSC_IDLE_NO>,
3331 <SYSC_IDLE_SMART>,
3332 <SYSC_IDLE_SMART_WKUP>;
3333 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3334 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3335 clock-names = "fck";
3336 #address-cells = <1>;
3337 #size-cells = <1>;
3338 ranges = <0x0 0x20000 0x1000>;
3339
3340 timer5: timer@0 {
3341 compatible = "ti,omap5430-timer";
3342 reg = <0x0 0x80>;
3343 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>;
3344 clock-names = "fck", "timer_sys_ck";
3345 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3346 };
3347 };
3348
3349 target-module@22000 { /* 0x48822000, ap 7 24.0 */
3350 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3351 reg = <0x22000 0x4>,
3352 <0x22010 0x4>;
3353 reg-names = "rev", "sysc";
3354 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3355 SYSC_OMAP4_SOFTRESET)>;
3356 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3357 <SYSC_IDLE_NO>,
3358 <SYSC_IDLE_SMART>,
3359 <SYSC_IDLE_SMART_WKUP>;
3360 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3361 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3362 clock-names = "fck";
3363 #address-cells = <1>;
3364 #size-cells = <1>;
3365 ranges = <0x0 0x22000 0x1000>;
3366
3367 timer6: timer@0 {
3368 compatible = "ti,omap5430-timer";
3369 reg = <0x0 0x80>;
3370 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>;
3371 clock-names = "fck", "timer_sys_ck";
3372 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3373 };
3374 };
3375
3376 target-module@24000 { /* 0x48824000, ap 9 26.0 */
3377 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3378 reg = <0x24000 0x4>,
3379 <0x24010 0x4>;
3380 reg-names = "rev", "sysc";
3381 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3382 SYSC_OMAP4_SOFTRESET)>;
3383 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3384 <SYSC_IDLE_NO>,
3385 <SYSC_IDLE_SMART>,
3386 <SYSC_IDLE_SMART_WKUP>;
3387 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3388 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3389 clock-names = "fck";
3390 #address-cells = <1>;
3391 #size-cells = <1>;
3392 ranges = <0x0 0x24000 0x1000>;
3393
3394 timer7: timer@0 {
3395 compatible = "ti,omap5430-timer";
3396 reg = <0x0 0x80>;
3397 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>;
3398 clock-names = "fck", "timer_sys_ck";
3399 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3400 };
3401 };
3402
3403 target-module@26000 { /* 0x48826000, ap 11 0c.0 */
3404 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3405 reg = <0x26000 0x4>,
3406 <0x26010 0x4>;
3407 reg-names = "rev", "sysc";
3408 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3409 SYSC_OMAP4_SOFTRESET)>;
3410 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3411 <SYSC_IDLE_NO>,
3412 <SYSC_IDLE_SMART>,
3413 <SYSC_IDLE_SMART_WKUP>;
3414 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3415 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3416 clock-names = "fck";
3417 #address-cells = <1>;
3418 #size-cells = <1>;
3419 ranges = <0x0 0x26000 0x1000>;
3420
3421 timer8: timer@0 {
3422 compatible = "ti,omap5430-timer";
3423 reg = <0x0 0x80>;
3424 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>;
3425 clock-names = "fck", "timer_sys_ck";
3426 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3427 };
3428 };
3429
3430 target-module@28000 { /* 0x48828000, ap 13 16.0 */
3431 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3432 reg = <0x28000 0x4>,
3433 <0x28010 0x4>;
3434 reg-names = "rev", "sysc";
3435 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3436 SYSC_OMAP4_SOFTRESET)>;
3437 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3438 <SYSC_IDLE_NO>,
3439 <SYSC_IDLE_SMART>,
3440 <SYSC_IDLE_SMART_WKUP>;
3441 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3442 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3443 clock-names = "fck";
3444 #address-cells = <1>;
3445 #size-cells = <1>;
3446 ranges = <0x0 0x28000 0x1000>;
3447
3448 timer13: timer@0 {
3449 compatible = "ti,omap5430-timer";
3450 reg = <0x0 0x80>;
3451 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>;
3452 clock-names = "fck", "timer_sys_ck";
3453 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
3454 ti,timer-pwm;
3455 };
3456 };
3457
3458 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
3459 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3460 reg = <0x2a000 0x4>,
3461 <0x2a010 0x4>;
3462 reg-names = "rev", "sysc";
3463 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3464 SYSC_OMAP4_SOFTRESET)>;
3465 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3466 <SYSC_IDLE_NO>,
3467 <SYSC_IDLE_SMART>,
3468 <SYSC_IDLE_SMART_WKUP>;
3469 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3470 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3471 clock-names = "fck";
3472 #address-cells = <1>;
3473 #size-cells = <1>;
3474 ranges = <0x0 0x2a000 0x1000>;
3475
3476 timer14: timer@0 {
3477 compatible = "ti,omap5430-timer";
3478 reg = <0x0 0x80>;
3479 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>;
3480 clock-names = "fck", "timer_sys_ck";
3481 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
3482 ti,timer-pwm;
3483 };
3484 };
3485
3486 target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
3487 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3488 reg = <0x2c000 0x4>,
3489 <0x2c010 0x4>;
3490 reg-names = "rev", "sysc";
3491 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3492 SYSC_OMAP4_SOFTRESET)>;
3493 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3494 <SYSC_IDLE_NO>,
3495 <SYSC_IDLE_SMART>,
3496 <SYSC_IDLE_SMART_WKUP>;
3497 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3498 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3499 clock-names = "fck";
3500 #address-cells = <1>;
3501 #size-cells = <1>;
3502 ranges = <0x0 0x2c000 0x1000>;
3503
3504 timer15: timer@0 {
3505 compatible = "ti,omap5430-timer";
3506 reg = <0x0 0x80>;
3507 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>;
3508 clock-names = "fck", "timer_sys_ck";
3509 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
3510 ti,timer-pwm;
3511 };
3512 };
3513
3514 target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
3515 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3516 reg = <0x2e000 0x4>,
3517 <0x2e010 0x4>;
3518 reg-names = "rev", "sysc";
3519 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3520 SYSC_OMAP4_SOFTRESET)>;
3521 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3522 <SYSC_IDLE_NO>,
3523 <SYSC_IDLE_SMART>,
3524 <SYSC_IDLE_SMART_WKUP>;
3525 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3526 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3527 clock-names = "fck";
3528 #address-cells = <1>;
3529 #size-cells = <1>;
3530 ranges = <0x0 0x2e000 0x1000>;
3531
3532 timer16: timer@0 {
3533 compatible = "ti,omap5430-timer";
3534 reg = <0x0 0x80>;
3535 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>;
3536 clock-names = "fck", "timer_sys_ck";
3537 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
3538 ti,timer-pwm;
3539 };
3540 };
3541
3542 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
3543 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3544 reg = <0x38074 0x4>,
3545 <0x38078 0x4>;
3546 reg-names = "rev", "sysc";
3547 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3548 <SYSC_IDLE_NO>,
3549 <SYSC_IDLE_SMART>,
3550 <SYSC_IDLE_SMART_WKUP>;
3551 /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
3552 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3553 clock-names = "fck";
3554 #address-cells = <1>;
3555 #size-cells = <1>;
3556 ranges = <0x0 0x38000 0x1000>;
3557
3558 rtc: rtc@0 {
3559 compatible = "ti,am3352-rtc";
3560 reg = <0x0 0x100>;
3561 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
3563 clocks = <&sys_32k_ck>;
3564 };
3565 };
3566
3567 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
3568 compatible = "ti,sysc-omap4", "ti,sysc";
3569 reg = <0x3a000 0x4>,
3570 <0x3a010 0x4>;
3571 reg-names = "rev", "sysc";
3572 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3573 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3574 <SYSC_IDLE_NO>,
3575 <SYSC_IDLE_SMART>;
3576 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3577 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3578 clock-names = "fck";
3579 #address-cells = <1>;
3580 #size-cells = <1>;
3581 ranges = <0x0 0x3a000 0x1000>;
3582
3583 mailbox2: mailbox@0 {
3584 compatible = "ti,omap4-mailbox";
3585 reg = <0x0 0x200>;
3586 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
3590 #mbox-cells = <1>;
3591 ti,mbox-num-users = <4>;
3592 ti,mbox-num-fifos = <12>;
3593 status = "disabled";
3594 };
3595 };
3596
3597 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
3598 compatible = "ti,sysc-omap4", "ti,sysc";
3599 reg = <0x3c000 0x4>,
3600 <0x3c010 0x4>;
3601 reg-names = "rev", "sysc";
3602 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3603 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3604 <SYSC_IDLE_NO>,
3605 <SYSC_IDLE_SMART>;
3606 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3607 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3608 clock-names = "fck";
3609 #address-cells = <1>;
3610 #size-cells = <1>;
3611 ranges = <0x0 0x3c000 0x1000>;
3612
3613 mailbox3: mailbox@0 {
3614 compatible = "ti,omap4-mailbox";
3615 reg = <0x0 0x200>;
3616 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
3620 #mbox-cells = <1>;
3621 ti,mbox-num-users = <4>;
3622 ti,mbox-num-fifos = <12>;
3623 status = "disabled";
3624 };
3625 };
3626
3627 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
3628 compatible = "ti,sysc-omap4", "ti,sysc";
3629 reg = <0x3e000 0x4>,
3630 <0x3e010 0x4>;
3631 reg-names = "rev", "sysc";
3632 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3633 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3634 <SYSC_IDLE_NO>,
3635 <SYSC_IDLE_SMART>;
3636 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3637 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3638 clock-names = "fck";
3639 #address-cells = <1>;
3640 #size-cells = <1>;
3641 ranges = <0x0 0x3e000 0x1000>;
3642
3643 mailbox4: mailbox@0 {
3644 compatible = "ti,omap4-mailbox";
3645 reg = <0x0 0x200>;
3646 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3647 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3648 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3649 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3650 #mbox-cells = <1>;
3651 ti,mbox-num-users = <4>;
3652 ti,mbox-num-fifos = <12>;
3653 status = "disabled";
3654 };
3655 };
3656
3657 target-module@40000 { /* 0x48840000, ap 39 64.0 */
3658 compatible = "ti,sysc-omap4", "ti,sysc";
3659 reg = <0x40000 0x4>,
3660 <0x40010 0x4>;
3661 reg-names = "rev", "sysc";
3662 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3663 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3664 <SYSC_IDLE_NO>,
3665 <SYSC_IDLE_SMART>;
3666 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3667 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3668 clock-names = "fck";
3669 #address-cells = <1>;
3670 #size-cells = <1>;
3671 ranges = <0x0 0x40000 0x1000>;
3672
3673 mailbox5: mailbox@0 {
3674 compatible = "ti,omap4-mailbox";
3675 reg = <0x0 0x200>;
3676 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3677 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3678 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3679 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
3680 #mbox-cells = <1>;
3681 ti,mbox-num-users = <4>;
3682 ti,mbox-num-fifos = <12>;
3683 status = "disabled";
3684 };
3685 };
3686
3687 target-module@42000 { /* 0x48842000, ap 41 4e.0 */
3688 compatible = "ti,sysc-omap4", "ti,sysc";
3689 reg = <0x42000 0x4>,
3690 <0x42010 0x4>;
3691 reg-names = "rev", "sysc";
3692 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3693 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3694 <SYSC_IDLE_NO>,
3695 <SYSC_IDLE_SMART>;
3696 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3697 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3698 clock-names = "fck";
3699 #address-cells = <1>;
3700 #size-cells = <1>;
3701 ranges = <0x0 0x42000 0x1000>;
3702
3703 mailbox6: mailbox@0 {
3704 compatible = "ti,omap4-mailbox";
3705 reg = <0x0 0x200>;
3706 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3707 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3708 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3709 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
3710 #mbox-cells = <1>;
3711 ti,mbox-num-users = <4>;
3712 ti,mbox-num-fifos = <12>;
3713 status = "disabled";
3714 };
3715 };
3716
3717 target-module@44000 { /* 0x48844000, ap 43 42.0 */
3718 compatible = "ti,sysc-omap4", "ti,sysc";
3719 reg = <0x44000 0x4>,
3720 <0x44010 0x4>;
3721 reg-names = "rev", "sysc";
3722 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3723 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3724 <SYSC_IDLE_NO>,
3725 <SYSC_IDLE_SMART>;
3726 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3727 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3728 clock-names = "fck";
3729 #address-cells = <1>;
3730 #size-cells = <1>;
3731 ranges = <0x0 0x44000 0x1000>;
3732
3733 mailbox7: mailbox@0 {
3734 compatible = "ti,omap4-mailbox";
3735 reg = <0x0 0x200>;
3736 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3737 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3738 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
3739 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
3740 #mbox-cells = <1>;
3741 ti,mbox-num-users = <4>;
3742 ti,mbox-num-fifos = <12>;
3743 status = "disabled";
3744 };
3745 };
3746
3747 target-module@46000 { /* 0x48846000, ap 45 48.0 */
3748 compatible = "ti,sysc-omap4", "ti,sysc";
3749 reg = <0x46000 0x4>,
3750 <0x46010 0x4>;
3751 reg-names = "rev", "sysc";
3752 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3753 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3754 <SYSC_IDLE_NO>,
3755 <SYSC_IDLE_SMART>;
3756 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3757 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3758 clock-names = "fck";
3759 #address-cells = <1>;
3760 #size-cells = <1>;
3761 ranges = <0x0 0x46000 0x1000>;
3762
3763 mailbox8: mailbox@0 {
3764 compatible = "ti,omap4-mailbox";
3765 reg = <0x0 0x200>;
3766 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3767 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3768 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3769 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
3770 #mbox-cells = <1>;
3771 ti,mbox-num-users = <4>;
3772 ti,mbox-num-fifos = <12>;
3773 status = "disabled";
3774 };
3775 };
3776
3777 target-module@48000 { /* 0x48848000, ap 47 36.0 */
3778 compatible = "ti,sysc";
3779 status = "disabled";
3780 #address-cells = <1>;
3781 #size-cells = <1>;
3782 ranges = <0x0 0x48000 0x1000>;
3783 };
3784
3785 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */
3786 compatible = "ti,sysc";
3787 status = "disabled";
3788 #address-cells = <1>;
3789 #size-cells = <1>;
3790 ranges = <0x0 0x4a000 0x1000>;
3791 };
3792
3793 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */
3794 compatible = "ti,sysc";
3795 status = "disabled";
3796 #address-cells = <1>;
3797 #size-cells = <1>;
3798 ranges = <0x0 0x4c000 0x1000>;
3799 };
3800
3801 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */
3802 compatible = "ti,sysc";
3803 status = "disabled";
3804 #address-cells = <1>;
3805 #size-cells = <1>;
3806 ranges = <0x0 0x4e000 0x1000>;
3807 };
3808
3809 target-module@50000 { /* 0x48850000, ap 55 40.0 */
3810 compatible = "ti,sysc";
3811 status = "disabled";
3812 #address-cells = <1>;
3813 #size-cells = <1>;
3814 ranges = <0x0 0x50000 0x1000>;
3815 };
3816
3817 target-module@52000 { /* 0x48852000, ap 57 54.0 */
3818 compatible = "ti,sysc";
3819 status = "disabled";
3820 #address-cells = <1>;
3821 #size-cells = <1>;
3822 ranges = <0x0 0x52000 0x1000>;
3823 };
3824
3825 target-module@54000 { /* 0x48854000, ap 59 1a.0 */
3826 compatible = "ti,sysc";
3827 status = "disabled";
3828 #address-cells = <1>;
3829 #size-cells = <1>;
3830 ranges = <0x0 0x54000 0x1000>;
3831 };
3832
3833 target-module@56000 { /* 0x48856000, ap 61 22.0 */
3834 compatible = "ti,sysc";
3835 status = "disabled";
3836 #address-cells = <1>;
3837 #size-cells = <1>;
3838 ranges = <0x0 0x56000 0x1000>;
3839 };
3840
3841 target-module@58000 { /* 0x48858000, ap 63 2a.0 */
3842 compatible = "ti,sysc";
3843 status = "disabled";
3844 #address-cells = <1>;
3845 #size-cells = <1>;
3846 ranges = <0x0 0x58000 0x1000>;
3847 };
3848
3849 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */
3850 compatible = "ti,sysc";
3851 status = "disabled";
3852 #address-cells = <1>;
3853 #size-cells = <1>;
3854 ranges = <0x0 0x5a000 0x1000>;
3855 };
3856
3857 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
3858 compatible = "ti,sysc";
3859 status = "disabled";
3860 #address-cells = <1>;
3861 #size-cells = <1>;
3862 ranges = <0x0 0x5c000 0x1000>;
3863 };
3864
3865 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
3866 compatible = "ti,sysc-omap4", "ti,sysc";
3867 reg = <0x5e000 0x4>,
3868 <0x5e010 0x4>;
3869 reg-names = "rev", "sysc";
3870 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3871 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3872 <SYSC_IDLE_NO>,
3873 <SYSC_IDLE_SMART>;
3874 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3875 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3876 clock-names = "fck";
3877 #address-cells = <1>;
3878 #size-cells = <1>;
3879 ranges = <0x0 0x5e000 0x1000>;
3880
3881 mailbox9: mailbox@0 {
3882 compatible = "ti,omap4-mailbox";
3883 reg = <0x0 0x200>;
3884 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
3885 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3886 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3887 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3888 #mbox-cells = <1>;
3889 ti,mbox-num-users = <4>;
3890 ti,mbox-num-fifos = <12>;
3891 status = "disabled";
3892 };
3893 };
3894
3895 target-module@60000 { /* 0x48860000, ap 71 4a.0 */
3896 compatible = "ti,sysc-omap4", "ti,sysc";
3897 reg = <0x60000 0x4>,
3898 <0x60010 0x4>;
3899 reg-names = "rev", "sysc";
3900 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3901 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3902 <SYSC_IDLE_NO>,
3903 <SYSC_IDLE_SMART>;
3904 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3905 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3906 clock-names = "fck";
3907 #address-cells = <1>;
3908 #size-cells = <1>;
3909 ranges = <0x0 0x60000 0x1000>;
3910
3911 mailbox10: mailbox@0 {
3912 compatible = "ti,omap4-mailbox";
3913 reg = <0x0 0x200>;
3914 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3915 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
3916 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
3917 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3918 #mbox-cells = <1>;
3919 ti,mbox-num-users = <4>;
3920 ti,mbox-num-fifos = <12>;
3921 status = "disabled";
3922 };
3923 };
3924
3925 target-module@62000 { /* 0x48862000, ap 73 74.0 */
3926 compatible = "ti,sysc-omap4", "ti,sysc";
3927 reg = <0x62000 0x4>,
3928 <0x62010 0x4>;
3929 reg-names = "rev", "sysc";
3930 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3931 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3932 <SYSC_IDLE_NO>,
3933 <SYSC_IDLE_SMART>;
3934 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3935 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3936 clock-names = "fck";
3937 #address-cells = <1>;
3938 #size-cells = <1>;
3939 ranges = <0x0 0x62000 0x1000>;
3940
3941 mailbox11: mailbox@0 {
3942 compatible = "ti,omap4-mailbox";
3943 reg = <0x0 0x200>;
3944 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
3945 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
3946 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
3947 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
3948 #mbox-cells = <1>;
3949 ti,mbox-num-users = <4>;
3950 ti,mbox-num-fifos = <12>;
3951 status = "disabled";
3952 };
3953 };
3954
3955 target-module@64000 { /* 0x48864000, ap 67 52.0 */
3956 compatible = "ti,sysc-omap4", "ti,sysc";
3957 reg = <0x64000 0x4>,
3958 <0x64010 0x4>;
3959 reg-names = "rev", "sysc";
3960 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3961 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3962 <SYSC_IDLE_NO>,
3963 <SYSC_IDLE_SMART>;
3964 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3965 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3966 clock-names = "fck";
3967 #address-cells = <1>;
3968 #size-cells = <1>;
3969 ranges = <0x0 0x64000 0x1000>;
3970
3971 mailbox12: mailbox@0 {
3972 compatible = "ti,omap4-mailbox";
3973 reg = <0x0 0x200>;
3974 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
3975 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
3976 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
3977 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
3978 #mbox-cells = <1>;
3979 ti,mbox-num-users = <4>;
3980 ti,mbox-num-fifos = <12>;
3981 status = "disabled";
3982 };
3983 };
3984
3985 target-module@80000 { /* 0x48880000, ap 83 0e.1 */
3986 compatible = "ti,sysc-omap4", "ti,sysc";
3987 reg = <0x80000 0x4>,
3988 <0x80010 0x4>;
3989 reg-names = "rev", "sysc";
3990 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
3991 ti,sysc-midle = <SYSC_IDLE_FORCE>,
3992 <SYSC_IDLE_NO>,
3993 <SYSC_IDLE_SMART>,
3994 <SYSC_IDLE_SMART_WKUP>;
3995 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3996 <SYSC_IDLE_NO>,
3997 <SYSC_IDLE_SMART>,
3998 <SYSC_IDLE_SMART_WKUP>;
3999 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4000 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
4001 clock-names = "fck";
4002 #address-cells = <1>;
4003 #size-cells = <1>;
4004 ranges = <0x0 0x80000 0x20000>;
4005
4006 omap_dwc3_1: omap_dwc3_1@0 {
4007 compatible = "ti,dwc3";
4008 reg = <0x0 0x10000>;
4009 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4010 #address-cells = <1>;
4011 #size-cells = <1>;
4012 utmi-mode = <2>;
4013 ranges = <0 0 0x20000>;
4014
4015 usb1: usb@10000 {
4016 compatible = "snps,dwc3";
4017 reg = <0x10000 0x17000>;
4018 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4019 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4020 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4021 interrupt-names = "peripheral",
4022 "host",
4023 "otg";
4024 phys = <&usb2_phy1>, <&usb3_phy1>;
4025 phy-names = "usb2-phy", "usb3-phy";
4026 maximum-speed = "super-speed";
4027 dr_mode = "otg";
4028 snps,dis_u3_susphy_quirk;
4029 snps,dis_u2_susphy_quirk;
4030 };
4031 };
4032 };
4033
4034 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
4035 compatible = "ti,sysc-omap4", "ti,sysc";
4036 reg = <0xc0000 0x4>,
4037 <0xc0010 0x4>;
4038 reg-names = "rev", "sysc";
4039 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4040 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4041 <SYSC_IDLE_NO>,
4042 <SYSC_IDLE_SMART>,
4043 <SYSC_IDLE_SMART_WKUP>;
4044 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4045 <SYSC_IDLE_NO>,
4046 <SYSC_IDLE_SMART>,
4047 <SYSC_IDLE_SMART_WKUP>;
4048 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4049 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4050 clock-names = "fck";
4051 #address-cells = <1>;
4052 #size-cells = <1>;
4053 ranges = <0x0 0xc0000 0x20000>;
4054
4055 omap_dwc3_2: omap_dwc3_2@0 {
4056 compatible = "ti,dwc3";
4057 reg = <0x0 0x10000>;
4058 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4059 #address-cells = <1>;
4060 #size-cells = <1>;
4061 utmi-mode = <2>;
4062 ranges = <0 0 0x20000>;
4063
4064 usb2: usb@10000 {
4065 compatible = "snps,dwc3";
4066 reg = <0x10000 0x17000>;
4067 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4068 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4069 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4070 interrupt-names = "peripheral",
4071 "host",
4072 "otg";
4073 phys = <&usb2_phy2>;
4074 phy-names = "usb2-phy";
4075 maximum-speed = "high-speed";
4076 dr_mode = "otg";
4077 snps,dis_u3_susphy_quirk;
4078 snps,dis_u2_susphy_quirk;
4079 snps,dis_metastability_quirk;
4080 };
4081 };
4082 };
4083
4084 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
4085 compatible = "ti,sysc-omap4", "ti,sysc";
4086 reg = <0x100000 0x4>,
4087 <0x100010 0x4>;
4088 reg-names = "rev", "sysc";
4089 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4090 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4091 <SYSC_IDLE_NO>,
4092 <SYSC_IDLE_SMART>,
4093 <SYSC_IDLE_SMART_WKUP>;
4094 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4095 <SYSC_IDLE_NO>,
4096 <SYSC_IDLE_SMART>,
4097 <SYSC_IDLE_SMART_WKUP>;
4098 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4099 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4100 clock-names = "fck";
4101 #address-cells = <1>;
4102 #size-cells = <1>;
4103 ranges = <0x0 0x100000 0x20000>;
4104
4105 omap_dwc3_3: omap_dwc3_3@0 {
4106 compatible = "ti,dwc3";
4107 reg = <0x0 0x10000>;
4108 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4109 #address-cells = <1>;
4110 #size-cells = <1>;
4111 utmi-mode = <2>;
4112 ranges = <0 0 0x20000>;
4113 status = "disabled";
4114
4115 usb3: usb@10000 {
4116 compatible = "snps,dwc3";
4117 reg = <0x10000 0x17000>;
4118 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4119 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4120 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4121 interrupt-names = "peripheral",
4122 "host",
4123 "otg";
4124 maximum-speed = "high-speed";
4125 dr_mode = "otg";
4126 snps,dis_u3_susphy_quirk;
4127 snps,dis_u2_susphy_quirk;
4128 };
4129 };
4130 };
4131
4132 target-module@170000 { /* 0x48970000, ap 21 0a.0 */
4133 compatible = "ti,sysc-omap4", "ti,sysc";
4134 reg = <0x170010 0x4>;
4135 reg-names = "sysc";
4136 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4137 <SYSC_IDLE_NO>,
4138 <SYSC_IDLE_SMART>;
4139 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4140 <SYSC_IDLE_NO>,
4141 <SYSC_IDLE_SMART>;
4142 clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
4143 clock-names = "fck";
4144 #address-cells = <1>;
4145 #size-cells = <1>;
4146 ranges = <0x0 0x170000 0x10000>;
4147 status = "disabled";
4148 };
4149
4150 target-module@190000 { /* 0x48990000, ap 23 2e.0 */
4151 compatible = "ti,sysc-omap4", "ti,sysc";
4152 reg = <0x190010 0x4>;
4153 reg-names = "sysc";
4154 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4155 <SYSC_IDLE_NO>,
4156 <SYSC_IDLE_SMART>;
4157 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4158 <SYSC_IDLE_NO>,
4159 <SYSC_IDLE_SMART>;
4160 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
4161 clock-names = "fck";
4162 #address-cells = <1>;
4163 #size-cells = <1>;
4164 ranges = <0x0 0x190000 0x10000>;
4165 status = "disabled";
4166 };
4167
4168 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
4169 compatible = "ti,sysc-omap4", "ti,sysc";
4170 reg = <0x1b0000 0x4>,
4171 <0x1b0010 0x4>;
4172 reg-names = "rev", "sysc";
4173 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4174 <SYSC_IDLE_NO>,
4175 <SYSC_IDLE_SMART>;
4176 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4177 <SYSC_IDLE_NO>,
4178 <SYSC_IDLE_SMART>;
4179 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
4180 clock-names = "fck";
4181 #address-cells = <1>;
4182 #size-cells = <1>;
4183 ranges = <0x0 0x1b0000 0x10000>;
4184 status = "disabled";
4185 };
4186
4187 target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
4188 compatible = "ti,sysc-omap4", "ti,sysc";
4189 reg = <0x1d0010 0x4>;
4190 reg-names = "sysc";
4191 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4192 <SYSC_IDLE_NO>,
4193 <SYSC_IDLE_SMART>;
4194 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4195 <SYSC_IDLE_NO>,
4196 <SYSC_IDLE_SMART>;
4197 clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
4198 clock-names = "fck";
4199 #address-cells = <1>;
4200 #size-cells = <1>;
4201 ranges = <0x0 0x1d0000 0x10000>;
4202
4203 vpe: vpe@0 {
4204 compatible = "ti,dra7-vpe";
4205 reg = <0x0000 0x120>,
4206 <0x0700 0x80>,
4207 <0x5700 0x18>,
4208 <0xd000 0x400>;
4209 reg-names = "vpe_top",
4210 "sc",
4211 "csc",
4212 "vpdma";
4213 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
4214 };
4215 };
4216 };
4217};
4218
4219&l4_wkup { /* 0x4ae00000 */
4220 compatible = "ti,dra7-l4-wkup", "simple-pm-bus";
4221 power-domains = <&prm_wkupaon>;
4222 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>;
4223 clock-names = "fck";
4224 reg = <0x4ae00000 0x800>,
4225 <0x4ae00800 0x800>,
4226 <0x4ae01000 0x1000>;
4227 reg-names = "ap", "la", "ia0";
4228 #address-cells = <1>;
4229 #size-cells = <1>;
4230 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
4231 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
4232 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */
4233 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */
4234
4235 segment@0 { /* 0x4ae00000 */
4236 compatible = "simple-pm-bus";
4237 #address-cells = <1>;
4238 #size-cells = <1>;
4239 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
4240 <0x00001000 0x00001000 0x001000>, /* ap 1 */
4241 <0x00000800 0x00000800 0x000800>, /* ap 2 */
4242 <0x00006000 0x00006000 0x002000>, /* ap 3 */
4243 <0x00008000 0x00008000 0x001000>, /* ap 4 */
4244 <0x00004000 0x00004000 0x001000>, /* ap 15 */
4245 <0x00005000 0x00005000 0x001000>, /* ap 16 */
4246 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */
4247 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */
4248
4249 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
4250 compatible = "ti,sysc-omap2", "ti,sysc";
4251 reg = <0x4000 0x4>,
4252 <0x4010 0x4>;
4253 reg-names = "rev", "sysc";
4254 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4255 <SYSC_IDLE_NO>,
4256 <SYSC_IDLE_SMART>,
4257 <SYSC_IDLE_SMART_WKUP>;
4258 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4259 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4260 clock-names = "fck";
4261 #address-cells = <1>;
4262 #size-cells = <1>;
4263 ranges = <0x0 0x4000 0x1000>;
4264
4265 counter32k: counter@0 {
4266 compatible = "ti,omap-counter32k";
4267 reg = <0x0 0x40>;
4268 };
4269 };
4270
4271 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */
4272 compatible = "ti,sysc-omap4", "ti,sysc";
4273 reg = <0x6000 0x4>;
4274 reg-names = "rev";
4275 #address-cells = <1>;
4276 #size-cells = <1>;
4277 ranges = <0x0 0x6000 0x2000>;
4278
4279 prm: prm@0 {
4280 compatible = "ti,dra7-prm", "simple-bus";
4281 reg = <0 0x3000>;
4282 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4283 #address-cells = <1>;
4284 #size-cells = <1>;
4285 ranges = <0 0 0x3000>;
4286
4287 prm_clocks: clocks {
4288 #address-cells = <1>;
4289 #size-cells = <0>;
4290 };
4291
4292 prm_clockdomains: clockdomains {
4293 };
4294 };
4295 };
4296
4297 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */
4298 compatible = "ti,sysc-omap4", "ti,sysc";
4299 reg = <0xc000 0x4>;
4300 reg-names = "rev";
4301 #address-cells = <1>;
4302 #size-cells = <1>;
4303 ranges = <0x0 0xc000 0x1000>;
4304
4305 scm_wkup: scm_conf@0 {
4306 compatible = "syscon";
4307 reg = <0 0x1000>;
4308 };
4309 };
4310 };
4311
4312 segment@10000 { /* 0x4ae10000 */
4313 compatible = "simple-pm-bus";
4314 #address-cells = <1>;
4315 #size-cells = <1>;
4316 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
4317 <0x00001000 0x00011000 0x001000>, /* ap 6 */
4318 <0x00004000 0x00014000 0x001000>, /* ap 7 */
4319 <0x00005000 0x00015000 0x001000>, /* ap 8 */
4320 <0x00008000 0x00018000 0x001000>, /* ap 9 */
4321 <0x00009000 0x00019000 0x001000>, /* ap 10 */
4322 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
4323 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
4324
4325 target-module@0 { /* 0x4ae10000, ap 5 20.0 */
4326 compatible = "ti,sysc-omap2", "ti,sysc";
4327 reg = <0x0 0x4>,
4328 <0x10 0x4>,
4329 <0x114 0x4>;
4330 reg-names = "rev", "sysc", "syss";
4331 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4332 SYSC_OMAP2_SOFTRESET |
4333 SYSC_OMAP2_AUTOIDLE)>;
4334 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4335 <SYSC_IDLE_NO>,
4336 <SYSC_IDLE_SMART>,
4337 <SYSC_IDLE_SMART_WKUP>;
4338 ti,syss-mask = <1>;
4339 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4340 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4341 <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
4342 clock-names = "fck", "dbclk";
4343 #address-cells = <1>;
4344 #size-cells = <1>;
4345 ranges = <0x0 0x0 0x1000>;
4346
4347 gpio1: gpio@0 {
4348 compatible = "ti,omap4-gpio";
4349 reg = <0x0 0x200>;
4350 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4351 gpio-controller;
4352 #gpio-cells = <2>;
4353 interrupt-controller;
4354 #interrupt-cells = <2>;
4355 };
4356 };
4357
4358 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
4359 compatible = "ti,sysc-omap2", "ti,sysc";
4360 reg = <0x4000 0x4>,
4361 <0x4010 0x4>,
4362 <0x4014 0x4>;
4363 reg-names = "rev", "sysc", "syss";
4364 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
4365 SYSC_OMAP2_SOFTRESET)>;
4366 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4367 <SYSC_IDLE_NO>,
4368 <SYSC_IDLE_SMART>,
4369 <SYSC_IDLE_SMART_WKUP>;
4370 ti,syss-mask = <1>;
4371 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4372 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4373 clock-names = "fck";
4374 #address-cells = <1>;
4375 #size-cells = <1>;
4376 ranges = <0x0 0x4000 0x1000>;
4377
4378 wdt2: wdt@0 {
4379 compatible = "ti,omap3-wdt";
4380 reg = <0x0 0x80>;
4381 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4382 };
4383 };
4384
4385 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
4386 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4387 reg = <0x8000 0x4>,
4388 <0x8010 0x4>;
4389 reg-names = "rev", "sysc";
4390 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4391 SYSC_OMAP4_SOFTRESET)>;
4392 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4393 <SYSC_IDLE_NO>,
4394 <SYSC_IDLE_SMART>,
4395 <SYSC_IDLE_SMART_WKUP>;
4396 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4397 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4398 clock-names = "fck";
4399 #address-cells = <1>;
4400 #size-cells = <1>;
4401 ranges = <0x0 0x8000 0x1000>;
4402
4403 timer1: timer@0 {
4404 compatible = "ti,omap5430-timer";
4405 reg = <0x0 0x80>;
4406 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
4407 clock-names = "fck";
4408 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4409 ti,timer-alwon;
4410 };
4411 };
4412
4413 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */
4414 compatible = "ti,sysc";
4415 status = "disabled";
4416 #address-cells = <1>;
4417 #size-cells = <1>;
4418 ranges = <0x0 0xc000 0x1000>;
4419 };
4420 };
4421
4422 segment@20000 { /* 0x4ae20000 */
4423 compatible = "simple-pm-bus";
4424 #address-cells = <1>;
4425 #size-cells = <1>;
4426 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
4427 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
4428 <0x00000000 0x00020000 0x001000>, /* ap 19 */
4429 <0x00001000 0x00021000 0x001000>, /* ap 20 */
4430 <0x00002000 0x00022000 0x001000>, /* ap 21 */
4431 <0x00003000 0x00023000 0x001000>, /* ap 22 */
4432 <0x00007000 0x00027000 0x000400>, /* ap 23 */
4433 <0x00008000 0x00028000 0x000800>, /* ap 24 */
4434 <0x00009000 0x00029000 0x000100>, /* ap 25 */
4435 <0x00008800 0x00028800 0x000200>, /* ap 26 */
4436 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */
4437 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */
4438 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */
4439 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */
4440
4441 target-module@0 { /* 0x4ae20000, ap 19 08.0 */
4442 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4443 reg = <0x0 0x4>,
4444 <0x10 0x4>;
4445 reg-names = "rev", "sysc";
4446 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4447 SYSC_OMAP4_SOFTRESET)>;
4448 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4449 <SYSC_IDLE_NO>,
4450 <SYSC_IDLE_SMART>,
4451 <SYSC_IDLE_SMART_WKUP>;
4452 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4453 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4454 clock-names = "fck";
4455 #address-cells = <1>;
4456 #size-cells = <1>;
4457 ranges = <0x0 0x0 0x1000>;
4458
4459 timer12: timer@0 {
4460 compatible = "ti,omap5430-timer";
4461 reg = <0x0 0x80>;
4462 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
4463 ti,timer-alwon;
4464 ti,timer-secure;
4465 };
4466 };
4467
4468 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */
4469 compatible = "ti,sysc";
4470 status = "disabled";
4471 #address-cells = <1>;
4472 #size-cells = <1>;
4473 ranges = <0x0 0x2000 0x1000>;
4474 };
4475
4476 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */
4477 compatible = "ti,sysc";
4478 status = "disabled";
4479 #address-cells = <1>;
4480 #size-cells = <1>;
4481 ranges = <0x00000000 0x00006000 0x00001000>,
4482 <0x00001000 0x00007000 0x00000400>,
4483 <0x00002000 0x00008000 0x00000800>,
4484 <0x00002800 0x00008800 0x00000200>,
4485 <0x00002a00 0x00008a00 0x00000100>,
4486 <0x00003000 0x00009000 0x00000100>;
4487 };
4488
4489 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
4490 compatible = "ti,sysc-omap2", "ti,sysc";
4491 reg = <0xb050 0x4>,
4492 <0xb054 0x4>,
4493 <0xb058 0x4>;
4494 reg-names = "rev", "sysc", "syss";
4495 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4496 SYSC_OMAP2_SOFTRESET |
4497 SYSC_OMAP2_AUTOIDLE)>;
4498 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4499 <SYSC_IDLE_NO>,
4500 <SYSC_IDLE_SMART>,
4501 <SYSC_IDLE_SMART_WKUP>;
4502 ti,syss-mask = <1>;
4503 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4504 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4505 clock-names = "fck";
4506 #address-cells = <1>;
4507 #size-cells = <1>;
4508 ranges = <0x0 0xb000 0x1000>;
4509
4510 uart10: serial@0 {
4511 compatible = "ti,dra742-uart";
4512 reg = <0x0 0x100>;
4513 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
4514 clock-frequency = <48000000>;
4515 status = "disabled";
4516 };
4517 };
4518
4519 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */
4520 compatible = "ti,sysc";
4521 status = "disabled";
4522 #address-cells = <1>;
4523 #size-cells = <1>;
4524 ranges = <0x0 0xf000 0x1000>;
4525 };
4526 };
4527
4528 segment@30000 { /* 0x4ae30000 */
4529 compatible = "simple-pm-bus";
4530 #address-cells = <1>;
4531 #size-cells = <1>;
4532 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
4533 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */
4534 <0x00000000 0x00030000 0x001000>, /* ap 33 */
4535 <0x00001000 0x00031000 0x001000>, /* ap 34 */
4536 <0x00002000 0x00032000 0x001000>, /* ap 35 */
4537 <0x00003000 0x00033000 0x001000>, /* ap 36 */
4538 <0x00004000 0x00034000 0x001000>, /* ap 37 */
4539 <0x00005000 0x00035000 0x001000>, /* ap 38 */
4540 <0x00006000 0x00036000 0x001000>, /* ap 39 */
4541 <0x00007000 0x00037000 0x001000>, /* ap 40 */
4542 <0x00008000 0x00038000 0x001000>, /* ap 41 */
4543 <0x00009000 0x00039000 0x001000>, /* ap 42 */
4544 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */
4545
4546 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */
4547 compatible = "ti,sysc";
4548 status = "disabled";
4549 #address-cells = <1>;
4550 #size-cells = <1>;
4551 ranges = <0x0 0x1000 0x1000>;
4552 };
4553
4554 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */
4555 compatible = "ti,sysc";
4556 status = "disabled";
4557 #address-cells = <1>;
4558 #size-cells = <1>;
4559 ranges = <0x0 0x3000 0x1000>;
4560 };
4561
4562 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */
4563 compatible = "ti,sysc";
4564 status = "disabled";
4565 #address-cells = <1>;
4566 #size-cells = <1>;
4567 ranges = <0x0 0x5000 0x1000>;
4568 };
4569
4570 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */
4571 compatible = "ti,sysc";
4572 status = "disabled";
4573 #address-cells = <1>;
4574 #size-cells = <1>;
4575 ranges = <0x0 0x7000 0x1000>;
4576 };
4577
4578 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */
4579 compatible = "ti,sysc";
4580 status = "disabled";
4581 #address-cells = <1>;
4582 #size-cells = <1>;
4583 ranges = <0x0 0x9000 0x1000>;
4584 };
4585
4586 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
4587 compatible = "ti,sysc-omap4", "ti,sysc";
4588 reg = <0xc020 0x4>;
4589 reg-names = "rev";
4590 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4591 clock-names = "fck";
4592 #address-cells = <1>;
4593 #size-cells = <1>;
4594 ranges = <0x0 0xc000 0x2000>;
4595
4596 dcan1: can@0 {
4597 compatible = "ti,dra7-d_can";
4598 reg = <0x0 0x2000>;
4599 syscon-raminit = <&scm_conf 0x558 0>;
4600 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
4601 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
4602 status = "disabled";
4603 };
4604 };
4605 };
4606};
4607
1&l4_cfg { /* 0x4a000000 */
2 compatible = "ti,dra7-l4-cfg", "simple-bus";
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
6 reg-names = "ap", "la", "ia0";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
12
13 segment@0 { /* 0x4a000000 */
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
19 <0x00001000 0x00001000 0x001000>, /* ap 2 */
20 <0x00002000 0x00002000 0x002000>, /* ap 3 */
21 <0x00004000 0x00004000 0x001000>, /* ap 4 */
22 <0x00005000 0x00005000 0x001000>, /* ap 5 */
23 <0x00006000 0x00006000 0x001000>, /* ap 6 */
24 <0x00008000 0x00008000 0x002000>, /* ap 7 */
25 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
26 <0x00056000 0x00056000 0x001000>, /* ap 9 */
27 <0x00057000 0x00057000 0x001000>, /* ap 10 */
28 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
29 <0x00060000 0x00060000 0x001000>, /* ap 12 */
30 <0x00080000 0x00080000 0x008000>, /* ap 13 */
31 <0x00088000 0x00088000 0x001000>, /* ap 14 */
32 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
33 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
34 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
35 <0x000da000 0x000da000 0x001000>, /* ap 18 */
36 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
37 <0x000de000 0x000de000 0x001000>, /* ap 20 */
38 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
39 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
40 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
41 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
42 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
43 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
44 <0x00090000 0x00090000 0x008000>, /* ap 59 */
45 <0x00098000 0x00098000 0x001000>; /* ap 60 */
46
47 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
48 compatible = "ti,sysc-omap4", "ti,sysc";
49 reg = <0x2000 0x4>;
50 reg-names = "rev";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges = <0x0 0x2000 0x2000>;
54
55 scm: scm@0 {
56 compatible = "ti,dra7-scm-core", "simple-bus";
57 reg = <0 0x2000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges = <0 0 0x2000>;
61
62 scm_conf: scm_conf@0 {
63 compatible = "syscon", "simple-bus";
64 reg = <0x0 0x1400>;
65 #address-cells = <1>;
66 #size-cells = <1>;
67 ranges = <0 0x0 0x1400>;
68
69 pbias_regulator: pbias_regulator@e00 {
70 compatible = "ti,pbias-dra7", "ti,pbias-omap";
71 reg = <0xe00 0x4>;
72 syscon = <&scm_conf>;
73 pbias_mmc_reg: pbias_mmc_omap5 {
74 regulator-name = "pbias_mmc_omap5";
75 regulator-min-microvolt = <1800000>;
76 regulator-max-microvolt = <3300000>;
77 };
78 };
79
80 phy_gmii_sel: phy-gmii-sel {
81 compatible = "ti,dra7xx-phy-gmii-sel";
82 reg = <0x554 0x4>;
83 #phy-cells = <1>;
84 };
85
86 scm_conf_clocks: clocks {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 };
90 };
91
92 dra7_pmx_core: pinmux@1400 {
93 compatible = "ti,dra7-padconf",
94 "pinctrl-single";
95 reg = <0x1400 0x0468>;
96 #address-cells = <1>;
97 #size-cells = <0>;
98 #pinctrl-cells = <1>;
99 #interrupt-cells = <1>;
100 interrupt-controller;
101 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = <0x3fffffff>;
103 };
104
105 scm_conf1: scm_conf@1c04 {
106 compatible = "syscon";
107 reg = <0x1c04 0x0020>;
108 #syscon-cells = <2>;
109 };
110
111 scm_conf_pcie: scm_conf@1c24 {
112 compatible = "syscon";
113 reg = <0x1c24 0x0024>;
114 };
115
116 sdma_xbar: dma-router@b78 {
117 compatible = "ti,dra7-dma-crossbar";
118 reg = <0xb78 0xfc>;
119 #dma-cells = <1>;
120 dma-requests = <205>;
121 ti,dma-safe-map = <0>;
122 dma-masters = <&sdma>;
123 };
124
125 edma_xbar: dma-router@c78 {
126 compatible = "ti,dra7-dma-crossbar";
127 reg = <0xc78 0x7c>;
128 #dma-cells = <2>;
129 dma-requests = <204>;
130 ti,dma-safe-map = <0>;
131 dma-masters = <&edma>;
132 };
133 };
134 };
135
136 target-module@5000 { /* 0x4a005000, ap 5 10.0 */
137 compatible = "ti,sysc-omap4", "ti,sysc";
138 reg = <0x5000 0x4>;
139 reg-names = "rev";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x0 0x5000 0x1000>;
143
144 cm_core_aon: cm_core_aon@0 {
145 compatible = "ti,dra7-cm-core-aon",
146 "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 reg = <0 0x2000>;
150 ranges = <0 0 0x2000>;
151
152 cm_core_aon_clocks: clocks {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 };
156
157 cm_core_aon_clockdomains: clockdomains {
158 };
159 };
160 };
161
162 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
163 compatible = "ti,sysc-omap4", "ti,sysc";
164 reg = <0x8000 0x4>;
165 reg-names = "rev";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0x0 0x8000 0x2000>;
169
170 cm_core: cm_core@0 {
171 compatible = "ti,dra7-cm-core", "simple-bus";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0 0x3000>;
175 ranges = <0 0 0x3000>;
176
177 cm_core_clocks: clocks {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 };
181
182 cm_core_clockdomains: clockdomains {
183 };
184 };
185 };
186
187 target-module@56000 { /* 0x4a056000, ap 9 02.0 */
188 compatible = "ti,sysc-omap2", "ti,sysc";
189 reg = <0x56000 0x4>,
190 <0x5602c 0x4>,
191 <0x56028 0x4>;
192 reg-names = "rev", "sysc", "syss";
193 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
194 SYSC_OMAP2_EMUFREE |
195 SYSC_OMAP2_SOFTRESET |
196 SYSC_OMAP2_AUTOIDLE)>;
197 ti,sysc-midle = <SYSC_IDLE_FORCE>,
198 <SYSC_IDLE_NO>,
199 <SYSC_IDLE_SMART>,
200 <SYSC_IDLE_SMART_WKUP>;
201 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
202 <SYSC_IDLE_NO>,
203 <SYSC_IDLE_SMART>,
204 <SYSC_IDLE_SMART_WKUP>;
205 ti,syss-mask = <1>;
206 /* Domains (P, C): core_pwrdm, dma_clkdm */
207 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
208 clock-names = "fck";
209 #address-cells = <1>;
210 #size-cells = <1>;
211 ranges = <0x0 0x56000 0x1000>;
212
213 sdma: dma-controller@0 {
214 compatible = "ti,omap4430-sdma", "ti,omap-sdma";
215 reg = <0x0 0x1000>;
216 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
220 #dma-cells = <1>;
221 dma-channels = <32>;
222 dma-requests = <127>;
223 };
224 };
225
226 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
227 compatible = "ti,sysc";
228 status = "disabled";
229 #address-cells = <1>;
230 #size-cells = <1>;
231 ranges = <0x0 0x5e000 0x2000>;
232 };
233
234 target-module@80000 { /* 0x4a080000, ap 13 20.0 */
235 compatible = "ti,sysc-omap2", "ti,sysc";
236 reg = <0x80000 0x4>,
237 <0x80010 0x4>,
238 <0x80014 0x4>;
239 reg-names = "rev", "sysc", "syss";
240 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
241 SYSC_OMAP2_AUTOIDLE)>;
242 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
243 <SYSC_IDLE_NO>,
244 <SYSC_IDLE_SMART>;
245 ti,syss-mask = <1>;
246 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
247 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
248 clock-names = "fck";
249 #address-cells = <1>;
250 #size-cells = <1>;
251 ranges = <0x0 0x80000 0x8000>;
252
253 ocp2scp@0 {
254 compatible = "ti,omap-ocp2scp";
255 #address-cells = <1>;
256 #size-cells = <1>;
257 ranges = <0 0 0x8000>;
258 reg = <0x0 0x20>;
259
260 usb2_phy1: phy@4000 {
261 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
262 reg = <0x4000 0x400>;
263 syscon-phy-power = <&scm_conf 0x300>;
264 clocks = <&usb_phy1_always_on_clk32k>,
265 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
266 clock-names = "wkupclk",
267 "refclk";
268 #phy-cells = <0>;
269 };
270
271 usb2_phy2: phy@5000 {
272 compatible = "ti,dra7x-usb2-phy2",
273 "ti,omap-usb2";
274 reg = <0x5000 0x400>;
275 syscon-phy-power = <&scm_conf 0xe74>;
276 clocks = <&usb_phy2_always_on_clk32k>,
277 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
278 clock-names = "wkupclk",
279 "refclk";
280 #phy-cells = <0>;
281 };
282
283 usb3_phy1: phy@4400 {
284 compatible = "ti,omap-usb3";
285 reg = <0x4400 0x80>,
286 <0x4800 0x64>,
287 <0x4c00 0x40>;
288 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
289 syscon-phy-power = <&scm_conf 0x370>;
290 clocks = <&usb_phy3_always_on_clk32k>,
291 <&sys_clkin1>,
292 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
293 clock-names = "wkupclk",
294 "sysclk",
295 "refclk";
296 #phy-cells = <0>;
297 };
298 };
299 };
300
301 target-module@90000 { /* 0x4a090000, ap 59 42.0 */
302 compatible = "ti,sysc-omap2", "ti,sysc";
303 reg = <0x90000 0x4>,
304 <0x90010 0x4>,
305 <0x90014 0x4>;
306 reg-names = "rev", "sysc", "syss";
307 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
308 SYSC_OMAP2_AUTOIDLE)>;
309 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
310 <SYSC_IDLE_NO>,
311 <SYSC_IDLE_SMART>;
312 ti,syss-mask = <1>;
313 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
314 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
315 clock-names = "fck";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0x0 0x90000 0x8000>;
319
320 ocp2scp@0 {
321 compatible = "ti,omap-ocp2scp";
322 #address-cells = <1>;
323 #size-cells = <1>;
324 ranges = <0 0 0x8000>;
325 reg = <0x0 0x20>;
326
327 pcie1_phy: pciephy@4000 {
328 compatible = "ti,phy-pipe3-pcie";
329 reg = <0x4000 0x80>, /* phy_rx */
330 <0x4400 0x64>; /* phy_tx */
331 reg-names = "phy_rx", "phy_tx";
332 syscon-phy-power = <&scm_conf_pcie 0x1c>;
333 syscon-pcs = <&scm_conf_pcie 0x10>;
334 clocks = <&dpll_pcie_ref_ck>,
335 <&dpll_pcie_ref_m2ldo_ck>,
336 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
337 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
338 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
339 <&optfclk_pciephy_div>,
340 <&sys_clkin1>;
341 clock-names = "dpll_ref", "dpll_ref_m2",
342 "wkupclk", "refclk",
343 "div-clk", "phy-div", "sysclk";
344 #phy-cells = <0>;
345 };
346
347 pcie2_phy: pciephy@5000 {
348 compatible = "ti,phy-pipe3-pcie";
349 reg = <0x5000 0x80>, /* phy_rx */
350 <0x5400 0x64>; /* phy_tx */
351 reg-names = "phy_rx", "phy_tx";
352 syscon-phy-power = <&scm_conf_pcie 0x20>;
353 syscon-pcs = <&scm_conf_pcie 0x10>;
354 clocks = <&dpll_pcie_ref_ck>,
355 <&dpll_pcie_ref_m2ldo_ck>,
356 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
357 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
358 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
359 <&optfclk_pciephy_div>,
360 <&sys_clkin1>;
361 clock-names = "dpll_ref", "dpll_ref_m2",
362 "wkupclk", "refclk",
363 "div-clk", "phy-div", "sysclk";
364 #phy-cells = <0>;
365 status = "disabled";
366 };
367
368 sata_phy: phy@6000 {
369 compatible = "ti,phy-pipe3-sata";
370 reg = <0x6000 0x80>, /* phy_rx */
371 <0x6400 0x64>, /* phy_tx */
372 <0x6800 0x40>; /* pll_ctrl */
373 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
374 syscon-phy-power = <&scm_conf 0x374>;
375 clocks = <&sys_clkin1>,
376 <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
377 clock-names = "sysclk", "refclk";
378 syscon-pllreset = <&scm_conf 0x3fc>;
379 #phy-cells = <0>;
380 };
381 };
382 };
383
384 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
385 compatible = "ti,sysc";
386 status = "disabled";
387 #address-cells = <1>;
388 #size-cells = <1>;
389 ranges = <0x0 0xa0000 0x8000>;
390 };
391
392 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
393 compatible = "ti,sysc-omap4-sr", "ti,sysc";
394 reg = <0xd9038 0x4>;
395 reg-names = "sysc";
396 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
397 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
398 <SYSC_IDLE_NO>,
399 <SYSC_IDLE_SMART>,
400 <SYSC_IDLE_SMART_WKUP>;
401 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
402 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
403 clock-names = "fck";
404 #address-cells = <1>;
405 #size-cells = <1>;
406 ranges = <0x0 0xd9000 0x1000>;
407
408 /* SmartReflex child device marked reserved in TRM */
409 };
410
411 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
412 compatible = "ti,sysc-omap4-sr", "ti,sysc";
413 reg = <0xdd038 0x4>;
414 reg-names = "sysc";
415 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
416 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
417 <SYSC_IDLE_NO>,
418 <SYSC_IDLE_SMART>,
419 <SYSC_IDLE_SMART_WKUP>;
420 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
421 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
422 clock-names = "fck";
423 #address-cells = <1>;
424 #size-cells = <1>;
425 ranges = <0x0 0xdd000 0x1000>;
426
427 /* SmartReflex child device marked reserved in TRM */
428 };
429
430 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
431 compatible = "ti,sysc";
432 status = "disabled";
433 #address-cells = <1>;
434 #size-cells = <1>;
435 ranges = <0x0 0xe0000 0x1000>;
436 };
437
438 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
439 compatible = "ti,sysc-omap4", "ti,sysc";
440 reg = <0xf4000 0x4>,
441 <0xf4010 0x4>;
442 reg-names = "rev", "sysc";
443 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
444 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
445 <SYSC_IDLE_NO>,
446 <SYSC_IDLE_SMART>;
447 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
448 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
449 clock-names = "fck";
450 #address-cells = <1>;
451 #size-cells = <1>;
452 ranges = <0x0 0xf4000 0x1000>;
453
454 mailbox1: mailbox@0 {
455 compatible = "ti,omap4-mailbox";
456 reg = <0x0 0x200>;
457 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
460 #mbox-cells = <1>;
461 ti,mbox-num-users = <3>;
462 ti,mbox-num-fifos = <8>;
463 status = "disabled";
464 };
465 };
466
467 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
468 compatible = "ti,sysc-omap2", "ti,sysc";
469 reg = <0xf6000 0x4>,
470 <0xf6010 0x4>,
471 <0xf6014 0x4>;
472 reg-names = "rev", "sysc", "syss";
473 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
474 SYSC_OMAP2_SOFTRESET |
475 SYSC_OMAP2_AUTOIDLE)>;
476 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
477 <SYSC_IDLE_NO>,
478 <SYSC_IDLE_SMART>;
479 ti,syss-mask = <1>;
480 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
481 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
482 clock-names = "fck";
483 #address-cells = <1>;
484 #size-cells = <1>;
485 ranges = <0x0 0xf6000 0x1000>;
486
487 hwspinlock: spinlock@0 {
488 compatible = "ti,omap4-hwspinlock";
489 reg = <0x0 0x1000>;
490 #hwlock-cells = <1>;
491 };
492 };
493 };
494
495 segment@100000 { /* 0x4a100000 */
496 compatible = "simple-bus";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
500 <0x00003000 0x00103000 0x001000>, /* ap 28 */
501 <0x00008000 0x00108000 0x001000>, /* ap 29 */
502 <0x00009000 0x00109000 0x001000>, /* ap 30 */
503 <0x00040000 0x00140000 0x010000>, /* ap 31 */
504 <0x00050000 0x00150000 0x001000>, /* ap 32 */
505 <0x00051000 0x00151000 0x001000>, /* ap 33 */
506 <0x00052000 0x00152000 0x001000>, /* ap 34 */
507 <0x00053000 0x00153000 0x001000>, /* ap 35 */
508 <0x00054000 0x00154000 0x001000>, /* ap 36 */
509 <0x00055000 0x00155000 0x001000>, /* ap 37 */
510 <0x00056000 0x00156000 0x001000>, /* ap 38 */
511 <0x00057000 0x00157000 0x001000>, /* ap 39 */
512 <0x00058000 0x00158000 0x001000>, /* ap 40 */
513 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
514 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
515 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
516 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
517 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
518 <0x00060000 0x00160000 0x001000>, /* ap 48 */
519 <0x00061000 0x00161000 0x001000>, /* ap 49 */
520 <0x00062000 0x00162000 0x001000>, /* ap 50 */
521 <0x00063000 0x00163000 0x001000>, /* ap 51 */
522 <0x00064000 0x00164000 0x001000>, /* ap 52 */
523 <0x00065000 0x00165000 0x001000>, /* ap 53 */
524 <0x00066000 0x00166000 0x001000>, /* ap 54 */
525 <0x00067000 0x00167000 0x001000>, /* ap 55 */
526 <0x00068000 0x00168000 0x001000>, /* ap 56 */
527 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
528 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
529 <0x00071000 0x00171000 0x001000>, /* ap 61 */
530 <0x00072000 0x00172000 0x001000>, /* ap 62 */
531 <0x00073000 0x00173000 0x001000>, /* ap 63 */
532 <0x00074000 0x00174000 0x001000>, /* ap 64 */
533 <0x00075000 0x00175000 0x001000>, /* ap 65 */
534 <0x00076000 0x00176000 0x001000>, /* ap 66 */
535 <0x00077000 0x00177000 0x001000>, /* ap 67 */
536 <0x00078000 0x00178000 0x001000>, /* ap 68 */
537 <0x00081000 0x00181000 0x001000>, /* ap 69 */
538 <0x00082000 0x00182000 0x001000>, /* ap 70 */
539 <0x00083000 0x00183000 0x001000>, /* ap 71 */
540 <0x00084000 0x00184000 0x001000>, /* ap 72 */
541 <0x00085000 0x00185000 0x001000>, /* ap 73 */
542 <0x00086000 0x00186000 0x001000>, /* ap 74 */
543 <0x00087000 0x00187000 0x001000>, /* ap 75 */
544 <0x00088000 0x00188000 0x001000>, /* ap 76 */
545 <0x00069000 0x00169000 0x001000>, /* ap 103 */
546 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
547 <0x00079000 0x00179000 0x001000>, /* ap 105 */
548 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
549 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
550 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
551 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
552 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
553 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
554 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
555 <0x00059000 0x00159000 0x001000>, /* ap 125 */
556 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
557
558 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
559 compatible = "ti,sysc";
560 status = "disabled";
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges = <0x0 0x2000 0x1000>;
564 };
565
566 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
567 compatible = "ti,sysc";
568 status = "disabled";
569 #address-cells = <1>;
570 #size-cells = <1>;
571 ranges = <0x0 0x8000 0x1000>;
572 };
573
574 target-module@40000 { /* 0x4a140000, ap 31 06.0 */
575 compatible = "ti,sysc";
576 status = "disabled";
577 #address-cells = <1>;
578 #size-cells = <1>;
579 ranges = <0x0 0x40000 0x10000>;
580 };
581
582 target-module@51000 { /* 0x4a151000, ap 33 50.0 */
583 compatible = "ti,sysc";
584 status = "disabled";
585 #address-cells = <1>;
586 #size-cells = <1>;
587 ranges = <0x0 0x51000 0x1000>;
588 };
589
590 target-module@53000 { /* 0x4a153000, ap 35 54.0 */
591 compatible = "ti,sysc";
592 status = "disabled";
593 #address-cells = <1>;
594 #size-cells = <1>;
595 ranges = <0x0 0x53000 0x1000>;
596 };
597
598 target-module@55000 { /* 0x4a155000, ap 37 46.0 */
599 compatible = "ti,sysc";
600 status = "disabled";
601 #address-cells = <1>;
602 #size-cells = <1>;
603 ranges = <0x0 0x55000 0x1000>;
604 };
605
606 target-module@57000 { /* 0x4a157000, ap 39 58.0 */
607 compatible = "ti,sysc";
608 status = "disabled";
609 #address-cells = <1>;
610 #size-cells = <1>;
611 ranges = <0x0 0x57000 0x1000>;
612 };
613
614 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
615 compatible = "ti,sysc";
616 status = "disabled";
617 #address-cells = <1>;
618 #size-cells = <1>;
619 ranges = <0x0 0x59000 0x1000>;
620 };
621
622 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
623 compatible = "ti,sysc";
624 status = "disabled";
625 #address-cells = <1>;
626 #size-cells = <1>;
627 ranges = <0x0 0x5b000 0x1000>;
628 };
629
630 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
631 compatible = "ti,sysc";
632 status = "disabled";
633 #address-cells = <1>;
634 #size-cells = <1>;
635 ranges = <0x0 0x5d000 0x1000>;
636 };
637
638 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
639 compatible = "ti,sysc";
640 status = "disabled";
641 #address-cells = <1>;
642 #size-cells = <1>;
643 ranges = <0x0 0x5f000 0x1000>;
644 };
645
646 target-module@61000 { /* 0x4a161000, ap 49 32.0 */
647 compatible = "ti,sysc";
648 status = "disabled";
649 #address-cells = <1>;
650 #size-cells = <1>;
651 ranges = <0x0 0x61000 0x1000>;
652 };
653
654 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
655 compatible = "ti,sysc";
656 status = "disabled";
657 #address-cells = <1>;
658 #size-cells = <1>;
659 ranges = <0x0 0x63000 0x1000>;
660 };
661
662 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
663 compatible = "ti,sysc";
664 status = "disabled";
665 #address-cells = <1>;
666 #size-cells = <1>;
667 ranges = <0x0 0x65000 0x1000>;
668 };
669
670 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
671 compatible = "ti,sysc";
672 status = "disabled";
673 #address-cells = <1>;
674 #size-cells = <1>;
675 ranges = <0x0 0x67000 0x1000>;
676 };
677
678 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
679 compatible = "ti,sysc";
680 status = "disabled";
681 #address-cells = <1>;
682 #size-cells = <1>;
683 ranges = <0x0 0x69000 0x1000>;
684 };
685
686 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
687 compatible = "ti,sysc";
688 status = "disabled";
689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0x0 0x6b000 0x1000>;
692 };
693
694 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
695 compatible = "ti,sysc";
696 status = "disabled";
697 #address-cells = <1>;
698 #size-cells = <1>;
699 ranges = <0x0 0x6d000 0x1000>;
700 };
701
702 target-module@71000 { /* 0x4a171000, ap 61 48.0 */
703 compatible = "ti,sysc";
704 status = "disabled";
705 #address-cells = <1>;
706 #size-cells = <1>;
707 ranges = <0x0 0x71000 0x1000>;
708 };
709
710 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
711 compatible = "ti,sysc";
712 status = "disabled";
713 #address-cells = <1>;
714 #size-cells = <1>;
715 ranges = <0x0 0x73000 0x1000>;
716 };
717
718 target-module@75000 { /* 0x4a175000, ap 65 64.0 */
719 compatible = "ti,sysc";
720 status = "disabled";
721 #address-cells = <1>;
722 #size-cells = <1>;
723 ranges = <0x0 0x75000 0x1000>;
724 };
725
726 target-module@77000 { /* 0x4a177000, ap 67 66.0 */
727 compatible = "ti,sysc";
728 status = "disabled";
729 #address-cells = <1>;
730 #size-cells = <1>;
731 ranges = <0x0 0x77000 0x1000>;
732 };
733
734 target-module@79000 { /* 0x4a179000, ap 105 34.0 */
735 compatible = "ti,sysc";
736 status = "disabled";
737 #address-cells = <1>;
738 #size-cells = <1>;
739 ranges = <0x0 0x79000 0x1000>;
740 };
741
742 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
743 compatible = "ti,sysc";
744 status = "disabled";
745 #address-cells = <1>;
746 #size-cells = <1>;
747 ranges = <0x0 0x7b000 0x1000>;
748 };
749
750 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
751 compatible = "ti,sysc";
752 status = "disabled";
753 #address-cells = <1>;
754 #size-cells = <1>;
755 ranges = <0x0 0x7d000 0x1000>;
756 };
757
758 target-module@81000 { /* 0x4a181000, ap 69 26.0 */
759 compatible = "ti,sysc";
760 status = "disabled";
761 #address-cells = <1>;
762 #size-cells = <1>;
763 ranges = <0x0 0x81000 0x1000>;
764 };
765
766 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
767 compatible = "ti,sysc";
768 status = "disabled";
769 #address-cells = <1>;
770 #size-cells = <1>;
771 ranges = <0x0 0x83000 0x1000>;
772 };
773
774 target-module@85000 { /* 0x4a185000, ap 73 36.0 */
775 compatible = "ti,sysc";
776 status = "disabled";
777 #address-cells = <1>;
778 #size-cells = <1>;
779 ranges = <0x0 0x85000 0x1000>;
780 };
781
782 target-module@87000 { /* 0x4a187000, ap 75 74.0 */
783 compatible = "ti,sysc";
784 status = "disabled";
785 #address-cells = <1>;
786 #size-cells = <1>;
787 ranges = <0x0 0x87000 0x1000>;
788 };
789 };
790
791 segment@200000 { /* 0x4a200000 */
792 compatible = "simple-bus";
793 #address-cells = <1>;
794 #size-cells = <1>;
795 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
796 <0x00019000 0x00219000 0x001000>, /* ap 44 */
797 <0x00000000 0x00200000 0x001000>, /* ap 77 */
798 <0x00001000 0x00201000 0x001000>, /* ap 78 */
799 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
800 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
801 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
802 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
803 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
804 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
805 <0x00010000 0x00210000 0x001000>, /* ap 85 */
806 <0x00011000 0x00211000 0x001000>, /* ap 86 */
807 <0x00012000 0x00212000 0x001000>, /* ap 87 */
808 <0x00013000 0x00213000 0x001000>, /* ap 88 */
809 <0x00014000 0x00214000 0x001000>, /* ap 89 */
810 <0x00015000 0x00215000 0x001000>, /* ap 90 */
811 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
812 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
813 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
814 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
815 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
816 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
817 <0x00020000 0x00220000 0x001000>, /* ap 97 */
818 <0x00021000 0x00221000 0x001000>, /* ap 98 */
819 <0x00024000 0x00224000 0x001000>, /* ap 99 */
820 <0x00025000 0x00225000 0x001000>, /* ap 100 */
821 <0x00026000 0x00226000 0x001000>, /* ap 101 */
822 <0x00027000 0x00227000 0x001000>, /* ap 102 */
823 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
824 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
825 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
826 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
827 <0x00030000 0x00230000 0x001000>, /* ap 113 */
828 <0x00031000 0x00231000 0x001000>, /* ap 114 */
829 <0x00032000 0x00232000 0x001000>, /* ap 115 */
830 <0x00033000 0x00233000 0x001000>, /* ap 116 */
831 <0x00034000 0x00234000 0x001000>, /* ap 117 */
832 <0x00035000 0x00235000 0x001000>, /* ap 118 */
833 <0x00036000 0x00236000 0x001000>, /* ap 119 */
834 <0x00037000 0x00237000 0x001000>, /* ap 120 */
835 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
836 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
837
838 target-module@0 { /* 0x4a200000, ap 77 3e.0 */
839 compatible = "ti,sysc";
840 status = "disabled";
841 #address-cells = <1>;
842 #size-cells = <1>;
843 ranges = <0x0 0x0 0x1000>;
844 };
845
846 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
847 compatible = "ti,sysc";
848 status = "disabled";
849 #address-cells = <1>;
850 #size-cells = <1>;
851 ranges = <0x0 0xa000 0x1000>;
852 };
853
854 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
855 compatible = "ti,sysc";
856 status = "disabled";
857 #address-cells = <1>;
858 #size-cells = <1>;
859 ranges = <0x0 0xc000 0x1000>;
860 };
861
862 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
863 compatible = "ti,sysc";
864 status = "disabled";
865 #address-cells = <1>;
866 #size-cells = <1>;
867 ranges = <0x0 0xe000 0x1000>;
868 };
869
870 target-module@10000 { /* 0x4a210000, ap 85 14.0 */
871 compatible = "ti,sysc";
872 status = "disabled";
873 #address-cells = <1>;
874 #size-cells = <1>;
875 ranges = <0x0 0x10000 0x1000>;
876 };
877
878 target-module@12000 { /* 0x4a212000, ap 87 16.0 */
879 compatible = "ti,sysc";
880 status = "disabled";
881 #address-cells = <1>;
882 #size-cells = <1>;
883 ranges = <0x0 0x12000 0x1000>;
884 };
885
886 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
887 compatible = "ti,sysc";
888 status = "disabled";
889 #address-cells = <1>;
890 #size-cells = <1>;
891 ranges = <0x0 0x14000 0x1000>;
892 };
893
894 target-module@18000 { /* 0x4a218000, ap 43 12.0 */
895 compatible = "ti,sysc";
896 status = "disabled";
897 #address-cells = <1>;
898 #size-cells = <1>;
899 ranges = <0x0 0x18000 0x1000>;
900 };
901
902 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
903 compatible = "ti,sysc";
904 status = "disabled";
905 #address-cells = <1>;
906 #size-cells = <1>;
907 ranges = <0x0 0x1a000 0x1000>;
908 };
909
910 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
911 compatible = "ti,sysc";
912 status = "disabled";
913 #address-cells = <1>;
914 #size-cells = <1>;
915 ranges = <0x0 0x1c000 0x1000>;
916 };
917
918 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
919 compatible = "ti,sysc";
920 status = "disabled";
921 #address-cells = <1>;
922 #size-cells = <1>;
923 ranges = <0x0 0x1e000 0x1000>;
924 };
925
926 target-module@20000 { /* 0x4a220000, ap 97 24.0 */
927 compatible = "ti,sysc";
928 status = "disabled";
929 #address-cells = <1>;
930 #size-cells = <1>;
931 ranges = <0x0 0x20000 0x1000>;
932 };
933
934 target-module@24000 { /* 0x4a224000, ap 99 44.0 */
935 compatible = "ti,sysc";
936 status = "disabled";
937 #address-cells = <1>;
938 #size-cells = <1>;
939 ranges = <0x0 0x24000 0x1000>;
940 };
941
942 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
943 compatible = "ti,sysc";
944 status = "disabled";
945 #address-cells = <1>;
946 #size-cells = <1>;
947 ranges = <0x0 0x26000 0x1000>;
948 };
949
950 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
951 compatible = "ti,sysc";
952 status = "disabled";
953 #address-cells = <1>;
954 #size-cells = <1>;
955 ranges = <0x0 0x2a000 0x1000>;
956 };
957
958 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
959 compatible = "ti,sysc";
960 status = "disabled";
961 #address-cells = <1>;
962 #size-cells = <1>;
963 ranges = <0x0 0x2c000 0x1000>;
964 };
965
966 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
967 compatible = "ti,sysc";
968 status = "disabled";
969 #address-cells = <1>;
970 #size-cells = <1>;
971 ranges = <0x0 0x2e000 0x1000>;
972 };
973
974 target-module@30000 { /* 0x4a230000, ap 113 70.0 */
975 compatible = "ti,sysc";
976 status = "disabled";
977 #address-cells = <1>;
978 #size-cells = <1>;
979 ranges = <0x0 0x30000 0x1000>;
980 };
981
982 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
983 compatible = "ti,sysc";
984 status = "disabled";
985 #address-cells = <1>;
986 #size-cells = <1>;
987 ranges = <0x0 0x32000 0x1000>;
988 };
989
990 target-module@34000 { /* 0x4a234000, ap 117 76.1 */
991 compatible = "ti,sysc";
992 status = "disabled";
993 #address-cells = <1>;
994 #size-cells = <1>;
995 ranges = <0x0 0x34000 0x1000>;
996 };
997
998 target-module@36000 { /* 0x4a236000, ap 119 62.0 */
999 compatible = "ti,sysc";
1000 status = "disabled";
1001 #address-cells = <1>;
1002 #size-cells = <1>;
1003 ranges = <0x0 0x36000 0x1000>;
1004 };
1005 };
1006};
1007
1008&l4_per1 { /* 0x48000000 */
1009 compatible = "ti,dra7-l4-per1", "simple-bus";
1010 reg = <0x48000000 0x800>,
1011 <0x48000800 0x800>,
1012 <0x48001000 0x400>,
1013 <0x48001400 0x400>,
1014 <0x48001800 0x400>,
1015 <0x48001c00 0x400>;
1016 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1017 #address-cells = <1>;
1018 #size-cells = <1>;
1019 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1020 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1021
1022 segment@0 { /* 0x48000000 */
1023 compatible = "simple-bus";
1024 #address-cells = <1>;
1025 #size-cells = <1>;
1026 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1027 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1028 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1029 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1030 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1031 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1032 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1033 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1034 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1035 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1036 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1037 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1038 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1039 <0x00055000 0x00055000 0x001000>, /* ap 13 */
1040 <0x00056000 0x00056000 0x001000>, /* ap 14 */
1041 <0x00057000 0x00057000 0x001000>, /* ap 15 */
1042 <0x00058000 0x00058000 0x001000>, /* ap 16 */
1043 <0x00059000 0x00059000 0x001000>, /* ap 17 */
1044 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
1045 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
1046 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
1047 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
1048 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
1049 <0x00060000 0x00060000 0x001000>, /* ap 23 */
1050 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
1051 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
1052 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1053 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1054 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1055 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1056 <0x00070000 0x00070000 0x001000>, /* ap 30 */
1057 <0x00071000 0x00071000 0x001000>, /* ap 31 */
1058 <0x00072000 0x00072000 0x001000>, /* ap 32 */
1059 <0x00073000 0x00073000 0x001000>, /* ap 33 */
1060 <0x00061000 0x00061000 0x001000>, /* ap 34 */
1061 <0x00053000 0x00053000 0x001000>, /* ap 35 */
1062 <0x00054000 0x00054000 0x001000>, /* ap 36 */
1063 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1064 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1065 <0x00078000 0x00078000 0x001000>, /* ap 39 */
1066 <0x00079000 0x00079000 0x001000>, /* ap 40 */
1067 <0x00086000 0x00086000 0x001000>, /* ap 41 */
1068 <0x00087000 0x00087000 0x001000>, /* ap 42 */
1069 <0x00088000 0x00088000 0x001000>, /* ap 43 */
1070 <0x00089000 0x00089000 0x001000>, /* ap 44 */
1071 <0x00051000 0x00051000 0x001000>, /* ap 45 */
1072 <0x00052000 0x00052000 0x001000>, /* ap 46 */
1073 <0x00098000 0x00098000 0x001000>, /* ap 47 */
1074 <0x00099000 0x00099000 0x001000>, /* ap 48 */
1075 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1076 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1077 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1078 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1079 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1080 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1081 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1082 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1083 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1084 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1085 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1086 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1087 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1088 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1089 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1090 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1091 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1092 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1093 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1094 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1095 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1096 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1097 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1098 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1099 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1100 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1101 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1102 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1103 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1104 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1105 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1106 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1107 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1108 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1109 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1110 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1111
1112 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1113 compatible = "ti,sysc-omap2", "ti,sysc";
1114 reg = <0x20050 0x4>,
1115 <0x20054 0x4>,
1116 <0x20058 0x4>;
1117 reg-names = "rev", "sysc", "syss";
1118 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1119 SYSC_OMAP2_SOFTRESET |
1120 SYSC_OMAP2_AUTOIDLE)>;
1121 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1122 <SYSC_IDLE_NO>,
1123 <SYSC_IDLE_SMART>,
1124 <SYSC_IDLE_SMART_WKUP>;
1125 ti,syss-mask = <1>;
1126 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1127 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1128 clock-names = "fck";
1129 #address-cells = <1>;
1130 #size-cells = <1>;
1131 ranges = <0x0 0x20000 0x1000>;
1132
1133 uart3: serial@0 {
1134 compatible = "ti,dra742-uart", "ti,omap4-uart";
1135 reg = <0x0 0x100>;
1136 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1137 clock-frequency = <48000000>;
1138 status = "disabled";
1139 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1140 dma-names = "tx", "rx";
1141 };
1142 };
1143
1144 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1145 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1146 reg = <0x32000 0x4>,
1147 <0x32010 0x4>;
1148 reg-names = "rev", "sysc";
1149 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1150 SYSC_OMAP4_SOFTRESET)>;
1151 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1152 <SYSC_IDLE_NO>,
1153 <SYSC_IDLE_SMART>,
1154 <SYSC_IDLE_SMART_WKUP>;
1155 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1156 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1157 clock-names = "fck";
1158 #address-cells = <1>;
1159 #size-cells = <1>;
1160 ranges = <0x0 0x32000 0x1000>;
1161
1162 timer2: timer@0 {
1163 compatible = "ti,omap5430-timer";
1164 reg = <0x0 0x80>;
1165 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>;
1166 clock-names = "fck", "timer_sys_ck";
1167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1168 };
1169 };
1170
1171 target-module@34000 { /* 0x48034000, ap 7 46.0 */
1172 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1173 reg = <0x34000 0x4>,
1174 <0x34010 0x4>;
1175 reg-names = "rev", "sysc";
1176 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1177 SYSC_OMAP4_SOFTRESET)>;
1178 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1179 <SYSC_IDLE_NO>,
1180 <SYSC_IDLE_SMART>,
1181 <SYSC_IDLE_SMART_WKUP>;
1182 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1183 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1184 clock-names = "fck";
1185 #address-cells = <1>;
1186 #size-cells = <1>;
1187 ranges = <0x0 0x34000 0x1000>;
1188
1189 timer3: timer@0 {
1190 compatible = "ti,omap5430-timer";
1191 reg = <0x0 0x80>;
1192 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>;
1193 clock-names = "fck", "timer_sys_ck";
1194 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1195 };
1196 };
1197
1198 target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1199 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1200 reg = <0x36000 0x4>,
1201 <0x36010 0x4>;
1202 reg-names = "rev", "sysc";
1203 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1204 SYSC_OMAP4_SOFTRESET)>;
1205 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1206 <SYSC_IDLE_NO>,
1207 <SYSC_IDLE_SMART>,
1208 <SYSC_IDLE_SMART_WKUP>;
1209 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1210 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1211 clock-names = "fck";
1212 #address-cells = <1>;
1213 #size-cells = <1>;
1214 ranges = <0x0 0x36000 0x1000>;
1215
1216 timer4: timer@0 {
1217 compatible = "ti,omap5430-timer";
1218 reg = <0x0 0x80>;
1219 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>;
1220 clock-names = "fck", "timer_sys_ck";
1221 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1222 };
1223 };
1224
1225 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1226 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1227 reg = <0x3e000 0x4>,
1228 <0x3e010 0x4>;
1229 reg-names = "rev", "sysc";
1230 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1231 SYSC_OMAP4_SOFTRESET)>;
1232 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1233 <SYSC_IDLE_NO>,
1234 <SYSC_IDLE_SMART>,
1235 <SYSC_IDLE_SMART_WKUP>;
1236 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1237 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1238 clock-names = "fck";
1239 #address-cells = <1>;
1240 #size-cells = <1>;
1241 ranges = <0x0 0x3e000 0x1000>;
1242
1243 timer9: timer@0 {
1244 compatible = "ti,omap5430-timer";
1245 reg = <0x0 0x80>;
1246 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>;
1247 clock-names = "fck", "timer_sys_ck";
1248 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1249 };
1250 };
1251
1252 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1253 compatible = "ti,sysc-omap2", "ti,sysc";
1254 reg = <0x51000 0x4>,
1255 <0x51010 0x4>,
1256 <0x51114 0x4>;
1257 reg-names = "rev", "sysc", "syss";
1258 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1259 SYSC_OMAP2_SOFTRESET |
1260 SYSC_OMAP2_AUTOIDLE)>;
1261 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1262 <SYSC_IDLE_NO>,
1263 <SYSC_IDLE_SMART>,
1264 <SYSC_IDLE_SMART_WKUP>;
1265 ti,syss-mask = <1>;
1266 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1267 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1268 <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1269 clock-names = "fck", "dbclk";
1270 #address-cells = <1>;
1271 #size-cells = <1>;
1272 ranges = <0x0 0x51000 0x1000>;
1273
1274 gpio7: gpio@0 {
1275 compatible = "ti,omap4-gpio";
1276 reg = <0x0 0x200>;
1277 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1278 gpio-controller;
1279 #gpio-cells = <2>;
1280 interrupt-controller;
1281 #interrupt-cells = <2>;
1282 };
1283 };
1284
1285 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1286 compatible = "ti,sysc-omap2", "ti,sysc";
1287 reg = <0x53000 0x4>,
1288 <0x53010 0x4>,
1289 <0x53114 0x4>;
1290 reg-names = "rev", "sysc", "syss";
1291 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1292 SYSC_OMAP2_SOFTRESET |
1293 SYSC_OMAP2_AUTOIDLE)>;
1294 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1295 <SYSC_IDLE_NO>,
1296 <SYSC_IDLE_SMART>,
1297 <SYSC_IDLE_SMART_WKUP>;
1298 ti,syss-mask = <1>;
1299 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1300 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1301 <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1302 clock-names = "fck", "dbclk";
1303 #address-cells = <1>;
1304 #size-cells = <1>;
1305 ranges = <0x0 0x53000 0x1000>;
1306
1307 gpio8: gpio@0 {
1308 compatible = "ti,omap4-gpio";
1309 reg = <0x0 0x200>;
1310 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1311 gpio-controller;
1312 #gpio-cells = <2>;
1313 interrupt-controller;
1314 #interrupt-cells = <2>;
1315 };
1316 };
1317
1318 target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1319 compatible = "ti,sysc-omap2", "ti,sysc";
1320 reg = <0x55000 0x4>,
1321 <0x55010 0x4>,
1322 <0x55114 0x4>;
1323 reg-names = "rev", "sysc", "syss";
1324 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1325 SYSC_OMAP2_SOFTRESET |
1326 SYSC_OMAP2_AUTOIDLE)>;
1327 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1328 <SYSC_IDLE_NO>,
1329 <SYSC_IDLE_SMART>,
1330 <SYSC_IDLE_SMART_WKUP>;
1331 ti,syss-mask = <1>;
1332 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1333 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1334 <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1335 clock-names = "fck", "dbclk";
1336 #address-cells = <1>;
1337 #size-cells = <1>;
1338 ranges = <0x0 0x55000 0x1000>;
1339
1340 gpio2: gpio@0 {
1341 compatible = "ti,omap4-gpio";
1342 reg = <0x0 0x200>;
1343 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1344 gpio-controller;
1345 #gpio-cells = <2>;
1346 interrupt-controller;
1347 #interrupt-cells = <2>;
1348 };
1349 };
1350
1351 target-module@57000 { /* 0x48057000, ap 15 06.0 */
1352 compatible = "ti,sysc-omap2", "ti,sysc";
1353 reg = <0x57000 0x4>,
1354 <0x57010 0x4>,
1355 <0x57114 0x4>;
1356 reg-names = "rev", "sysc", "syss";
1357 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1358 SYSC_OMAP2_SOFTRESET |
1359 SYSC_OMAP2_AUTOIDLE)>;
1360 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1361 <SYSC_IDLE_NO>,
1362 <SYSC_IDLE_SMART>,
1363 <SYSC_IDLE_SMART_WKUP>;
1364 ti,syss-mask = <1>;
1365 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1366 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1367 <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1368 clock-names = "fck", "dbclk";
1369 #address-cells = <1>;
1370 #size-cells = <1>;
1371 ranges = <0x0 0x57000 0x1000>;
1372
1373 gpio3: gpio@0 {
1374 compatible = "ti,omap4-gpio";
1375 reg = <0x0 0x200>;
1376 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1377 gpio-controller;
1378 #gpio-cells = <2>;
1379 interrupt-controller;
1380 #interrupt-cells = <2>;
1381 };
1382 };
1383
1384 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1385 compatible = "ti,sysc-omap2", "ti,sysc";
1386 reg = <0x59000 0x4>,
1387 <0x59010 0x4>,
1388 <0x59114 0x4>;
1389 reg-names = "rev", "sysc", "syss";
1390 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1391 SYSC_OMAP2_SOFTRESET |
1392 SYSC_OMAP2_AUTOIDLE)>;
1393 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1394 <SYSC_IDLE_NO>,
1395 <SYSC_IDLE_SMART>,
1396 <SYSC_IDLE_SMART_WKUP>;
1397 ti,syss-mask = <1>;
1398 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1399 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1400 <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1401 clock-names = "fck", "dbclk";
1402 #address-cells = <1>;
1403 #size-cells = <1>;
1404 ranges = <0x0 0x59000 0x1000>;
1405
1406 gpio4: gpio@0 {
1407 compatible = "ti,omap4-gpio";
1408 reg = <0x0 0x200>;
1409 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1410 gpio-controller;
1411 #gpio-cells = <2>;
1412 interrupt-controller;
1413 #interrupt-cells = <2>;
1414 };
1415 };
1416
1417 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1418 compatible = "ti,sysc-omap2", "ti,sysc";
1419 reg = <0x5b000 0x4>,
1420 <0x5b010 0x4>,
1421 <0x5b114 0x4>;
1422 reg-names = "rev", "sysc", "syss";
1423 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1424 SYSC_OMAP2_SOFTRESET |
1425 SYSC_OMAP2_AUTOIDLE)>;
1426 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1427 <SYSC_IDLE_NO>,
1428 <SYSC_IDLE_SMART>,
1429 <SYSC_IDLE_SMART_WKUP>;
1430 ti,syss-mask = <1>;
1431 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1432 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1433 <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1434 clock-names = "fck", "dbclk";
1435 #address-cells = <1>;
1436 #size-cells = <1>;
1437 ranges = <0x0 0x5b000 0x1000>;
1438
1439 gpio5: gpio@0 {
1440 compatible = "ti,omap4-gpio";
1441 reg = <0x0 0x200>;
1442 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1443 gpio-controller;
1444 #gpio-cells = <2>;
1445 interrupt-controller;
1446 #interrupt-cells = <2>;
1447 };
1448 };
1449
1450 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1451 compatible = "ti,sysc-omap2", "ti,sysc";
1452 reg = <0x5d000 0x4>,
1453 <0x5d010 0x4>,
1454 <0x5d114 0x4>;
1455 reg-names = "rev", "sysc", "syss";
1456 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1457 SYSC_OMAP2_SOFTRESET |
1458 SYSC_OMAP2_AUTOIDLE)>;
1459 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1460 <SYSC_IDLE_NO>,
1461 <SYSC_IDLE_SMART>,
1462 <SYSC_IDLE_SMART_WKUP>;
1463 ti,syss-mask = <1>;
1464 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1465 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1466 <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1467 clock-names = "fck", "dbclk";
1468 #address-cells = <1>;
1469 #size-cells = <1>;
1470 ranges = <0x0 0x5d000 0x1000>;
1471
1472 gpio6: gpio@0 {
1473 compatible = "ti,omap4-gpio";
1474 reg = <0x0 0x200>;
1475 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1476 gpio-controller;
1477 #gpio-cells = <2>;
1478 interrupt-controller;
1479 #interrupt-cells = <2>;
1480 };
1481 };
1482
1483 target-module@60000 { /* 0x48060000, ap 23 32.0 */
1484 compatible = "ti,sysc-omap2", "ti,sysc";
1485 reg = <0x60000 0x8>,
1486 <0x60010 0x8>,
1487 <0x60090 0x8>;
1488 reg-names = "rev", "sysc", "syss";
1489 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1490 SYSC_OMAP2_ENAWAKEUP |
1491 SYSC_OMAP2_SOFTRESET |
1492 SYSC_OMAP2_AUTOIDLE)>;
1493 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1494 <SYSC_IDLE_NO>,
1495 <SYSC_IDLE_SMART>,
1496 <SYSC_IDLE_SMART_WKUP>;
1497 ti,syss-mask = <1>;
1498 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1499 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1500 clock-names = "fck";
1501 #address-cells = <1>;
1502 #size-cells = <1>;
1503 ranges = <0x0 0x60000 0x1000>;
1504
1505 i2c3: i2c@0 {
1506 compatible = "ti,omap4-i2c";
1507 reg = <0x0 0x100>;
1508 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1509 #address-cells = <1>;
1510 #size-cells = <0>;
1511 status = "disabled";
1512 };
1513 };
1514
1515 target-module@66000 { /* 0x48066000, ap 63 14.0 */
1516 compatible = "ti,sysc-omap2", "ti,sysc";
1517 reg = <0x66050 0x4>,
1518 <0x66054 0x4>,
1519 <0x66058 0x4>;
1520 reg-names = "rev", "sysc", "syss";
1521 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1522 SYSC_OMAP2_SOFTRESET |
1523 SYSC_OMAP2_AUTOIDLE)>;
1524 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1525 <SYSC_IDLE_NO>,
1526 <SYSC_IDLE_SMART>,
1527 <SYSC_IDLE_SMART_WKUP>;
1528 ti,syss-mask = <1>;
1529 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1530 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1531 clock-names = "fck";
1532 #address-cells = <1>;
1533 #size-cells = <1>;
1534 ranges = <0x0 0x66000 0x1000>;
1535
1536 uart5: serial@0 {
1537 compatible = "ti,dra742-uart", "ti,omap4-uart";
1538 reg = <0x0 0x100>;
1539 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1540 clock-frequency = <48000000>;
1541 status = "disabled";
1542 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1543 dma-names = "tx", "rx";
1544 };
1545 };
1546
1547 target-module@68000 { /* 0x48068000, ap 53 1c.0 */
1548 compatible = "ti,sysc-omap2", "ti,sysc";
1549 reg = <0x68050 0x4>,
1550 <0x68054 0x4>,
1551 <0x68058 0x4>;
1552 reg-names = "rev", "sysc", "syss";
1553 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1554 SYSC_OMAP2_SOFTRESET |
1555 SYSC_OMAP2_AUTOIDLE)>;
1556 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1557 <SYSC_IDLE_NO>,
1558 <SYSC_IDLE_SMART>,
1559 <SYSC_IDLE_SMART_WKUP>;
1560 ti,syss-mask = <1>;
1561 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1562 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1563 clock-names = "fck";
1564 #address-cells = <1>;
1565 #size-cells = <1>;
1566 ranges = <0x0 0x68000 0x1000>;
1567
1568 uart6: serial@0 {
1569 compatible = "ti,dra742-uart", "ti,omap4-uart";
1570 reg = <0x0 0x100>;
1571 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1572 clock-frequency = <48000000>;
1573 status = "disabled";
1574 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1575 dma-names = "tx", "rx";
1576 };
1577 };
1578
1579 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
1580 compatible = "ti,sysc-omap2", "ti,sysc";
1581 reg = <0x6a050 0x4>,
1582 <0x6a054 0x4>,
1583 <0x6a058 0x4>;
1584 reg-names = "rev", "sysc", "syss";
1585 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1586 SYSC_OMAP2_SOFTRESET |
1587 SYSC_OMAP2_AUTOIDLE)>;
1588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1589 <SYSC_IDLE_NO>,
1590 <SYSC_IDLE_SMART>,
1591 <SYSC_IDLE_SMART_WKUP>;
1592 ti,syss-mask = <1>;
1593 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1594 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1595 clock-names = "fck";
1596 #address-cells = <1>;
1597 #size-cells = <1>;
1598 ranges = <0x0 0x6a000 0x1000>;
1599
1600 uart1: serial@0 {
1601 compatible = "ti,dra742-uart", "ti,omap4-uart";
1602 reg = <0x0 0x100>;
1603 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1604 clock-frequency = <48000000>;
1605 status = "disabled";
1606 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1607 dma-names = "tx", "rx";
1608 };
1609 };
1610
1611 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
1612 compatible = "ti,sysc-omap2", "ti,sysc";
1613 reg = <0x6c050 0x4>,
1614 <0x6c054 0x4>,
1615 <0x6c058 0x4>;
1616 reg-names = "rev", "sysc", "syss";
1617 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1618 SYSC_OMAP2_SOFTRESET |
1619 SYSC_OMAP2_AUTOIDLE)>;
1620 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1621 <SYSC_IDLE_NO>,
1622 <SYSC_IDLE_SMART>,
1623 <SYSC_IDLE_SMART_WKUP>;
1624 ti,syss-mask = <1>;
1625 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1626 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1627 clock-names = "fck";
1628 #address-cells = <1>;
1629 #size-cells = <1>;
1630 ranges = <0x0 0x6c000 0x1000>;
1631
1632 uart2: serial@0 {
1633 compatible = "ti,dra742-uart", "ti,omap4-uart";
1634 reg = <0x0 0x100>;
1635 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1636 clock-frequency = <48000000>;
1637 status = "disabled";
1638 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1639 dma-names = "tx", "rx";
1640 };
1641 };
1642
1643 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
1644 compatible = "ti,sysc-omap2", "ti,sysc";
1645 reg = <0x6e050 0x4>,
1646 <0x6e054 0x4>,
1647 <0x6e058 0x4>;
1648 reg-names = "rev", "sysc", "syss";
1649 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1650 SYSC_OMAP2_SOFTRESET |
1651 SYSC_OMAP2_AUTOIDLE)>;
1652 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1653 <SYSC_IDLE_NO>,
1654 <SYSC_IDLE_SMART>,
1655 <SYSC_IDLE_SMART_WKUP>;
1656 ti,syss-mask = <1>;
1657 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1658 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1659 clock-names = "fck";
1660 #address-cells = <1>;
1661 #size-cells = <1>;
1662 ranges = <0x0 0x6e000 0x1000>;
1663
1664 uart4: serial@0 {
1665 compatible = "ti,dra742-uart", "ti,omap4-uart";
1666 reg = <0x0 0x100>;
1667 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1668 clock-frequency = <48000000>;
1669 status = "disabled";
1670 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1671 dma-names = "tx", "rx";
1672 };
1673 };
1674
1675 target-module@70000 { /* 0x48070000, ap 30 22.0 */
1676 compatible = "ti,sysc-omap2", "ti,sysc";
1677 reg = <0x70000 0x8>,
1678 <0x70010 0x8>,
1679 <0x70090 0x8>;
1680 reg-names = "rev", "sysc", "syss";
1681 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1682 SYSC_OMAP2_ENAWAKEUP |
1683 SYSC_OMAP2_SOFTRESET |
1684 SYSC_OMAP2_AUTOIDLE)>;
1685 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1686 <SYSC_IDLE_NO>,
1687 <SYSC_IDLE_SMART>,
1688 <SYSC_IDLE_SMART_WKUP>;
1689 ti,syss-mask = <1>;
1690 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1691 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1692 clock-names = "fck";
1693 #address-cells = <1>;
1694 #size-cells = <1>;
1695 ranges = <0x0 0x70000 0x1000>;
1696
1697 i2c1: i2c@0 {
1698 compatible = "ti,omap4-i2c";
1699 reg = <0x0 0x100>;
1700 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1703 status = "disabled";
1704 };
1705 };
1706
1707 target-module@72000 { /* 0x48072000, ap 32 2a.0 */
1708 compatible = "ti,sysc-omap2", "ti,sysc";
1709 reg = <0x72000 0x8>,
1710 <0x72010 0x8>,
1711 <0x72090 0x8>;
1712 reg-names = "rev", "sysc", "syss";
1713 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1714 SYSC_OMAP2_ENAWAKEUP |
1715 SYSC_OMAP2_SOFTRESET |
1716 SYSC_OMAP2_AUTOIDLE)>;
1717 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1718 <SYSC_IDLE_NO>,
1719 <SYSC_IDLE_SMART>,
1720 <SYSC_IDLE_SMART_WKUP>;
1721 ti,syss-mask = <1>;
1722 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1723 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1724 clock-names = "fck";
1725 #address-cells = <1>;
1726 #size-cells = <1>;
1727 ranges = <0x0 0x72000 0x1000>;
1728
1729 i2c2: i2c@0 {
1730 compatible = "ti,omap4-i2c";
1731 reg = <0x0 0x100>;
1732 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1733 #address-cells = <1>;
1734 #size-cells = <0>;
1735 status = "disabled";
1736 };
1737 };
1738
1739 target-module@78000 { /* 0x48078000, ap 39 0a.0 */
1740 compatible = "ti,sysc-omap2", "ti,sysc";
1741 reg = <0x78000 0x4>,
1742 <0x78010 0x4>,
1743 <0x78014 0x4>;
1744 reg-names = "rev", "sysc", "syss";
1745 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1746 SYSC_OMAP2_SOFTRESET |
1747 SYSC_OMAP2_AUTOIDLE)>;
1748 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1749 <SYSC_IDLE_NO>,
1750 <SYSC_IDLE_SMART>,
1751 <SYSC_IDLE_SMART_WKUP>;
1752 ti,syss-mask = <1>;
1753 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1754 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1755 clock-names = "fck";
1756 #address-cells = <1>;
1757 #size-cells = <1>;
1758 ranges = <0x0 0x78000 0x1000>;
1759
1760 elm: elm@0 {
1761 compatible = "ti,am3352-elm";
1762 reg = <0x0 0xfc0>; /* device IO registers */
1763 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1764 status = "disabled";
1765 };
1766 };
1767
1768 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
1769 compatible = "ti,sysc-omap2", "ti,sysc";
1770 reg = <0x7a000 0x8>,
1771 <0x7a010 0x8>,
1772 <0x7a090 0x8>;
1773 reg-names = "rev", "sysc", "syss";
1774 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1775 SYSC_OMAP2_ENAWAKEUP |
1776 SYSC_OMAP2_SOFTRESET |
1777 SYSC_OMAP2_AUTOIDLE)>;
1778 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1779 <SYSC_IDLE_NO>,
1780 <SYSC_IDLE_SMART>,
1781 <SYSC_IDLE_SMART_WKUP>;
1782 ti,syss-mask = <1>;
1783 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1784 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1785 clock-names = "fck";
1786 #address-cells = <1>;
1787 #size-cells = <1>;
1788 ranges = <0x0 0x7a000 0x1000>;
1789
1790 i2c4: i2c@0 {
1791 compatible = "ti,omap4-i2c";
1792 reg = <0x0 0x100>;
1793 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1796 status = "disabled";
1797 };
1798 };
1799
1800 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
1801 compatible = "ti,sysc-omap2", "ti,sysc";
1802 reg = <0x7c000 0x8>,
1803 <0x7c010 0x8>,
1804 <0x7c090 0x8>;
1805 reg-names = "rev", "sysc", "syss";
1806 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1807 SYSC_OMAP2_ENAWAKEUP |
1808 SYSC_OMAP2_SOFTRESET |
1809 SYSC_OMAP2_AUTOIDLE)>;
1810 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1811 <SYSC_IDLE_NO>,
1812 <SYSC_IDLE_SMART>,
1813 <SYSC_IDLE_SMART_WKUP>;
1814 ti,syss-mask = <1>;
1815 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1816 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1817 clock-names = "fck";
1818 #address-cells = <1>;
1819 #size-cells = <1>;
1820 ranges = <0x0 0x7c000 0x1000>;
1821
1822 i2c5: i2c@0 {
1823 compatible = "ti,omap4-i2c";
1824 reg = <0x0 0x100>;
1825 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1828 status = "disabled";
1829 };
1830 };
1831
1832 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1833 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1834 reg = <0x86000 0x4>,
1835 <0x86010 0x4>;
1836 reg-names = "rev", "sysc";
1837 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1838 SYSC_OMAP4_SOFTRESET)>;
1839 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1840 <SYSC_IDLE_NO>,
1841 <SYSC_IDLE_SMART>,
1842 <SYSC_IDLE_SMART_WKUP>;
1843 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1844 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1845 clock-names = "fck";
1846 #address-cells = <1>;
1847 #size-cells = <1>;
1848 ranges = <0x0 0x86000 0x1000>;
1849
1850 timer10: timer@0 {
1851 compatible = "ti,omap5430-timer";
1852 reg = <0x0 0x80>;
1853 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>;
1854 clock-names = "fck", "timer_sys_ck";
1855 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1856 };
1857 };
1858
1859 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1860 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1861 reg = <0x88000 0x4>,
1862 <0x88010 0x4>;
1863 reg-names = "rev", "sysc";
1864 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1865 SYSC_OMAP4_SOFTRESET)>;
1866 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1867 <SYSC_IDLE_NO>,
1868 <SYSC_IDLE_SMART>,
1869 <SYSC_IDLE_SMART_WKUP>;
1870 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1871 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1872 clock-names = "fck";
1873 #address-cells = <1>;
1874 #size-cells = <1>;
1875 ranges = <0x0 0x88000 0x1000>;
1876
1877 timer11: timer@0 {
1878 compatible = "ti,omap5430-timer";
1879 reg = <0x0 0x80>;
1880 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>;
1881 clock-names = "fck", "timer_sys_ck";
1882 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1883 };
1884 };
1885
1886 target-module@90000 { /* 0x48090000, ap 55 12.0 */
1887 compatible = "ti,sysc-omap2", "ti,sysc";
1888 reg = <0x91fe0 0x4>,
1889 <0x91fe4 0x4>;
1890 reg-names = "rev", "sysc";
1891 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1892 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1893 <SYSC_IDLE_NO>;
1894 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1895 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1896 clock-names = "fck";
1897 #address-cells = <1>;
1898 #size-cells = <1>;
1899 ranges = <0x0 0x90000 0x2000>;
1900
1901 rng: rng@0 {
1902 compatible = "ti,omap4-rng";
1903 reg = <0x0 0x2000>;
1904 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1905 clocks = <&l3_iclk_div>;
1906 clock-names = "fck";
1907 };
1908 };
1909
1910 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1911 compatible = "ti,sysc-omap4", "ti,sysc";
1912 reg = <0x98000 0x4>,
1913 <0x98010 0x4>;
1914 reg-names = "rev", "sysc";
1915 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1916 SYSC_OMAP4_SOFTRESET)>;
1917 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1918 <SYSC_IDLE_NO>,
1919 <SYSC_IDLE_SMART>,
1920 <SYSC_IDLE_SMART_WKUP>;
1921 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1922 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1923 clock-names = "fck";
1924 #address-cells = <1>;
1925 #size-cells = <1>;
1926 ranges = <0x0 0x98000 0x1000>;
1927
1928 mcspi1: spi@0 {
1929 compatible = "ti,omap4-mcspi";
1930 reg = <0x0 0x200>;
1931 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1934 ti,spi-num-cs = <4>;
1935 dmas = <&sdma_xbar 35>,
1936 <&sdma_xbar 36>,
1937 <&sdma_xbar 37>,
1938 <&sdma_xbar 38>,
1939 <&sdma_xbar 39>,
1940 <&sdma_xbar 40>,
1941 <&sdma_xbar 41>,
1942 <&sdma_xbar 42>;
1943 dma-names = "tx0", "rx0", "tx1", "rx1",
1944 "tx2", "rx2", "tx3", "rx3";
1945 status = "disabled";
1946 };
1947 };
1948
1949 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1950 compatible = "ti,sysc-omap4", "ti,sysc";
1951 reg = <0x9a000 0x4>,
1952 <0x9a010 0x4>;
1953 reg-names = "rev", "sysc";
1954 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1955 SYSC_OMAP4_SOFTRESET)>;
1956 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1957 <SYSC_IDLE_NO>,
1958 <SYSC_IDLE_SMART>,
1959 <SYSC_IDLE_SMART_WKUP>;
1960 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1961 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1962 clock-names = "fck";
1963 #address-cells = <1>;
1964 #size-cells = <1>;
1965 ranges = <0x0 0x9a000 0x1000>;
1966
1967 mcspi2: spi@0 {
1968 compatible = "ti,omap4-mcspi";
1969 reg = <0x0 0x200>;
1970 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1971 #address-cells = <1>;
1972 #size-cells = <0>;
1973 ti,spi-num-cs = <2>;
1974 dmas = <&sdma_xbar 43>,
1975 <&sdma_xbar 44>,
1976 <&sdma_xbar 45>,
1977 <&sdma_xbar 46>;
1978 dma-names = "tx0", "rx0", "tx1", "rx1";
1979 status = "disabled";
1980 };
1981 };
1982
1983 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
1984 compatible = "ti,sysc-omap4", "ti,sysc";
1985 reg = <0x9c000 0x4>,
1986 <0x9c010 0x4>;
1987 reg-names = "rev", "sysc";
1988 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1989 SYSC_OMAP4_SOFTRESET)>;
1990 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1991 <SYSC_IDLE_NO>,
1992 <SYSC_IDLE_SMART>,
1993 <SYSC_IDLE_SMART_WKUP>;
1994 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1995 <SYSC_IDLE_NO>,
1996 <SYSC_IDLE_SMART>,
1997 <SYSC_IDLE_SMART_WKUP>;
1998 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
1999 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2000 clock-names = "fck";
2001 #address-cells = <1>;
2002 #size-cells = <1>;
2003 ranges = <0x0 0x9c000 0x1000>;
2004
2005 mmc1: mmc@0 {
2006 compatible = "ti,dra7-sdhci";
2007 reg = <0x0 0x400>;
2008 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2009 status = "disabled";
2010 pbias-supply = <&pbias_mmc_reg>;
2011 max-frequency = <192000000>;
2012 mmc-ddr-1_8v;
2013 mmc-ddr-3_3v;
2014 };
2015 };
2016
2017 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
2018 compatible = "ti,sysc";
2019 status = "disabled";
2020 #address-cells = <1>;
2021 #size-cells = <1>;
2022 ranges = <0x0 0xa2000 0x1000>;
2023 };
2024
2025 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
2026 compatible = "ti,sysc";
2027 status = "disabled";
2028 #address-cells = <1>;
2029 #size-cells = <1>;
2030 ranges = <0x00000000 0x000a4000 0x00001000>,
2031 <0x00001000 0x000a5000 0x00001000>;
2032 };
2033
2034 des_target: target-module@a5000 { /* 0x480a5000 */
2035 compatible = "ti,sysc-omap2", "ti,sysc";
2036 reg = <0xa5030 0x4>,
2037 <0xa5034 0x4>,
2038 <0xa5038 0x4>;
2039 reg-names = "rev", "sysc", "syss";
2040 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2041 SYSC_OMAP2_AUTOIDLE)>;
2042 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2043 <SYSC_IDLE_NO>,
2044 <SYSC_IDLE_SMART>,
2045 <SYSC_IDLE_SMART_WKUP>;
2046 ti,syss-mask = <1>;
2047 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
2048 clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
2049 clock-names = "fck";
2050 #address-cells = <1>;
2051 #size-cells = <1>;
2052 ranges = <0 0xa5000 0x00001000>;
2053
2054 des: des@0 {
2055 compatible = "ti,omap4-des";
2056 reg = <0 0xa0>;
2057 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2058 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2059 dma-names = "tx", "rx";
2060 clocks = <&l3_iclk_div>;
2061 clock-names = "fck";
2062 };
2063 };
2064
2065 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
2066 compatible = "ti,sysc";
2067 status = "disabled";
2068 #address-cells = <1>;
2069 #size-cells = <1>;
2070 ranges = <0x0 0xa8000 0x4000>;
2071 };
2072
2073 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
2074 compatible = "ti,sysc-omap4", "ti,sysc";
2075 reg = <0xad000 0x4>,
2076 <0xad010 0x4>;
2077 reg-names = "rev", "sysc";
2078 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2079 SYSC_OMAP4_SOFTRESET)>;
2080 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2081 <SYSC_IDLE_NO>,
2082 <SYSC_IDLE_SMART>,
2083 <SYSC_IDLE_SMART_WKUP>;
2084 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2085 <SYSC_IDLE_NO>,
2086 <SYSC_IDLE_SMART>,
2087 <SYSC_IDLE_SMART_WKUP>;
2088 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2089 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2090 clock-names = "fck";
2091 #address-cells = <1>;
2092 #size-cells = <1>;
2093 ranges = <0x0 0xad000 0x1000>;
2094
2095 mmc3: mmc@0 {
2096 compatible = "ti,dra7-sdhci";
2097 reg = <0x0 0x400>;
2098 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2099 status = "disabled";
2100 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2101 max-frequency = <64000000>;
2102 /* SDMA is not supported */
2103 sdhci-caps-mask = <0x0 0x400000>;
2104 };
2105 };
2106
2107 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
2108 compatible = "ti,sysc-omap2", "ti,sysc";
2109 reg = <0xb2000 0x4>,
2110 <0xb2014 0x4>,
2111 <0xb2018 0x4>;
2112 reg-names = "rev", "sysc", "syss";
2113 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2114 SYSC_OMAP2_AUTOIDLE)>;
2115 ti,syss-mask = <1>;
2116 ti,no-reset-on-init;
2117 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2118 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2119 clock-names = "fck";
2120 #address-cells = <1>;
2121 #size-cells = <1>;
2122 ranges = <0x0 0xb2000 0x1000>;
2123
2124 hdqw1w: 1w@0 {
2125 compatible = "ti,omap3-1w";
2126 reg = <0x0 0x1000>;
2127 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2128 };
2129 };
2130
2131 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
2132 compatible = "ti,sysc-omap4", "ti,sysc";
2133 reg = <0xb4000 0x4>,
2134 <0xb4010 0x4>;
2135 reg-names = "rev", "sysc";
2136 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2137 SYSC_OMAP4_SOFTRESET)>;
2138 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2139 <SYSC_IDLE_NO>,
2140 <SYSC_IDLE_SMART>,
2141 <SYSC_IDLE_SMART_WKUP>;
2142 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2143 <SYSC_IDLE_NO>,
2144 <SYSC_IDLE_SMART>,
2145 <SYSC_IDLE_SMART_WKUP>;
2146 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2147 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2148 clock-names = "fck";
2149 #address-cells = <1>;
2150 #size-cells = <1>;
2151 ranges = <0x0 0xb4000 0x1000>;
2152
2153 mmc2: mmc@0 {
2154 compatible = "ti,dra7-sdhci";
2155 reg = <0x0 0x400>;
2156 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2157 status = "disabled";
2158 max-frequency = <192000000>;
2159 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2160 sdhci-caps-mask = <0x7 0x0>;
2161 mmc-hs200-1_8v;
2162 mmc-ddr-1_8v;
2163 mmc-ddr-3_3v;
2164 };
2165 };
2166
2167 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
2168 compatible = "ti,sysc-omap4", "ti,sysc";
2169 reg = <0xb8000 0x4>,
2170 <0xb8010 0x4>;
2171 reg-names = "rev", "sysc";
2172 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2173 SYSC_OMAP4_SOFTRESET)>;
2174 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2175 <SYSC_IDLE_NO>,
2176 <SYSC_IDLE_SMART>,
2177 <SYSC_IDLE_SMART_WKUP>;
2178 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2179 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2180 clock-names = "fck";
2181 #address-cells = <1>;
2182 #size-cells = <1>;
2183 ranges = <0x0 0xb8000 0x1000>;
2184
2185 mcspi3: spi@0 {
2186 compatible = "ti,omap4-mcspi";
2187 reg = <0x0 0x200>;
2188 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2189 #address-cells = <1>;
2190 #size-cells = <0>;
2191 ti,spi-num-cs = <2>;
2192 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2193 dma-names = "tx0", "rx0";
2194 status = "disabled";
2195 };
2196 };
2197
2198 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2199 compatible = "ti,sysc-omap4", "ti,sysc";
2200 reg = <0xba000 0x4>,
2201 <0xba010 0x4>;
2202 reg-names = "rev", "sysc";
2203 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2204 SYSC_OMAP4_SOFTRESET)>;
2205 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2206 <SYSC_IDLE_NO>,
2207 <SYSC_IDLE_SMART>,
2208 <SYSC_IDLE_SMART_WKUP>;
2209 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2210 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2211 clock-names = "fck";
2212 #address-cells = <1>;
2213 #size-cells = <1>;
2214 ranges = <0x0 0xba000 0x1000>;
2215
2216 mcspi4: spi@0 {
2217 compatible = "ti,omap4-mcspi";
2218 reg = <0x0 0x200>;
2219 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2220 #address-cells = <1>;
2221 #size-cells = <0>;
2222 ti,spi-num-cs = <1>;
2223 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2224 dma-names = "tx0", "rx0";
2225 status = "disabled";
2226 };
2227 };
2228
2229 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2230 compatible = "ti,sysc-omap4", "ti,sysc";
2231 reg = <0xd1000 0x4>,
2232 <0xd1010 0x4>;
2233 reg-names = "rev", "sysc";
2234 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2235 SYSC_OMAP4_SOFTRESET)>;
2236 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2237 <SYSC_IDLE_NO>,
2238 <SYSC_IDLE_SMART>,
2239 <SYSC_IDLE_SMART_WKUP>;
2240 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2241 <SYSC_IDLE_NO>,
2242 <SYSC_IDLE_SMART>,
2243 <SYSC_IDLE_SMART_WKUP>;
2244 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2245 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2246 clock-names = "fck";
2247 #address-cells = <1>;
2248 #size-cells = <1>;
2249 ranges = <0x0 0xd1000 0x1000>;
2250
2251 mmc4: mmc@0 {
2252 compatible = "ti,dra7-sdhci";
2253 reg = <0x0 0x400>;
2254 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2255 status = "disabled";
2256 max-frequency = <192000000>;
2257 /* SDMA is not supported */
2258 sdhci-caps-mask = <0x0 0x400000>;
2259 };
2260 };
2261
2262 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2263 compatible = "ti,sysc";
2264 status = "disabled";
2265 #address-cells = <1>;
2266 #size-cells = <1>;
2267 ranges = <0x0 0xd5000 0x1000>;
2268 };
2269 };
2270
2271 segment@200000 { /* 0x48200000 */
2272 compatible = "simple-bus";
2273 #address-cells = <1>;
2274 #size-cells = <1>;
2275 };
2276};
2277
2278&l4_per2 { /* 0x48400000 */
2279 compatible = "ti,dra7-l4-per2", "simple-bus";
2280 reg = <0x48400000 0x800>,
2281 <0x48400800 0x800>,
2282 <0x48401000 0x400>,
2283 <0x48401400 0x400>,
2284 <0x48401800 0x400>;
2285 reg-names = "ap", "la", "ia0", "ia1", "ia2";
2286 #address-cells = <1>;
2287 #size-cells = <1>;
2288 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
2289 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2290 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2291 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2292 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2293 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2294 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2295 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2296 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2297
2298 segment@0 { /* 0x48400000 */
2299 compatible = "simple-bus";
2300 #address-cells = <1>;
2301 #size-cells = <1>;
2302 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2303 <0x00001000 0x00001000 0x000400>, /* ap 1 */
2304 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2305 <0x00084000 0x00084000 0x004000>, /* ap 3 */
2306 <0x00001400 0x00001400 0x000400>, /* ap 4 */
2307 <0x00001800 0x00001800 0x000400>, /* ap 5 */
2308 <0x00088000 0x00088000 0x001000>, /* ap 6 */
2309 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */
2310 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */
2311 <0x00060000 0x00060000 0x002000>, /* ap 9 */
2312 <0x00062000 0x00062000 0x001000>, /* ap 10 */
2313 <0x00064000 0x00064000 0x002000>, /* ap 11 */
2314 <0x00066000 0x00066000 0x001000>, /* ap 12 */
2315 <0x00068000 0x00068000 0x002000>, /* ap 13 */
2316 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */
2317 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */
2318 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */
2319 <0x00036000 0x00036000 0x001000>, /* ap 17 */
2320 <0x00037000 0x00037000 0x001000>, /* ap 18 */
2321 <0x00070000 0x00070000 0x002000>, /* ap 19 */
2322 <0x00072000 0x00072000 0x001000>, /* ap 20 */
2323 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */
2324 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */
2325 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
2326 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */
2327 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */
2328 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */
2329 <0x00040000 0x00040000 0x001000>, /* ap 27 */
2330 <0x00041000 0x00041000 0x001000>, /* ap 28 */
2331 <0x00042000 0x00042000 0x001000>, /* ap 29 */
2332 <0x00043000 0x00043000 0x001000>, /* ap 30 */
2333 <0x00080000 0x00080000 0x002000>, /* ap 31 */
2334 <0x00082000 0x00082000 0x001000>, /* ap 32 */
2335 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */
2336 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */
2337 <0x00074000 0x00074000 0x002000>, /* ap 35 */
2338 <0x00076000 0x00076000 0x001000>, /* ap 36 */
2339 <0x00050000 0x00050000 0x001000>, /* ap 37 */
2340 <0x00051000 0x00051000 0x001000>, /* ap 38 */
2341 <0x00078000 0x00078000 0x002000>, /* ap 39 */
2342 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */
2343 <0x00054000 0x00054000 0x001000>, /* ap 41 */
2344 <0x00055000 0x00055000 0x001000>, /* ap 42 */
2345 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */
2346 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */
2347 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */
2348 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */
2349 <0x00020000 0x00020000 0x001000>, /* ap 47 */
2350 <0x00021000 0x00021000 0x001000>, /* ap 48 */
2351 <0x00022000 0x00022000 0x001000>, /* ap 49 */
2352 <0x00023000 0x00023000 0x001000>, /* ap 50 */
2353 <0x00024000 0x00024000 0x001000>, /* ap 51 */
2354 <0x00025000 0x00025000 0x001000>, /* ap 52 */
2355 <0x00046000 0x00046000 0x001000>, /* ap 53 */
2356 <0x00047000 0x00047000 0x001000>, /* ap 54 */
2357 <0x00048000 0x00048000 0x001000>, /* ap 55 */
2358 <0x00049000 0x00049000 0x001000>, /* ap 56 */
2359 <0x00058000 0x00058000 0x002000>, /* ap 57 */
2360 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */
2361 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */
2362 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */
2363 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */
2364 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */
2365 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2366 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2367 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2368 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2369 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2370 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2371 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2372 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2373
2374 target-module@20000 { /* 0x48420000, ap 47 02.0 */
2375 compatible = "ti,sysc-omap2", "ti,sysc";
2376 reg = <0x20050 0x4>,
2377 <0x20054 0x4>,
2378 <0x20058 0x4>;
2379 reg-names = "rev", "sysc", "syss";
2380 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2381 SYSC_OMAP2_SOFTRESET |
2382 SYSC_OMAP2_AUTOIDLE)>;
2383 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2384 <SYSC_IDLE_NO>,
2385 <SYSC_IDLE_SMART>,
2386 <SYSC_IDLE_SMART_WKUP>;
2387 ti,syss-mask = <1>;
2388 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2389 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2390 clock-names = "fck";
2391 #address-cells = <1>;
2392 #size-cells = <1>;
2393 ranges = <0x0 0x20000 0x1000>;
2394
2395 uart7: serial@0 {
2396 compatible = "ti,dra742-uart", "ti,omap4-uart";
2397 reg = <0x0 0x100>;
2398 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2399 clock-frequency = <48000000>;
2400 status = "disabled";
2401 };
2402 };
2403
2404 target-module@22000 { /* 0x48422000, ap 49 0a.0 */
2405 compatible = "ti,sysc-omap2", "ti,sysc";
2406 reg = <0x22050 0x4>,
2407 <0x22054 0x4>,
2408 <0x22058 0x4>;
2409 reg-names = "rev", "sysc", "syss";
2410 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2411 SYSC_OMAP2_SOFTRESET |
2412 SYSC_OMAP2_AUTOIDLE)>;
2413 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2414 <SYSC_IDLE_NO>,
2415 <SYSC_IDLE_SMART>,
2416 <SYSC_IDLE_SMART_WKUP>;
2417 ti,syss-mask = <1>;
2418 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2419 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2420 clock-names = "fck";
2421 #address-cells = <1>;
2422 #size-cells = <1>;
2423 ranges = <0x0 0x22000 0x1000>;
2424
2425 uart8: serial@0 {
2426 compatible = "ti,dra742-uart", "ti,omap4-uart";
2427 reg = <0x0 0x100>;
2428 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2429 clock-frequency = <48000000>;
2430 status = "disabled";
2431 };
2432 };
2433
2434 target-module@24000 { /* 0x48424000, ap 51 12.0 */
2435 compatible = "ti,sysc-omap2", "ti,sysc";
2436 reg = <0x24050 0x4>,
2437 <0x24054 0x4>,
2438 <0x24058 0x4>;
2439 reg-names = "rev", "sysc", "syss";
2440 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2441 SYSC_OMAP2_SOFTRESET |
2442 SYSC_OMAP2_AUTOIDLE)>;
2443 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2444 <SYSC_IDLE_NO>,
2445 <SYSC_IDLE_SMART>,
2446 <SYSC_IDLE_SMART_WKUP>;
2447 ti,syss-mask = <1>;
2448 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2449 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2450 clock-names = "fck";
2451 #address-cells = <1>;
2452 #size-cells = <1>;
2453 ranges = <0x0 0x24000 0x1000>;
2454
2455 uart9: serial@0 {
2456 compatible = "ti,dra742-uart", "ti,omap4-uart";
2457 reg = <0x0 0x100>;
2458 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2459 clock-frequency = <48000000>;
2460 status = "disabled";
2461 };
2462 };
2463
2464 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
2465 compatible = "ti,sysc";
2466 status = "disabled";
2467 #address-cells = <1>;
2468 #size-cells = <1>;
2469 ranges = <0x0 0x2c000 0x1000>;
2470 };
2471
2472 target-module@36000 { /* 0x48436000, ap 17 06.0 */
2473 compatible = "ti,sysc";
2474 status = "disabled";
2475 #address-cells = <1>;
2476 #size-cells = <1>;
2477 ranges = <0x0 0x36000 0x1000>;
2478 };
2479
2480 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
2481 compatible = "ti,sysc";
2482 status = "disabled";
2483 #address-cells = <1>;
2484 #size-cells = <1>;
2485 ranges = <0x0 0x3a000 0x1000>;
2486 };
2487
2488 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
2489 compatible = "ti,sysc-omap4", "ti,sysc";
2490 reg = <0x3c000 0x4>;
2491 reg-names = "rev";
2492 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2493 clock-names = "fck";
2494 #address-cells = <1>;
2495 #size-cells = <1>;
2496 ranges = <0x0 0x3c000 0x1000>;
2497
2498 atl: atl@0 {
2499 compatible = "ti,dra7-atl";
2500 reg = <0x0 0x3ff>;
2501 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2502 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2503 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2504 clock-names = "fck";
2505 status = "disabled";
2506 };
2507 };
2508
2509 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
2510 compatible = "ti,sysc-omap4", "ti,sysc";
2511 reg = <0x3e000 0x4>,
2512 <0x3e004 0x4>;
2513 reg-names = "rev", "sysc";
2514 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2515 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2516 <SYSC_IDLE_NO>,
2517 <SYSC_IDLE_SMART>;
2518 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2519 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2520 clock-names = "fck";
2521 #address-cells = <1>;
2522 #size-cells = <1>;
2523 ranges = <0x0 0x3e000 0x1000>;
2524
2525 epwmss0: epwmss@0 {
2526 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2527 reg = <0x0 0x30>;
2528 #address-cells = <1>;
2529 #size-cells = <1>;
2530 status = "disabled";
2531 ranges = <0 0 0x1000>;
2532
2533 ecap0: ecap@100 {
2534 compatible = "ti,dra746-ecap",
2535 "ti,am3352-ecap";
2536 #pwm-cells = <3>;
2537 reg = <0x100 0x80>;
2538 clocks = <&l4_root_clk_div>;
2539 clock-names = "fck";
2540 status = "disabled";
2541 };
2542
2543 ehrpwm0: pwm@200 {
2544 compatible = "ti,dra746-ehrpwm",
2545 "ti,am3352-ehrpwm";
2546 #pwm-cells = <3>;
2547 reg = <0x200 0x80>;
2548 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2549 clock-names = "tbclk", "fck";
2550 status = "disabled";
2551 };
2552 };
2553 };
2554
2555 target-module@40000 { /* 0x48440000, ap 27 38.0 */
2556 compatible = "ti,sysc-omap4", "ti,sysc";
2557 reg = <0x40000 0x4>,
2558 <0x40004 0x4>;
2559 reg-names = "rev", "sysc";
2560 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2561 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2562 <SYSC_IDLE_NO>,
2563 <SYSC_IDLE_SMART>;
2564 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2565 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2566 clock-names = "fck";
2567 #address-cells = <1>;
2568 #size-cells = <1>;
2569 ranges = <0x0 0x40000 0x1000>;
2570
2571 epwmss1: epwmss@0 {
2572 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2573 reg = <0x0 0x30>;
2574 #address-cells = <1>;
2575 #size-cells = <1>;
2576 status = "disabled";
2577 ranges = <0 0 0x1000>;
2578
2579 ecap1: ecap@100 {
2580 compatible = "ti,dra746-ecap",
2581 "ti,am3352-ecap";
2582 #pwm-cells = <3>;
2583 reg = <0x100 0x80>;
2584 clocks = <&l4_root_clk_div>;
2585 clock-names = "fck";
2586 status = "disabled";
2587 };
2588
2589 ehrpwm1: pwm@200 {
2590 compatible = "ti,dra746-ehrpwm",
2591 "ti,am3352-ehrpwm";
2592 #pwm-cells = <3>;
2593 reg = <0x200 0x80>;
2594 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2595 clock-names = "tbclk", "fck";
2596 status = "disabled";
2597 };
2598 };
2599 };
2600
2601 target-module@42000 { /* 0x48442000, ap 29 20.0 */
2602 compatible = "ti,sysc-omap4", "ti,sysc";
2603 reg = <0x42000 0x4>,
2604 <0x42004 0x4>;
2605 reg-names = "rev", "sysc";
2606 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2607 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2608 <SYSC_IDLE_NO>,
2609 <SYSC_IDLE_SMART>;
2610 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2611 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2612 clock-names = "fck";
2613 #address-cells = <1>;
2614 #size-cells = <1>;
2615 ranges = <0x0 0x42000 0x1000>;
2616
2617 epwmss2: epwmss@0 {
2618 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2619 reg = <0x0 0x30>;
2620 #address-cells = <1>;
2621 #size-cells = <1>;
2622 status = "disabled";
2623 ranges = <0 0 0x1000>;
2624
2625 ecap2: ecap@100 {
2626 compatible = "ti,dra746-ecap",
2627 "ti,am3352-ecap";
2628 #pwm-cells = <3>;
2629 reg = <0x100 0x80>;
2630 clocks = <&l4_root_clk_div>;
2631 clock-names = "fck";
2632 status = "disabled";
2633 };
2634
2635 ehrpwm2: pwm@200 {
2636 compatible = "ti,dra746-ehrpwm",
2637 "ti,am3352-ehrpwm";
2638 #pwm-cells = <3>;
2639 reg = <0x200 0x80>;
2640 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2641 clock-names = "tbclk", "fck";
2642 status = "disabled";
2643 };
2644 };
2645 };
2646
2647 target-module@46000 { /* 0x48446000, ap 53 40.0 */
2648 compatible = "ti,sysc";
2649 status = "disabled";
2650 #address-cells = <1>;
2651 #size-cells = <1>;
2652 ranges = <0x0 0x46000 0x1000>;
2653 };
2654
2655 target-module@48000 { /* 0x48448000, ap 55 48.0 */
2656 compatible = "ti,sysc";
2657 status = "disabled";
2658 #address-cells = <1>;
2659 #size-cells = <1>;
2660 ranges = <0x0 0x48000 0x1000>;
2661 };
2662
2663 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
2664 compatible = "ti,sysc";
2665 status = "disabled";
2666 #address-cells = <1>;
2667 #size-cells = <1>;
2668 ranges = <0x0 0x4a000 0x1000>;
2669 };
2670
2671 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
2672 compatible = "ti,sysc";
2673 status = "disabled";
2674 #address-cells = <1>;
2675 #size-cells = <1>;
2676 ranges = <0x0 0x4c000 0x1000>;
2677 };
2678
2679 target-module@50000 { /* 0x48450000, ap 37 24.0 */
2680 compatible = "ti,sysc";
2681 status = "disabled";
2682 #address-cells = <1>;
2683 #size-cells = <1>;
2684 ranges = <0x0 0x50000 0x1000>;
2685 };
2686
2687 target-module@54000 { /* 0x48454000, ap 41 2c.0 */
2688 compatible = "ti,sysc";
2689 status = "disabled";
2690 #address-cells = <1>;
2691 #size-cells = <1>;
2692 ranges = <0x0 0x54000 0x1000>;
2693 };
2694
2695 target-module@58000 { /* 0x48458000, ap 57 28.0 */
2696 compatible = "ti,sysc";
2697 status = "disabled";
2698 #address-cells = <1>;
2699 #size-cells = <1>;
2700 ranges = <0x0 0x58000 0x2000>;
2701 };
2702
2703 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
2704 compatible = "ti,sysc";
2705 status = "disabled";
2706 #address-cells = <1>;
2707 #size-cells = <1>;
2708 ranges = <0x0 0x5b000 0x1000>;
2709 };
2710
2711 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
2712 compatible = "ti,sysc";
2713 status = "disabled";
2714 #address-cells = <1>;
2715 #size-cells = <1>;
2716 ranges = <0x0 0x5d000 0x1000>;
2717 };
2718
2719 target-module@60000 { /* 0x48460000, ap 9 0e.0 */
2720 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2721 reg = <0x60000 0x4>,
2722 <0x60004 0x4>;
2723 reg-names = "rev", "sysc";
2724 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2725 <SYSC_IDLE_NO>,
2726 <SYSC_IDLE_SMART>;
2727 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2728 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2729 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2730 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2731 clock-names = "fck", "ahclkx", "ahclkr";
2732 #address-cells = <1>;
2733 #size-cells = <1>;
2734 ranges = <0x0 0x60000 0x2000>,
2735 <0x45800000 0x45800000 0x400000>;
2736
2737 mcasp1: mcasp@0 {
2738 compatible = "ti,dra7-mcasp-audio";
2739 reg = <0x0 0x2000>,
2740 <0x45800000 0x1000>; /* L3 data port */
2741 reg-names = "mpu","dat";
2742 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2743 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2744 interrupt-names = "tx", "rx";
2745 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2746 dma-names = "tx", "rx";
2747 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2748 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2749 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2750 clock-names = "fck", "ahclkx", "ahclkr";
2751 status = "disabled";
2752 };
2753 };
2754
2755 target-module@64000 { /* 0x48464000, ap 11 1e.0 */
2756 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2757 reg = <0x64000 0x4>,
2758 <0x64004 0x4>;
2759 reg-names = "rev", "sysc";
2760 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2761 <SYSC_IDLE_NO>,
2762 <SYSC_IDLE_SMART>;
2763 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2764 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2765 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2766 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2767 clock-names = "fck", "ahclkx", "ahclkr";
2768 #address-cells = <1>;
2769 #size-cells = <1>;
2770 ranges = <0x0 0x64000 0x2000>,
2771 <0x45c00000 0x45c00000 0x400000>;
2772
2773 mcasp2: mcasp@0 {
2774 compatible = "ti,dra7-mcasp-audio";
2775 reg = <0x0 0x2000>,
2776 <0x45c00000 0x1000>; /* L3 data port */
2777 reg-names = "mpu","dat";
2778 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2779 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2780 interrupt-names = "tx", "rx";
2781 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2782 dma-names = "tx", "rx";
2783 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2784 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2785 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2786 clock-names = "fck", "ahclkx", "ahclkr";
2787 status = "disabled";
2788 };
2789 };
2790
2791 target-module@68000 { /* 0x48468000, ap 13 26.0 */
2792 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2793 reg = <0x68000 0x4>,
2794 <0x68004 0x4>;
2795 reg-names = "rev", "sysc";
2796 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2797 <SYSC_IDLE_NO>,
2798 <SYSC_IDLE_SMART>;
2799 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2800 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2801 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2802 clock-names = "fck", "ahclkx";
2803 #address-cells = <1>;
2804 #size-cells = <1>;
2805 ranges = <0x0 0x68000 0x2000>,
2806 <0x46000000 0x46000000 0x400000>;
2807
2808 mcasp3: mcasp@0 {
2809 compatible = "ti,dra7-mcasp-audio";
2810 reg = <0x0 0x2000>,
2811 <0x46000000 0x1000>; /* L3 data port */
2812 reg-names = "mpu","dat";
2813 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2814 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2815 interrupt-names = "tx", "rx";
2816 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2817 dma-names = "tx", "rx";
2818 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2819 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2820 clock-names = "fck", "ahclkx";
2821 status = "disabled";
2822 };
2823 };
2824
2825 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
2826 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2827 reg = <0x6c000 0x4>,
2828 <0x6c004 0x4>;
2829 reg-names = "rev", "sysc";
2830 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2831 <SYSC_IDLE_NO>,
2832 <SYSC_IDLE_SMART>;
2833 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2834 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2835 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2836 clock-names = "fck", "ahclkx";
2837 #address-cells = <1>;
2838 #size-cells = <1>;
2839 ranges = <0x0 0x6c000 0x2000>,
2840 <0x48436000 0x48436000 0x400000>;
2841
2842 mcasp4: mcasp@0 {
2843 compatible = "ti,dra7-mcasp-audio";
2844 reg = <0x0 0x2000>,
2845 <0x48436000 0x1000>; /* L3 data port */
2846 reg-names = "mpu","dat";
2847 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2848 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2849 interrupt-names = "tx", "rx";
2850 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2851 dma-names = "tx", "rx";
2852 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2853 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2854 clock-names = "fck", "ahclkx";
2855 status = "disabled";
2856 };
2857 };
2858
2859 target-module@70000 { /* 0x48470000, ap 19 36.0 */
2860 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2861 reg = <0x70000 0x4>,
2862 <0x70004 0x4>;
2863 reg-names = "rev", "sysc";
2864 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2865 <SYSC_IDLE_NO>,
2866 <SYSC_IDLE_SMART>;
2867 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2868 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2869 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2870 clock-names = "fck", "ahclkx";
2871 #address-cells = <1>;
2872 #size-cells = <1>;
2873 ranges = <0x0 0x70000 0x2000>,
2874 <0x4843a000 0x4843a000 0x400000>;
2875
2876 mcasp5: mcasp@0 {
2877 compatible = "ti,dra7-mcasp-audio";
2878 reg = <0x0 0x2000>,
2879 <0x4843a000 0x1000>; /* L3 data port */
2880 reg-names = "mpu","dat";
2881 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2882 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2883 interrupt-names = "tx", "rx";
2884 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2885 dma-names = "tx", "rx";
2886 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2887 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2888 clock-names = "fck", "ahclkx";
2889 status = "disabled";
2890 };
2891 };
2892
2893 target-module@74000 { /* 0x48474000, ap 35 14.0 */
2894 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2895 reg = <0x74000 0x4>,
2896 <0x74004 0x4>;
2897 reg-names = "rev", "sysc";
2898 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2899 <SYSC_IDLE_NO>,
2900 <SYSC_IDLE_SMART>;
2901 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2902 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2903 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2904 clock-names = "fck", "ahclkx";
2905 #address-cells = <1>;
2906 #size-cells = <1>;
2907 ranges = <0x0 0x74000 0x2000>,
2908 <0x4844c000 0x4844c000 0x400000>;
2909
2910 mcasp6: mcasp@0 {
2911 compatible = "ti,dra7-mcasp-audio";
2912 reg = <0x0 0x2000>,
2913 <0x4844c000 0x1000>; /* L3 data port */
2914 reg-names = "mpu","dat";
2915 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2916 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2917 interrupt-names = "tx", "rx";
2918 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2919 dma-names = "tx", "rx";
2920 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2921 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2922 clock-names = "fck", "ahclkx";
2923 status = "disabled";
2924 };
2925 };
2926
2927 target-module@78000 { /* 0x48478000, ap 39 0c.0 */
2928 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2929 reg = <0x78000 0x4>,
2930 <0x78004 0x4>;
2931 reg-names = "rev", "sysc";
2932 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2933 <SYSC_IDLE_NO>,
2934 <SYSC_IDLE_SMART>;
2935 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2936 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2937 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2938 clock-names = "fck", "ahclkx";
2939 #address-cells = <1>;
2940 #size-cells = <1>;
2941 ranges = <0x0 0x78000 0x2000>,
2942 <0x48450000 0x48450000 0x400000>;
2943
2944 mcasp7: mcasp@0 {
2945 compatible = "ti,dra7-mcasp-audio";
2946 reg = <0x0 0x2000>,
2947 <0x48450000 0x1000>; /* L3 data port */
2948 reg-names = "mpu","dat";
2949 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2950 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2951 interrupt-names = "tx", "rx";
2952 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2953 dma-names = "tx", "rx";
2954 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2955 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2956 clock-names = "fck", "ahclkx";
2957 status = "disabled";
2958 };
2959 };
2960
2961 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
2962 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2963 reg = <0x7c000 0x4>,
2964 <0x7c004 0x4>;
2965 reg-names = "rev", "sysc";
2966 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2967 <SYSC_IDLE_NO>,
2968 <SYSC_IDLE_SMART>;
2969 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2970 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2971 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2972 clock-names = "fck", "ahclkx";
2973 #address-cells = <1>;
2974 #size-cells = <1>;
2975 ranges = <0x0 0x7c000 0x2000>,
2976 <0x48454000 0x48454000 0x400000>;
2977
2978 mcasp8: mcasp@0 {
2979 compatible = "ti,dra7-mcasp-audio";
2980 reg = <0x0 0x2000>,
2981 <0x48454000 0x1000>; /* L3 data port */
2982 reg-names = "mpu","dat";
2983 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2984 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2985 interrupt-names = "tx", "rx";
2986 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
2987 dma-names = "tx", "rx";
2988 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2989 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2990 clock-names = "fck", "ahclkx";
2991 status = "disabled";
2992 };
2993 };
2994
2995 target-module@80000 { /* 0x48480000, ap 31 16.0 */
2996 compatible = "ti,sysc-omap4", "ti,sysc";
2997 reg = <0x80020 0x4>;
2998 reg-names = "rev";
2999 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
3000 clock-names = "fck";
3001 #address-cells = <1>;
3002 #size-cells = <1>;
3003 ranges = <0x0 0x80000 0x2000>;
3004
3005 dcan2: can@0 {
3006 compatible = "ti,dra7-d_can";
3007 reg = <0x0 0x2000>;
3008 syscon-raminit = <&scm_conf 0x558 1>;
3009 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
3010 clocks = <&sys_clkin1>;
3011 status = "disabled";
3012 };
3013 };
3014
3015 target-module@84000 { /* 0x48484000, ap 3 10.0 */
3016 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3017 reg = <0x85200 0x4>,
3018 <0x85208 0x4>,
3019 <0x85204 0x4>;
3020 reg-names = "rev", "sysc", "syss";
3021 ti,sysc-mask = <0>;
3022 ti,sysc-midle = <SYSC_IDLE_FORCE>,
3023 <SYSC_IDLE_NO>;
3024 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3025 <SYSC_IDLE_NO>;
3026 ti,syss-mask = <1>;
3027 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3028 clock-names = "fck";
3029 #address-cells = <1>;
3030 #size-cells = <1>;
3031 ranges = <0x0 0x84000 0x4000>;
3032 /*
3033 * Do not allow gating of cpsw clock as workaround
3034 * for errata i877. Keeping internal clock disabled
3035 * causes the device switching characteristics
3036 * to degrade over time and eventually fail to meet
3037 * the data manual delay time/skew specs.
3038 */
3039 ti,no-idle;
3040
3041 mac: ethernet@0 {
3042 compatible = "ti,dra7-cpsw","ti,cpsw";
3043 clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3044 clock-names = "fck", "cpts";
3045 cpdma_channels = <8>;
3046 ale_entries = <1024>;
3047 bd_ram_size = <0x2000>;
3048 mac_control = <0x20>;
3049 slaves = <2>;
3050 active_slave = <0>;
3051 cpts_clock_mult = <0x784CFE14>;
3052 cpts_clock_shift = <29>;
3053 reg = <0x0 0x1000
3054 0x1200 0x2e00>;
3055 #address-cells = <1>;
3056 #size-cells = <1>;
3057
3058 /*
3059 * rx_thresh_pend
3060 * rx_pend
3061 * tx_pend
3062 * misc_pend
3063 */
3064 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3065 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3066 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3067 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3068 ranges = <0 0 0x4000>;
3069 syscon = <&scm_conf>;
3070 status = "disabled";
3071
3072 davinci_mdio: mdio@1000 {
3073 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3074 clocks = <&gmac_main_clk>;
3075 clock-names = "fck";
3076 #address-cells = <1>;
3077 #size-cells = <0>;
3078 bus_freq = <1000000>;
3079 reg = <0x1000 0x100>;
3080 };
3081
3082 cpsw_emac0: slave@200 {
3083 /* Filled in by U-Boot */
3084 mac-address = [ 00 00 00 00 00 00 ];
3085 phys = <&phy_gmii_sel 1>;
3086 };
3087
3088 cpsw_emac1: slave@300 {
3089 /* Filled in by U-Boot */
3090 mac-address = [ 00 00 00 00 00 00 ];
3091 phys = <&phy_gmii_sel 2>;
3092 };
3093 };
3094
3095 mac_sw: switch@0 {
3096 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
3097 reg = <0x0 0x4000>;
3098 ranges = <0 0 0x4000>;
3099 clocks = <&gmac_main_clk>;
3100 clock-names = "fck";
3101 #address-cells = <1>;
3102 #size-cells = <1>;
3103 syscon = <&scm_conf>;
3104 status = "disabled";
3105
3106 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3110 interrupt-names = "rx_thresh", "rx", "tx", "misc";
3111
3112 ethernet-ports {
3113 #address-cells = <1>;
3114 #size-cells = <0>;
3115
3116 cpsw_port1: port@1 {
3117 reg = <1>;
3118 label = "port1";
3119 mac-address = [ 00 00 00 00 00 00 ];
3120 phys = <&phy_gmii_sel 1>;
3121 };
3122
3123 cpsw_port2: port@2 {
3124 reg = <2>;
3125 label = "port2";
3126 mac-address = [ 00 00 00 00 00 00 ];
3127 phys = <&phy_gmii_sel 2>;
3128 };
3129 };
3130
3131 davinci_mdio_sw: mdio@1000 {
3132 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3133 clocks = <&gmac_main_clk>;
3134 clock-names = "fck";
3135 #address-cells = <1>;
3136 #size-cells = <0>;
3137 bus_freq = <1000000>;
3138 reg = <0x1000 0x100>;
3139 };
3140
3141 cpts {
3142 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3143 clock-names = "cpts";
3144 };
3145 };
3146 };
3147 };
3148};
3149
3150&l4_per3 { /* 0x48800000 */
3151 compatible = "ti,dra7-l4-per3", "simple-bus";
3152 reg = <0x48800000 0x800>,
3153 <0x48800800 0x800>,
3154 <0x48801000 0x400>,
3155 <0x48801400 0x400>,
3156 <0x48801800 0x400>;
3157 reg-names = "ap", "la", "ia0", "ia1", "ia2";
3158 #address-cells = <1>;
3159 #size-cells = <1>;
3160 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
3161
3162 segment@0 { /* 0x48800000 */
3163 compatible = "simple-bus";
3164 #address-cells = <1>;
3165 #size-cells = <1>;
3166 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
3167 <0x00000800 0x00000800 0x000800>, /* ap 1 */
3168 <0x00001000 0x00001000 0x000400>, /* ap 2 */
3169 <0x00001400 0x00001400 0x000400>, /* ap 3 */
3170 <0x00001800 0x00001800 0x000400>, /* ap 4 */
3171 <0x00020000 0x00020000 0x001000>, /* ap 5 */
3172 <0x00021000 0x00021000 0x001000>, /* ap 6 */
3173 <0x00022000 0x00022000 0x001000>, /* ap 7 */
3174 <0x00023000 0x00023000 0x001000>, /* ap 8 */
3175 <0x00024000 0x00024000 0x001000>, /* ap 9 */
3176 <0x00025000 0x00025000 0x001000>, /* ap 10 */
3177 <0x00026000 0x00026000 0x001000>, /* ap 11 */
3178 <0x00027000 0x00027000 0x001000>, /* ap 12 */
3179 <0x00028000 0x00028000 0x001000>, /* ap 13 */
3180 <0x00029000 0x00029000 0x001000>, /* ap 14 */
3181 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */
3182 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */
3183 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */
3184 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */
3185 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */
3186 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */
3187 <0x00170000 0x00170000 0x010000>, /* ap 21 */
3188 <0x00180000 0x00180000 0x001000>, /* ap 22 */
3189 <0x00190000 0x00190000 0x010000>, /* ap 23 */
3190 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */
3191 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */
3192 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */
3193 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */
3194 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */
3195 <0x00038000 0x00038000 0x001000>, /* ap 29 */
3196 <0x00039000 0x00039000 0x001000>, /* ap 30 */
3197 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */
3198 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */
3199 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */
3200 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */
3201 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */
3202 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */
3203 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */
3204 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */
3205 <0x00040000 0x00040000 0x001000>, /* ap 39 */
3206 <0x00041000 0x00041000 0x001000>, /* ap 40 */
3207 <0x00042000 0x00042000 0x001000>, /* ap 41 */
3208 <0x00043000 0x00043000 0x001000>, /* ap 42 */
3209 <0x00044000 0x00044000 0x001000>, /* ap 43 */
3210 <0x00045000 0x00045000 0x001000>, /* ap 44 */
3211 <0x00046000 0x00046000 0x001000>, /* ap 45 */
3212 <0x00047000 0x00047000 0x001000>, /* ap 46 */
3213 <0x00048000 0x00048000 0x001000>, /* ap 47 */
3214 <0x00049000 0x00049000 0x001000>, /* ap 48 */
3215 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */
3216 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */
3217 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */
3218 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */
3219 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */
3220 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */
3221 <0x00050000 0x00050000 0x001000>, /* ap 55 */
3222 <0x00051000 0x00051000 0x001000>, /* ap 56 */
3223 <0x00052000 0x00052000 0x001000>, /* ap 57 */
3224 <0x00053000 0x00053000 0x001000>, /* ap 58 */
3225 <0x00054000 0x00054000 0x001000>, /* ap 59 */
3226 <0x00055000 0x00055000 0x001000>, /* ap 60 */
3227 <0x00056000 0x00056000 0x001000>, /* ap 61 */
3228 <0x00057000 0x00057000 0x001000>, /* ap 62 */
3229 <0x00058000 0x00058000 0x001000>, /* ap 63 */
3230 <0x00059000 0x00059000 0x001000>, /* ap 64 */
3231 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */
3232 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */
3233 <0x00064000 0x00064000 0x001000>, /* ap 67 */
3234 <0x00065000 0x00065000 0x001000>, /* ap 68 */
3235 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */
3236 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */
3237 <0x00060000 0x00060000 0x001000>, /* ap 71 */
3238 <0x00061000 0x00061000 0x001000>, /* ap 72 */
3239 <0x00062000 0x00062000 0x001000>, /* ap 73 */
3240 <0x00063000 0x00063000 0x001000>, /* ap 74 */
3241 <0x00140000 0x00140000 0x020000>, /* ap 75 */
3242 <0x00160000 0x00160000 0x001000>, /* ap 76 */
3243 <0x00016000 0x00016000 0x001000>, /* ap 77 */
3244 <0x00017000 0x00017000 0x001000>, /* ap 78 */
3245 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */
3246 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */
3247 <0x00004000 0x00004000 0x001000>, /* ap 81 */
3248 <0x00005000 0x00005000 0x001000>, /* ap 82 */
3249 <0x00080000 0x00080000 0x020000>, /* ap 83 */
3250 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */
3251 <0x00100000 0x00100000 0x020000>, /* ap 85 */
3252 <0x00120000 0x00120000 0x001000>, /* ap 86 */
3253 <0x00010000 0x00010000 0x001000>, /* ap 87 */
3254 <0x00011000 0x00011000 0x001000>, /* ap 88 */
3255 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */
3256 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */
3257 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */
3258 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */
3259 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */
3260 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */
3261 <0x00002000 0x00002000 0x001000>, /* ap 95 */
3262 <0x00003000 0x00003000 0x001000>; /* ap 96 */
3263
3264 target-module@2000 { /* 0x48802000, ap 95 7c.0 */
3265 compatible = "ti,sysc-omap4", "ti,sysc";
3266 reg = <0x2000 0x4>,
3267 <0x2010 0x4>;
3268 reg-names = "rev", "sysc";
3269 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3270 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3271 <SYSC_IDLE_NO>,
3272 <SYSC_IDLE_SMART>;
3273 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3274 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3275 clock-names = "fck";
3276 #address-cells = <1>;
3277 #size-cells = <1>;
3278 ranges = <0x0 0x2000 0x1000>;
3279
3280 mailbox13: mailbox@0 {
3281 compatible = "ti,omap4-mailbox";
3282 reg = <0x0 0x200>;
3283 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
3284 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3285 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
3286 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
3287 #mbox-cells = <1>;
3288 ti,mbox-num-users = <4>;
3289 ti,mbox-num-fifos = <12>;
3290 status = "disabled";
3291 };
3292 };
3293
3294 target-module@4000 { /* 0x48804000, ap 81 20.0 */
3295 compatible = "ti,sysc";
3296 status = "disabled";
3297 #address-cells = <1>;
3298 #size-cells = <1>;
3299 ranges = <0x0 0x4000 0x1000>;
3300 };
3301
3302 target-module@a000 { /* 0x4880a000, ap 89 18.0 */
3303 compatible = "ti,sysc";
3304 status = "disabled";
3305 #address-cells = <1>;
3306 #size-cells = <1>;
3307 ranges = <0x0 0xa000 0x1000>;
3308 };
3309
3310 target-module@10000 { /* 0x48810000, ap 87 28.0 */
3311 compatible = "ti,sysc";
3312 status = "disabled";
3313 #address-cells = <1>;
3314 #size-cells = <1>;
3315 ranges = <0x0 0x10000 0x1000>;
3316 };
3317
3318 target-module@16000 { /* 0x48816000, ap 77 1e.0 */
3319 compatible = "ti,sysc";
3320 status = "disabled";
3321 #address-cells = <1>;
3322 #size-cells = <1>;
3323 ranges = <0x0 0x16000 0x1000>;
3324 };
3325
3326 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */
3327 compatible = "ti,sysc";
3328 status = "disabled";
3329 #address-cells = <1>;
3330 #size-cells = <1>;
3331 ranges = <0x0 0x1c000 0x1000>;
3332 };
3333
3334 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
3335 compatible = "ti,sysc";
3336 status = "disabled";
3337 #address-cells = <1>;
3338 #size-cells = <1>;
3339 ranges = <0x0 0x1e000 0x1000>;
3340 };
3341
3342 target-module@20000 { /* 0x48820000, ap 5 08.0 */
3343 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3344 reg = <0x20000 0x4>,
3345 <0x20010 0x4>;
3346 reg-names = "rev", "sysc";
3347 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3348 SYSC_OMAP4_SOFTRESET)>;
3349 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3350 <SYSC_IDLE_NO>,
3351 <SYSC_IDLE_SMART>,
3352 <SYSC_IDLE_SMART_WKUP>;
3353 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3354 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3355 clock-names = "fck";
3356 #address-cells = <1>;
3357 #size-cells = <1>;
3358 ranges = <0x0 0x20000 0x1000>;
3359
3360 timer5: timer@0 {
3361 compatible = "ti,omap5430-timer";
3362 reg = <0x0 0x80>;
3363 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>;
3364 clock-names = "fck", "timer_sys_ck";
3365 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3366 };
3367 };
3368
3369 target-module@22000 { /* 0x48822000, ap 7 24.0 */
3370 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3371 reg = <0x22000 0x4>,
3372 <0x22010 0x4>;
3373 reg-names = "rev", "sysc";
3374 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3375 SYSC_OMAP4_SOFTRESET)>;
3376 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3377 <SYSC_IDLE_NO>,
3378 <SYSC_IDLE_SMART>,
3379 <SYSC_IDLE_SMART_WKUP>;
3380 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3381 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3382 clock-names = "fck";
3383 #address-cells = <1>;
3384 #size-cells = <1>;
3385 ranges = <0x0 0x22000 0x1000>;
3386
3387 timer6: timer@0 {
3388 compatible = "ti,omap5430-timer";
3389 reg = <0x0 0x80>;
3390 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>;
3391 clock-names = "fck", "timer_sys_ck";
3392 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3393 };
3394 };
3395
3396 target-module@24000 { /* 0x48824000, ap 9 26.0 */
3397 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3398 reg = <0x24000 0x4>,
3399 <0x24010 0x4>;
3400 reg-names = "rev", "sysc";
3401 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3402 SYSC_OMAP4_SOFTRESET)>;
3403 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3404 <SYSC_IDLE_NO>,
3405 <SYSC_IDLE_SMART>,
3406 <SYSC_IDLE_SMART_WKUP>;
3407 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3408 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3409 clock-names = "fck";
3410 #address-cells = <1>;
3411 #size-cells = <1>;
3412 ranges = <0x0 0x24000 0x1000>;
3413
3414 timer7: timer@0 {
3415 compatible = "ti,omap5430-timer";
3416 reg = <0x0 0x80>;
3417 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>;
3418 clock-names = "fck", "timer_sys_ck";
3419 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3420 };
3421 };
3422
3423 target-module@26000 { /* 0x48826000, ap 11 0c.0 */
3424 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3425 reg = <0x26000 0x4>,
3426 <0x26010 0x4>;
3427 reg-names = "rev", "sysc";
3428 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3429 SYSC_OMAP4_SOFTRESET)>;
3430 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3431 <SYSC_IDLE_NO>,
3432 <SYSC_IDLE_SMART>,
3433 <SYSC_IDLE_SMART_WKUP>;
3434 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3435 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3436 clock-names = "fck";
3437 #address-cells = <1>;
3438 #size-cells = <1>;
3439 ranges = <0x0 0x26000 0x1000>;
3440
3441 timer8: timer@0 {
3442 compatible = "ti,omap5430-timer";
3443 reg = <0x0 0x80>;
3444 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>;
3445 clock-names = "fck", "timer_sys_ck";
3446 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3447 };
3448 };
3449
3450 target-module@28000 { /* 0x48828000, ap 13 16.0 */
3451 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3452 reg = <0x28000 0x4>,
3453 <0x28010 0x4>;
3454 reg-names = "rev", "sysc";
3455 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3456 SYSC_OMAP4_SOFTRESET)>;
3457 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3458 <SYSC_IDLE_NO>,
3459 <SYSC_IDLE_SMART>,
3460 <SYSC_IDLE_SMART_WKUP>;
3461 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3462 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3463 clock-names = "fck";
3464 #address-cells = <1>;
3465 #size-cells = <1>;
3466 ranges = <0x0 0x28000 0x1000>;
3467
3468 timer13: timer@0 {
3469 compatible = "ti,omap5430-timer";
3470 reg = <0x0 0x80>;
3471 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>;
3472 clock-names = "fck", "timer_sys_ck";
3473 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
3474 ti,timer-pwm;
3475 };
3476 };
3477
3478 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
3479 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3480 reg = <0x2a000 0x4>,
3481 <0x2a010 0x4>;
3482 reg-names = "rev", "sysc";
3483 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3484 SYSC_OMAP4_SOFTRESET)>;
3485 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3486 <SYSC_IDLE_NO>,
3487 <SYSC_IDLE_SMART>,
3488 <SYSC_IDLE_SMART_WKUP>;
3489 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3490 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3491 clock-names = "fck";
3492 #address-cells = <1>;
3493 #size-cells = <1>;
3494 ranges = <0x0 0x2a000 0x1000>;
3495
3496 timer14: timer@0 {
3497 compatible = "ti,omap5430-timer";
3498 reg = <0x0 0x80>;
3499 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>;
3500 clock-names = "fck", "timer_sys_ck";
3501 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
3502 ti,timer-pwm;
3503 };
3504 };
3505
3506 target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
3507 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3508 reg = <0x2c000 0x4>,
3509 <0x2c010 0x4>;
3510 reg-names = "rev", "sysc";
3511 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3512 SYSC_OMAP4_SOFTRESET)>;
3513 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3514 <SYSC_IDLE_NO>,
3515 <SYSC_IDLE_SMART>,
3516 <SYSC_IDLE_SMART_WKUP>;
3517 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3518 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3519 clock-names = "fck";
3520 #address-cells = <1>;
3521 #size-cells = <1>;
3522 ranges = <0x0 0x2c000 0x1000>;
3523
3524 timer15: timer@0 {
3525 compatible = "ti,omap5430-timer";
3526 reg = <0x0 0x80>;
3527 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>;
3528 clock-names = "fck", "timer_sys_ck";
3529 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
3530 ti,timer-pwm;
3531 };
3532 };
3533
3534 target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
3535 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3536 reg = <0x2e000 0x4>,
3537 <0x2e010 0x4>;
3538 reg-names = "rev", "sysc";
3539 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3540 SYSC_OMAP4_SOFTRESET)>;
3541 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3542 <SYSC_IDLE_NO>,
3543 <SYSC_IDLE_SMART>,
3544 <SYSC_IDLE_SMART_WKUP>;
3545 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3546 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3547 clock-names = "fck";
3548 #address-cells = <1>;
3549 #size-cells = <1>;
3550 ranges = <0x0 0x2e000 0x1000>;
3551
3552 timer16: timer@0 {
3553 compatible = "ti,omap5430-timer";
3554 reg = <0x0 0x80>;
3555 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>;
3556 clock-names = "fck", "timer_sys_ck";
3557 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
3558 ti,timer-pwm;
3559 };
3560 };
3561
3562 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
3563 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3564 ti,hwmods = "rtcss";
3565 reg = <0x38074 0x4>,
3566 <0x38078 0x4>;
3567 reg-names = "rev", "sysc";
3568 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3569 <SYSC_IDLE_NO>,
3570 <SYSC_IDLE_SMART>,
3571 <SYSC_IDLE_SMART_WKUP>;
3572 /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
3573 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3574 clock-names = "fck";
3575 #address-cells = <1>;
3576 #size-cells = <1>;
3577 ranges = <0x0 0x38000 0x1000>;
3578
3579 rtc: rtc@0 {
3580 compatible = "ti,am3352-rtc";
3581 reg = <0x0 0x100>;
3582 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
3584 clocks = <&sys_32k_ck>;
3585 };
3586 };
3587
3588 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
3589 compatible = "ti,sysc-omap4", "ti,sysc";
3590 reg = <0x3a000 0x4>,
3591 <0x3a010 0x4>;
3592 reg-names = "rev", "sysc";
3593 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3594 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3595 <SYSC_IDLE_NO>,
3596 <SYSC_IDLE_SMART>;
3597 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3598 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3599 clock-names = "fck";
3600 #address-cells = <1>;
3601 #size-cells = <1>;
3602 ranges = <0x0 0x3a000 0x1000>;
3603
3604 mailbox2: mailbox@0 {
3605 compatible = "ti,omap4-mailbox";
3606 reg = <0x0 0x200>;
3607 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
3611 #mbox-cells = <1>;
3612 ti,mbox-num-users = <4>;
3613 ti,mbox-num-fifos = <12>;
3614 status = "disabled";
3615 };
3616 };
3617
3618 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
3619 compatible = "ti,sysc-omap4", "ti,sysc";
3620 reg = <0x3c000 0x4>,
3621 <0x3c010 0x4>;
3622 reg-names = "rev", "sysc";
3623 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3624 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3625 <SYSC_IDLE_NO>,
3626 <SYSC_IDLE_SMART>;
3627 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3628 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3629 clock-names = "fck";
3630 #address-cells = <1>;
3631 #size-cells = <1>;
3632 ranges = <0x0 0x3c000 0x1000>;
3633
3634 mailbox3: mailbox@0 {
3635 compatible = "ti,omap4-mailbox";
3636 reg = <0x0 0x200>;
3637 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3638 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3639 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
3640 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
3641 #mbox-cells = <1>;
3642 ti,mbox-num-users = <4>;
3643 ti,mbox-num-fifos = <12>;
3644 status = "disabled";
3645 };
3646 };
3647
3648 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
3649 compatible = "ti,sysc-omap4", "ti,sysc";
3650 reg = <0x3e000 0x4>,
3651 <0x3e010 0x4>;
3652 reg-names = "rev", "sysc";
3653 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3654 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3655 <SYSC_IDLE_NO>,
3656 <SYSC_IDLE_SMART>;
3657 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3658 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3659 clock-names = "fck";
3660 #address-cells = <1>;
3661 #size-cells = <1>;
3662 ranges = <0x0 0x3e000 0x1000>;
3663
3664 mailbox4: mailbox@0 {
3665 compatible = "ti,omap4-mailbox";
3666 reg = <0x0 0x200>;
3667 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3668 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3669 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3670 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3671 #mbox-cells = <1>;
3672 ti,mbox-num-users = <4>;
3673 ti,mbox-num-fifos = <12>;
3674 status = "disabled";
3675 };
3676 };
3677
3678 target-module@40000 { /* 0x48840000, ap 39 64.0 */
3679 compatible = "ti,sysc-omap4", "ti,sysc";
3680 reg = <0x40000 0x4>,
3681 <0x40010 0x4>;
3682 reg-names = "rev", "sysc";
3683 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3684 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3685 <SYSC_IDLE_NO>,
3686 <SYSC_IDLE_SMART>;
3687 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3688 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3689 clock-names = "fck";
3690 #address-cells = <1>;
3691 #size-cells = <1>;
3692 ranges = <0x0 0x40000 0x1000>;
3693
3694 mailbox5: mailbox@0 {
3695 compatible = "ti,omap4-mailbox";
3696 reg = <0x0 0x200>;
3697 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3698 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3699 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3700 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
3701 #mbox-cells = <1>;
3702 ti,mbox-num-users = <4>;
3703 ti,mbox-num-fifos = <12>;
3704 status = "disabled";
3705 };
3706 };
3707
3708 target-module@42000 { /* 0x48842000, ap 41 4e.0 */
3709 compatible = "ti,sysc-omap4", "ti,sysc";
3710 reg = <0x42000 0x4>,
3711 <0x42010 0x4>;
3712 reg-names = "rev", "sysc";
3713 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3714 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3715 <SYSC_IDLE_NO>,
3716 <SYSC_IDLE_SMART>;
3717 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3718 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3719 clock-names = "fck";
3720 #address-cells = <1>;
3721 #size-cells = <1>;
3722 ranges = <0x0 0x42000 0x1000>;
3723
3724 mailbox6: mailbox@0 {
3725 compatible = "ti,omap4-mailbox";
3726 reg = <0x0 0x200>;
3727 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3728 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
3731 #mbox-cells = <1>;
3732 ti,mbox-num-users = <4>;
3733 ti,mbox-num-fifos = <12>;
3734 status = "disabled";
3735 };
3736 };
3737
3738 target-module@44000 { /* 0x48844000, ap 43 42.0 */
3739 compatible = "ti,sysc-omap4", "ti,sysc";
3740 reg = <0x44000 0x4>,
3741 <0x44010 0x4>;
3742 reg-names = "rev", "sysc";
3743 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3744 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3745 <SYSC_IDLE_NO>,
3746 <SYSC_IDLE_SMART>;
3747 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3748 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3749 clock-names = "fck";
3750 #address-cells = <1>;
3751 #size-cells = <1>;
3752 ranges = <0x0 0x44000 0x1000>;
3753
3754 mailbox7: mailbox@0 {
3755 compatible = "ti,omap4-mailbox";
3756 reg = <0x0 0x200>;
3757 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3758 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3759 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
3760 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
3761 #mbox-cells = <1>;
3762 ti,mbox-num-users = <4>;
3763 ti,mbox-num-fifos = <12>;
3764 status = "disabled";
3765 };
3766 };
3767
3768 target-module@46000 { /* 0x48846000, ap 45 48.0 */
3769 compatible = "ti,sysc-omap4", "ti,sysc";
3770 reg = <0x46000 0x4>,
3771 <0x46010 0x4>;
3772 reg-names = "rev", "sysc";
3773 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3774 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3775 <SYSC_IDLE_NO>,
3776 <SYSC_IDLE_SMART>;
3777 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3778 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3779 clock-names = "fck";
3780 #address-cells = <1>;
3781 #size-cells = <1>;
3782 ranges = <0x0 0x46000 0x1000>;
3783
3784 mailbox8: mailbox@0 {
3785 compatible = "ti,omap4-mailbox";
3786 reg = <0x0 0x200>;
3787 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3788 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3789 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3790 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
3791 #mbox-cells = <1>;
3792 ti,mbox-num-users = <4>;
3793 ti,mbox-num-fifos = <12>;
3794 status = "disabled";
3795 };
3796 };
3797
3798 target-module@48000 { /* 0x48848000, ap 47 36.0 */
3799 compatible = "ti,sysc";
3800 status = "disabled";
3801 #address-cells = <1>;
3802 #size-cells = <1>;
3803 ranges = <0x0 0x48000 0x1000>;
3804 };
3805
3806 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */
3807 compatible = "ti,sysc";
3808 status = "disabled";
3809 #address-cells = <1>;
3810 #size-cells = <1>;
3811 ranges = <0x0 0x4a000 0x1000>;
3812 };
3813
3814 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */
3815 compatible = "ti,sysc";
3816 status = "disabled";
3817 #address-cells = <1>;
3818 #size-cells = <1>;
3819 ranges = <0x0 0x4c000 0x1000>;
3820 };
3821
3822 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */
3823 compatible = "ti,sysc";
3824 status = "disabled";
3825 #address-cells = <1>;
3826 #size-cells = <1>;
3827 ranges = <0x0 0x4e000 0x1000>;
3828 };
3829
3830 target-module@50000 { /* 0x48850000, ap 55 40.0 */
3831 compatible = "ti,sysc";
3832 status = "disabled";
3833 #address-cells = <1>;
3834 #size-cells = <1>;
3835 ranges = <0x0 0x50000 0x1000>;
3836 };
3837
3838 target-module@52000 { /* 0x48852000, ap 57 54.0 */
3839 compatible = "ti,sysc";
3840 status = "disabled";
3841 #address-cells = <1>;
3842 #size-cells = <1>;
3843 ranges = <0x0 0x52000 0x1000>;
3844 };
3845
3846 target-module@54000 { /* 0x48854000, ap 59 1a.0 */
3847 compatible = "ti,sysc";
3848 status = "disabled";
3849 #address-cells = <1>;
3850 #size-cells = <1>;
3851 ranges = <0x0 0x54000 0x1000>;
3852 };
3853
3854 target-module@56000 { /* 0x48856000, ap 61 22.0 */
3855 compatible = "ti,sysc";
3856 status = "disabled";
3857 #address-cells = <1>;
3858 #size-cells = <1>;
3859 ranges = <0x0 0x56000 0x1000>;
3860 };
3861
3862 target-module@58000 { /* 0x48858000, ap 63 2a.0 */
3863 compatible = "ti,sysc";
3864 status = "disabled";
3865 #address-cells = <1>;
3866 #size-cells = <1>;
3867 ranges = <0x0 0x58000 0x1000>;
3868 };
3869
3870 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */
3871 compatible = "ti,sysc";
3872 status = "disabled";
3873 #address-cells = <1>;
3874 #size-cells = <1>;
3875 ranges = <0x0 0x5a000 0x1000>;
3876 };
3877
3878 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
3879 compatible = "ti,sysc";
3880 status = "disabled";
3881 #address-cells = <1>;
3882 #size-cells = <1>;
3883 ranges = <0x0 0x5c000 0x1000>;
3884 };
3885
3886 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
3887 compatible = "ti,sysc-omap4", "ti,sysc";
3888 reg = <0x5e000 0x4>,
3889 <0x5e010 0x4>;
3890 reg-names = "rev", "sysc";
3891 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3892 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3893 <SYSC_IDLE_NO>,
3894 <SYSC_IDLE_SMART>;
3895 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3896 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3897 clock-names = "fck";
3898 #address-cells = <1>;
3899 #size-cells = <1>;
3900 ranges = <0x0 0x5e000 0x1000>;
3901
3902 mailbox9: mailbox@0 {
3903 compatible = "ti,omap4-mailbox";
3904 reg = <0x0 0x200>;
3905 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
3906 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3907 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3908 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3909 #mbox-cells = <1>;
3910 ti,mbox-num-users = <4>;
3911 ti,mbox-num-fifos = <12>;
3912 status = "disabled";
3913 };
3914 };
3915
3916 target-module@60000 { /* 0x48860000, ap 71 4a.0 */
3917 compatible = "ti,sysc-omap4", "ti,sysc";
3918 reg = <0x60000 0x4>,
3919 <0x60010 0x4>;
3920 reg-names = "rev", "sysc";
3921 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3922 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3923 <SYSC_IDLE_NO>,
3924 <SYSC_IDLE_SMART>;
3925 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3926 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3927 clock-names = "fck";
3928 #address-cells = <1>;
3929 #size-cells = <1>;
3930 ranges = <0x0 0x60000 0x1000>;
3931
3932 mailbox10: mailbox@0 {
3933 compatible = "ti,omap4-mailbox";
3934 reg = <0x0 0x200>;
3935 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3936 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
3937 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
3938 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3939 #mbox-cells = <1>;
3940 ti,mbox-num-users = <4>;
3941 ti,mbox-num-fifos = <12>;
3942 status = "disabled";
3943 };
3944 };
3945
3946 target-module@62000 { /* 0x48862000, ap 73 74.0 */
3947 compatible = "ti,sysc-omap4", "ti,sysc";
3948 reg = <0x62000 0x4>,
3949 <0x62010 0x4>;
3950 reg-names = "rev", "sysc";
3951 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3952 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3953 <SYSC_IDLE_NO>,
3954 <SYSC_IDLE_SMART>;
3955 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3956 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3957 clock-names = "fck";
3958 #address-cells = <1>;
3959 #size-cells = <1>;
3960 ranges = <0x0 0x62000 0x1000>;
3961
3962 mailbox11: mailbox@0 {
3963 compatible = "ti,omap4-mailbox";
3964 reg = <0x0 0x200>;
3965 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
3966 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
3967 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
3968 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
3969 #mbox-cells = <1>;
3970 ti,mbox-num-users = <4>;
3971 ti,mbox-num-fifos = <12>;
3972 status = "disabled";
3973 };
3974 };
3975
3976 target-module@64000 { /* 0x48864000, ap 67 52.0 */
3977 compatible = "ti,sysc-omap4", "ti,sysc";
3978 reg = <0x64000 0x4>,
3979 <0x64010 0x4>;
3980 reg-names = "rev", "sysc";
3981 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3982 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3983 <SYSC_IDLE_NO>,
3984 <SYSC_IDLE_SMART>;
3985 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3986 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3987 clock-names = "fck";
3988 #address-cells = <1>;
3989 #size-cells = <1>;
3990 ranges = <0x0 0x64000 0x1000>;
3991
3992 mailbox12: mailbox@0 {
3993 compatible = "ti,omap4-mailbox";
3994 reg = <0x0 0x200>;
3995 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
3996 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
3997 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
3998 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
3999 #mbox-cells = <1>;
4000 ti,mbox-num-users = <4>;
4001 ti,mbox-num-fifos = <12>;
4002 status = "disabled";
4003 };
4004 };
4005
4006 target-module@80000 { /* 0x48880000, ap 83 0e.1 */
4007 compatible = "ti,sysc-omap4", "ti,sysc";
4008 reg = <0x80000 0x4>,
4009 <0x80010 0x4>;
4010 reg-names = "rev", "sysc";
4011 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4012 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4013 <SYSC_IDLE_NO>,
4014 <SYSC_IDLE_SMART>,
4015 <SYSC_IDLE_SMART_WKUP>;
4016 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4017 <SYSC_IDLE_NO>,
4018 <SYSC_IDLE_SMART>,
4019 <SYSC_IDLE_SMART_WKUP>;
4020 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4021 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
4022 clock-names = "fck";
4023 #address-cells = <1>;
4024 #size-cells = <1>;
4025 ranges = <0x0 0x80000 0x20000>;
4026
4027 omap_dwc3_1: omap_dwc3_1@0 {
4028 compatible = "ti,dwc3";
4029 reg = <0x0 0x10000>;
4030 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4031 #address-cells = <1>;
4032 #size-cells = <1>;
4033 utmi-mode = <2>;
4034 ranges = <0 0 0x20000>;
4035
4036 usb1: usb@10000 {
4037 compatible = "snps,dwc3";
4038 reg = <0x10000 0x17000>;
4039 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4040 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4041 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4042 interrupt-names = "peripheral",
4043 "host",
4044 "otg";
4045 phys = <&usb2_phy1>, <&usb3_phy1>;
4046 phy-names = "usb2-phy", "usb3-phy";
4047 maximum-speed = "super-speed";
4048 dr_mode = "otg";
4049 snps,dis_u3_susphy_quirk;
4050 snps,dis_u2_susphy_quirk;
4051 };
4052 };
4053 };
4054
4055 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
4056 compatible = "ti,sysc-omap4", "ti,sysc";
4057 reg = <0xc0000 0x4>,
4058 <0xc0010 0x4>;
4059 reg-names = "rev", "sysc";
4060 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4061 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4062 <SYSC_IDLE_NO>,
4063 <SYSC_IDLE_SMART>,
4064 <SYSC_IDLE_SMART_WKUP>;
4065 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4066 <SYSC_IDLE_NO>,
4067 <SYSC_IDLE_SMART>,
4068 <SYSC_IDLE_SMART_WKUP>;
4069 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4070 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4071 clock-names = "fck";
4072 #address-cells = <1>;
4073 #size-cells = <1>;
4074 ranges = <0x0 0xc0000 0x20000>;
4075
4076 omap_dwc3_2: omap_dwc3_2@0 {
4077 compatible = "ti,dwc3";
4078 reg = <0x0 0x10000>;
4079 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4080 #address-cells = <1>;
4081 #size-cells = <1>;
4082 utmi-mode = <2>;
4083 ranges = <0 0 0x20000>;
4084
4085 usb2: usb@10000 {
4086 compatible = "snps,dwc3";
4087 reg = <0x10000 0x17000>;
4088 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4089 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4090 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4091 interrupt-names = "peripheral",
4092 "host",
4093 "otg";
4094 phys = <&usb2_phy2>;
4095 phy-names = "usb2-phy";
4096 maximum-speed = "high-speed";
4097 dr_mode = "otg";
4098 snps,dis_u3_susphy_quirk;
4099 snps,dis_u2_susphy_quirk;
4100 snps,dis_metastability_quirk;
4101 };
4102 };
4103 };
4104
4105 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
4106 compatible = "ti,sysc-omap4", "ti,sysc";
4107 reg = <0x100000 0x4>,
4108 <0x100010 0x4>;
4109 reg-names = "rev", "sysc";
4110 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4111 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4112 <SYSC_IDLE_NO>,
4113 <SYSC_IDLE_SMART>,
4114 <SYSC_IDLE_SMART_WKUP>;
4115 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4116 <SYSC_IDLE_NO>,
4117 <SYSC_IDLE_SMART>,
4118 <SYSC_IDLE_SMART_WKUP>;
4119 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4120 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4121 clock-names = "fck";
4122 #address-cells = <1>;
4123 #size-cells = <1>;
4124 ranges = <0x0 0x100000 0x20000>;
4125
4126 omap_dwc3_3: omap_dwc3_3@0 {
4127 compatible = "ti,dwc3";
4128 reg = <0x0 0x10000>;
4129 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4130 #address-cells = <1>;
4131 #size-cells = <1>;
4132 utmi-mode = <2>;
4133 ranges = <0 0 0x20000>;
4134 status = "disabled";
4135
4136 usb3: usb@10000 {
4137 compatible = "snps,dwc3";
4138 reg = <0x10000 0x17000>;
4139 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4140 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4141 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4142 interrupt-names = "peripheral",
4143 "host",
4144 "otg";
4145 maximum-speed = "high-speed";
4146 dr_mode = "otg";
4147 snps,dis_u3_susphy_quirk;
4148 snps,dis_u2_susphy_quirk;
4149 };
4150 };
4151 };
4152
4153 usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
4154 compatible = "ti,sysc-omap4", "ti,sysc";
4155 reg = <0x140000 0x4>,
4156 <0x140010 0x4>;
4157 reg-names = "rev", "sysc";
4158 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4159 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4160 <SYSC_IDLE_NO>,
4161 <SYSC_IDLE_SMART>,
4162 <SYSC_IDLE_SMART_WKUP>;
4163 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4164 <SYSC_IDLE_NO>,
4165 <SYSC_IDLE_SMART>,
4166 <SYSC_IDLE_SMART_WKUP>;
4167 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4168 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
4169 clock-names = "fck";
4170 #address-cells = <1>;
4171 #size-cells = <1>;
4172 ranges = <0x0 0x140000 0x20000>;
4173 };
4174
4175 target-module@170000 { /* 0x48970000, ap 21 0a.0 */
4176 compatible = "ti,sysc-omap4", "ti,sysc";
4177 reg = <0x170010 0x4>;
4178 reg-names = "sysc";
4179 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4180 <SYSC_IDLE_NO>,
4181 <SYSC_IDLE_SMART>;
4182 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4183 <SYSC_IDLE_NO>,
4184 <SYSC_IDLE_SMART>;
4185 clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
4186 clock-names = "fck";
4187 #address-cells = <1>;
4188 #size-cells = <1>;
4189 ranges = <0x0 0x170000 0x10000>;
4190 status = "disabled";
4191 };
4192
4193 target-module@190000 { /* 0x48990000, ap 23 2e.0 */
4194 compatible = "ti,sysc-omap4", "ti,sysc";
4195 reg = <0x190010 0x4>;
4196 reg-names = "sysc";
4197 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4198 <SYSC_IDLE_NO>,
4199 <SYSC_IDLE_SMART>;
4200 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4201 <SYSC_IDLE_NO>,
4202 <SYSC_IDLE_SMART>;
4203 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
4204 clock-names = "fck";
4205 #address-cells = <1>;
4206 #size-cells = <1>;
4207 ranges = <0x0 0x190000 0x10000>;
4208 status = "disabled";
4209 };
4210
4211 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
4212 compatible = "ti,sysc-omap4", "ti,sysc";
4213 reg = <0x1b0000 0x4>,
4214 <0x1b0010 0x4>;
4215 reg-names = "rev", "sysc";
4216 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4217 <SYSC_IDLE_NO>,
4218 <SYSC_IDLE_SMART>;
4219 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4220 <SYSC_IDLE_NO>,
4221 <SYSC_IDLE_SMART>;
4222 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
4223 clock-names = "fck";
4224 #address-cells = <1>;
4225 #size-cells = <1>;
4226 ranges = <0x0 0x1b0000 0x10000>;
4227 status = "disabled";
4228 };
4229
4230 target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
4231 compatible = "ti,sysc-omap4", "ti,sysc";
4232 reg = <0x1d0010 0x4>;
4233 reg-names = "sysc";
4234 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4235 <SYSC_IDLE_NO>,
4236 <SYSC_IDLE_SMART>;
4237 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4238 <SYSC_IDLE_NO>,
4239 <SYSC_IDLE_SMART>;
4240 clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
4241 clock-names = "fck";
4242 #address-cells = <1>;
4243 #size-cells = <1>;
4244 ranges = <0x0 0x1d0000 0x10000>;
4245
4246 vpe: vpe@0 {
4247 compatible = "ti,dra7-vpe";
4248 reg = <0x0000 0x120>,
4249 <0x0700 0x80>,
4250 <0x5700 0x18>,
4251 <0xd000 0x400>;
4252 reg-names = "vpe_top",
4253 "sc",
4254 "csc",
4255 "vpdma";
4256 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
4257 };
4258 };
4259 };
4260};
4261
4262&l4_wkup { /* 0x4ae00000 */
4263 compatible = "ti,dra7-l4-wkup", "simple-bus";
4264 reg = <0x4ae00000 0x800>,
4265 <0x4ae00800 0x800>,
4266 <0x4ae01000 0x1000>;
4267 reg-names = "ap", "la", "ia0";
4268 #address-cells = <1>;
4269 #size-cells = <1>;
4270 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
4271 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
4272 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */
4273 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */
4274
4275 segment@0 { /* 0x4ae00000 */
4276 compatible = "simple-bus";
4277 #address-cells = <1>;
4278 #size-cells = <1>;
4279 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
4280 <0x00001000 0x00001000 0x001000>, /* ap 1 */
4281 <0x00000800 0x00000800 0x000800>, /* ap 2 */
4282 <0x00006000 0x00006000 0x002000>, /* ap 3 */
4283 <0x00008000 0x00008000 0x001000>, /* ap 4 */
4284 <0x00004000 0x00004000 0x001000>, /* ap 15 */
4285 <0x00005000 0x00005000 0x001000>, /* ap 16 */
4286 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */
4287 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */
4288
4289 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
4290 compatible = "ti,sysc-omap2", "ti,sysc";
4291 reg = <0x4000 0x4>,
4292 <0x4010 0x4>;
4293 reg-names = "rev", "sysc";
4294 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4295 <SYSC_IDLE_NO>,
4296 <SYSC_IDLE_SMART>,
4297 <SYSC_IDLE_SMART_WKUP>;
4298 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4299 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4300 clock-names = "fck";
4301 #address-cells = <1>;
4302 #size-cells = <1>;
4303 ranges = <0x0 0x4000 0x1000>;
4304
4305 counter32k: counter@0 {
4306 compatible = "ti,omap-counter32k";
4307 reg = <0x0 0x40>;
4308 };
4309 };
4310
4311 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */
4312 compatible = "ti,sysc-omap4", "ti,sysc";
4313 reg = <0x6000 0x4>;
4314 reg-names = "rev";
4315 #address-cells = <1>;
4316 #size-cells = <1>;
4317 ranges = <0x0 0x6000 0x2000>;
4318
4319 prm: prm@0 {
4320 compatible = "ti,dra7-prm", "simple-bus";
4321 reg = <0 0x3000>;
4322 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4323 #address-cells = <1>;
4324 #size-cells = <1>;
4325 ranges = <0 0 0x3000>;
4326
4327 prm_clocks: clocks {
4328 #address-cells = <1>;
4329 #size-cells = <0>;
4330 };
4331
4332 prm_clockdomains: clockdomains {
4333 };
4334 };
4335 };
4336
4337 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */
4338 compatible = "ti,sysc-omap4", "ti,sysc";
4339 reg = <0xc000 0x4>;
4340 reg-names = "rev";
4341 #address-cells = <1>;
4342 #size-cells = <1>;
4343 ranges = <0x0 0xc000 0x1000>;
4344
4345 scm_wkup: scm_conf@0 {
4346 compatible = "syscon";
4347 reg = <0 0x1000>;
4348 };
4349 };
4350 };
4351
4352 segment@10000 { /* 0x4ae10000 */
4353 compatible = "simple-bus";
4354 #address-cells = <1>;
4355 #size-cells = <1>;
4356 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
4357 <0x00001000 0x00011000 0x001000>, /* ap 6 */
4358 <0x00004000 0x00014000 0x001000>, /* ap 7 */
4359 <0x00005000 0x00015000 0x001000>, /* ap 8 */
4360 <0x00008000 0x00018000 0x001000>, /* ap 9 */
4361 <0x00009000 0x00019000 0x001000>, /* ap 10 */
4362 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
4363 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
4364
4365 target-module@0 { /* 0x4ae10000, ap 5 20.0 */
4366 compatible = "ti,sysc-omap2", "ti,sysc";
4367 reg = <0x0 0x4>,
4368 <0x10 0x4>,
4369 <0x114 0x4>;
4370 reg-names = "rev", "sysc", "syss";
4371 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4372 SYSC_OMAP2_SOFTRESET |
4373 SYSC_OMAP2_AUTOIDLE)>;
4374 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4375 <SYSC_IDLE_NO>,
4376 <SYSC_IDLE_SMART>,
4377 <SYSC_IDLE_SMART_WKUP>;
4378 ti,syss-mask = <1>;
4379 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4380 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4381 <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
4382 clock-names = "fck", "dbclk";
4383 #address-cells = <1>;
4384 #size-cells = <1>;
4385 ranges = <0x0 0x0 0x1000>;
4386
4387 gpio1: gpio@0 {
4388 compatible = "ti,omap4-gpio";
4389 reg = <0x0 0x200>;
4390 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4391 gpio-controller;
4392 #gpio-cells = <2>;
4393 interrupt-controller;
4394 #interrupt-cells = <2>;
4395 };
4396 };
4397
4398 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
4399 compatible = "ti,sysc-omap2", "ti,sysc";
4400 reg = <0x4000 0x4>,
4401 <0x4010 0x4>,
4402 <0x4014 0x4>;
4403 reg-names = "rev", "sysc", "syss";
4404 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
4405 SYSC_OMAP2_SOFTRESET)>;
4406 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4407 <SYSC_IDLE_NO>,
4408 <SYSC_IDLE_SMART>,
4409 <SYSC_IDLE_SMART_WKUP>;
4410 ti,syss-mask = <1>;
4411 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4412 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4413 clock-names = "fck";
4414 #address-cells = <1>;
4415 #size-cells = <1>;
4416 ranges = <0x0 0x4000 0x1000>;
4417
4418 wdt2: wdt@0 {
4419 compatible = "ti,omap3-wdt";
4420 reg = <0x0 0x80>;
4421 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4422 };
4423 };
4424
4425 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
4426 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4427 reg = <0x8000 0x4>,
4428 <0x8010 0x4>;
4429 reg-names = "rev", "sysc";
4430 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4431 SYSC_OMAP4_SOFTRESET)>;
4432 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4433 <SYSC_IDLE_NO>,
4434 <SYSC_IDLE_SMART>,
4435 <SYSC_IDLE_SMART_WKUP>;
4436 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4437 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4438 clock-names = "fck";
4439 #address-cells = <1>;
4440 #size-cells = <1>;
4441 ranges = <0x0 0x8000 0x1000>;
4442
4443 timer1: timer@0 {
4444 compatible = "ti,omap5430-timer";
4445 reg = <0x0 0x80>;
4446 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
4447 clock-names = "fck";
4448 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4449 ti,timer-alwon;
4450 };
4451 };
4452
4453 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */
4454 compatible = "ti,sysc";
4455 status = "disabled";
4456 #address-cells = <1>;
4457 #size-cells = <1>;
4458 ranges = <0x0 0xc000 0x1000>;
4459 };
4460 };
4461
4462 segment@20000 { /* 0x4ae20000 */
4463 compatible = "simple-bus";
4464 #address-cells = <1>;
4465 #size-cells = <1>;
4466 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
4467 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
4468 <0x00000000 0x00020000 0x001000>, /* ap 19 */
4469 <0x00001000 0x00021000 0x001000>, /* ap 20 */
4470 <0x00002000 0x00022000 0x001000>, /* ap 21 */
4471 <0x00003000 0x00023000 0x001000>, /* ap 22 */
4472 <0x00007000 0x00027000 0x000400>, /* ap 23 */
4473 <0x00008000 0x00028000 0x000800>, /* ap 24 */
4474 <0x00009000 0x00029000 0x000100>, /* ap 25 */
4475 <0x00008800 0x00028800 0x000200>, /* ap 26 */
4476 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */
4477 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */
4478 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */
4479 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */
4480
4481 target-module@0 { /* 0x4ae20000, ap 19 08.0 */
4482 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4483 reg = <0x0 0x4>,
4484 <0x10 0x4>;
4485 reg-names = "rev", "sysc";
4486 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4487 SYSC_OMAP4_SOFTRESET)>;
4488 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4489 <SYSC_IDLE_NO>,
4490 <SYSC_IDLE_SMART>,
4491 <SYSC_IDLE_SMART_WKUP>;
4492 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4493 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4494 clock-names = "fck";
4495 #address-cells = <1>;
4496 #size-cells = <1>;
4497 ranges = <0x0 0x0 0x1000>;
4498
4499 timer12: timer@0 {
4500 compatible = "ti,omap5430-timer";
4501 reg = <0x0 0x80>;
4502 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
4503 ti,timer-alwon;
4504 ti,timer-secure;
4505 };
4506 };
4507
4508 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */
4509 compatible = "ti,sysc";
4510 status = "disabled";
4511 #address-cells = <1>;
4512 #size-cells = <1>;
4513 ranges = <0x0 0x2000 0x1000>;
4514 };
4515
4516 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */
4517 compatible = "ti,sysc";
4518 status = "disabled";
4519 #address-cells = <1>;
4520 #size-cells = <1>;
4521 ranges = <0x00000000 0x00006000 0x00001000>,
4522 <0x00001000 0x00007000 0x00000400>,
4523 <0x00002000 0x00008000 0x00000800>,
4524 <0x00002800 0x00008800 0x00000200>,
4525 <0x00002a00 0x00008a00 0x00000100>,
4526 <0x00003000 0x00009000 0x00000100>;
4527 };
4528
4529 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
4530 compatible = "ti,sysc-omap2", "ti,sysc";
4531 reg = <0xb050 0x4>,
4532 <0xb054 0x4>,
4533 <0xb058 0x4>;
4534 reg-names = "rev", "sysc", "syss";
4535 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4536 SYSC_OMAP2_SOFTRESET |
4537 SYSC_OMAP2_AUTOIDLE)>;
4538 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4539 <SYSC_IDLE_NO>,
4540 <SYSC_IDLE_SMART>,
4541 <SYSC_IDLE_SMART_WKUP>;
4542 ti,syss-mask = <1>;
4543 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4544 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4545 clock-names = "fck";
4546 #address-cells = <1>;
4547 #size-cells = <1>;
4548 ranges = <0x0 0xb000 0x1000>;
4549
4550 uart10: serial@0 {
4551 compatible = "ti,dra742-uart", "ti,omap4-uart";
4552 reg = <0x0 0x100>;
4553 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
4554 clock-frequency = <48000000>;
4555 status = "disabled";
4556 };
4557 };
4558
4559 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */
4560 compatible = "ti,sysc";
4561 status = "disabled";
4562 #address-cells = <1>;
4563 #size-cells = <1>;
4564 ranges = <0x0 0xf000 0x1000>;
4565 };
4566 };
4567
4568 segment@30000 { /* 0x4ae30000 */
4569 compatible = "simple-bus";
4570 #address-cells = <1>;
4571 #size-cells = <1>;
4572 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
4573 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */
4574 <0x00000000 0x00030000 0x001000>, /* ap 33 */
4575 <0x00001000 0x00031000 0x001000>, /* ap 34 */
4576 <0x00002000 0x00032000 0x001000>, /* ap 35 */
4577 <0x00003000 0x00033000 0x001000>, /* ap 36 */
4578 <0x00004000 0x00034000 0x001000>, /* ap 37 */
4579 <0x00005000 0x00035000 0x001000>, /* ap 38 */
4580 <0x00006000 0x00036000 0x001000>, /* ap 39 */
4581 <0x00007000 0x00037000 0x001000>, /* ap 40 */
4582 <0x00008000 0x00038000 0x001000>, /* ap 41 */
4583 <0x00009000 0x00039000 0x001000>, /* ap 42 */
4584 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */
4585
4586 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */
4587 compatible = "ti,sysc";
4588 status = "disabled";
4589 #address-cells = <1>;
4590 #size-cells = <1>;
4591 ranges = <0x0 0x1000 0x1000>;
4592 };
4593
4594 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */
4595 compatible = "ti,sysc";
4596 status = "disabled";
4597 #address-cells = <1>;
4598 #size-cells = <1>;
4599 ranges = <0x0 0x3000 0x1000>;
4600 };
4601
4602 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */
4603 compatible = "ti,sysc";
4604 status = "disabled";
4605 #address-cells = <1>;
4606 #size-cells = <1>;
4607 ranges = <0x0 0x5000 0x1000>;
4608 };
4609
4610 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */
4611 compatible = "ti,sysc";
4612 status = "disabled";
4613 #address-cells = <1>;
4614 #size-cells = <1>;
4615 ranges = <0x0 0x7000 0x1000>;
4616 };
4617
4618 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */
4619 compatible = "ti,sysc";
4620 status = "disabled";
4621 #address-cells = <1>;
4622 #size-cells = <1>;
4623 ranges = <0x0 0x9000 0x1000>;
4624 };
4625
4626 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
4627 compatible = "ti,sysc-omap4", "ti,sysc";
4628 reg = <0xc020 0x4>;
4629 reg-names = "rev";
4630 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4631 clock-names = "fck";
4632 #address-cells = <1>;
4633 #size-cells = <1>;
4634 ranges = <0x0 0xc000 0x2000>;
4635
4636 dcan1: can@0 {
4637 compatible = "ti,dra7-d_can";
4638 reg = <0x0 0x2000>;
4639 syscon-raminit = <&scm_conf 0x558 0>;
4640 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
4641 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
4642 status = "disabled";
4643 };
4644 };
4645 };
4646};
4647