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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * STM32 ALSA SoC Digital Audio Interface (I2S) driver.
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/delay.h>
13#include <linux/module.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h>
16#include <linux/regmap.h>
17#include <linux/reset.h>
18#include <linux/spinlock.h>
19
20#include <sound/dmaengine_pcm.h>
21#include <sound/pcm_params.h>
22
23#define STM32_I2S_CR1_REG 0x0
24#define STM32_I2S_CFG1_REG 0x08
25#define STM32_I2S_CFG2_REG 0x0C
26#define STM32_I2S_IER_REG 0x10
27#define STM32_I2S_SR_REG 0x14
28#define STM32_I2S_IFCR_REG 0x18
29#define STM32_I2S_TXDR_REG 0X20
30#define STM32_I2S_RXDR_REG 0x30
31#define STM32_I2S_CGFR_REG 0X50
32#define STM32_I2S_HWCFGR_REG 0x3F0
33#define STM32_I2S_VERR_REG 0x3F4
34#define STM32_I2S_IPIDR_REG 0x3F8
35#define STM32_I2S_SIDR_REG 0x3FC
36
37/* Bit definition for SPI2S_CR1 register */
38#define I2S_CR1_SPE BIT(0)
39#define I2S_CR1_CSTART BIT(9)
40#define I2S_CR1_CSUSP BIT(10)
41#define I2S_CR1_HDDIR BIT(11)
42#define I2S_CR1_SSI BIT(12)
43#define I2S_CR1_CRC33_17 BIT(13)
44#define I2S_CR1_RCRCI BIT(14)
45#define I2S_CR1_TCRCI BIT(15)
46
47/* Bit definition for SPI_CFG2 register */
48#define I2S_CFG2_IOSWP_SHIFT 15
49#define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
50#define I2S_CFG2_LSBFRST BIT(23)
51#define I2S_CFG2_AFCNTR BIT(31)
52
53/* Bit definition for SPI_CFG1 register */
54#define I2S_CFG1_FTHVL_SHIFT 5
55#define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
56#define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
57
58#define I2S_CFG1_TXDMAEN BIT(15)
59#define I2S_CFG1_RXDMAEN BIT(14)
60
61/* Bit definition for SPI2S_IER register */
62#define I2S_IER_RXPIE BIT(0)
63#define I2S_IER_TXPIE BIT(1)
64#define I2S_IER_DPXPIE BIT(2)
65#define I2S_IER_EOTIE BIT(3)
66#define I2S_IER_TXTFIE BIT(4)
67#define I2S_IER_UDRIE BIT(5)
68#define I2S_IER_OVRIE BIT(6)
69#define I2S_IER_CRCEIE BIT(7)
70#define I2S_IER_TIFREIE BIT(8)
71#define I2S_IER_MODFIE BIT(9)
72#define I2S_IER_TSERFIE BIT(10)
73
74/* Bit definition for SPI2S_SR register */
75#define I2S_SR_RXP BIT(0)
76#define I2S_SR_TXP BIT(1)
77#define I2S_SR_DPXP BIT(2)
78#define I2S_SR_EOT BIT(3)
79#define I2S_SR_TXTF BIT(4)
80#define I2S_SR_UDR BIT(5)
81#define I2S_SR_OVR BIT(6)
82#define I2S_SR_CRCERR BIT(7)
83#define I2S_SR_TIFRE BIT(8)
84#define I2S_SR_MODF BIT(9)
85#define I2S_SR_TSERF BIT(10)
86#define I2S_SR_SUSP BIT(11)
87#define I2S_SR_TXC BIT(12)
88#define I2S_SR_RXPLVL GENMASK(14, 13)
89#define I2S_SR_RXWNE BIT(15)
90
91#define I2S_SR_MASK GENMASK(15, 0)
92
93/* Bit definition for SPI_IFCR register */
94#define I2S_IFCR_EOTC BIT(3)
95#define I2S_IFCR_TXTFC BIT(4)
96#define I2S_IFCR_UDRC BIT(5)
97#define I2S_IFCR_OVRC BIT(6)
98#define I2S_IFCR_CRCEC BIT(7)
99#define I2S_IFCR_TIFREC BIT(8)
100#define I2S_IFCR_MODFC BIT(9)
101#define I2S_IFCR_TSERFC BIT(10)
102#define I2S_IFCR_SUSPC BIT(11)
103
104#define I2S_IFCR_MASK GENMASK(11, 3)
105
106/* Bit definition for SPI_I2SCGFR register */
107#define I2S_CGFR_I2SMOD BIT(0)
108
109#define I2S_CGFR_I2SCFG_SHIFT 1
110#define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
111#define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
112
113#define I2S_CGFR_I2SSTD_SHIFT 4
114#define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
115#define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
116
117#define I2S_CGFR_PCMSYNC BIT(7)
118
119#define I2S_CGFR_DATLEN_SHIFT 8
120#define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
121#define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
122
123#define I2S_CGFR_CHLEN_SHIFT 10
124#define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
125#define I2S_CGFR_CKPOL BIT(11)
126#define I2S_CGFR_FIXCH BIT(12)
127#define I2S_CGFR_WSINV BIT(13)
128#define I2S_CGFR_DATFMT BIT(14)
129
130#define I2S_CGFR_I2SDIV_SHIFT 16
131#define I2S_CGFR_I2SDIV_BIT_H 23
132#define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
133 I2S_CGFR_I2SDIV_SHIFT)
134#define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
135#define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
136 I2S_CGFR_I2SDIV_SHIFT)) - 1)
137
138#define I2S_CGFR_ODD_SHIFT 24
139#define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
140#define I2S_CGFR_MCKOE BIT(25)
141
142/* Registers below apply to I2S version 1.1 and more */
143
144/* Bit definition for SPI_HWCFGR register */
145#define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
146
147/* Bit definition for SPI_VERR register */
148#define I2S_VERR_MIN_MASK GENMASK(3, 0)
149#define I2S_VERR_MAJ_MASK GENMASK(7, 4)
150
151/* Bit definition for SPI_IPIDR register */
152#define I2S_IPIDR_ID_MASK GENMASK(31, 0)
153
154/* Bit definition for SPI_SIDR register */
155#define I2S_SIDR_ID_MASK GENMASK(31, 0)
156
157#define I2S_IPIDR_NUMBER 0x00130022
158
159enum i2s_master_mode {
160 I2S_MS_NOT_SET,
161 I2S_MS_MASTER,
162 I2S_MS_SLAVE,
163};
164
165enum i2s_mode {
166 I2S_I2SMOD_TX_SLAVE,
167 I2S_I2SMOD_RX_SLAVE,
168 I2S_I2SMOD_TX_MASTER,
169 I2S_I2SMOD_RX_MASTER,
170 I2S_I2SMOD_FD_SLAVE,
171 I2S_I2SMOD_FD_MASTER,
172};
173
174enum i2s_fifo_th {
175 I2S_FIFO_TH_NONE,
176 I2S_FIFO_TH_ONE_QUARTER,
177 I2S_FIFO_TH_HALF,
178 I2S_FIFO_TH_THREE_QUARTER,
179 I2S_FIFO_TH_FULL,
180};
181
182enum i2s_std {
183 I2S_STD_I2S,
184 I2S_STD_LEFT_J,
185 I2S_STD_RIGHT_J,
186 I2S_STD_DSP,
187};
188
189enum i2s_datlen {
190 I2S_I2SMOD_DATLEN_16,
191 I2S_I2SMOD_DATLEN_24,
192 I2S_I2SMOD_DATLEN_32,
193};
194
195#define STM32_I2S_FIFO_SIZE 16
196
197#define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
198#define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
199
200#define STM32_I2S_NAME_LEN 32
201#define STM32_I2S_RATE_11K 11025
202
203/**
204 * struct stm32_i2s_data - private data of I2S
205 * @regmap_conf: I2S register map configuration pointer
206 * @regmap: I2S register map pointer
207 * @pdev: device data pointer
208 * @dai_drv: DAI driver pointer
209 * @dma_data_tx: dma configuration data for tx channel
210 * @dma_data_rx: dma configuration data for tx channel
211 * @substream: PCM substream data pointer
212 * @i2sclk: kernel clock feeding the I2S clock generator
213 * @i2smclk: master clock from I2S mclk provider
214 * @pclk: peripheral clock driving bus interface
215 * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
216 * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
217 * @base: mmio register base virtual address
218 * @phys_addr: I2S registers physical base address
219 * @lock_fd: lock to manage race conditions in full duplex mode
220 * @irq_lock: prevent race condition with IRQ
221 * @mclk_rate: master clock frequency (Hz)
222 * @fmt: DAI protocol
223 * @divider: prescaler division ratio
224 * @div: prescaler div field
225 * @odd: prescaler odd field
226 * @refcount: keep count of opened streams on I2S
227 * @ms_flg: master mode flag.
228 */
229struct stm32_i2s_data {
230 const struct regmap_config *regmap_conf;
231 struct regmap *regmap;
232 struct platform_device *pdev;
233 struct snd_soc_dai_driver *dai_drv;
234 struct snd_dmaengine_dai_dma_data dma_data_tx;
235 struct snd_dmaengine_dai_dma_data dma_data_rx;
236 struct snd_pcm_substream *substream;
237 struct clk *i2sclk;
238 struct clk *i2smclk;
239 struct clk *pclk;
240 struct clk *x8kclk;
241 struct clk *x11kclk;
242 void __iomem *base;
243 dma_addr_t phys_addr;
244 spinlock_t lock_fd; /* Manage race conditions for full duplex */
245 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
246 unsigned int mclk_rate;
247 unsigned int fmt;
248 unsigned int divider;
249 unsigned int div;
250 bool odd;
251 int refcount;
252 int ms_flg;
253};
254
255struct stm32_i2smclk_data {
256 struct clk_hw hw;
257 unsigned long freq;
258 struct stm32_i2s_data *i2s_data;
259};
260
261#define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
262
263static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
264 unsigned long input_rate,
265 unsigned long output_rate)
266{
267 unsigned int ratio, div, divider = 1;
268 bool odd;
269
270 ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
271
272 /* Check the parity of the divider */
273 odd = ratio & 0x1;
274
275 /* Compute the div prescaler */
276 div = ratio >> 1;
277
278 /* If div is 0 actual divider is 1 */
279 if (div) {
280 divider = ((2 * div) + odd);
281 dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
282 div, odd, divider);
283 }
284
285 /* Division by three is not allowed by I2S prescaler */
286 if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
287 dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
288 return -EINVAL;
289 }
290
291 if (input_rate % divider)
292 dev_dbg(&i2s->pdev->dev,
293 "Rate not accurate. requested (%ld), actual (%ld)\n",
294 output_rate, input_rate / divider);
295
296 i2s->div = div;
297 i2s->odd = odd;
298 i2s->divider = divider;
299
300 return 0;
301}
302
303static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
304{
305 u32 cgfr, cgfr_mask;
306
307 cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
308 cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
309
310 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
311 cgfr_mask, cgfr);
312}
313
314static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
315 unsigned int rate)
316{
317 struct platform_device *pdev = i2s->pdev;
318 struct clk *parent_clk;
319 int ret;
320
321 if (!(rate % STM32_I2S_RATE_11K))
322 parent_clk = i2s->x11kclk;
323 else
324 parent_clk = i2s->x8kclk;
325
326 ret = clk_set_parent(i2s->i2sclk, parent_clk);
327 if (ret)
328 dev_err(&pdev->dev,
329 "Error %d setting i2sclk parent clock\n", ret);
330
331 return ret;
332}
333
334static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
335 unsigned long *prate)
336{
337 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
338 struct stm32_i2s_data *i2s = mclk->i2s_data;
339 int ret;
340
341 ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
342 if (ret)
343 return ret;
344
345 mclk->freq = *prate / i2s->divider;
346
347 return mclk->freq;
348}
349
350static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
351 unsigned long parent_rate)
352{
353 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
354
355 return mclk->freq;
356}
357
358static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
359 unsigned long parent_rate)
360{
361 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
362 struct stm32_i2s_data *i2s = mclk->i2s_data;
363 int ret;
364
365 ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
366 if (ret)
367 return ret;
368
369 ret = stm32_i2s_set_clk_div(i2s);
370 if (ret)
371 return ret;
372
373 mclk->freq = rate;
374
375 return 0;
376}
377
378static int stm32_i2smclk_enable(struct clk_hw *hw)
379{
380 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
381 struct stm32_i2s_data *i2s = mclk->i2s_data;
382
383 dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
384
385 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
386 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
387}
388
389static void stm32_i2smclk_disable(struct clk_hw *hw)
390{
391 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
392 struct stm32_i2s_data *i2s = mclk->i2s_data;
393
394 dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
395
396 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
397}
398
399static const struct clk_ops mclk_ops = {
400 .enable = stm32_i2smclk_enable,
401 .disable = stm32_i2smclk_disable,
402 .recalc_rate = stm32_i2smclk_recalc_rate,
403 .round_rate = stm32_i2smclk_round_rate,
404 .set_rate = stm32_i2smclk_set_rate,
405};
406
407static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
408{
409 struct clk_hw *hw;
410 struct stm32_i2smclk_data *mclk;
411 struct device *dev = &i2s->pdev->dev;
412 const char *pname = __clk_get_name(i2s->i2sclk);
413 char *mclk_name, *p, *s = (char *)pname;
414 int ret, i = 0;
415
416 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
417 if (!mclk)
418 return -ENOMEM;
419
420 mclk_name = devm_kcalloc(dev, sizeof(char),
421 STM32_I2S_NAME_LEN, GFP_KERNEL);
422 if (!mclk_name)
423 return -ENOMEM;
424
425 /*
426 * Forge mclk clock name from parent clock name and suffix.
427 * String after "_" char is stripped in parent name.
428 */
429 p = mclk_name;
430 while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
431 *p++ = *s++;
432 i++;
433 }
434 strcat(p, "_mclk");
435
436 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
437 mclk->i2s_data = i2s;
438 hw = &mclk->hw;
439
440 dev_dbg(dev, "Register master clock %s\n", mclk_name);
441 ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
442 if (ret) {
443 dev_err(dev, "mclk register fails with error %d\n", ret);
444 return ret;
445 }
446 i2s->i2smclk = hw->clk;
447
448 /* register mclk provider */
449 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
450}
451
452static irqreturn_t stm32_i2s_isr(int irq, void *devid)
453{
454 struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
455 struct platform_device *pdev = i2s->pdev;
456 u32 sr, ier;
457 unsigned long flags;
458 int err = 0;
459
460 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
461 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
462
463 flags = sr & ier;
464 if (!flags) {
465 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
466 sr, ier);
467 return IRQ_NONE;
468 }
469
470 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
471 I2S_IFCR_MASK, flags);
472
473 if (flags & I2S_SR_OVR) {
474 dev_dbg(&pdev->dev, "Overrun\n");
475 err = 1;
476 }
477
478 if (flags & I2S_SR_UDR) {
479 dev_dbg(&pdev->dev, "Underrun\n");
480 err = 1;
481 }
482
483 if (flags & I2S_SR_TIFRE)
484 dev_dbg(&pdev->dev, "Frame error\n");
485
486 spin_lock(&i2s->irq_lock);
487 if (err && i2s->substream)
488 snd_pcm_stop_xrun(i2s->substream);
489 spin_unlock(&i2s->irq_lock);
490
491 return IRQ_HANDLED;
492}
493
494static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
495{
496 switch (reg) {
497 case STM32_I2S_CR1_REG:
498 case STM32_I2S_CFG1_REG:
499 case STM32_I2S_CFG2_REG:
500 case STM32_I2S_IER_REG:
501 case STM32_I2S_SR_REG:
502 case STM32_I2S_RXDR_REG:
503 case STM32_I2S_CGFR_REG:
504 case STM32_I2S_HWCFGR_REG:
505 case STM32_I2S_VERR_REG:
506 case STM32_I2S_IPIDR_REG:
507 case STM32_I2S_SIDR_REG:
508 return true;
509 default:
510 return false;
511 }
512}
513
514static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
515{
516 switch (reg) {
517 case STM32_I2S_SR_REG:
518 case STM32_I2S_RXDR_REG:
519 return true;
520 default:
521 return false;
522 }
523}
524
525static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
526{
527 switch (reg) {
528 case STM32_I2S_CR1_REG:
529 case STM32_I2S_CFG1_REG:
530 case STM32_I2S_CFG2_REG:
531 case STM32_I2S_IER_REG:
532 case STM32_I2S_IFCR_REG:
533 case STM32_I2S_TXDR_REG:
534 case STM32_I2S_CGFR_REG:
535 return true;
536 default:
537 return false;
538 }
539}
540
541static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
542{
543 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
544 u32 cgfr;
545 u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
546 I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
547
548 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
549
550 /*
551 * winv = 0 : default behavior (high/low) for all standards
552 * ckpol = 0 for all standards.
553 */
554 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
555 case SND_SOC_DAIFMT_I2S:
556 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
557 break;
558 case SND_SOC_DAIFMT_MSB:
559 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
560 break;
561 case SND_SOC_DAIFMT_LSB:
562 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
563 break;
564 case SND_SOC_DAIFMT_DSP_A:
565 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
566 break;
567 /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
568 default:
569 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
570 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
571 return -EINVAL;
572 }
573
574 /* DAI clock strobing */
575 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
576 case SND_SOC_DAIFMT_NB_NF:
577 break;
578 case SND_SOC_DAIFMT_IB_NF:
579 cgfr |= I2S_CGFR_CKPOL;
580 break;
581 case SND_SOC_DAIFMT_NB_IF:
582 cgfr |= I2S_CGFR_WSINV;
583 break;
584 case SND_SOC_DAIFMT_IB_IF:
585 cgfr |= I2S_CGFR_CKPOL;
586 cgfr |= I2S_CGFR_WSINV;
587 break;
588 default:
589 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
590 fmt & SND_SOC_DAIFMT_INV_MASK);
591 return -EINVAL;
592 }
593
594 /* DAI clock master masks */
595 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
596 case SND_SOC_DAIFMT_CBM_CFM:
597 i2s->ms_flg = I2S_MS_SLAVE;
598 break;
599 case SND_SOC_DAIFMT_CBS_CFS:
600 i2s->ms_flg = I2S_MS_MASTER;
601 break;
602 default:
603 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
604 fmt & SND_SOC_DAIFMT_MASTER_MASK);
605 return -EINVAL;
606 }
607
608 i2s->fmt = fmt;
609 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
610 cgfr_mask, cgfr);
611}
612
613static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
614 int clk_id, unsigned int freq, int dir)
615{
616 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
617 int ret = 0;
618
619 dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
620 freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
621 dir ? "output" : "input");
622
623 /* MCLK generation is available only in master mode */
624 if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
625 if (!i2s->i2smclk) {
626 dev_dbg(cpu_dai->dev, "No MCLK registered\n");
627 return 0;
628 }
629
630 /* Assume shutdown if requested frequency is 0Hz */
631 if (!freq) {
632 /* Release mclk rate only if rate was actually set */
633 if (i2s->mclk_rate) {
634 clk_rate_exclusive_put(i2s->i2smclk);
635 i2s->mclk_rate = 0;
636 }
637 return regmap_update_bits(i2s->regmap,
638 STM32_I2S_CGFR_REG,
639 I2S_CGFR_MCKOE, 0);
640 }
641 /* If master clock is used, set parent clock now */
642 ret = stm32_i2s_set_parent_clock(i2s, freq);
643 if (ret)
644 return ret;
645 ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
646 if (ret) {
647 dev_err(cpu_dai->dev, "Could not set mclk rate\n");
648 return ret;
649 }
650 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
651 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
652 if (!ret)
653 i2s->mclk_rate = freq;
654 }
655
656 return ret;
657}
658
659static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
660 struct snd_pcm_hw_params *params)
661{
662 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
663 unsigned long i2s_clock_rate;
664 unsigned int nb_bits, frame_len;
665 unsigned int rate = params_rate(params);
666 u32 cgfr;
667 int ret;
668
669 if (!(rate % 11025))
670 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
671 else
672 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
673 i2s_clock_rate = clk_get_rate(i2s->i2sclk);
674
675 /*
676 * mckl = mclk_ratio x ws
677 * i2s mode : mclk_ratio = 256
678 * dsp mode : mclk_ratio = 128
679 *
680 * mclk on
681 * i2s mode : div = i2s_clk / (mclk_ratio * ws)
682 * dsp mode : div = i2s_clk / (mclk_ratio * ws)
683 * mclk off
684 * i2s mode : div = i2s_clk / (nb_bits x ws)
685 * dsp mode : div = i2s_clk / (nb_bits x ws)
686 */
687 if (i2s->mclk_rate) {
688 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
689 i2s->mclk_rate);
690 if (ret)
691 return ret;
692 } else {
693 frame_len = 32;
694 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
695 SND_SOC_DAIFMT_DSP_A)
696 frame_len = 16;
697
698 /* master clock not enabled */
699 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
700 if (ret < 0)
701 return ret;
702
703 nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
704 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
705 (nb_bits * rate));
706 if (ret)
707 return ret;
708 }
709
710 ret = stm32_i2s_set_clk_div(i2s);
711 if (ret < 0)
712 return ret;
713
714 /* Set bitclock and frameclock to their inactive state */
715 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
716 I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
717}
718
719static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
720 struct snd_pcm_hw_params *params,
721 struct snd_pcm_substream *substream)
722{
723 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
724 int format = params_width(params);
725 u32 cfgr, cfgr_mask, cfg1;
726 unsigned int fthlv;
727 int ret;
728
729 switch (format) {
730 case 16:
731 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
732 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
733 break;
734 case 32:
735 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
736 I2S_CGFR_CHLEN;
737 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
738 break;
739 default:
740 dev_err(cpu_dai->dev, "Unexpected format %d", format);
741 return -EINVAL;
742 }
743
744 if (STM32_I2S_IS_SLAVE(i2s)) {
745 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
746
747 /* As data length is either 16 or 32 bits, fixch always set */
748 cfgr |= I2S_CGFR_FIXCH;
749 cfgr_mask |= I2S_CGFR_FIXCH;
750 } else {
751 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
752 }
753 cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
754
755 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
756 cfgr_mask, cfgr);
757 if (ret < 0)
758 return ret;
759
760 fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
761 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
762
763 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
764 I2S_CFG1_FTHVL_MASK, cfg1);
765}
766
767static int stm32_i2s_startup(struct snd_pcm_substream *substream,
768 struct snd_soc_dai *cpu_dai)
769{
770 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
771 unsigned long flags;
772 int ret;
773
774 spin_lock_irqsave(&i2s->irq_lock, flags);
775 i2s->substream = substream;
776 spin_unlock_irqrestore(&i2s->irq_lock, flags);
777
778 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
779 snd_pcm_hw_constraint_single(substream->runtime,
780 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
781
782 ret = clk_prepare_enable(i2s->i2sclk);
783 if (ret < 0) {
784 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
785 return ret;
786 }
787
788 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
789 I2S_IFCR_MASK, I2S_IFCR_MASK);
790}
791
792static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
793 struct snd_pcm_hw_params *params,
794 struct snd_soc_dai *cpu_dai)
795{
796 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
797 int ret;
798
799 ret = stm32_i2s_configure(cpu_dai, params, substream);
800 if (ret < 0) {
801 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
802 return ret;
803 }
804
805 if (STM32_I2S_IS_MASTER(i2s))
806 ret = stm32_i2s_configure_clock(cpu_dai, params);
807
808 return ret;
809}
810
811static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
812 struct snd_soc_dai *cpu_dai)
813{
814 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
815 bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
816 u32 cfg1_mask, ier;
817 int ret;
818
819 switch (cmd) {
820 case SNDRV_PCM_TRIGGER_START:
821 case SNDRV_PCM_TRIGGER_RESUME:
822 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
823 /* Enable i2s */
824 dev_dbg(cpu_dai->dev, "start I2S %s\n",
825 playback_flg ? "playback" : "capture");
826
827 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
828 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
829 cfg1_mask, cfg1_mask);
830
831 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
832 I2S_CR1_SPE, I2S_CR1_SPE);
833 if (ret < 0) {
834 dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
835 return ret;
836 }
837
838 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
839 I2S_CR1_CSTART, I2S_CR1_CSTART);
840 if (ret < 0) {
841 dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
842 return ret;
843 }
844
845 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
846 I2S_IFCR_MASK, I2S_IFCR_MASK);
847
848 spin_lock(&i2s->lock_fd);
849 i2s->refcount++;
850 if (playback_flg) {
851 ier = I2S_IER_UDRIE;
852 } else {
853 ier = I2S_IER_OVRIE;
854
855 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
856 /* dummy write to gate bus clocks */
857 regmap_write(i2s->regmap,
858 STM32_I2S_TXDR_REG, 0);
859 }
860 spin_unlock(&i2s->lock_fd);
861
862 if (STM32_I2S_IS_SLAVE(i2s))
863 ier |= I2S_IER_TIFREIE;
864
865 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
866 break;
867 case SNDRV_PCM_TRIGGER_STOP:
868 case SNDRV_PCM_TRIGGER_SUSPEND:
869 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
870 dev_dbg(cpu_dai->dev, "stop I2S %s\n",
871 playback_flg ? "playback" : "capture");
872
873 if (playback_flg)
874 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
875 I2S_IER_UDRIE,
876 (unsigned int)~I2S_IER_UDRIE);
877 else
878 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
879 I2S_IER_OVRIE,
880 (unsigned int)~I2S_IER_OVRIE);
881
882 spin_lock(&i2s->lock_fd);
883 i2s->refcount--;
884 if (i2s->refcount) {
885 spin_unlock(&i2s->lock_fd);
886 break;
887 }
888
889 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
890 I2S_CR1_SPE, 0);
891 if (ret < 0) {
892 dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
893 spin_unlock(&i2s->lock_fd);
894 return ret;
895 }
896 spin_unlock(&i2s->lock_fd);
897
898 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
899 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
900 cfg1_mask, 0);
901 break;
902 default:
903 return -EINVAL;
904 }
905
906 return 0;
907}
908
909static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
910 struct snd_soc_dai *cpu_dai)
911{
912 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
913 unsigned long flags;
914
915 clk_disable_unprepare(i2s->i2sclk);
916
917 spin_lock_irqsave(&i2s->irq_lock, flags);
918 i2s->substream = NULL;
919 spin_unlock_irqrestore(&i2s->irq_lock, flags);
920}
921
922static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
923{
924 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
925 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
926 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
927
928 /* Buswidth will be set by framework */
929 dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
930 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
931 dma_data_tx->maxburst = 1;
932 dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
933 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
934 dma_data_rx->maxburst = 1;
935
936 snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
937
938 return 0;
939}
940
941static const struct regmap_config stm32_h7_i2s_regmap_conf = {
942 .reg_bits = 32,
943 .reg_stride = 4,
944 .val_bits = 32,
945 .max_register = STM32_I2S_SIDR_REG,
946 .readable_reg = stm32_i2s_readable_reg,
947 .volatile_reg = stm32_i2s_volatile_reg,
948 .writeable_reg = stm32_i2s_writeable_reg,
949 .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
950 .fast_io = true,
951 .cache_type = REGCACHE_FLAT,
952};
953
954static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
955 .set_sysclk = stm32_i2s_set_sysclk,
956 .set_fmt = stm32_i2s_set_dai_fmt,
957 .startup = stm32_i2s_startup,
958 .hw_params = stm32_i2s_hw_params,
959 .trigger = stm32_i2s_trigger,
960 .shutdown = stm32_i2s_shutdown,
961};
962
963static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
964 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
965 .buffer_bytes_max = 8 * PAGE_SIZE,
966 .period_bytes_min = 1024,
967 .period_bytes_max = 4 * PAGE_SIZE,
968 .periods_min = 2,
969 .periods_max = 8,
970};
971
972static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
973 .pcm_hardware = &stm32_i2s_pcm_hw,
974 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
975 .prealloc_buffer_size = PAGE_SIZE * 8,
976};
977
978static const struct snd_soc_component_driver stm32_i2s_component = {
979 .name = "stm32-i2s",
980};
981
982static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
983 char *stream_name)
984{
985 stream->stream_name = stream_name;
986 stream->channels_min = 1;
987 stream->channels_max = 2;
988 stream->rates = SNDRV_PCM_RATE_8000_192000;
989 stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
990 SNDRV_PCM_FMTBIT_S32_LE;
991}
992
993static int stm32_i2s_dais_init(struct platform_device *pdev,
994 struct stm32_i2s_data *i2s)
995{
996 struct snd_soc_dai_driver *dai_ptr;
997
998 dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
999 GFP_KERNEL);
1000 if (!dai_ptr)
1001 return -ENOMEM;
1002
1003 dai_ptr->probe = stm32_i2s_dai_probe;
1004 dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
1005 dai_ptr->id = 1;
1006 stm32_i2s_dai_init(&dai_ptr->playback, "playback");
1007 stm32_i2s_dai_init(&dai_ptr->capture, "capture");
1008 i2s->dai_drv = dai_ptr;
1009
1010 return 0;
1011}
1012
1013static const struct of_device_id stm32_i2s_ids[] = {
1014 {
1015 .compatible = "st,stm32h7-i2s",
1016 .data = &stm32_h7_i2s_regmap_conf
1017 },
1018 {},
1019};
1020
1021static int stm32_i2s_parse_dt(struct platform_device *pdev,
1022 struct stm32_i2s_data *i2s)
1023{
1024 struct device_node *np = pdev->dev.of_node;
1025 const struct of_device_id *of_id;
1026 struct reset_control *rst;
1027 struct resource *res;
1028 int irq, ret;
1029
1030 if (!np)
1031 return -ENODEV;
1032
1033 of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
1034 if (of_id)
1035 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
1036 else
1037 return -EINVAL;
1038
1039 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1040 if (IS_ERR(i2s->base))
1041 return PTR_ERR(i2s->base);
1042
1043 i2s->phys_addr = res->start;
1044
1045 /* Get clocks */
1046 i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
1047 if (IS_ERR(i2s->pclk)) {
1048 if (PTR_ERR(i2s->pclk) != -EPROBE_DEFER)
1049 dev_err(&pdev->dev, "Could not get pclk: %ld\n",
1050 PTR_ERR(i2s->pclk));
1051 return PTR_ERR(i2s->pclk);
1052 }
1053
1054 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
1055 if (IS_ERR(i2s->i2sclk)) {
1056 if (PTR_ERR(i2s->i2sclk) != -EPROBE_DEFER)
1057 dev_err(&pdev->dev, "Could not get i2sclk: %ld\n",
1058 PTR_ERR(i2s->i2sclk));
1059 return PTR_ERR(i2s->i2sclk);
1060 }
1061
1062 i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
1063 if (IS_ERR(i2s->x8kclk)) {
1064 if (PTR_ERR(i2s->x8kclk) != -EPROBE_DEFER)
1065 dev_err(&pdev->dev, "Could not get x8k parent clock: %ld\n",
1066 PTR_ERR(i2s->x8kclk));
1067 return PTR_ERR(i2s->x8kclk);
1068 }
1069
1070 i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
1071 if (IS_ERR(i2s->x11kclk)) {
1072 if (PTR_ERR(i2s->x11kclk) != -EPROBE_DEFER)
1073 dev_err(&pdev->dev, "Could not get x11k parent clock: %ld\n",
1074 PTR_ERR(i2s->x11kclk));
1075 return PTR_ERR(i2s->x11kclk);
1076 }
1077
1078 /* Register mclk provider if requested */
1079 if (of_find_property(np, "#clock-cells", NULL)) {
1080 ret = stm32_i2s_add_mclk_provider(i2s);
1081 if (ret < 0)
1082 return ret;
1083 }
1084
1085 /* Get irqs */
1086 irq = platform_get_irq(pdev, 0);
1087 if (irq < 0)
1088 return irq;
1089
1090 ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
1091 dev_name(&pdev->dev), i2s);
1092 if (ret) {
1093 dev_err(&pdev->dev, "irq request returned %d\n", ret);
1094 return ret;
1095 }
1096
1097 /* Reset */
1098 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1099 if (IS_ERR(rst)) {
1100 if (PTR_ERR(rst) != -EPROBE_DEFER)
1101 dev_err(&pdev->dev, "Reset controller error %ld\n",
1102 PTR_ERR(rst));
1103 return PTR_ERR(rst);
1104 }
1105 reset_control_assert(rst);
1106 udelay(2);
1107 reset_control_deassert(rst);
1108
1109 return 0;
1110}
1111
1112static int stm32_i2s_remove(struct platform_device *pdev)
1113{
1114 snd_dmaengine_pcm_unregister(&pdev->dev);
1115 snd_soc_unregister_component(&pdev->dev);
1116
1117 return 0;
1118}
1119
1120static int stm32_i2s_probe(struct platform_device *pdev)
1121{
1122 struct stm32_i2s_data *i2s;
1123 u32 val;
1124 int ret;
1125
1126 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1127 if (!i2s)
1128 return -ENOMEM;
1129
1130 i2s->pdev = pdev;
1131 i2s->ms_flg = I2S_MS_NOT_SET;
1132 spin_lock_init(&i2s->lock_fd);
1133 spin_lock_init(&i2s->irq_lock);
1134 platform_set_drvdata(pdev, i2s);
1135
1136 ret = stm32_i2s_parse_dt(pdev, i2s);
1137 if (ret)
1138 return ret;
1139
1140 ret = stm32_i2s_dais_init(pdev, i2s);
1141 if (ret)
1142 return ret;
1143
1144 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
1145 i2s->base, i2s->regmap_conf);
1146 if (IS_ERR(i2s->regmap)) {
1147 if (PTR_ERR(i2s->regmap) != -EPROBE_DEFER)
1148 dev_err(&pdev->dev, "Regmap init error %ld\n",
1149 PTR_ERR(i2s->regmap));
1150 return PTR_ERR(i2s->regmap);
1151 }
1152
1153 ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
1154 if (ret) {
1155 if (ret != -EPROBE_DEFER)
1156 dev_err(&pdev->dev, "PCM DMA register error %d\n", ret);
1157 return ret;
1158 }
1159
1160 ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
1161 i2s->dai_drv, 1);
1162 if (ret) {
1163 snd_dmaengine_pcm_unregister(&pdev->dev);
1164 return ret;
1165 }
1166
1167 /* Set SPI/I2S in i2s mode */
1168 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
1169 I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
1170 if (ret)
1171 goto error;
1172
1173 ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
1174 if (ret)
1175 goto error;
1176
1177 if (val == I2S_IPIDR_NUMBER) {
1178 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
1179 if (ret)
1180 goto error;
1181
1182 if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
1183 dev_err(&pdev->dev,
1184 "Device does not support i2s mode\n");
1185 ret = -EPERM;
1186 goto error;
1187 }
1188
1189 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
1190 if (ret)
1191 goto error;
1192
1193 dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
1194 FIELD_GET(I2S_VERR_MAJ_MASK, val),
1195 FIELD_GET(I2S_VERR_MIN_MASK, val));
1196 }
1197
1198 return ret;
1199
1200error:
1201 stm32_i2s_remove(pdev);
1202
1203 return ret;
1204}
1205
1206MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
1207
1208#ifdef CONFIG_PM_SLEEP
1209static int stm32_i2s_suspend(struct device *dev)
1210{
1211 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1212
1213 regcache_cache_only(i2s->regmap, true);
1214 regcache_mark_dirty(i2s->regmap);
1215
1216 return 0;
1217}
1218
1219static int stm32_i2s_resume(struct device *dev)
1220{
1221 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1222
1223 regcache_cache_only(i2s->regmap, false);
1224 return regcache_sync(i2s->regmap);
1225}
1226#endif /* CONFIG_PM_SLEEP */
1227
1228static const struct dev_pm_ops stm32_i2s_pm_ops = {
1229 SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
1230};
1231
1232static struct platform_driver stm32_i2s_driver = {
1233 .driver = {
1234 .name = "st,stm32-i2s",
1235 .of_match_table = stm32_i2s_ids,
1236 .pm = &stm32_i2s_pm_ops,
1237 },
1238 .probe = stm32_i2s_probe,
1239 .remove = stm32_i2s_remove,
1240};
1241
1242module_platform_driver(stm32_i2s_driver);
1243
1244MODULE_DESCRIPTION("STM32 Soc i2s Interface");
1245MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1246MODULE_ALIAS("platform:stm32-i2s");
1247MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * STM32 ALSA SoC Digital Audio Interface (I2S) driver.
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/module.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/regmap.h>
16#include <linux/reset.h>
17#include <linux/spinlock.h>
18
19#include <sound/dmaengine_pcm.h>
20#include <sound/pcm_params.h>
21
22#define STM32_I2S_CR1_REG 0x0
23#define STM32_I2S_CFG1_REG 0x08
24#define STM32_I2S_CFG2_REG 0x0C
25#define STM32_I2S_IER_REG 0x10
26#define STM32_I2S_SR_REG 0x14
27#define STM32_I2S_IFCR_REG 0x18
28#define STM32_I2S_TXDR_REG 0X20
29#define STM32_I2S_RXDR_REG 0x30
30#define STM32_I2S_CGFR_REG 0X50
31#define STM32_I2S_HWCFGR_REG 0x3F0
32#define STM32_I2S_VERR_REG 0x3F4
33#define STM32_I2S_IPIDR_REG 0x3F8
34#define STM32_I2S_SIDR_REG 0x3FC
35
36/* Bit definition for SPI2S_CR1 register */
37#define I2S_CR1_SPE BIT(0)
38#define I2S_CR1_CSTART BIT(9)
39#define I2S_CR1_CSUSP BIT(10)
40#define I2S_CR1_HDDIR BIT(11)
41#define I2S_CR1_SSI BIT(12)
42#define I2S_CR1_CRC33_17 BIT(13)
43#define I2S_CR1_RCRCI BIT(14)
44#define I2S_CR1_TCRCI BIT(15)
45
46/* Bit definition for SPI_CFG2 register */
47#define I2S_CFG2_IOSWP_SHIFT 15
48#define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
49#define I2S_CFG2_LSBFRST BIT(23)
50#define I2S_CFG2_AFCNTR BIT(31)
51
52/* Bit definition for SPI_CFG1 register */
53#define I2S_CFG1_FTHVL_SHIFT 5
54#define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
55#define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
56
57#define I2S_CFG1_TXDMAEN BIT(15)
58#define I2S_CFG1_RXDMAEN BIT(14)
59
60/* Bit definition for SPI2S_IER register */
61#define I2S_IER_RXPIE BIT(0)
62#define I2S_IER_TXPIE BIT(1)
63#define I2S_IER_DPXPIE BIT(2)
64#define I2S_IER_EOTIE BIT(3)
65#define I2S_IER_TXTFIE BIT(4)
66#define I2S_IER_UDRIE BIT(5)
67#define I2S_IER_OVRIE BIT(6)
68#define I2S_IER_CRCEIE BIT(7)
69#define I2S_IER_TIFREIE BIT(8)
70#define I2S_IER_MODFIE BIT(9)
71#define I2S_IER_TSERFIE BIT(10)
72
73/* Bit definition for SPI2S_SR register */
74#define I2S_SR_RXP BIT(0)
75#define I2S_SR_TXP BIT(1)
76#define I2S_SR_DPXP BIT(2)
77#define I2S_SR_EOT BIT(3)
78#define I2S_SR_TXTF BIT(4)
79#define I2S_SR_UDR BIT(5)
80#define I2S_SR_OVR BIT(6)
81#define I2S_SR_CRCERR BIT(7)
82#define I2S_SR_TIFRE BIT(8)
83#define I2S_SR_MODF BIT(9)
84#define I2S_SR_TSERF BIT(10)
85#define I2S_SR_SUSP BIT(11)
86#define I2S_SR_TXC BIT(12)
87#define I2S_SR_RXPLVL GENMASK(14, 13)
88#define I2S_SR_RXWNE BIT(15)
89
90#define I2S_SR_MASK GENMASK(15, 0)
91
92/* Bit definition for SPI_IFCR register */
93#define I2S_IFCR_EOTC BIT(3)
94#define I2S_IFCR_TXTFC BIT(4)
95#define I2S_IFCR_UDRC BIT(5)
96#define I2S_IFCR_OVRC BIT(6)
97#define I2S_IFCR_CRCEC BIT(7)
98#define I2S_IFCR_TIFREC BIT(8)
99#define I2S_IFCR_MODFC BIT(9)
100#define I2S_IFCR_TSERFC BIT(10)
101#define I2S_IFCR_SUSPC BIT(11)
102
103#define I2S_IFCR_MASK GENMASK(11, 3)
104
105/* Bit definition for SPI_I2SCGFR register */
106#define I2S_CGFR_I2SMOD BIT(0)
107
108#define I2S_CGFR_I2SCFG_SHIFT 1
109#define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
110#define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
111
112#define I2S_CGFR_I2SSTD_SHIFT 4
113#define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
114#define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
115
116#define I2S_CGFR_PCMSYNC BIT(7)
117
118#define I2S_CGFR_DATLEN_SHIFT 8
119#define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
120#define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
121
122#define I2S_CGFR_CHLEN_SHIFT 10
123#define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
124#define I2S_CGFR_CKPOL BIT(11)
125#define I2S_CGFR_FIXCH BIT(12)
126#define I2S_CGFR_WSINV BIT(13)
127#define I2S_CGFR_DATFMT BIT(14)
128
129#define I2S_CGFR_I2SDIV_SHIFT 16
130#define I2S_CGFR_I2SDIV_BIT_H 23
131#define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
132 I2S_CGFR_I2SDIV_SHIFT)
133#define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
134#define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
135 I2S_CGFR_I2SDIV_SHIFT)) - 1)
136
137#define I2S_CGFR_ODD_SHIFT 24
138#define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
139#define I2S_CGFR_MCKOE BIT(25)
140
141/* Registers below apply to I2S version 1.1 and more */
142
143/* Bit definition for SPI_HWCFGR register */
144#define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
145
146/* Bit definition for SPI_VERR register */
147#define I2S_VERR_MIN_MASK GENMASK(3, 0)
148#define I2S_VERR_MAJ_MASK GENMASK(7, 4)
149
150/* Bit definition for SPI_IPIDR register */
151#define I2S_IPIDR_ID_MASK GENMASK(31, 0)
152
153/* Bit definition for SPI_SIDR register */
154#define I2S_SIDR_ID_MASK GENMASK(31, 0)
155
156#define I2S_IPIDR_NUMBER 0x00130022
157
158enum i2s_master_mode {
159 I2S_MS_NOT_SET,
160 I2S_MS_MASTER,
161 I2S_MS_SLAVE,
162};
163
164enum i2s_mode {
165 I2S_I2SMOD_TX_SLAVE,
166 I2S_I2SMOD_RX_SLAVE,
167 I2S_I2SMOD_TX_MASTER,
168 I2S_I2SMOD_RX_MASTER,
169 I2S_I2SMOD_FD_SLAVE,
170 I2S_I2SMOD_FD_MASTER,
171};
172
173enum i2s_fifo_th {
174 I2S_FIFO_TH_NONE,
175 I2S_FIFO_TH_ONE_QUARTER,
176 I2S_FIFO_TH_HALF,
177 I2S_FIFO_TH_THREE_QUARTER,
178 I2S_FIFO_TH_FULL,
179};
180
181enum i2s_std {
182 I2S_STD_I2S,
183 I2S_STD_LEFT_J,
184 I2S_STD_RIGHT_J,
185 I2S_STD_DSP,
186};
187
188enum i2s_datlen {
189 I2S_I2SMOD_DATLEN_16,
190 I2S_I2SMOD_DATLEN_24,
191 I2S_I2SMOD_DATLEN_32,
192};
193
194#define STM32_I2S_FIFO_SIZE 16
195
196#define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
197#define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
198
199/**
200 * struct stm32_i2s_data - private data of I2S
201 * @regmap_conf: I2S register map configuration pointer
202 * @regmap: I2S register map pointer
203 * @pdev: device data pointer
204 * @dai_drv: DAI driver pointer
205 * @dma_data_tx: dma configuration data for tx channel
206 * @dma_data_rx: dma configuration data for tx channel
207 * @substream: PCM substream data pointer
208 * @i2sclk: kernel clock feeding the I2S clock generator
209 * @pclk: peripheral clock driving bus interface
210 * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
211 * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
212 * @base: mmio register base virtual address
213 * @phys_addr: I2S registers physical base address
214 * @lock_fd: lock to manage race conditions in full duplex mode
215 * @irq_lock: prevent race condition with IRQ
216 * @mclk_rate: master clock frequency (Hz)
217 * @fmt: DAI protocol
218 * @refcount: keep count of opened streams on I2S
219 * @ms_flg: master mode flag.
220 */
221struct stm32_i2s_data {
222 const struct regmap_config *regmap_conf;
223 struct regmap *regmap;
224 struct platform_device *pdev;
225 struct snd_soc_dai_driver *dai_drv;
226 struct snd_dmaengine_dai_dma_data dma_data_tx;
227 struct snd_dmaengine_dai_dma_data dma_data_rx;
228 struct snd_pcm_substream *substream;
229 struct clk *i2sclk;
230 struct clk *pclk;
231 struct clk *x8kclk;
232 struct clk *x11kclk;
233 void __iomem *base;
234 dma_addr_t phys_addr;
235 spinlock_t lock_fd; /* Manage race conditions for full duplex */
236 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
237 unsigned int mclk_rate;
238 unsigned int fmt;
239 int refcount;
240 int ms_flg;
241};
242
243static irqreturn_t stm32_i2s_isr(int irq, void *devid)
244{
245 struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
246 struct platform_device *pdev = i2s->pdev;
247 u32 sr, ier;
248 unsigned long flags;
249 int err = 0;
250
251 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
252 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
253
254 flags = sr & ier;
255 if (!flags) {
256 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
257 sr, ier);
258 return IRQ_NONE;
259 }
260
261 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
262 I2S_IFCR_MASK, flags);
263
264 if (flags & I2S_SR_OVR) {
265 dev_dbg(&pdev->dev, "Overrun\n");
266 err = 1;
267 }
268
269 if (flags & I2S_SR_UDR) {
270 dev_dbg(&pdev->dev, "Underrun\n");
271 err = 1;
272 }
273
274 if (flags & I2S_SR_TIFRE)
275 dev_dbg(&pdev->dev, "Frame error\n");
276
277 spin_lock(&i2s->irq_lock);
278 if (err && i2s->substream)
279 snd_pcm_stop_xrun(i2s->substream);
280 spin_unlock(&i2s->irq_lock);
281
282 return IRQ_HANDLED;
283}
284
285static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
286{
287 switch (reg) {
288 case STM32_I2S_CR1_REG:
289 case STM32_I2S_CFG1_REG:
290 case STM32_I2S_CFG2_REG:
291 case STM32_I2S_IER_REG:
292 case STM32_I2S_SR_REG:
293 case STM32_I2S_RXDR_REG:
294 case STM32_I2S_CGFR_REG:
295 case STM32_I2S_HWCFGR_REG:
296 case STM32_I2S_VERR_REG:
297 case STM32_I2S_IPIDR_REG:
298 case STM32_I2S_SIDR_REG:
299 return true;
300 default:
301 return false;
302 }
303}
304
305static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
306{
307 switch (reg) {
308 case STM32_I2S_SR_REG:
309 case STM32_I2S_RXDR_REG:
310 return true;
311 default:
312 return false;
313 }
314}
315
316static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
317{
318 switch (reg) {
319 case STM32_I2S_CR1_REG:
320 case STM32_I2S_CFG1_REG:
321 case STM32_I2S_CFG2_REG:
322 case STM32_I2S_IER_REG:
323 case STM32_I2S_IFCR_REG:
324 case STM32_I2S_TXDR_REG:
325 case STM32_I2S_CGFR_REG:
326 return true;
327 default:
328 return false;
329 }
330}
331
332static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
333{
334 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
335 u32 cgfr;
336 u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
337 I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
338
339 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
340
341 /*
342 * winv = 0 : default behavior (high/low) for all standards
343 * ckpol = 0 for all standards.
344 */
345 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
346 case SND_SOC_DAIFMT_I2S:
347 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
348 break;
349 case SND_SOC_DAIFMT_MSB:
350 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
351 break;
352 case SND_SOC_DAIFMT_LSB:
353 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
354 break;
355 case SND_SOC_DAIFMT_DSP_A:
356 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
357 break;
358 /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
359 default:
360 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
361 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
362 return -EINVAL;
363 }
364
365 /* DAI clock strobing */
366 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
367 case SND_SOC_DAIFMT_NB_NF:
368 break;
369 case SND_SOC_DAIFMT_IB_NF:
370 cgfr |= I2S_CGFR_CKPOL;
371 break;
372 case SND_SOC_DAIFMT_NB_IF:
373 cgfr |= I2S_CGFR_WSINV;
374 break;
375 case SND_SOC_DAIFMT_IB_IF:
376 cgfr |= I2S_CGFR_CKPOL;
377 cgfr |= I2S_CGFR_WSINV;
378 break;
379 default:
380 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
381 fmt & SND_SOC_DAIFMT_INV_MASK);
382 return -EINVAL;
383 }
384
385 /* DAI clock master masks */
386 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
387 case SND_SOC_DAIFMT_CBM_CFM:
388 i2s->ms_flg = I2S_MS_SLAVE;
389 break;
390 case SND_SOC_DAIFMT_CBS_CFS:
391 i2s->ms_flg = I2S_MS_MASTER;
392 break;
393 default:
394 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
395 fmt & SND_SOC_DAIFMT_MASTER_MASK);
396 return -EINVAL;
397 }
398
399 i2s->fmt = fmt;
400 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
401 cgfr_mask, cgfr);
402}
403
404static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
405 int clk_id, unsigned int freq, int dir)
406{
407 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
408
409 dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq);
410
411 if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) {
412 i2s->mclk_rate = freq;
413
414 /* Enable master clock if master mode and mclk-fs are set */
415 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
416 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
417 }
418
419 return 0;
420}
421
422static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
423 struct snd_pcm_hw_params *params)
424{
425 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
426 unsigned long i2s_clock_rate;
427 unsigned int tmp, div, real_div, nb_bits, frame_len;
428 unsigned int rate = params_rate(params);
429 int ret;
430 u32 cgfr, cgfr_mask;
431 bool odd;
432
433 if (!(rate % 11025))
434 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
435 else
436 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
437 i2s_clock_rate = clk_get_rate(i2s->i2sclk);
438
439 /*
440 * mckl = mclk_ratio x ws
441 * i2s mode : mclk_ratio = 256
442 * dsp mode : mclk_ratio = 128
443 *
444 * mclk on
445 * i2s mode : div = i2s_clk / (mclk_ratio * ws)
446 * dsp mode : div = i2s_clk / (mclk_ratio * ws)
447 * mclk off
448 * i2s mode : div = i2s_clk / (nb_bits x ws)
449 * dsp mode : div = i2s_clk / (nb_bits x ws)
450 */
451 if (i2s->mclk_rate) {
452 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate);
453 } else {
454 frame_len = 32;
455 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
456 SND_SOC_DAIFMT_DSP_A)
457 frame_len = 16;
458
459 /* master clock not enabled */
460 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
461 if (ret < 0)
462 return ret;
463
464 nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
465 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate));
466 }
467
468 /* Check the parity of the divider */
469 odd = tmp & 0x1;
470
471 /* Compute the div prescaler */
472 div = tmp >> 1;
473
474 cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT);
475 cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
476
477 real_div = ((2 * div) + odd);
478 dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n",
479 i2s_clock_rate, rate);
480 dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
481 div, odd, real_div);
482
483 if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) {
484 dev_err(cpu_dai->dev, "Wrong divider setting\n");
485 return -EINVAL;
486 }
487
488 if (!div && !odd)
489 dev_warn(cpu_dai->dev, "real divider forced to 1\n");
490
491 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
492 cgfr_mask, cgfr);
493 if (ret < 0)
494 return ret;
495
496 /* Set bitclock and frameclock to their inactive state */
497 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
498 I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
499}
500
501static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
502 struct snd_pcm_hw_params *params,
503 struct snd_pcm_substream *substream)
504{
505 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
506 int format = params_width(params);
507 u32 cfgr, cfgr_mask, cfg1;
508 unsigned int fthlv;
509 int ret;
510
511 switch (format) {
512 case 16:
513 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
514 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
515 break;
516 case 32:
517 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
518 I2S_CGFR_CHLEN;
519 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
520 break;
521 default:
522 dev_err(cpu_dai->dev, "Unexpected format %d", format);
523 return -EINVAL;
524 }
525
526 if (STM32_I2S_IS_SLAVE(i2s)) {
527 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
528
529 /* As data length is either 16 or 32 bits, fixch always set */
530 cfgr |= I2S_CGFR_FIXCH;
531 cfgr_mask |= I2S_CGFR_FIXCH;
532 } else {
533 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
534 }
535 cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
536
537 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
538 cfgr_mask, cfgr);
539 if (ret < 0)
540 return ret;
541
542 fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
543 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
544
545 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
546 I2S_CFG1_FTHVL_MASK, cfg1);
547}
548
549static int stm32_i2s_startup(struct snd_pcm_substream *substream,
550 struct snd_soc_dai *cpu_dai)
551{
552 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
553 unsigned long flags;
554 int ret;
555
556 spin_lock_irqsave(&i2s->irq_lock, flags);
557 i2s->substream = substream;
558 spin_unlock_irqrestore(&i2s->irq_lock, flags);
559
560 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
561 snd_pcm_hw_constraint_single(substream->runtime,
562 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
563
564 ret = clk_prepare_enable(i2s->i2sclk);
565 if (ret < 0) {
566 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
567 return ret;
568 }
569
570 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
571 I2S_IFCR_MASK, I2S_IFCR_MASK);
572}
573
574static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
575 struct snd_pcm_hw_params *params,
576 struct snd_soc_dai *cpu_dai)
577{
578 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
579 int ret;
580
581 ret = stm32_i2s_configure(cpu_dai, params, substream);
582 if (ret < 0) {
583 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
584 return ret;
585 }
586
587 if (STM32_I2S_IS_MASTER(i2s))
588 ret = stm32_i2s_configure_clock(cpu_dai, params);
589
590 return ret;
591}
592
593static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
594 struct snd_soc_dai *cpu_dai)
595{
596 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
597 bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
598 u32 cfg1_mask, ier;
599 int ret;
600
601 switch (cmd) {
602 case SNDRV_PCM_TRIGGER_START:
603 case SNDRV_PCM_TRIGGER_RESUME:
604 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
605 /* Enable i2s */
606 dev_dbg(cpu_dai->dev, "start I2S %s\n",
607 playback_flg ? "playback" : "capture");
608
609 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
610 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
611 cfg1_mask, cfg1_mask);
612
613 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
614 I2S_CR1_SPE, I2S_CR1_SPE);
615 if (ret < 0) {
616 dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
617 return ret;
618 }
619
620 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
621 I2S_CR1_CSTART, I2S_CR1_CSTART);
622 if (ret < 0) {
623 dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
624 return ret;
625 }
626
627 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
628 I2S_IFCR_MASK, I2S_IFCR_MASK);
629
630 spin_lock(&i2s->lock_fd);
631 i2s->refcount++;
632 if (playback_flg) {
633 ier = I2S_IER_UDRIE;
634 } else {
635 ier = I2S_IER_OVRIE;
636
637 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
638 /* dummy write to gate bus clocks */
639 regmap_write(i2s->regmap,
640 STM32_I2S_TXDR_REG, 0);
641 }
642 spin_unlock(&i2s->lock_fd);
643
644 if (STM32_I2S_IS_SLAVE(i2s))
645 ier |= I2S_IER_TIFREIE;
646
647 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
648 break;
649 case SNDRV_PCM_TRIGGER_STOP:
650 case SNDRV_PCM_TRIGGER_SUSPEND:
651 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
652 dev_dbg(cpu_dai->dev, "stop I2S %s\n",
653 playback_flg ? "playback" : "capture");
654
655 if (playback_flg)
656 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
657 I2S_IER_UDRIE,
658 (unsigned int)~I2S_IER_UDRIE);
659 else
660 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
661 I2S_IER_OVRIE,
662 (unsigned int)~I2S_IER_OVRIE);
663
664 spin_lock(&i2s->lock_fd);
665 i2s->refcount--;
666 if (i2s->refcount) {
667 spin_unlock(&i2s->lock_fd);
668 break;
669 }
670
671 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
672 I2S_CR1_SPE, 0);
673 if (ret < 0) {
674 dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
675 spin_unlock(&i2s->lock_fd);
676 return ret;
677 }
678 spin_unlock(&i2s->lock_fd);
679
680 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
681 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
682 cfg1_mask, 0);
683 break;
684 default:
685 return -EINVAL;
686 }
687
688 return 0;
689}
690
691static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
692 struct snd_soc_dai *cpu_dai)
693{
694 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
695 unsigned long flags;
696
697 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
698 I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
699
700 clk_disable_unprepare(i2s->i2sclk);
701
702 spin_lock_irqsave(&i2s->irq_lock, flags);
703 i2s->substream = NULL;
704 spin_unlock_irqrestore(&i2s->irq_lock, flags);
705}
706
707static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
708{
709 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
710 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
711 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
712
713 /* Buswidth will be set by framework */
714 dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
715 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
716 dma_data_tx->maxburst = 1;
717 dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
718 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
719 dma_data_rx->maxburst = 1;
720
721 snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
722
723 return 0;
724}
725
726static const struct regmap_config stm32_h7_i2s_regmap_conf = {
727 .reg_bits = 32,
728 .reg_stride = 4,
729 .val_bits = 32,
730 .max_register = STM32_I2S_SIDR_REG,
731 .readable_reg = stm32_i2s_readable_reg,
732 .volatile_reg = stm32_i2s_volatile_reg,
733 .writeable_reg = stm32_i2s_writeable_reg,
734 .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
735 .fast_io = true,
736 .cache_type = REGCACHE_FLAT,
737};
738
739static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
740 .set_sysclk = stm32_i2s_set_sysclk,
741 .set_fmt = stm32_i2s_set_dai_fmt,
742 .startup = stm32_i2s_startup,
743 .hw_params = stm32_i2s_hw_params,
744 .trigger = stm32_i2s_trigger,
745 .shutdown = stm32_i2s_shutdown,
746};
747
748static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
749 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
750 .buffer_bytes_max = 8 * PAGE_SIZE,
751 .period_bytes_min = 1024,
752 .period_bytes_max = 4 * PAGE_SIZE,
753 .periods_min = 2,
754 .periods_max = 8,
755};
756
757static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
758 .pcm_hardware = &stm32_i2s_pcm_hw,
759 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
760 .prealloc_buffer_size = PAGE_SIZE * 8,
761};
762
763static const struct snd_soc_component_driver stm32_i2s_component = {
764 .name = "stm32-i2s",
765};
766
767static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
768 char *stream_name)
769{
770 stream->stream_name = stream_name;
771 stream->channels_min = 1;
772 stream->channels_max = 2;
773 stream->rates = SNDRV_PCM_RATE_8000_192000;
774 stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
775 SNDRV_PCM_FMTBIT_S32_LE;
776}
777
778static int stm32_i2s_dais_init(struct platform_device *pdev,
779 struct stm32_i2s_data *i2s)
780{
781 struct snd_soc_dai_driver *dai_ptr;
782
783 dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
784 GFP_KERNEL);
785 if (!dai_ptr)
786 return -ENOMEM;
787
788 dai_ptr->probe = stm32_i2s_dai_probe;
789 dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
790 dai_ptr->id = 1;
791 stm32_i2s_dai_init(&dai_ptr->playback, "playback");
792 stm32_i2s_dai_init(&dai_ptr->capture, "capture");
793 i2s->dai_drv = dai_ptr;
794
795 return 0;
796}
797
798static const struct of_device_id stm32_i2s_ids[] = {
799 {
800 .compatible = "st,stm32h7-i2s",
801 .data = &stm32_h7_i2s_regmap_conf
802 },
803 {},
804};
805
806static int stm32_i2s_parse_dt(struct platform_device *pdev,
807 struct stm32_i2s_data *i2s)
808{
809 struct device_node *np = pdev->dev.of_node;
810 const struct of_device_id *of_id;
811 struct reset_control *rst;
812 struct resource *res;
813 int irq, ret;
814
815 if (!np)
816 return -ENODEV;
817
818 of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
819 if (of_id)
820 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
821 else
822 return -EINVAL;
823
824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
825 i2s->base = devm_ioremap_resource(&pdev->dev, res);
826 if (IS_ERR(i2s->base))
827 return PTR_ERR(i2s->base);
828
829 i2s->phys_addr = res->start;
830
831 /* Get clocks */
832 i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
833 if (IS_ERR(i2s->pclk)) {
834 dev_err(&pdev->dev, "Could not get pclk\n");
835 return PTR_ERR(i2s->pclk);
836 }
837
838 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
839 if (IS_ERR(i2s->i2sclk)) {
840 dev_err(&pdev->dev, "Could not get i2sclk\n");
841 return PTR_ERR(i2s->i2sclk);
842 }
843
844 i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
845 if (IS_ERR(i2s->x8kclk)) {
846 dev_err(&pdev->dev, "missing x8k parent clock\n");
847 return PTR_ERR(i2s->x8kclk);
848 }
849
850 i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
851 if (IS_ERR(i2s->x11kclk)) {
852 dev_err(&pdev->dev, "missing x11k parent clock\n");
853 return PTR_ERR(i2s->x11kclk);
854 }
855
856 /* Get irqs */
857 irq = platform_get_irq(pdev, 0);
858 if (irq < 0)
859 return irq;
860
861 ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
862 dev_name(&pdev->dev), i2s);
863 if (ret) {
864 dev_err(&pdev->dev, "irq request returned %d\n", ret);
865 return ret;
866 }
867
868 /* Reset */
869 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
870 if (!IS_ERR(rst)) {
871 reset_control_assert(rst);
872 udelay(2);
873 reset_control_deassert(rst);
874 }
875
876 return 0;
877}
878
879static int stm32_i2s_probe(struct platform_device *pdev)
880{
881 struct stm32_i2s_data *i2s;
882 u32 val;
883 int ret;
884
885 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
886 if (!i2s)
887 return -ENOMEM;
888
889 ret = stm32_i2s_parse_dt(pdev, i2s);
890 if (ret)
891 return ret;
892
893 i2s->pdev = pdev;
894 i2s->ms_flg = I2S_MS_NOT_SET;
895 spin_lock_init(&i2s->lock_fd);
896 spin_lock_init(&i2s->irq_lock);
897 platform_set_drvdata(pdev, i2s);
898
899 ret = stm32_i2s_dais_init(pdev, i2s);
900 if (ret)
901 return ret;
902
903 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
904 i2s->base, i2s->regmap_conf);
905 if (IS_ERR(i2s->regmap)) {
906 dev_err(&pdev->dev, "regmap init failed\n");
907 return PTR_ERR(i2s->regmap);
908 }
909
910 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
911 i2s->dai_drv, 1);
912 if (ret)
913 return ret;
914
915 ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
916 &stm32_i2s_pcm_config, 0);
917 if (ret)
918 return ret;
919
920 /* Set SPI/I2S in i2s mode */
921 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
922 I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
923 if (ret)
924 return ret;
925
926 ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
927 if (ret)
928 return ret;
929
930 if (val == I2S_IPIDR_NUMBER) {
931 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
932 if (ret)
933 return ret;
934
935 if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
936 dev_err(&pdev->dev,
937 "Device does not support i2s mode\n");
938 return -EPERM;
939 }
940
941 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
942
943 dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
944 FIELD_GET(I2S_VERR_MAJ_MASK, val),
945 FIELD_GET(I2S_VERR_MIN_MASK, val));
946 }
947
948 return ret;
949}
950
951MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
952
953#ifdef CONFIG_PM_SLEEP
954static int stm32_i2s_suspend(struct device *dev)
955{
956 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
957
958 regcache_cache_only(i2s->regmap, true);
959 regcache_mark_dirty(i2s->regmap);
960
961 return 0;
962}
963
964static int stm32_i2s_resume(struct device *dev)
965{
966 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
967
968 regcache_cache_only(i2s->regmap, false);
969 return regcache_sync(i2s->regmap);
970}
971#endif /* CONFIG_PM_SLEEP */
972
973static const struct dev_pm_ops stm32_i2s_pm_ops = {
974 SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
975};
976
977static struct platform_driver stm32_i2s_driver = {
978 .driver = {
979 .name = "st,stm32-i2s",
980 .of_match_table = stm32_i2s_ids,
981 .pm = &stm32_i2s_pm_ops,
982 },
983 .probe = stm32_i2s_probe,
984};
985
986module_platform_driver(stm32_i2s_driver);
987
988MODULE_DESCRIPTION("STM32 Soc i2s Interface");
989MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
990MODULE_ALIAS("platform:stm32-i2s");
991MODULE_LICENSE("GPL v2");