Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (C) 2013 NVIDIA Corporation
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 * Benoit Goby <benoit@android.com>
9 * Venu Byravarasu <vbyravarasu@nvidia.com>
10 */
11
12#include <linux/delay.h>
13#include <linux/err.h>
14#include <linux/export.h>
15#include <linux/gpio/consumer.h>
16#include <linux/iopoll.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/resource.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24
25#include <linux/regulator/consumer.h>
26
27#include <linux/usb/ehci_def.h>
28#include <linux/usb/of.h>
29#include <linux/usb/tegra_usb_phy.h>
30#include <linux/usb/ulpi.h>
31
32#define ULPI_VIEWPORT 0x170
33
34/* PORTSC PTS/PHCD bits, Tegra20 only */
35#define TEGRA_USB_PORTSC1 0x184
36#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
37#define TEGRA_USB_PORTSC1_PHCD BIT(23)
38
39/* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
40#define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
41#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
42#define TEGRA_USB_HOSTPC1_DEVLC_PHCD BIT(22)
43
44/* Bits of PORTSC1, which will get cleared by writing 1 into them */
45#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
46
47#define USB_SUSP_CTRL 0x400
48#define USB_WAKE_ON_RESUME_EN BIT(2)
49#define USB_WAKE_ON_CNNT_EN_DEV BIT(3)
50#define USB_WAKE_ON_DISCON_EN_DEV BIT(4)
51#define USB_SUSP_CLR BIT(5)
52#define USB_PHY_CLK_VALID BIT(7)
53#define UTMIP_RESET BIT(11)
54#define UHSIC_RESET BIT(11)
55#define UTMIP_PHY_ENABLE BIT(12)
56#define ULPI_PHY_ENABLE BIT(13)
57#define USB_SUSP_SET BIT(14)
58#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
59
60#define USB_PHY_VBUS_SENSORS 0x404
61#define B_SESS_VLD_WAKEUP_EN BIT(14)
62#define A_SESS_VLD_WAKEUP_EN BIT(22)
63#define A_VBUS_VLD_WAKEUP_EN BIT(30)
64
65#define USB_PHY_VBUS_WAKEUP_ID 0x408
66#define VBUS_WAKEUP_STS BIT(10)
67#define VBUS_WAKEUP_WAKEUP_EN BIT(30)
68
69#define USB1_LEGACY_CTRL 0x410
70#define USB1_NO_LEGACY_MODE BIT(0)
71#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
72#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
73#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
74 (1 << 1)
75#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
76#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
77
78#define ULPI_TIMING_CTRL_0 0x424
79#define ULPI_OUTPUT_PINMUX_BYP BIT(10)
80#define ULPI_CLKOUT_PINMUX_BYP BIT(11)
81
82#define ULPI_TIMING_CTRL_1 0x428
83#define ULPI_DATA_TRIMMER_LOAD BIT(0)
84#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
85#define ULPI_STPDIRNXT_TRIMMER_LOAD BIT(16)
86#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
87#define ULPI_DIR_TRIMMER_LOAD BIT(24)
88#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
89
90#define UTMIP_PLL_CFG1 0x804
91#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
92#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
93
94#define UTMIP_XCVR_CFG0 0x808
95#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
96#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
97#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
98#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
99#define UTMIP_FORCE_PD_POWERDOWN BIT(14)
100#define UTMIP_FORCE_PD2_POWERDOWN BIT(16)
101#define UTMIP_FORCE_PDZI_POWERDOWN BIT(18)
102#define UTMIP_XCVR_LSBIAS_SEL BIT(21)
103#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
104#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
105
106#define UTMIP_BIAS_CFG0 0x80c
107#define UTMIP_OTGPD BIT(11)
108#define UTMIP_BIASPD BIT(10)
109#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
110#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
111#define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
112
113#define UTMIP_HSRX_CFG0 0x810
114#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
115#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
116
117#define UTMIP_HSRX_CFG1 0x814
118#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
119
120#define UTMIP_TX_CFG0 0x820
121#define UTMIP_FS_PREABMLE_J BIT(19)
122#define UTMIP_HS_DISCON_DISABLE BIT(8)
123
124#define UTMIP_MISC_CFG0 0x824
125#define UTMIP_DPDM_OBSERVE BIT(26)
126#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
127#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
128#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
129#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
130#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
131#define UTMIP_SUSPEND_EXIT_ON_EDGE BIT(22)
132
133#define UTMIP_MISC_CFG1 0x828
134#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
135#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
136
137#define UTMIP_DEBOUNCE_CFG0 0x82c
138#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
139
140#define UTMIP_BAT_CHRG_CFG0 0x830
141#define UTMIP_PD_CHRG BIT(0)
142
143#define UTMIP_SPARE_CFG0 0x834
144#define FUSE_SETUP_SEL BIT(3)
145
146#define UTMIP_XCVR_CFG1 0x838
147#define UTMIP_FORCE_PDDISC_POWERDOWN BIT(0)
148#define UTMIP_FORCE_PDCHRP_POWERDOWN BIT(2)
149#define UTMIP_FORCE_PDDR_POWERDOWN BIT(4)
150#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
151
152#define UTMIP_BIAS_CFG1 0x83c
153#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
154
155/* For Tegra30 and above only, the address is different in Tegra20 */
156#define USB_USBMODE 0x1f8
157#define USB_USBMODE_MASK (3 << 0)
158#define USB_USBMODE_HOST (3 << 0)
159#define USB_USBMODE_DEVICE (2 << 0)
160
161static DEFINE_SPINLOCK(utmip_pad_lock);
162static unsigned int utmip_pad_count;
163
164struct tegra_xtal_freq {
165 unsigned int freq;
166 u8 enable_delay;
167 u8 stable_count;
168 u8 active_delay;
169 u8 xtal_freq_count;
170 u16 debounce;
171};
172
173static const struct tegra_xtal_freq tegra_freq_table[] = {
174 {
175 .freq = 12000000,
176 .enable_delay = 0x02,
177 .stable_count = 0x2F,
178 .active_delay = 0x04,
179 .xtal_freq_count = 0x76,
180 .debounce = 0x7530,
181 },
182 {
183 .freq = 13000000,
184 .enable_delay = 0x02,
185 .stable_count = 0x33,
186 .active_delay = 0x05,
187 .xtal_freq_count = 0x7F,
188 .debounce = 0x7EF4,
189 },
190 {
191 .freq = 19200000,
192 .enable_delay = 0x03,
193 .stable_count = 0x4B,
194 .active_delay = 0x06,
195 .xtal_freq_count = 0xBB,
196 .debounce = 0xBB80,
197 },
198 {
199 .freq = 26000000,
200 .enable_delay = 0x04,
201 .stable_count = 0x66,
202 .active_delay = 0x09,
203 .xtal_freq_count = 0xFE,
204 .debounce = 0xFDE8,
205 },
206};
207
208static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)
209{
210 return container_of(u_phy, struct tegra_usb_phy, u_phy);
211}
212
213static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
214{
215 void __iomem *base = phy->regs;
216 u32 val;
217
218 if (phy->soc_config->has_hostpc) {
219 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
220 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
221 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
222 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
223 } else {
224 val = readl_relaxed(base + TEGRA_USB_PORTSC1);
225 val &= ~TEGRA_PORTSC1_RWC_BITS;
226 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
227 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
228 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
229 }
230}
231
232static void set_phcd(struct tegra_usb_phy *phy, bool enable)
233{
234 void __iomem *base = phy->regs;
235 u32 val;
236
237 if (phy->soc_config->has_hostpc) {
238 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
239 if (enable)
240 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
241 else
242 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
243 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
244 } else {
245 val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
246 if (enable)
247 val |= TEGRA_USB_PORTSC1_PHCD;
248 else
249 val &= ~TEGRA_USB_PORTSC1_PHCD;
250 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
251 }
252}
253
254static int utmip_pad_open(struct tegra_usb_phy *phy)
255{
256 int ret;
257
258 ret = clk_prepare_enable(phy->pad_clk);
259 if (ret) {
260 dev_err(phy->u_phy.dev,
261 "Failed to enable UTMI-pads clock: %d\n", ret);
262 return ret;
263 }
264
265 spin_lock(&utmip_pad_lock);
266
267 ret = reset_control_deassert(phy->pad_rst);
268 if (ret) {
269 dev_err(phy->u_phy.dev,
270 "Failed to initialize UTMI-pads reset: %d\n", ret);
271 goto unlock;
272 }
273
274 ret = reset_control_assert(phy->pad_rst);
275 if (ret) {
276 dev_err(phy->u_phy.dev,
277 "Failed to assert UTMI-pads reset: %d\n", ret);
278 goto unlock;
279 }
280
281 udelay(1);
282
283 ret = reset_control_deassert(phy->pad_rst);
284 if (ret)
285 dev_err(phy->u_phy.dev,
286 "Failed to deassert UTMI-pads reset: %d\n", ret);
287unlock:
288 spin_unlock(&utmip_pad_lock);
289
290 clk_disable_unprepare(phy->pad_clk);
291
292 return ret;
293}
294
295static int utmip_pad_close(struct tegra_usb_phy *phy)
296{
297 int ret;
298
299 ret = clk_prepare_enable(phy->pad_clk);
300 if (ret) {
301 dev_err(phy->u_phy.dev,
302 "Failed to enable UTMI-pads clock: %d\n", ret);
303 return ret;
304 }
305
306 ret = reset_control_assert(phy->pad_rst);
307 if (ret)
308 dev_err(phy->u_phy.dev,
309 "Failed to assert UTMI-pads reset: %d\n", ret);
310
311 udelay(1);
312
313 clk_disable_unprepare(phy->pad_clk);
314
315 return ret;
316}
317
318static int utmip_pad_power_on(struct tegra_usb_phy *phy)
319{
320 struct tegra_utmip_config *config = phy->config;
321 void __iomem *base = phy->pad_regs;
322 u32 val;
323 int err;
324
325 err = clk_prepare_enable(phy->pad_clk);
326 if (err)
327 return err;
328
329 spin_lock(&utmip_pad_lock);
330
331 if (utmip_pad_count++ == 0) {
332 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
333 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
334
335 if (phy->soc_config->requires_extra_tuning_parameters) {
336 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
337 UTMIP_HSDISCON_LEVEL(~0) |
338 UTMIP_HSDISCON_LEVEL_MSB(~0));
339
340 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
341 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
342 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
343 }
344 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
345 }
346
347 if (phy->pad_wakeup) {
348 phy->pad_wakeup = false;
349 utmip_pad_count--;
350 }
351
352 spin_unlock(&utmip_pad_lock);
353
354 clk_disable_unprepare(phy->pad_clk);
355
356 return 0;
357}
358
359static int utmip_pad_power_off(struct tegra_usb_phy *phy)
360{
361 void __iomem *base = phy->pad_regs;
362 u32 val;
363 int ret;
364
365 ret = clk_prepare_enable(phy->pad_clk);
366 if (ret)
367 return ret;
368
369 spin_lock(&utmip_pad_lock);
370
371 if (!utmip_pad_count) {
372 dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
373 ret = -EINVAL;
374 goto ulock;
375 }
376
377 /*
378 * In accordance to TRM, OTG and Bias pad circuits could be turned off
379 * to save power if wake is enabled, but the VBUS-change detection
380 * method is board-specific and these circuits may need to be enabled
381 * to generate wakeup event, hence we will just keep them both enabled.
382 */
383 if (phy->wakeup_enabled) {
384 phy->pad_wakeup = true;
385 utmip_pad_count++;
386 }
387
388 if (--utmip_pad_count == 0) {
389 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
390 val |= UTMIP_OTGPD | UTMIP_BIASPD;
391 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
392 }
393ulock:
394 spin_unlock(&utmip_pad_lock);
395
396 clk_disable_unprepare(phy->pad_clk);
397
398 return ret;
399}
400
401static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
402{
403 u32 tmp;
404
405 return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
406 2000, 6000);
407}
408
409static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
410{
411 void __iomem *base = phy->regs;
412 u32 val;
413
414 /*
415 * The USB driver may have already initiated the phy clock
416 * disable so wait to see if the clock turns off and if not
417 * then proceed with gating the clock.
418 */
419 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
420 return;
421
422 if (phy->is_legacy_phy) {
423 val = readl_relaxed(base + USB_SUSP_CTRL);
424 val |= USB_SUSP_SET;
425 writel_relaxed(val, base + USB_SUSP_CTRL);
426
427 usleep_range(10, 100);
428
429 val = readl_relaxed(base + USB_SUSP_CTRL);
430 val &= ~USB_SUSP_SET;
431 writel_relaxed(val, base + USB_SUSP_CTRL);
432 } else {
433 set_phcd(phy, true);
434 }
435
436 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
437 dev_err(phy->u_phy.dev,
438 "Timeout waiting for PHY to stabilize on disable\n");
439}
440
441static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
442{
443 void __iomem *base = phy->regs;
444 u32 val;
445
446 /*
447 * The USB driver may have already initiated the phy clock
448 * enable so wait to see if the clock turns on and if not
449 * then proceed with ungating the clock.
450 */
451 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
452 USB_PHY_CLK_VALID) == 0)
453 return;
454
455 if (phy->is_legacy_phy) {
456 val = readl_relaxed(base + USB_SUSP_CTRL);
457 val |= USB_SUSP_CLR;
458 writel_relaxed(val, base + USB_SUSP_CTRL);
459
460 usleep_range(10, 100);
461
462 val = readl_relaxed(base + USB_SUSP_CTRL);
463 val &= ~USB_SUSP_CLR;
464 writel_relaxed(val, base + USB_SUSP_CTRL);
465 } else {
466 set_phcd(phy, false);
467 }
468
469 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
470 USB_PHY_CLK_VALID))
471 dev_err(phy->u_phy.dev,
472 "Timeout waiting for PHY to stabilize on enable\n");
473}
474
475static int utmi_phy_power_on(struct tegra_usb_phy *phy)
476{
477 struct tegra_utmip_config *config = phy->config;
478 void __iomem *base = phy->regs;
479 u32 val;
480 int err;
481
482 val = readl_relaxed(base + USB_SUSP_CTRL);
483 val |= UTMIP_RESET;
484 writel_relaxed(val, base + USB_SUSP_CTRL);
485
486 if (phy->is_legacy_phy) {
487 val = readl_relaxed(base + USB1_LEGACY_CTRL);
488 val |= USB1_NO_LEGACY_MODE;
489 writel_relaxed(val, base + USB1_LEGACY_CTRL);
490 }
491
492 val = readl_relaxed(base + UTMIP_TX_CFG0);
493 val |= UTMIP_FS_PREABMLE_J;
494 writel_relaxed(val, base + UTMIP_TX_CFG0);
495
496 val = readl_relaxed(base + UTMIP_HSRX_CFG0);
497 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
498 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
499 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
500 writel_relaxed(val, base + UTMIP_HSRX_CFG0);
501
502 val = readl_relaxed(base + UTMIP_HSRX_CFG1);
503 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
504 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
505 writel_relaxed(val, base + UTMIP_HSRX_CFG1);
506
507 val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
508 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
509 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
510 writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
511
512 val = readl_relaxed(base + UTMIP_MISC_CFG0);
513 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
514 writel_relaxed(val, base + UTMIP_MISC_CFG0);
515
516 if (!phy->soc_config->utmi_pll_config_in_car_module) {
517 val = readl_relaxed(base + UTMIP_MISC_CFG1);
518 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
519 UTMIP_PLLU_STABLE_COUNT(~0));
520 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
521 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
522 writel_relaxed(val, base + UTMIP_MISC_CFG1);
523
524 val = readl_relaxed(base + UTMIP_PLL_CFG1);
525 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
526 UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
527 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
528 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
529 writel_relaxed(val, base + UTMIP_PLL_CFG1);
530 }
531
532 val = readl_relaxed(base + USB_SUSP_CTRL);
533 val &= ~USB_WAKE_ON_RESUME_EN;
534 writel_relaxed(val, base + USB_SUSP_CTRL);
535
536 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
537 val = readl_relaxed(base + USB_SUSP_CTRL);
538 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
539 writel_relaxed(val, base + USB_SUSP_CTRL);
540
541 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
542 val &= ~VBUS_WAKEUP_WAKEUP_EN;
543 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
544
545 val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
546 val &= ~(A_VBUS_VLD_WAKEUP_EN | A_SESS_VLD_WAKEUP_EN);
547 val &= ~(B_SESS_VLD_WAKEUP_EN);
548 writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
549
550 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
551 val &= ~UTMIP_PD_CHRG;
552 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
553 } else {
554 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
555 val |= UTMIP_PD_CHRG;
556 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
557 }
558
559 err = utmip_pad_power_on(phy);
560 if (err)
561 return err;
562
563 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
564 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
565 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
566 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
567 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
568
569 if (!config->xcvr_setup_use_fuses) {
570 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
571 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
572 }
573 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
574 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
575
576 if (phy->soc_config->requires_extra_tuning_parameters) {
577 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
578 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
579 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
580 }
581 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
582
583 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
584 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
585 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
586 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
587 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
588
589 val = readl_relaxed(base + UTMIP_BIAS_CFG1);
590 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
591 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
592 writel_relaxed(val, base + UTMIP_BIAS_CFG1);
593
594 val = readl_relaxed(base + UTMIP_SPARE_CFG0);
595 if (config->xcvr_setup_use_fuses)
596 val |= FUSE_SETUP_SEL;
597 else
598 val &= ~FUSE_SETUP_SEL;
599 writel_relaxed(val, base + UTMIP_SPARE_CFG0);
600
601 if (!phy->is_legacy_phy) {
602 val = readl_relaxed(base + USB_SUSP_CTRL);
603 val |= UTMIP_PHY_ENABLE;
604 writel_relaxed(val, base + USB_SUSP_CTRL);
605 }
606
607 val = readl_relaxed(base + USB_SUSP_CTRL);
608 val &= ~UTMIP_RESET;
609 writel_relaxed(val, base + USB_SUSP_CTRL);
610
611 if (phy->is_legacy_phy) {
612 val = readl_relaxed(base + USB1_LEGACY_CTRL);
613 val &= ~USB1_VBUS_SENSE_CTL_MASK;
614 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
615 writel_relaxed(val, base + USB1_LEGACY_CTRL);
616
617 val = readl_relaxed(base + USB_SUSP_CTRL);
618 val &= ~USB_SUSP_SET;
619 writel_relaxed(val, base + USB_SUSP_CTRL);
620 }
621
622 utmi_phy_clk_enable(phy);
623
624 if (phy->soc_config->requires_usbmode_setup) {
625 val = readl_relaxed(base + USB_USBMODE);
626 val &= ~USB_USBMODE_MASK;
627 if (phy->mode == USB_DR_MODE_HOST)
628 val |= USB_USBMODE_HOST;
629 else
630 val |= USB_USBMODE_DEVICE;
631 writel_relaxed(val, base + USB_USBMODE);
632 }
633
634 if (!phy->is_legacy_phy)
635 set_pts(phy, 0);
636
637 return 0;
638}
639
640static int utmi_phy_power_off(struct tegra_usb_phy *phy)
641{
642 void __iomem *base = phy->regs;
643 u32 val;
644
645 /*
646 * Give hardware time to settle down after VBUS disconnection,
647 * otherwise PHY will immediately wake up from suspend.
648 */
649 if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST)
650 readl_relaxed_poll_timeout(base + USB_PHY_VBUS_WAKEUP_ID,
651 val, !(val & VBUS_WAKEUP_STS),
652 5000, 100000);
653
654 utmi_phy_clk_disable(phy);
655
656 /* PHY won't resume if reset is asserted */
657 if (!phy->wakeup_enabled) {
658 val = readl_relaxed(base + USB_SUSP_CTRL);
659 val |= UTMIP_RESET;
660 writel_relaxed(val, base + USB_SUSP_CTRL);
661 }
662
663 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
664 val |= UTMIP_PD_CHRG;
665 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
666
667 if (!phy->wakeup_enabled) {
668 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
669 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
670 UTMIP_FORCE_PDZI_POWERDOWN;
671 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
672 }
673
674 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
675 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
676 UTMIP_FORCE_PDDR_POWERDOWN;
677 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
678
679 if (phy->wakeup_enabled) {
680 val = readl_relaxed(base + USB_SUSP_CTRL);
681 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
682 val |= USB_WAKEUP_DEBOUNCE_COUNT(5);
683 val |= USB_WAKE_ON_RESUME_EN;
684 writel_relaxed(val, base + USB_SUSP_CTRL);
685
686 /*
687 * Ask VBUS sensor to generate wake event once cable is
688 * connected.
689 */
690 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
691 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
692 val |= VBUS_WAKEUP_WAKEUP_EN;
693 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
694
695 val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
696 val |= A_VBUS_VLD_WAKEUP_EN;
697 writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
698 }
699 }
700
701 return utmip_pad_power_off(phy);
702}
703
704static void utmi_phy_preresume(struct tegra_usb_phy *phy)
705{
706 void __iomem *base = phy->regs;
707 u32 val;
708
709 val = readl_relaxed(base + UTMIP_TX_CFG0);
710 val |= UTMIP_HS_DISCON_DISABLE;
711 writel_relaxed(val, base + UTMIP_TX_CFG0);
712}
713
714static void utmi_phy_postresume(struct tegra_usb_phy *phy)
715{
716 void __iomem *base = phy->regs;
717 u32 val;
718
719 val = readl_relaxed(base + UTMIP_TX_CFG0);
720 val &= ~UTMIP_HS_DISCON_DISABLE;
721 writel_relaxed(val, base + UTMIP_TX_CFG0);
722}
723
724static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
725 enum tegra_usb_phy_port_speed port_speed)
726{
727 void __iomem *base = phy->regs;
728 u32 val;
729
730 val = readl_relaxed(base + UTMIP_MISC_CFG0);
731 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
732 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
733 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
734 else
735 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
736 writel_relaxed(val, base + UTMIP_MISC_CFG0);
737 usleep_range(1, 10);
738
739 val = readl_relaxed(base + UTMIP_MISC_CFG0);
740 val |= UTMIP_DPDM_OBSERVE;
741 writel_relaxed(val, base + UTMIP_MISC_CFG0);
742 usleep_range(10, 100);
743}
744
745static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
746{
747 void __iomem *base = phy->regs;
748 u32 val;
749
750 val = readl_relaxed(base + UTMIP_MISC_CFG0);
751 val &= ~UTMIP_DPDM_OBSERVE;
752 writel_relaxed(val, base + UTMIP_MISC_CFG0);
753 usleep_range(10, 100);
754}
755
756static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
757{
758 void __iomem *base = phy->regs;
759 u32 val;
760 int err;
761
762 gpiod_set_value_cansleep(phy->reset_gpio, 1);
763
764 err = clk_prepare_enable(phy->clk);
765 if (err)
766 return err;
767
768 usleep_range(5000, 6000);
769
770 gpiod_set_value_cansleep(phy->reset_gpio, 0);
771
772 usleep_range(1000, 2000);
773
774 val = readl_relaxed(base + USB_SUSP_CTRL);
775 val |= UHSIC_RESET;
776 writel_relaxed(val, base + USB_SUSP_CTRL);
777
778 val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
779 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
780 writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
781
782 val = readl_relaxed(base + USB_SUSP_CTRL);
783 val |= ULPI_PHY_ENABLE;
784 writel_relaxed(val, base + USB_SUSP_CTRL);
785
786 val = 0;
787 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
788
789 val |= ULPI_DATA_TRIMMER_SEL(4);
790 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
791 val |= ULPI_DIR_TRIMMER_SEL(4);
792 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
793 usleep_range(10, 100);
794
795 val |= ULPI_DATA_TRIMMER_LOAD;
796 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
797 val |= ULPI_DIR_TRIMMER_LOAD;
798 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
799
800 /* Fix VbusInvalid due to floating VBUS */
801 err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
802 if (err) {
803 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
804 goto disable_clk;
805 }
806
807 err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
808 if (err) {
809 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
810 goto disable_clk;
811 }
812
813 val = readl_relaxed(base + USB_SUSP_CTRL);
814 val |= USB_SUSP_CLR;
815 writel_relaxed(val, base + USB_SUSP_CTRL);
816 usleep_range(100, 1000);
817
818 val = readl_relaxed(base + USB_SUSP_CTRL);
819 val &= ~USB_SUSP_CLR;
820 writel_relaxed(val, base + USB_SUSP_CTRL);
821
822 return 0;
823
824disable_clk:
825 clk_disable_unprepare(phy->clk);
826
827 return err;
828}
829
830static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
831{
832 gpiod_set_value_cansleep(phy->reset_gpio, 1);
833 usleep_range(5000, 6000);
834 clk_disable_unprepare(phy->clk);
835
836 /*
837 * Wakeup currently unimplemented for ULPI, thus PHY needs to be
838 * force-resumed.
839 */
840 if (WARN_ON_ONCE(phy->wakeup_enabled)) {
841 ulpi_phy_power_on(phy);
842 return -EOPNOTSUPP;
843 }
844
845 return 0;
846}
847
848static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
849{
850 int err;
851
852 if (phy->powered_on)
853 return 0;
854
855 if (phy->is_ulpi_phy)
856 err = ulpi_phy_power_on(phy);
857 else
858 err = utmi_phy_power_on(phy);
859 if (err)
860 return err;
861
862 phy->powered_on = true;
863
864 /* Let PHY settle down */
865 usleep_range(2000, 2500);
866
867 return 0;
868}
869
870static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
871{
872 int err;
873
874 if (!phy->powered_on)
875 return 0;
876
877 if (phy->is_ulpi_phy)
878 err = ulpi_phy_power_off(phy);
879 else
880 err = utmi_phy_power_off(phy);
881 if (err)
882 return err;
883
884 phy->powered_on = false;
885
886 return 0;
887}
888
889static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
890{
891 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
892
893 if (WARN_ON(!phy->freq))
894 return;
895
896 tegra_usb_phy_power_off(phy);
897
898 if (!phy->is_ulpi_phy)
899 utmip_pad_close(phy);
900
901 regulator_disable(phy->vbus);
902 clk_disable_unprepare(phy->pll_u);
903
904 phy->freq = NULL;
905}
906
907static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable)
908{
909 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
910
911 phy->wakeup_enabled = enable;
912
913 return 0;
914}
915
916static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
917{
918 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
919
920 if (WARN_ON(!phy->freq))
921 return -EINVAL;
922
923 if (suspend)
924 return tegra_usb_phy_power_off(phy);
925 else
926 return tegra_usb_phy_power_on(phy);
927}
928
929static int tegra_usb_phy_init(struct usb_phy *u_phy)
930{
931 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
932 unsigned long parent_rate;
933 unsigned int i;
934 int err;
935
936 if (WARN_ON(phy->freq))
937 return 0;
938
939 err = clk_prepare_enable(phy->pll_u);
940 if (err)
941 return err;
942
943 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
944 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
945 if (tegra_freq_table[i].freq == parent_rate) {
946 phy->freq = &tegra_freq_table[i];
947 break;
948 }
949 }
950 if (!phy->freq) {
951 dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
952 parent_rate);
953 err = -EINVAL;
954 goto disable_clk;
955 }
956
957 err = regulator_enable(phy->vbus);
958 if (err) {
959 dev_err(phy->u_phy.dev,
960 "Failed to enable USB VBUS regulator: %d\n", err);
961 goto disable_clk;
962 }
963
964 if (!phy->is_ulpi_phy) {
965 err = utmip_pad_open(phy);
966 if (err)
967 goto disable_vbus;
968 }
969
970 err = tegra_usb_phy_power_on(phy);
971 if (err)
972 goto close_phy;
973
974 return 0;
975
976close_phy:
977 if (!phy->is_ulpi_phy)
978 utmip_pad_close(phy);
979
980disable_vbus:
981 regulator_disable(phy->vbus);
982
983disable_clk:
984 clk_disable_unprepare(phy->pll_u);
985
986 phy->freq = NULL;
987
988 return err;
989}
990
991void tegra_usb_phy_preresume(struct usb_phy *u_phy)
992{
993 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
994
995 if (!phy->is_ulpi_phy)
996 utmi_phy_preresume(phy);
997}
998EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
999
1000void tegra_usb_phy_postresume(struct usb_phy *u_phy)
1001{
1002 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1003
1004 if (!phy->is_ulpi_phy)
1005 utmi_phy_postresume(phy);
1006}
1007EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
1008
1009void tegra_ehci_phy_restore_start(struct usb_phy *u_phy,
1010 enum tegra_usb_phy_port_speed port_speed)
1011{
1012 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1013
1014 if (!phy->is_ulpi_phy)
1015 utmi_phy_restore_start(phy, port_speed);
1016}
1017EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
1018
1019void tegra_ehci_phy_restore_end(struct usb_phy *u_phy)
1020{
1021 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1022
1023 if (!phy->is_ulpi_phy)
1024 utmi_phy_restore_end(phy);
1025}
1026EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
1027
1028static int read_utmi_param(struct platform_device *pdev, const char *param,
1029 u8 *dest)
1030{
1031 u32 value;
1032 int err;
1033
1034 err = of_property_read_u32(pdev->dev.of_node, param, &value);
1035 if (err)
1036 dev_err(&pdev->dev,
1037 "Failed to read USB UTMI parameter %s: %d\n",
1038 param, err);
1039 else
1040 *dest = value;
1041
1042 return err;
1043}
1044
1045static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
1046 struct platform_device *pdev)
1047{
1048 struct tegra_utmip_config *config;
1049 struct resource *res;
1050 int err;
1051
1052 tegra_phy->is_ulpi_phy = false;
1053
1054 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1055 if (!res) {
1056 dev_err(&pdev->dev, "Failed to get UTMI pad regs\n");
1057 return -ENXIO;
1058 }
1059
1060 /*
1061 * Note that UTMI pad registers are shared by all PHYs, therefore
1062 * devm_platform_ioremap_resource() can't be used here.
1063 */
1064 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
1065 resource_size(res));
1066 if (!tegra_phy->pad_regs) {
1067 dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
1068 return -ENOMEM;
1069 }
1070
1071 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
1072 GFP_KERNEL);
1073 if (!tegra_phy->config)
1074 return -ENOMEM;
1075
1076 config = tegra_phy->config;
1077
1078 err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
1079 &config->hssync_start_delay);
1080 if (err)
1081 return err;
1082
1083 err = read_utmi_param(pdev, "nvidia,elastic-limit",
1084 &config->elastic_limit);
1085 if (err)
1086 return err;
1087
1088 err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
1089 &config->idle_wait_delay);
1090 if (err)
1091 return err;
1092
1093 err = read_utmi_param(pdev, "nvidia,term-range-adj",
1094 &config->term_range_adj);
1095 if (err)
1096 return err;
1097
1098 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
1099 &config->xcvr_lsfslew);
1100 if (err)
1101 return err;
1102
1103 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
1104 &config->xcvr_lsrslew);
1105 if (err)
1106 return err;
1107
1108 if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
1109 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1110 &config->xcvr_hsslew);
1111 if (err)
1112 return err;
1113
1114 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1115 &config->hssquelch_level);
1116 if (err)
1117 return err;
1118
1119 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1120 &config->hsdiscon_level);
1121 if (err)
1122 return err;
1123 }
1124
1125 config->xcvr_setup_use_fuses = of_property_read_bool(
1126 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
1127
1128 if (!config->xcvr_setup_use_fuses) {
1129 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1130 &config->xcvr_setup);
1131 if (err)
1132 return err;
1133 }
1134
1135 return 0;
1136}
1137
1138static const struct tegra_phy_soc_config tegra20_soc_config = {
1139 .utmi_pll_config_in_car_module = false,
1140 .has_hostpc = false,
1141 .requires_usbmode_setup = false,
1142 .requires_extra_tuning_parameters = false,
1143};
1144
1145static const struct tegra_phy_soc_config tegra30_soc_config = {
1146 .utmi_pll_config_in_car_module = true,
1147 .has_hostpc = true,
1148 .requires_usbmode_setup = true,
1149 .requires_extra_tuning_parameters = true,
1150};
1151
1152static const struct of_device_id tegra_usb_phy_id_table[] = {
1153 { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
1154 { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
1155 { },
1156};
1157MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
1158
1159static int tegra_usb_phy_probe(struct platform_device *pdev)
1160{
1161 struct device_node *np = pdev->dev.of_node;
1162 struct tegra_usb_phy *tegra_phy;
1163 enum usb_phy_interface phy_type;
1164 struct reset_control *reset;
1165 struct gpio_desc *gpiod;
1166 struct resource *res;
1167 struct usb_phy *phy;
1168 int err;
1169
1170 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
1171 if (!tegra_phy)
1172 return -ENOMEM;
1173
1174 tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
1175
1176 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1177 if (!res) {
1178 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1179 return -ENXIO;
1180 }
1181
1182 /*
1183 * Note that PHY and USB controller are using shared registers,
1184 * therefore devm_platform_ioremap_resource() can't be used here.
1185 */
1186 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1187 resource_size(res));
1188 if (!tegra_phy->regs) {
1189 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1190 return -ENOMEM;
1191 }
1192
1193 tegra_phy->is_legacy_phy =
1194 of_property_read_bool(np, "nvidia,has-legacy-mode");
1195
1196 if (of_find_property(np, "dr_mode", NULL))
1197 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1198 else
1199 tegra_phy->mode = USB_DR_MODE_HOST;
1200
1201 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1202 dev_err(&pdev->dev, "dr_mode is invalid\n");
1203 return -EINVAL;
1204 }
1205
1206 /* On some boards, the VBUS regulator doesn't need to be controlled */
1207 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1208 if (IS_ERR(tegra_phy->vbus))
1209 return PTR_ERR(tegra_phy->vbus);
1210
1211 tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
1212 err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
1213 if (err) {
1214 dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
1215 return err;
1216 }
1217
1218 phy_type = of_usb_get_phy_mode(np);
1219 switch (phy_type) {
1220 case USBPHY_INTERFACE_MODE_UTMI:
1221 err = utmi_phy_probe(tegra_phy, pdev);
1222 if (err)
1223 return err;
1224
1225 tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
1226 err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
1227 if (err) {
1228 dev_err(&pdev->dev,
1229 "Failed to get UTMIP pad clock: %d\n", err);
1230 return err;
1231 }
1232
1233 reset = devm_reset_control_get_optional_shared(&pdev->dev,
1234 "utmi-pads");
1235 err = PTR_ERR_OR_ZERO(reset);
1236 if (err) {
1237 dev_err(&pdev->dev,
1238 "Failed to get UTMI-pads reset: %d\n", err);
1239 return err;
1240 }
1241 tegra_phy->pad_rst = reset;
1242 break;
1243
1244 case USBPHY_INTERFACE_MODE_ULPI:
1245 tegra_phy->is_ulpi_phy = true;
1246
1247 tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
1248 err = PTR_ERR_OR_ZERO(tegra_phy->clk);
1249 if (err) {
1250 dev_err(&pdev->dev,
1251 "Failed to get ULPI clock: %d\n", err);
1252 return err;
1253 }
1254
1255 gpiod = devm_gpiod_get_from_of_node(&pdev->dev, np,
1256 "nvidia,phy-reset-gpio",
1257 0, GPIOD_OUT_HIGH,
1258 "ulpi_phy_reset_b");
1259 err = PTR_ERR_OR_ZERO(gpiod);
1260 if (err) {
1261 dev_err(&pdev->dev,
1262 "Request failed for reset GPIO: %d\n", err);
1263 return err;
1264 }
1265 tegra_phy->reset_gpio = gpiod;
1266
1267 phy = devm_otg_ulpi_create(&pdev->dev,
1268 &ulpi_viewport_access_ops, 0);
1269 if (!phy) {
1270 dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
1271 return -ENOMEM;
1272 }
1273
1274 tegra_phy->ulpi = phy;
1275 tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
1276 break;
1277
1278 default:
1279 dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1280 phy_type);
1281 return -EINVAL;
1282 }
1283
1284 tegra_phy->u_phy.dev = &pdev->dev;
1285 tegra_phy->u_phy.init = tegra_usb_phy_init;
1286 tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
1287 tegra_phy->u_phy.set_wakeup = tegra_usb_phy_set_wakeup;
1288 tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
1289
1290 platform_set_drvdata(pdev, tegra_phy);
1291
1292 return usb_add_phy_dev(&tegra_phy->u_phy);
1293}
1294
1295static int tegra_usb_phy_remove(struct platform_device *pdev)
1296{
1297 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1298
1299 usb_remove_phy(&tegra_phy->u_phy);
1300
1301 return 0;
1302}
1303
1304static struct platform_driver tegra_usb_phy_driver = {
1305 .probe = tegra_usb_phy_probe,
1306 .remove = tegra_usb_phy_remove,
1307 .driver = {
1308 .name = "tegra-phy",
1309 .of_match_table = tegra_usb_phy_id_table,
1310 },
1311};
1312module_platform_driver(tegra_usb_phy_driver);
1313
1314MODULE_DESCRIPTION("Tegra USB PHY driver");
1315MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (C) 2013 NVIDIA Corporation
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 * Benoit Goby <benoit@android.com>
9 * Venu Byravarasu <vbyravarasu@nvidia.com>
10 */
11
12#include <linux/resource.h>
13#include <linux/delay.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/export.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/iopoll.h>
20#include <linux/gpio.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_gpio.h>
24#include <linux/usb/otg.h>
25#include <linux/usb/ulpi.h>
26#include <linux/usb/of.h>
27#include <linux/usb/ehci_def.h>
28#include <linux/usb/tegra_usb_phy.h>
29#include <linux/regulator/consumer.h>
30
31#define ULPI_VIEWPORT 0x170
32
33/* PORTSC PTS/PHCD bits, Tegra20 only */
34#define TEGRA_USB_PORTSC1 0x184
35#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
36#define TEGRA_USB_PORTSC1_PHCD (1 << 23)
37
38/* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
39#define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
40#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
41#define TEGRA_USB_HOSTPC1_DEVLC_PHCD (1 << 22)
42
43/* Bits of PORTSC1, which will get cleared by writing 1 into them */
44#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
45
46#define USB_SUSP_CTRL 0x400
47#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
48#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
49#define USB_SUSP_CLR (1 << 5)
50#define USB_PHY_CLK_VALID (1 << 7)
51#define UTMIP_RESET (1 << 11)
52#define UHSIC_RESET (1 << 11)
53#define UTMIP_PHY_ENABLE (1 << 12)
54#define ULPI_PHY_ENABLE (1 << 13)
55#define USB_SUSP_SET (1 << 14)
56#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
57
58#define USB1_LEGACY_CTRL 0x410
59#define USB1_NO_LEGACY_MODE (1 << 0)
60#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
61#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
62#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
63 (1 << 1)
64#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
65#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
66
67#define ULPI_TIMING_CTRL_0 0x424
68#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
69#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
70
71#define ULPI_TIMING_CTRL_1 0x428
72#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
73#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
74#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
75#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
76#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
77#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
78
79#define UTMIP_PLL_CFG1 0x804
80#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
81#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
82
83#define UTMIP_XCVR_CFG0 0x808
84#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
85#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
86#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
87#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
88#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
89#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
90#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
91#define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
92#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
93#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
94
95#define UTMIP_BIAS_CFG0 0x80c
96#define UTMIP_OTGPD (1 << 11)
97#define UTMIP_BIASPD (1 << 10)
98#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
99#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
100#define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
101
102#define UTMIP_HSRX_CFG0 0x810
103#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
104#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
105
106#define UTMIP_HSRX_CFG1 0x814
107#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
108
109#define UTMIP_TX_CFG0 0x820
110#define UTMIP_FS_PREABMLE_J (1 << 19)
111#define UTMIP_HS_DISCON_DISABLE (1 << 8)
112
113#define UTMIP_MISC_CFG0 0x824
114#define UTMIP_DPDM_OBSERVE (1 << 26)
115#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
116#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
117#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
118#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
119#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
120#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
121
122#define UTMIP_MISC_CFG1 0x828
123#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
124#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
125
126#define UTMIP_DEBOUNCE_CFG0 0x82c
127#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
128
129#define UTMIP_BAT_CHRG_CFG0 0x830
130#define UTMIP_PD_CHRG (1 << 0)
131
132#define UTMIP_SPARE_CFG0 0x834
133#define FUSE_SETUP_SEL (1 << 3)
134
135#define UTMIP_XCVR_CFG1 0x838
136#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
137#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
138#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
139#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
140
141#define UTMIP_BIAS_CFG1 0x83c
142#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
143
144/* For Tegra30 and above only, the address is different in Tegra20 */
145#define USB_USBMODE 0x1f8
146#define USB_USBMODE_MASK (3 << 0)
147#define USB_USBMODE_HOST (3 << 0)
148#define USB_USBMODE_DEVICE (2 << 0)
149
150static DEFINE_SPINLOCK(utmip_pad_lock);
151static int utmip_pad_count;
152
153struct tegra_xtal_freq {
154 int freq;
155 u8 enable_delay;
156 u8 stable_count;
157 u8 active_delay;
158 u8 xtal_freq_count;
159 u16 debounce;
160};
161
162static const struct tegra_xtal_freq tegra_freq_table[] = {
163 {
164 .freq = 12000000,
165 .enable_delay = 0x02,
166 .stable_count = 0x2F,
167 .active_delay = 0x04,
168 .xtal_freq_count = 0x76,
169 .debounce = 0x7530,
170 },
171 {
172 .freq = 13000000,
173 .enable_delay = 0x02,
174 .stable_count = 0x33,
175 .active_delay = 0x05,
176 .xtal_freq_count = 0x7F,
177 .debounce = 0x7EF4,
178 },
179 {
180 .freq = 19200000,
181 .enable_delay = 0x03,
182 .stable_count = 0x4B,
183 .active_delay = 0x06,
184 .xtal_freq_count = 0xBB,
185 .debounce = 0xBB80,
186 },
187 {
188 .freq = 26000000,
189 .enable_delay = 0x04,
190 .stable_count = 0x66,
191 .active_delay = 0x09,
192 .xtal_freq_count = 0xFE,
193 .debounce = 0xFDE8,
194 },
195};
196
197static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
198{
199 void __iomem *base = phy->regs;
200 unsigned long val;
201
202 if (phy->soc_config->has_hostpc) {
203 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
204 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
205 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
206 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
207 } else {
208 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
209 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
210 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
211 writel(val, base + TEGRA_USB_PORTSC1);
212 }
213}
214
215static void set_phcd(struct tegra_usb_phy *phy, bool enable)
216{
217 void __iomem *base = phy->regs;
218 unsigned long val;
219
220 if (phy->soc_config->has_hostpc) {
221 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
222 if (enable)
223 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
224 else
225 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
226 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
227 } else {
228 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
229 if (enable)
230 val |= TEGRA_USB_PORTSC1_PHCD;
231 else
232 val &= ~TEGRA_USB_PORTSC1_PHCD;
233 writel(val, base + TEGRA_USB_PORTSC1);
234 }
235}
236
237static int utmip_pad_open(struct tegra_usb_phy *phy)
238{
239 int ret;
240
241 phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
242 if (IS_ERR(phy->pad_clk)) {
243 ret = PTR_ERR(phy->pad_clk);
244 dev_err(phy->u_phy.dev,
245 "Failed to get UTMIP pad clock: %d\n", ret);
246 return ret;
247 }
248
249 phy->pad_rst = devm_reset_control_get_optional_shared(
250 phy->u_phy.dev, "utmi-pads");
251 if (IS_ERR(phy->pad_rst)) {
252 ret = PTR_ERR(phy->pad_rst);
253 dev_err(phy->u_phy.dev,
254 "Failed to get UTMI-pads reset: %d\n", ret);
255 return ret;
256 }
257
258 ret = clk_prepare_enable(phy->pad_clk);
259 if (ret) {
260 dev_err(phy->u_phy.dev,
261 "Failed to enable UTMI-pads clock: %d\n", ret);
262 return ret;
263 }
264
265 spin_lock(&utmip_pad_lock);
266
267 ret = reset_control_deassert(phy->pad_rst);
268 if (ret) {
269 dev_err(phy->u_phy.dev,
270 "Failed to initialize UTMI-pads reset: %d\n", ret);
271 goto unlock;
272 }
273
274 ret = reset_control_assert(phy->pad_rst);
275 if (ret) {
276 dev_err(phy->u_phy.dev,
277 "Failed to assert UTMI-pads reset: %d\n", ret);
278 goto unlock;
279 }
280
281 udelay(1);
282
283 ret = reset_control_deassert(phy->pad_rst);
284 if (ret)
285 dev_err(phy->u_phy.dev,
286 "Failed to deassert UTMI-pads reset: %d\n", ret);
287unlock:
288 spin_unlock(&utmip_pad_lock);
289
290 clk_disable_unprepare(phy->pad_clk);
291
292 return ret;
293}
294
295static int utmip_pad_close(struct tegra_usb_phy *phy)
296{
297 int ret;
298
299 ret = clk_prepare_enable(phy->pad_clk);
300 if (ret) {
301 dev_err(phy->u_phy.dev,
302 "Failed to enable UTMI-pads clock: %d\n", ret);
303 return ret;
304 }
305
306 ret = reset_control_assert(phy->pad_rst);
307 if (ret)
308 dev_err(phy->u_phy.dev,
309 "Failed to assert UTMI-pads reset: %d\n", ret);
310
311 udelay(1);
312
313 clk_disable_unprepare(phy->pad_clk);
314
315 return ret;
316}
317
318static void utmip_pad_power_on(struct tegra_usb_phy *phy)
319{
320 unsigned long val, flags;
321 void __iomem *base = phy->pad_regs;
322 struct tegra_utmip_config *config = phy->config;
323
324 clk_prepare_enable(phy->pad_clk);
325
326 spin_lock_irqsave(&utmip_pad_lock, flags);
327
328 if (utmip_pad_count++ == 0) {
329 val = readl(base + UTMIP_BIAS_CFG0);
330 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
331
332 if (phy->soc_config->requires_extra_tuning_parameters) {
333 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
334 UTMIP_HSDISCON_LEVEL(~0) |
335 UTMIP_HSDISCON_LEVEL_MSB(~0));
336
337 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
338 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
339 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
340 }
341 writel(val, base + UTMIP_BIAS_CFG0);
342 }
343
344 spin_unlock_irqrestore(&utmip_pad_lock, flags);
345
346 clk_disable_unprepare(phy->pad_clk);
347}
348
349static int utmip_pad_power_off(struct tegra_usb_phy *phy)
350{
351 unsigned long val, flags;
352 void __iomem *base = phy->pad_regs;
353
354 if (!utmip_pad_count) {
355 dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
356 return -EINVAL;
357 }
358
359 clk_prepare_enable(phy->pad_clk);
360
361 spin_lock_irqsave(&utmip_pad_lock, flags);
362
363 if (--utmip_pad_count == 0) {
364 val = readl(base + UTMIP_BIAS_CFG0);
365 val |= UTMIP_OTGPD | UTMIP_BIASPD;
366 writel(val, base + UTMIP_BIAS_CFG0);
367 }
368
369 spin_unlock_irqrestore(&utmip_pad_lock, flags);
370
371 clk_disable_unprepare(phy->pad_clk);
372
373 return 0;
374}
375
376static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
377{
378 u32 tmp;
379
380 return readl_poll_timeout(reg, tmp, (tmp & mask) == result,
381 2000, 6000);
382}
383
384static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
385{
386 unsigned long val;
387 void __iomem *base = phy->regs;
388
389 /*
390 * The USB driver may have already initiated the phy clock
391 * disable so wait to see if the clock turns off and if not
392 * then proceed with gating the clock.
393 */
394 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
395 return;
396
397 if (phy->is_legacy_phy) {
398 val = readl(base + USB_SUSP_CTRL);
399 val |= USB_SUSP_SET;
400 writel(val, base + USB_SUSP_CTRL);
401
402 udelay(10);
403
404 val = readl(base + USB_SUSP_CTRL);
405 val &= ~USB_SUSP_SET;
406 writel(val, base + USB_SUSP_CTRL);
407 } else
408 set_phcd(phy, true);
409
410 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
411 dev_err(phy->u_phy.dev,
412 "Timeout waiting for PHY to stabilize on disable\n");
413}
414
415static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
416{
417 unsigned long val;
418 void __iomem *base = phy->regs;
419
420 /*
421 * The USB driver may have already initiated the phy clock
422 * enable so wait to see if the clock turns on and if not
423 * then proceed with ungating the clock.
424 */
425 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
426 USB_PHY_CLK_VALID) == 0)
427 return;
428
429 if (phy->is_legacy_phy) {
430 val = readl(base + USB_SUSP_CTRL);
431 val |= USB_SUSP_CLR;
432 writel(val, base + USB_SUSP_CTRL);
433
434 udelay(10);
435
436 val = readl(base + USB_SUSP_CTRL);
437 val &= ~USB_SUSP_CLR;
438 writel(val, base + USB_SUSP_CTRL);
439 } else
440 set_phcd(phy, false);
441
442 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
443 USB_PHY_CLK_VALID))
444 dev_err(phy->u_phy.dev,
445 "Timeout waiting for PHY to stabilize on enable\n");
446}
447
448static int utmi_phy_power_on(struct tegra_usb_phy *phy)
449{
450 unsigned long val;
451 void __iomem *base = phy->regs;
452 struct tegra_utmip_config *config = phy->config;
453
454 val = readl(base + USB_SUSP_CTRL);
455 val |= UTMIP_RESET;
456 writel(val, base + USB_SUSP_CTRL);
457
458 if (phy->is_legacy_phy) {
459 val = readl(base + USB1_LEGACY_CTRL);
460 val |= USB1_NO_LEGACY_MODE;
461 writel(val, base + USB1_LEGACY_CTRL);
462 }
463
464 val = readl(base + UTMIP_TX_CFG0);
465 val |= UTMIP_FS_PREABMLE_J;
466 writel(val, base + UTMIP_TX_CFG0);
467
468 val = readl(base + UTMIP_HSRX_CFG0);
469 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
470 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
471 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
472 writel(val, base + UTMIP_HSRX_CFG0);
473
474 val = readl(base + UTMIP_HSRX_CFG1);
475 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
476 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
477 writel(val, base + UTMIP_HSRX_CFG1);
478
479 val = readl(base + UTMIP_DEBOUNCE_CFG0);
480 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
481 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
482 writel(val, base + UTMIP_DEBOUNCE_CFG0);
483
484 val = readl(base + UTMIP_MISC_CFG0);
485 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
486 writel(val, base + UTMIP_MISC_CFG0);
487
488 if (!phy->soc_config->utmi_pll_config_in_car_module) {
489 val = readl(base + UTMIP_MISC_CFG1);
490 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
491 UTMIP_PLLU_STABLE_COUNT(~0));
492 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
493 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
494 writel(val, base + UTMIP_MISC_CFG1);
495
496 val = readl(base + UTMIP_PLL_CFG1);
497 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
498 UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
499 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
500 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
501 writel(val, base + UTMIP_PLL_CFG1);
502 }
503
504 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
505 val = readl(base + USB_SUSP_CTRL);
506 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
507 writel(val, base + USB_SUSP_CTRL);
508
509 val = readl(base + UTMIP_BAT_CHRG_CFG0);
510 val &= ~UTMIP_PD_CHRG;
511 writel(val, base + UTMIP_BAT_CHRG_CFG0);
512 } else {
513 val = readl(base + UTMIP_BAT_CHRG_CFG0);
514 val |= UTMIP_PD_CHRG;
515 writel(val, base + UTMIP_BAT_CHRG_CFG0);
516 }
517
518 utmip_pad_power_on(phy);
519
520 val = readl(base + UTMIP_XCVR_CFG0);
521 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
522 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
523 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
524 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
525
526 if (!config->xcvr_setup_use_fuses) {
527 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
528 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
529 }
530 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
531 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
532
533 if (phy->soc_config->requires_extra_tuning_parameters) {
534 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
535 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
536 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
537 }
538 writel(val, base + UTMIP_XCVR_CFG0);
539
540 val = readl(base + UTMIP_XCVR_CFG1);
541 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
542 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
543 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
544 writel(val, base + UTMIP_XCVR_CFG1);
545
546 val = readl(base + UTMIP_BIAS_CFG1);
547 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
548 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
549 writel(val, base + UTMIP_BIAS_CFG1);
550
551 val = readl(base + UTMIP_SPARE_CFG0);
552 if (config->xcvr_setup_use_fuses)
553 val |= FUSE_SETUP_SEL;
554 else
555 val &= ~FUSE_SETUP_SEL;
556 writel(val, base + UTMIP_SPARE_CFG0);
557
558 if (!phy->is_legacy_phy) {
559 val = readl(base + USB_SUSP_CTRL);
560 val |= UTMIP_PHY_ENABLE;
561 writel(val, base + USB_SUSP_CTRL);
562 }
563
564 val = readl(base + USB_SUSP_CTRL);
565 val &= ~UTMIP_RESET;
566 writel(val, base + USB_SUSP_CTRL);
567
568 if (phy->is_legacy_phy) {
569 val = readl(base + USB1_LEGACY_CTRL);
570 val &= ~USB1_VBUS_SENSE_CTL_MASK;
571 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
572 writel(val, base + USB1_LEGACY_CTRL);
573
574 val = readl(base + USB_SUSP_CTRL);
575 val &= ~USB_SUSP_SET;
576 writel(val, base + USB_SUSP_CTRL);
577 }
578
579 utmi_phy_clk_enable(phy);
580
581 if (phy->soc_config->requires_usbmode_setup) {
582 val = readl(base + USB_USBMODE);
583 val &= ~USB_USBMODE_MASK;
584 if (phy->mode == USB_DR_MODE_HOST)
585 val |= USB_USBMODE_HOST;
586 else
587 val |= USB_USBMODE_DEVICE;
588 writel(val, base + USB_USBMODE);
589 }
590
591 if (!phy->is_legacy_phy)
592 set_pts(phy, 0);
593
594 return 0;
595}
596
597static int utmi_phy_power_off(struct tegra_usb_phy *phy)
598{
599 unsigned long val;
600 void __iomem *base = phy->regs;
601
602 utmi_phy_clk_disable(phy);
603
604 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
605 val = readl(base + USB_SUSP_CTRL);
606 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
607 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
608 writel(val, base + USB_SUSP_CTRL);
609 }
610
611 val = readl(base + USB_SUSP_CTRL);
612 val |= UTMIP_RESET;
613 writel(val, base + USB_SUSP_CTRL);
614
615 val = readl(base + UTMIP_BAT_CHRG_CFG0);
616 val |= UTMIP_PD_CHRG;
617 writel(val, base + UTMIP_BAT_CHRG_CFG0);
618
619 val = readl(base + UTMIP_XCVR_CFG0);
620 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
621 UTMIP_FORCE_PDZI_POWERDOWN;
622 writel(val, base + UTMIP_XCVR_CFG0);
623
624 val = readl(base + UTMIP_XCVR_CFG1);
625 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
626 UTMIP_FORCE_PDDR_POWERDOWN;
627 writel(val, base + UTMIP_XCVR_CFG1);
628
629 return utmip_pad_power_off(phy);
630}
631
632static void utmi_phy_preresume(struct tegra_usb_phy *phy)
633{
634 unsigned long val;
635 void __iomem *base = phy->regs;
636
637 val = readl(base + UTMIP_TX_CFG0);
638 val |= UTMIP_HS_DISCON_DISABLE;
639 writel(val, base + UTMIP_TX_CFG0);
640}
641
642static void utmi_phy_postresume(struct tegra_usb_phy *phy)
643{
644 unsigned long val;
645 void __iomem *base = phy->regs;
646
647 val = readl(base + UTMIP_TX_CFG0);
648 val &= ~UTMIP_HS_DISCON_DISABLE;
649 writel(val, base + UTMIP_TX_CFG0);
650}
651
652static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
653 enum tegra_usb_phy_port_speed port_speed)
654{
655 unsigned long val;
656 void __iomem *base = phy->regs;
657
658 val = readl(base + UTMIP_MISC_CFG0);
659 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
660 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
661 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
662 else
663 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
664 writel(val, base + UTMIP_MISC_CFG0);
665 udelay(1);
666
667 val = readl(base + UTMIP_MISC_CFG0);
668 val |= UTMIP_DPDM_OBSERVE;
669 writel(val, base + UTMIP_MISC_CFG0);
670 udelay(10);
671}
672
673static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
674{
675 unsigned long val;
676 void __iomem *base = phy->regs;
677
678 val = readl(base + UTMIP_MISC_CFG0);
679 val &= ~UTMIP_DPDM_OBSERVE;
680 writel(val, base + UTMIP_MISC_CFG0);
681 udelay(10);
682}
683
684static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
685{
686 int ret;
687 unsigned long val;
688 void __iomem *base = phy->regs;
689
690 ret = gpio_direction_output(phy->reset_gpio, 0);
691 if (ret < 0) {
692 dev_err(phy->u_phy.dev, "GPIO %d not set to 0: %d\n",
693 phy->reset_gpio, ret);
694 return ret;
695 }
696 msleep(5);
697 ret = gpio_direction_output(phy->reset_gpio, 1);
698 if (ret < 0) {
699 dev_err(phy->u_phy.dev, "GPIO %d not set to 1: %d\n",
700 phy->reset_gpio, ret);
701 return ret;
702 }
703
704 clk_prepare_enable(phy->clk);
705 msleep(1);
706
707 val = readl(base + USB_SUSP_CTRL);
708 val |= UHSIC_RESET;
709 writel(val, base + USB_SUSP_CTRL);
710
711 val = readl(base + ULPI_TIMING_CTRL_0);
712 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
713 writel(val, base + ULPI_TIMING_CTRL_0);
714
715 val = readl(base + USB_SUSP_CTRL);
716 val |= ULPI_PHY_ENABLE;
717 writel(val, base + USB_SUSP_CTRL);
718
719 val = 0;
720 writel(val, base + ULPI_TIMING_CTRL_1);
721
722 val |= ULPI_DATA_TRIMMER_SEL(4);
723 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
724 val |= ULPI_DIR_TRIMMER_SEL(4);
725 writel(val, base + ULPI_TIMING_CTRL_1);
726 udelay(10);
727
728 val |= ULPI_DATA_TRIMMER_LOAD;
729 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
730 val |= ULPI_DIR_TRIMMER_LOAD;
731 writel(val, base + ULPI_TIMING_CTRL_1);
732
733 /* Fix VbusInvalid due to floating VBUS */
734 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
735 if (ret) {
736 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", ret);
737 return ret;
738 }
739
740 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
741 if (ret) {
742 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", ret);
743 return ret;
744 }
745
746 val = readl(base + USB_SUSP_CTRL);
747 val |= USB_SUSP_CLR;
748 writel(val, base + USB_SUSP_CTRL);
749 udelay(100);
750
751 val = readl(base + USB_SUSP_CTRL);
752 val &= ~USB_SUSP_CLR;
753 writel(val, base + USB_SUSP_CTRL);
754
755 return 0;
756}
757
758static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
759{
760 clk_disable(phy->clk);
761 return gpio_direction_output(phy->reset_gpio, 0);
762}
763
764static void tegra_usb_phy_close(struct tegra_usb_phy *phy)
765{
766 if (!IS_ERR(phy->vbus))
767 regulator_disable(phy->vbus);
768
769 if (!phy->is_ulpi_phy)
770 utmip_pad_close(phy);
771
772 clk_disable_unprepare(phy->pll_u);
773}
774
775static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
776{
777 if (phy->is_ulpi_phy)
778 return ulpi_phy_power_on(phy);
779 else
780 return utmi_phy_power_on(phy);
781}
782
783static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
784{
785 if (phy->is_ulpi_phy)
786 return ulpi_phy_power_off(phy);
787 else
788 return utmi_phy_power_off(phy);
789}
790
791static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
792{
793 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
794 if (suspend)
795 return tegra_usb_phy_power_off(phy);
796 else
797 return tegra_usb_phy_power_on(phy);
798}
799
800static int ulpi_open(struct tegra_usb_phy *phy)
801{
802 int err;
803
804 phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
805 if (IS_ERR(phy->clk)) {
806 err = PTR_ERR(phy->clk);
807 dev_err(phy->u_phy.dev, "Failed to get ULPI clock: %d\n", err);
808 return err;
809 }
810
811 err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
812 "ulpi_phy_reset_b");
813 if (err < 0) {
814 dev_err(phy->u_phy.dev, "Request failed for GPIO %d: %d\n",
815 phy->reset_gpio, err);
816 return err;
817 }
818
819 err = gpio_direction_output(phy->reset_gpio, 0);
820 if (err < 0) {
821 dev_err(phy->u_phy.dev,
822 "GPIO %d direction not set to output: %d\n",
823 phy->reset_gpio, err);
824 return err;
825 }
826
827 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
828 if (!phy->ulpi) {
829 dev_err(phy->u_phy.dev, "Failed to create ULPI OTG\n");
830 err = -ENOMEM;
831 return err;
832 }
833
834 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
835 return 0;
836}
837
838static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
839{
840 unsigned long parent_rate;
841 int i;
842 int err;
843
844 phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
845 if (IS_ERR(phy->pll_u)) {
846 err = PTR_ERR(phy->pll_u);
847 dev_err(phy->u_phy.dev,
848 "Failed to get pll_u clock: %d\n", err);
849 return err;
850 }
851
852 err = clk_prepare_enable(phy->pll_u);
853 if (err)
854 return err;
855
856 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
857 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
858 if (tegra_freq_table[i].freq == parent_rate) {
859 phy->freq = &tegra_freq_table[i];
860 break;
861 }
862 }
863 if (!phy->freq) {
864 dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
865 parent_rate);
866 err = -EINVAL;
867 goto fail;
868 }
869
870 if (!IS_ERR(phy->vbus)) {
871 err = regulator_enable(phy->vbus);
872 if (err) {
873 dev_err(phy->u_phy.dev,
874 "Failed to enable USB VBUS regulator: %d\n",
875 err);
876 goto fail;
877 }
878 }
879
880 if (phy->is_ulpi_phy)
881 err = ulpi_open(phy);
882 else
883 err = utmip_pad_open(phy);
884 if (err < 0)
885 goto fail;
886
887 return 0;
888
889fail:
890 clk_disable_unprepare(phy->pll_u);
891 return err;
892}
893
894void tegra_usb_phy_preresume(struct usb_phy *x)
895{
896 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
897
898 if (!phy->is_ulpi_phy)
899 utmi_phy_preresume(phy);
900}
901EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
902
903void tegra_usb_phy_postresume(struct usb_phy *x)
904{
905 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
906
907 if (!phy->is_ulpi_phy)
908 utmi_phy_postresume(phy);
909}
910EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
911
912void tegra_ehci_phy_restore_start(struct usb_phy *x,
913 enum tegra_usb_phy_port_speed port_speed)
914{
915 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
916
917 if (!phy->is_ulpi_phy)
918 utmi_phy_restore_start(phy, port_speed);
919}
920EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
921
922void tegra_ehci_phy_restore_end(struct usb_phy *x)
923{
924 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
925
926 if (!phy->is_ulpi_phy)
927 utmi_phy_restore_end(phy);
928}
929EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
930
931static int read_utmi_param(struct platform_device *pdev, const char *param,
932 u8 *dest)
933{
934 u32 value;
935 int err = of_property_read_u32(pdev->dev.of_node, param, &value);
936 *dest = (u8)value;
937 if (err < 0)
938 dev_err(&pdev->dev,
939 "Failed to read USB UTMI parameter %s: %d\n",
940 param, err);
941 return err;
942}
943
944static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
945 struct platform_device *pdev)
946{
947 struct resource *res;
948 int err;
949 struct tegra_utmip_config *config;
950
951 tegra_phy->is_ulpi_phy = false;
952
953 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
954 if (!res) {
955 dev_err(&pdev->dev, "Failed to get UTMI pad regs\n");
956 return -ENXIO;
957 }
958
959 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
960 resource_size(res));
961 if (!tegra_phy->pad_regs) {
962 dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
963 return -ENOMEM;
964 }
965
966 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
967 GFP_KERNEL);
968 if (!tegra_phy->config)
969 return -ENOMEM;
970
971 config = tegra_phy->config;
972
973 err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
974 &config->hssync_start_delay);
975 if (err < 0)
976 return err;
977
978 err = read_utmi_param(pdev, "nvidia,elastic-limit",
979 &config->elastic_limit);
980 if (err < 0)
981 return err;
982
983 err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
984 &config->idle_wait_delay);
985 if (err < 0)
986 return err;
987
988 err = read_utmi_param(pdev, "nvidia,term-range-adj",
989 &config->term_range_adj);
990 if (err < 0)
991 return err;
992
993 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
994 &config->xcvr_lsfslew);
995 if (err < 0)
996 return err;
997
998 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
999 &config->xcvr_lsrslew);
1000 if (err < 0)
1001 return err;
1002
1003 if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
1004 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1005 &config->xcvr_hsslew);
1006 if (err < 0)
1007 return err;
1008
1009 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1010 &config->hssquelch_level);
1011 if (err < 0)
1012 return err;
1013
1014 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1015 &config->hsdiscon_level);
1016 if (err < 0)
1017 return err;
1018 }
1019
1020 config->xcvr_setup_use_fuses = of_property_read_bool(
1021 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
1022
1023 if (!config->xcvr_setup_use_fuses) {
1024 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1025 &config->xcvr_setup);
1026 if (err < 0)
1027 return err;
1028 }
1029
1030 return 0;
1031}
1032
1033static const struct tegra_phy_soc_config tegra20_soc_config = {
1034 .utmi_pll_config_in_car_module = false,
1035 .has_hostpc = false,
1036 .requires_usbmode_setup = false,
1037 .requires_extra_tuning_parameters = false,
1038};
1039
1040static const struct tegra_phy_soc_config tegra30_soc_config = {
1041 .utmi_pll_config_in_car_module = true,
1042 .has_hostpc = true,
1043 .requires_usbmode_setup = true,
1044 .requires_extra_tuning_parameters = true,
1045};
1046
1047static const struct of_device_id tegra_usb_phy_id_table[] = {
1048 { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
1049 { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
1050 { },
1051};
1052MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
1053
1054static int tegra_usb_phy_probe(struct platform_device *pdev)
1055{
1056 const struct of_device_id *match;
1057 struct resource *res;
1058 struct tegra_usb_phy *tegra_phy = NULL;
1059 struct device_node *np = pdev->dev.of_node;
1060 enum usb_phy_interface phy_type;
1061 int err;
1062
1063 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
1064 if (!tegra_phy)
1065 return -ENOMEM;
1066
1067 match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
1068 if (!match) {
1069 dev_err(&pdev->dev, "Error: No device match found\n");
1070 return -ENODEV;
1071 }
1072 tegra_phy->soc_config = match->data;
1073
1074 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1075 if (!res) {
1076 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1077 return -ENXIO;
1078 }
1079
1080 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1081 resource_size(res));
1082 if (!tegra_phy->regs) {
1083 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1084 return -ENOMEM;
1085 }
1086
1087 tegra_phy->is_legacy_phy =
1088 of_property_read_bool(np, "nvidia,has-legacy-mode");
1089
1090 phy_type = of_usb_get_phy_mode(np);
1091 switch (phy_type) {
1092 case USBPHY_INTERFACE_MODE_UTMI:
1093 err = utmi_phy_probe(tegra_phy, pdev);
1094 if (err < 0)
1095 return err;
1096 break;
1097
1098 case USBPHY_INTERFACE_MODE_ULPI:
1099 tegra_phy->is_ulpi_phy = true;
1100
1101 tegra_phy->reset_gpio =
1102 of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1103 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1104 dev_err(&pdev->dev,
1105 "Invalid GPIO: %d\n", tegra_phy->reset_gpio);
1106 return tegra_phy->reset_gpio;
1107 }
1108 tegra_phy->config = NULL;
1109 break;
1110
1111 default:
1112 dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1113 phy_type);
1114 return -EINVAL;
1115 }
1116
1117 if (of_find_property(np, "dr_mode", NULL))
1118 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1119 else
1120 tegra_phy->mode = USB_DR_MODE_HOST;
1121
1122 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1123 dev_err(&pdev->dev, "dr_mode is invalid\n");
1124 return -EINVAL;
1125 }
1126
1127 /* On some boards, the VBUS regulator doesn't need to be controlled */
1128 if (of_find_property(np, "vbus-supply", NULL)) {
1129 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1130 if (IS_ERR(tegra_phy->vbus))
1131 return PTR_ERR(tegra_phy->vbus);
1132 } else {
1133 dev_notice(&pdev->dev, "no vbus regulator");
1134 tegra_phy->vbus = ERR_PTR(-ENODEV);
1135 }
1136
1137 tegra_phy->u_phy.dev = &pdev->dev;
1138 err = tegra_usb_phy_init(tegra_phy);
1139 if (err < 0)
1140 return err;
1141
1142 tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
1143
1144 platform_set_drvdata(pdev, tegra_phy);
1145
1146 err = usb_add_phy_dev(&tegra_phy->u_phy);
1147 if (err < 0) {
1148 tegra_usb_phy_close(tegra_phy);
1149 return err;
1150 }
1151
1152 return 0;
1153}
1154
1155static int tegra_usb_phy_remove(struct platform_device *pdev)
1156{
1157 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1158
1159 usb_remove_phy(&tegra_phy->u_phy);
1160 tegra_usb_phy_close(tegra_phy);
1161
1162 return 0;
1163}
1164
1165static struct platform_driver tegra_usb_phy_driver = {
1166 .probe = tegra_usb_phy_probe,
1167 .remove = tegra_usb_phy_remove,
1168 .driver = {
1169 .name = "tegra-phy",
1170 .of_match_table = tegra_usb_phy_id_table,
1171 },
1172};
1173module_platform_driver(tegra_usb_phy_driver);
1174
1175MODULE_DESCRIPTION("Tegra USB PHY driver");
1176MODULE_LICENSE("GPL v2");