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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018 Intel Corporation */
3
4#ifndef _IGC_H_
5#define _IGC_H_
6
7#include <linux/kobject.h>
8#include <linux/pci.h>
9#include <linux/netdevice.h>
10#include <linux/vmalloc.h>
11#include <linux/ethtool.h>
12#include <linux/sctp.h>
13#include <linux/ptp_clock_kernel.h>
14#include <linux/timecounter.h>
15#include <linux/net_tstamp.h>
16
17#include "igc_hw.h"
18
19void igc_ethtool_set_ops(struct net_device *);
20
21/* Transmit and receive queues */
22#define IGC_MAX_RX_QUEUES 4
23#define IGC_MAX_TX_QUEUES 4
24
25#define MAX_Q_VECTORS 8
26#define MAX_STD_JUMBO_FRAME_SIZE 9216
27
28#define MAX_ETYPE_FILTER 8
29#define IGC_RETA_SIZE 128
30
31/* SDP support */
32#define IGC_N_EXTTS 2
33#define IGC_N_PEROUT 2
34#define IGC_N_SDP 4
35
36enum igc_mac_filter_type {
37 IGC_MAC_FILTER_TYPE_DST = 0,
38 IGC_MAC_FILTER_TYPE_SRC
39};
40
41struct igc_tx_queue_stats {
42 u64 packets;
43 u64 bytes;
44 u64 restart_queue;
45 u64 restart_queue2;
46};
47
48struct igc_rx_queue_stats {
49 u64 packets;
50 u64 bytes;
51 u64 drops;
52 u64 csum_err;
53 u64 alloc_failed;
54};
55
56struct igc_rx_packet_stats {
57 u64 ipv4_packets; /* IPv4 headers processed */
58 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
59 u64 ipv6_packets; /* IPv6 headers processed */
60 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
61 u64 tcp_packets; /* TCP headers processed */
62 u64 udp_packets; /* UDP headers processed */
63 u64 sctp_packets; /* SCTP headers processed */
64 u64 nfs_packets; /* NFS headers processe */
65 u64 other_packets;
66};
67
68struct igc_ring_container {
69 struct igc_ring *ring; /* pointer to linked list of rings */
70 unsigned int total_bytes; /* total bytes processed this int */
71 unsigned int total_packets; /* total packets processed this int */
72 u16 work_limit; /* total work allowed per interrupt */
73 u8 count; /* total number of rings in vector */
74 u8 itr; /* current ITR setting for ring */
75};
76
77struct igc_ring {
78 struct igc_q_vector *q_vector; /* backlink to q_vector */
79 struct net_device *netdev; /* back pointer to net_device */
80 struct device *dev; /* device for dma mapping */
81 union { /* array of buffer info structs */
82 struct igc_tx_buffer *tx_buffer_info;
83 struct igc_rx_buffer *rx_buffer_info;
84 };
85 void *desc; /* descriptor ring memory */
86 unsigned long flags; /* ring specific flags */
87 void __iomem *tail; /* pointer to ring tail register */
88 dma_addr_t dma; /* phys address of the ring */
89 unsigned int size; /* length of desc. ring in bytes */
90
91 u16 count; /* number of desc. in the ring */
92 u8 queue_index; /* logical index of the ring*/
93 u8 reg_idx; /* physical index of the ring */
94 bool launchtime_enable; /* true if LaunchTime is enabled */
95
96 u32 start_time;
97 u32 end_time;
98
99 /* everything past this point are written often */
100 u16 next_to_clean;
101 u16 next_to_use;
102 u16 next_to_alloc;
103
104 union {
105 /* TX */
106 struct {
107 struct igc_tx_queue_stats tx_stats;
108 struct u64_stats_sync tx_syncp;
109 struct u64_stats_sync tx_syncp2;
110 };
111 /* RX */
112 struct {
113 struct igc_rx_queue_stats rx_stats;
114 struct igc_rx_packet_stats pkt_stats;
115 struct u64_stats_sync rx_syncp;
116 struct sk_buff *skb;
117 };
118 };
119
120 struct xdp_rxq_info xdp_rxq;
121 struct xsk_buff_pool *xsk_pool;
122} ____cacheline_internodealigned_in_smp;
123
124/* Board specific private data structure */
125struct igc_adapter {
126 struct net_device *netdev;
127
128 struct ethtool_eee eee;
129 u16 eee_advert;
130
131 unsigned long state;
132 unsigned int flags;
133 unsigned int num_q_vectors;
134
135 struct msix_entry *msix_entries;
136
137 /* TX */
138 u16 tx_work_limit;
139 u32 tx_timeout_count;
140 int num_tx_queues;
141 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
142
143 /* RX */
144 int num_rx_queues;
145 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
146
147 struct timer_list watchdog_timer;
148 struct timer_list dma_err_timer;
149 struct timer_list phy_info_timer;
150
151 u32 wol;
152 u32 en_mng_pt;
153 u16 link_speed;
154 u16 link_duplex;
155
156 u8 port_num;
157
158 u8 __iomem *io_addr;
159 /* Interrupt Throttle Rate */
160 u32 rx_itr_setting;
161 u32 tx_itr_setting;
162
163 struct work_struct reset_task;
164 struct work_struct watchdog_task;
165 struct work_struct dma_err_task;
166 bool fc_autoneg;
167
168 u8 tx_timeout_factor;
169
170 int msg_enable;
171 u32 max_frame_size;
172 u32 min_frame_size;
173
174 ktime_t base_time;
175 ktime_t cycle_time;
176
177 /* OS defined structs */
178 struct pci_dev *pdev;
179 /* lock for statistics */
180 spinlock_t stats64_lock;
181 struct rtnl_link_stats64 stats64;
182
183 /* structs defined in igc_hw.h */
184 struct igc_hw hw;
185 struct igc_hw_stats stats;
186
187 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
188 u32 eims_enable_mask;
189 u32 eims_other;
190
191 u16 tx_ring_count;
192 u16 rx_ring_count;
193
194 u32 tx_hwtstamp_timeouts;
195 u32 tx_hwtstamp_skipped;
196 u32 rx_hwtstamp_cleared;
197
198 u32 rss_queues;
199 u32 rss_indir_tbl_init;
200
201 /* Any access to elements in nfc_rule_list is protected by the
202 * nfc_rule_lock.
203 */
204 struct mutex nfc_rule_lock;
205 struct list_head nfc_rule_list;
206 unsigned int nfc_rule_count;
207
208 u8 rss_indir_tbl[IGC_RETA_SIZE];
209
210 unsigned long link_check_timeout;
211 struct igc_info ei;
212
213 u32 test_icr;
214
215 struct ptp_clock *ptp_clock;
216 struct ptp_clock_info ptp_caps;
217 struct work_struct ptp_tx_work;
218 struct sk_buff *ptp_tx_skb;
219 struct hwtstamp_config tstamp_config;
220 unsigned long ptp_tx_start;
221 unsigned int ptp_flags;
222 /* System time value lock */
223 spinlock_t tmreg_lock;
224 struct cyclecounter cc;
225 struct timecounter tc;
226 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
227 ktime_t ptp_reset_start; /* Reset time in clock mono */
228
229 char fw_version[32];
230
231 struct bpf_prog *xdp_prog;
232
233 bool pps_sys_wrap_on;
234
235 struct ptp_pin_desc sdp_config[IGC_N_SDP];
236 struct {
237 struct timespec64 start;
238 struct timespec64 period;
239 } perout[IGC_N_PEROUT];
240};
241
242void igc_up(struct igc_adapter *adapter);
243void igc_down(struct igc_adapter *adapter);
244int igc_open(struct net_device *netdev);
245int igc_close(struct net_device *netdev);
246int igc_setup_tx_resources(struct igc_ring *ring);
247int igc_setup_rx_resources(struct igc_ring *ring);
248void igc_free_tx_resources(struct igc_ring *ring);
249void igc_free_rx_resources(struct igc_ring *ring);
250unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
251void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
252 const u32 max_rss_queues);
253int igc_reinit_queues(struct igc_adapter *adapter);
254void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
255bool igc_has_link(struct igc_adapter *adapter);
256void igc_reset(struct igc_adapter *adapter);
257int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
258void igc_update_stats(struct igc_adapter *adapter);
259void igc_disable_rx_ring(struct igc_ring *ring);
260void igc_enable_rx_ring(struct igc_ring *ring);
261void igc_disable_tx_ring(struct igc_ring *ring);
262void igc_enable_tx_ring(struct igc_ring *ring);
263int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
264
265/* igc_dump declarations */
266void igc_rings_dump(struct igc_adapter *adapter);
267void igc_regs_dump(struct igc_adapter *adapter);
268
269extern char igc_driver_name[];
270
271#define IGC_REGS_LEN 740
272
273/* flags controlling PTP/1588 function */
274#define IGC_PTP_ENABLED BIT(0)
275
276/* Flags definitions */
277#define IGC_FLAG_HAS_MSI BIT(0)
278#define IGC_FLAG_QUEUE_PAIRS BIT(3)
279#define IGC_FLAG_DMAC BIT(4)
280#define IGC_FLAG_PTP BIT(8)
281#define IGC_FLAG_WOL_SUPPORTED BIT(8)
282#define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
283#define IGC_FLAG_MEDIA_RESET BIT(10)
284#define IGC_FLAG_MAS_ENABLE BIT(12)
285#define IGC_FLAG_HAS_MSIX BIT(13)
286#define IGC_FLAG_EEE BIT(14)
287#define IGC_FLAG_VLAN_PROMISC BIT(15)
288#define IGC_FLAG_RX_LEGACY BIT(16)
289#define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
290
291#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
292#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
293
294#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
295#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
296#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
297
298/* Interrupt defines */
299#define IGC_START_ITR 648 /* ~6000 ints/sec */
300#define IGC_4K_ITR 980
301#define IGC_20K_ITR 196
302#define IGC_70K_ITR 56
303
304#define IGC_DEFAULT_ITR 3 /* dynamic */
305#define IGC_MAX_ITR_USECS 10000
306#define IGC_MIN_ITR_USECS 10
307#define NON_Q_VECTORS 1
308#define MAX_MSIX_ENTRIES 10
309
310/* TX/RX descriptor defines */
311#define IGC_DEFAULT_TXD 256
312#define IGC_DEFAULT_TX_WORK 128
313#define IGC_MIN_TXD 80
314#define IGC_MAX_TXD 4096
315
316#define IGC_DEFAULT_RXD 256
317#define IGC_MIN_RXD 80
318#define IGC_MAX_RXD 4096
319
320/* Supported Rx Buffer Sizes */
321#define IGC_RXBUFFER_256 256
322#define IGC_RXBUFFER_2048 2048
323#define IGC_RXBUFFER_3072 3072
324
325#define AUTO_ALL_MODES 0
326#define IGC_RX_HDR_LEN IGC_RXBUFFER_256
327
328/* Transmit and receive latency (for PTP timestamps) */
329#define IGC_I225_TX_LATENCY_10 240
330#define IGC_I225_TX_LATENCY_100 58
331#define IGC_I225_TX_LATENCY_1000 80
332#define IGC_I225_TX_LATENCY_2500 1325
333#define IGC_I225_RX_LATENCY_10 6450
334#define IGC_I225_RX_LATENCY_100 185
335#define IGC_I225_RX_LATENCY_1000 300
336#define IGC_I225_RX_LATENCY_2500 1485
337
338/* RX and TX descriptor control thresholds.
339 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
340 * descriptors available in its onboard memory.
341 * Setting this to 0 disables RX descriptor prefetch.
342 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
343 * available in host memory.
344 * If PTHRESH is 0, this should also be 0.
345 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
346 * descriptors until either it has this many to write back, or the
347 * ITR timer expires.
348 */
349#define IGC_RX_PTHRESH 8
350#define IGC_RX_HTHRESH 8
351#define IGC_TX_PTHRESH 8
352#define IGC_TX_HTHRESH 1
353#define IGC_RX_WTHRESH 4
354#define IGC_TX_WTHRESH 16
355
356#define IGC_RX_DMA_ATTR \
357 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
358
359#define IGC_TS_HDR_LEN 16
360
361#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
362
363#if (PAGE_SIZE < 8192)
364#define IGC_MAX_FRAME_BUILD_SKB \
365 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
366#else
367#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
368#endif
369
370/* How many Rx Buffers do we bundle into one write to the hardware ? */
371#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
372
373/* VLAN info */
374#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
375#define IGC_TX_FLAGS_VLAN_SHIFT 16
376
377/* igc_test_staterr - tests bits within Rx descriptor status and error fields */
378static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
379 const u32 stat_err_bits)
380{
381 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
382}
383
384enum igc_state_t {
385 __IGC_TESTING,
386 __IGC_RESETTING,
387 __IGC_DOWN,
388 __IGC_PTP_TX_IN_PROGRESS,
389};
390
391enum igc_tx_flags {
392 /* cmd_type flags */
393 IGC_TX_FLAGS_VLAN = 0x01,
394 IGC_TX_FLAGS_TSO = 0x02,
395 IGC_TX_FLAGS_TSTAMP = 0x04,
396
397 /* olinfo flags */
398 IGC_TX_FLAGS_IPV4 = 0x10,
399 IGC_TX_FLAGS_CSUM = 0x20,
400};
401
402enum igc_boards {
403 board_base,
404};
405
406/* The largest size we can write to the descriptor is 65535. In order to
407 * maintain a power of two alignment we have to limit ourselves to 32K.
408 */
409#define IGC_MAX_TXD_PWR 15
410#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
411
412/* Tx Descriptors needed, worst case */
413#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
414#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
415
416enum igc_tx_buffer_type {
417 IGC_TX_BUFFER_TYPE_SKB,
418 IGC_TX_BUFFER_TYPE_XDP,
419 IGC_TX_BUFFER_TYPE_XSK,
420};
421
422/* wrapper around a pointer to a socket buffer,
423 * so a DMA handle can be stored along with the buffer
424 */
425struct igc_tx_buffer {
426 union igc_adv_tx_desc *next_to_watch;
427 unsigned long time_stamp;
428 enum igc_tx_buffer_type type;
429 union {
430 struct sk_buff *skb;
431 struct xdp_frame *xdpf;
432 };
433 unsigned int bytecount;
434 u16 gso_segs;
435 __be16 protocol;
436
437 DEFINE_DMA_UNMAP_ADDR(dma);
438 DEFINE_DMA_UNMAP_LEN(len);
439 u32 tx_flags;
440};
441
442struct igc_rx_buffer {
443 union {
444 struct {
445 dma_addr_t dma;
446 struct page *page;
447#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
448 __u32 page_offset;
449#else
450 __u16 page_offset;
451#endif
452 __u16 pagecnt_bias;
453 };
454 struct xdp_buff *xdp;
455 };
456};
457
458struct igc_q_vector {
459 struct igc_adapter *adapter; /* backlink */
460 void __iomem *itr_register;
461 u32 eims_value; /* EIMS mask value */
462
463 u16 itr_val;
464 u8 set_itr;
465
466 struct igc_ring_container rx, tx;
467
468 struct napi_struct napi;
469
470 struct rcu_head rcu; /* to avoid race with update stats on free */
471 char name[IFNAMSIZ + 9];
472 struct net_device poll_dev;
473
474 /* for dynamic allocation of rings associated with this q_vector */
475 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
476};
477
478enum igc_filter_match_flags {
479 IGC_FILTER_FLAG_ETHER_TYPE = 0x1,
480 IGC_FILTER_FLAG_VLAN_TCI = 0x2,
481 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
482 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8,
483};
484
485struct igc_nfc_filter {
486 u8 match_flags;
487 u16 etype;
488 u16 vlan_tci;
489 u8 src_addr[ETH_ALEN];
490 u8 dst_addr[ETH_ALEN];
491};
492
493struct igc_nfc_rule {
494 struct list_head list;
495 struct igc_nfc_filter filter;
496 u32 location;
497 u16 action;
498};
499
500/* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority
501 * based, and 8 ethertype based.
502 */
503#define IGC_MAX_RXNFC_RULES 32
504
505/* igc_desc_unused - calculate if we have unused descriptors */
506static inline u16 igc_desc_unused(const struct igc_ring *ring)
507{
508 u16 ntc = ring->next_to_clean;
509 u16 ntu = ring->next_to_use;
510
511 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
512}
513
514static inline s32 igc_get_phy_info(struct igc_hw *hw)
515{
516 if (hw->phy.ops.get_phy_info)
517 return hw->phy.ops.get_phy_info(hw);
518
519 return 0;
520}
521
522static inline s32 igc_reset_phy(struct igc_hw *hw)
523{
524 if (hw->phy.ops.reset)
525 return hw->phy.ops.reset(hw);
526
527 return 0;
528}
529
530static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
531{
532 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
533}
534
535enum igc_ring_flags_t {
536 IGC_RING_FLAG_RX_3K_BUFFER,
537 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
538 IGC_RING_FLAG_RX_SCTP_CSUM,
539 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
540 IGC_RING_FLAG_TX_CTX_IDX,
541 IGC_RING_FLAG_TX_DETECT_HANG,
542 IGC_RING_FLAG_AF_XDP_ZC,
543};
544
545#define ring_uses_large_buffer(ring) \
546 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
547#define set_ring_uses_large_buffer(ring) \
548 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
549#define clear_ring_uses_large_buffer(ring) \
550 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
551
552#define ring_uses_build_skb(ring) \
553 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
554
555static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
556{
557#if (PAGE_SIZE < 8192)
558 if (ring_uses_large_buffer(ring))
559 return IGC_RXBUFFER_3072;
560
561 if (ring_uses_build_skb(ring))
562 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
563#endif
564 return IGC_RXBUFFER_2048;
565}
566
567static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
568{
569#if (PAGE_SIZE < 8192)
570 if (ring_uses_large_buffer(ring))
571 return 1;
572#endif
573 return 0;
574}
575
576static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
577{
578 if (hw->phy.ops.read_reg)
579 return hw->phy.ops.read_reg(hw, offset, data);
580
581 return -EOPNOTSUPP;
582}
583
584void igc_reinit_locked(struct igc_adapter *);
585struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
586 u32 location);
587int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
588void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
589
590void igc_ptp_init(struct igc_adapter *adapter);
591void igc_ptp_reset(struct igc_adapter *adapter);
592void igc_ptp_suspend(struct igc_adapter *adapter);
593void igc_ptp_stop(struct igc_adapter *adapter);
594ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
595int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
596int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
597void igc_ptp_tx_hang(struct igc_adapter *adapter);
598void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
599
600#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
601
602#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
603
604#define IGC_RX_DESC(R, i) \
605 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
606#define IGC_TX_DESC(R, i) \
607 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
608#define IGC_TX_CTXTDESC(R, i) \
609 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
610
611#endif /* _IGC_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018 Intel Corporation */
3
4#ifndef _IGC_H_
5#define _IGC_H_
6
7#include <linux/kobject.h>
8#include <linux/pci.h>
9#include <linux/netdevice.h>
10#include <linux/vmalloc.h>
11#include <linux/ethtool.h>
12#include <linux/sctp.h>
13
14#include "igc_hw.h"
15
16/* forward declaration */
17void igc_set_ethtool_ops(struct net_device *);
18
19struct igc_adapter;
20struct igc_ring;
21
22void igc_up(struct igc_adapter *adapter);
23void igc_down(struct igc_adapter *adapter);
24int igc_setup_tx_resources(struct igc_ring *ring);
25int igc_setup_rx_resources(struct igc_ring *ring);
26void igc_free_tx_resources(struct igc_ring *ring);
27void igc_free_rx_resources(struct igc_ring *ring);
28unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
29void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
30 const u32 max_rss_queues);
31int igc_reinit_queues(struct igc_adapter *adapter);
32void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
33bool igc_has_link(struct igc_adapter *adapter);
34void igc_reset(struct igc_adapter *adapter);
35int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
36int igc_add_mac_steering_filter(struct igc_adapter *adapter,
37 const u8 *addr, u8 queue, u8 flags);
38int igc_del_mac_steering_filter(struct igc_adapter *adapter,
39 const u8 *addr, u8 queue, u8 flags);
40void igc_update_stats(struct igc_adapter *adapter);
41
42extern char igc_driver_name[];
43extern char igc_driver_version[];
44
45#define IGC_REGS_LEN 740
46#define IGC_RETA_SIZE 128
47
48/* Interrupt defines */
49#define IGC_START_ITR 648 /* ~6000 ints/sec */
50#define IGC_FLAG_HAS_MSI BIT(0)
51#define IGC_FLAG_QUEUE_PAIRS BIT(3)
52#define IGC_FLAG_DMAC BIT(4)
53#define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
54#define IGC_FLAG_MEDIA_RESET BIT(10)
55#define IGC_FLAG_MAS_ENABLE BIT(12)
56#define IGC_FLAG_HAS_MSIX BIT(13)
57#define IGC_FLAG_VLAN_PROMISC BIT(15)
58#define IGC_FLAG_RX_LEGACY BIT(16)
59
60#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
61#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
62
63#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
64#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
65#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
66
67#define IGC_START_ITR 648 /* ~6000 ints/sec */
68#define IGC_4K_ITR 980
69#define IGC_20K_ITR 196
70#define IGC_70K_ITR 56
71
72#define IGC_DEFAULT_ITR 3 /* dynamic */
73#define IGC_MAX_ITR_USECS 10000
74#define IGC_MIN_ITR_USECS 10
75#define NON_Q_VECTORS 1
76#define MAX_MSIX_ENTRIES 10
77
78/* TX/RX descriptor defines */
79#define IGC_DEFAULT_TXD 256
80#define IGC_DEFAULT_TX_WORK 128
81#define IGC_MIN_TXD 80
82#define IGC_MAX_TXD 4096
83
84#define IGC_DEFAULT_RXD 256
85#define IGC_MIN_RXD 80
86#define IGC_MAX_RXD 4096
87
88/* Transmit and receive queues */
89#define IGC_MAX_RX_QUEUES 4
90#define IGC_MAX_TX_QUEUES 4
91
92#define MAX_Q_VECTORS 8
93#define MAX_STD_JUMBO_FRAME_SIZE 9216
94
95/* Supported Rx Buffer Sizes */
96#define IGC_RXBUFFER_256 256
97#define IGC_RXBUFFER_2048 2048
98#define IGC_RXBUFFER_3072 3072
99
100#define AUTO_ALL_MODES 0
101#define IGC_RX_HDR_LEN IGC_RXBUFFER_256
102
103/* RX and TX descriptor control thresholds.
104 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
105 * descriptors available in its onboard memory.
106 * Setting this to 0 disables RX descriptor prefetch.
107 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
108 * available in host memory.
109 * If PTHRESH is 0, this should also be 0.
110 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
111 * descriptors until either it has this many to write back, or the
112 * ITR timer expires.
113 */
114#define IGC_RX_PTHRESH 8
115#define IGC_RX_HTHRESH 8
116#define IGC_TX_PTHRESH 8
117#define IGC_TX_HTHRESH 1
118#define IGC_RX_WTHRESH 4
119#define IGC_TX_WTHRESH 16
120
121#define IGC_RX_DMA_ATTR \
122 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
123
124#define IGC_TS_HDR_LEN 16
125
126#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
127
128#if (PAGE_SIZE < 8192)
129#define IGC_MAX_FRAME_BUILD_SKB \
130 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
131#else
132#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
133#endif
134
135/* How many Rx Buffers do we bundle into one write to the hardware ? */
136#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
137
138/* VLAN info */
139#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
140
141/* igc_test_staterr - tests bits within Rx descriptor status and error fields */
142static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
143 const u32 stat_err_bits)
144{
145 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
146}
147
148enum igc_state_t {
149 __IGC_TESTING,
150 __IGC_RESETTING,
151 __IGC_DOWN,
152 __IGC_PTP_TX_IN_PROGRESS,
153};
154
155enum igc_tx_flags {
156 /* cmd_type flags */
157 IGC_TX_FLAGS_VLAN = 0x01,
158 IGC_TX_FLAGS_TSO = 0x02,
159 IGC_TX_FLAGS_TSTAMP = 0x04,
160
161 /* olinfo flags */
162 IGC_TX_FLAGS_IPV4 = 0x10,
163 IGC_TX_FLAGS_CSUM = 0x20,
164};
165
166enum igc_boards {
167 board_base,
168};
169
170/* The largest size we can write to the descriptor is 65535. In order to
171 * maintain a power of two alignment we have to limit ourselves to 32K.
172 */
173#define IGC_MAX_TXD_PWR 15
174#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
175
176/* Tx Descriptors needed, worst case */
177#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
178#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
179
180/* wrapper around a pointer to a socket buffer,
181 * so a DMA handle can be stored along with the buffer
182 */
183struct igc_tx_buffer {
184 union igc_adv_tx_desc *next_to_watch;
185 unsigned long time_stamp;
186 struct sk_buff *skb;
187 unsigned int bytecount;
188 u16 gso_segs;
189 __be16 protocol;
190
191 DEFINE_DMA_UNMAP_ADDR(dma);
192 DEFINE_DMA_UNMAP_LEN(len);
193 u32 tx_flags;
194};
195
196struct igc_rx_buffer {
197 dma_addr_t dma;
198 struct page *page;
199#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
200 __u32 page_offset;
201#else
202 __u16 page_offset;
203#endif
204 __u16 pagecnt_bias;
205};
206
207struct igc_tx_queue_stats {
208 u64 packets;
209 u64 bytes;
210 u64 restart_queue;
211 u64 restart_queue2;
212};
213
214struct igc_rx_queue_stats {
215 u64 packets;
216 u64 bytes;
217 u64 drops;
218 u64 csum_err;
219 u64 alloc_failed;
220};
221
222struct igc_rx_packet_stats {
223 u64 ipv4_packets; /* IPv4 headers processed */
224 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
225 u64 ipv6_packets; /* IPv6 headers processed */
226 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
227 u64 tcp_packets; /* TCP headers processed */
228 u64 udp_packets; /* UDP headers processed */
229 u64 sctp_packets; /* SCTP headers processed */
230 u64 nfs_packets; /* NFS headers processe */
231 u64 other_packets;
232};
233
234struct igc_ring_container {
235 struct igc_ring *ring; /* pointer to linked list of rings */
236 unsigned int total_bytes; /* total bytes processed this int */
237 unsigned int total_packets; /* total packets processed this int */
238 u16 work_limit; /* total work allowed per interrupt */
239 u8 count; /* total number of rings in vector */
240 u8 itr; /* current ITR setting for ring */
241};
242
243struct igc_ring {
244 struct igc_q_vector *q_vector; /* backlink to q_vector */
245 struct net_device *netdev; /* back pointer to net_device */
246 struct device *dev; /* device for dma mapping */
247 union { /* array of buffer info structs */
248 struct igc_tx_buffer *tx_buffer_info;
249 struct igc_rx_buffer *rx_buffer_info;
250 };
251 void *desc; /* descriptor ring memory */
252 unsigned long flags; /* ring specific flags */
253 void __iomem *tail; /* pointer to ring tail register */
254 dma_addr_t dma; /* phys address of the ring */
255 unsigned int size; /* length of desc. ring in bytes */
256
257 u16 count; /* number of desc. in the ring */
258 u8 queue_index; /* logical index of the ring*/
259 u8 reg_idx; /* physical index of the ring */
260 bool launchtime_enable; /* true if LaunchTime is enabled */
261
262 /* everything past this point are written often */
263 u16 next_to_clean;
264 u16 next_to_use;
265 u16 next_to_alloc;
266
267 union {
268 /* TX */
269 struct {
270 struct igc_tx_queue_stats tx_stats;
271 struct u64_stats_sync tx_syncp;
272 struct u64_stats_sync tx_syncp2;
273 };
274 /* RX */
275 struct {
276 struct igc_rx_queue_stats rx_stats;
277 struct igc_rx_packet_stats pkt_stats;
278 struct u64_stats_sync rx_syncp;
279 struct sk_buff *skb;
280 };
281 };
282} ____cacheline_internodealigned_in_smp;
283
284struct igc_q_vector {
285 struct igc_adapter *adapter; /* backlink */
286 void __iomem *itr_register;
287 u32 eims_value; /* EIMS mask value */
288
289 u16 itr_val;
290 u8 set_itr;
291
292 struct igc_ring_container rx, tx;
293
294 struct napi_struct napi;
295
296 struct rcu_head rcu; /* to avoid race with update stats on free */
297 char name[IFNAMSIZ + 9];
298 struct net_device poll_dev;
299
300 /* for dynamic allocation of rings associated with this q_vector */
301 struct igc_ring ring[0] ____cacheline_internodealigned_in_smp;
302};
303
304#define MAX_ETYPE_FILTER (4 - 1)
305
306enum igc_filter_match_flags {
307 IGC_FILTER_FLAG_ETHER_TYPE = 0x1,
308 IGC_FILTER_FLAG_VLAN_TCI = 0x2,
309 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
310 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8,
311};
312
313/* RX network flow classification data structure */
314struct igc_nfc_input {
315 /* Byte layout in order, all values with MSB first:
316 * match_flags - 1 byte
317 * etype - 2 bytes
318 * vlan_tci - 2 bytes
319 */
320 u8 match_flags;
321 __be16 etype;
322 __be16 vlan_tci;
323 u8 src_addr[ETH_ALEN];
324 u8 dst_addr[ETH_ALEN];
325};
326
327struct igc_nfc_filter {
328 struct hlist_node nfc_node;
329 struct igc_nfc_input filter;
330 unsigned long cookie;
331 u16 etype_reg_index;
332 u16 sw_idx;
333 u16 action;
334};
335
336struct igc_mac_addr {
337 u8 addr[ETH_ALEN];
338 u8 queue;
339 u8 state; /* bitmask */
340};
341
342#define IGC_MAC_STATE_DEFAULT 0x1
343#define IGC_MAC_STATE_IN_USE 0x2
344#define IGC_MAC_STATE_SRC_ADDR 0x4
345#define IGC_MAC_STATE_QUEUE_STEERING 0x8
346
347#define IGC_MAX_RXNFC_FILTERS 16
348
349/* Board specific private data structure */
350struct igc_adapter {
351 struct net_device *netdev;
352
353 unsigned long state;
354 unsigned int flags;
355 unsigned int num_q_vectors;
356
357 struct msix_entry *msix_entries;
358
359 /* TX */
360 u16 tx_work_limit;
361 u32 tx_timeout_count;
362 int num_tx_queues;
363 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
364
365 /* RX */
366 int num_rx_queues;
367 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
368
369 struct timer_list watchdog_timer;
370 struct timer_list dma_err_timer;
371 struct timer_list phy_info_timer;
372
373 u16 link_speed;
374 u16 link_duplex;
375
376 u8 port_num;
377
378 u8 __iomem *io_addr;
379 /* Interrupt Throttle Rate */
380 u32 rx_itr_setting;
381 u32 tx_itr_setting;
382
383 struct work_struct reset_task;
384 struct work_struct watchdog_task;
385 struct work_struct dma_err_task;
386 bool fc_autoneg;
387
388 u8 tx_timeout_factor;
389
390 int msg_enable;
391 u32 max_frame_size;
392 u32 min_frame_size;
393
394 /* OS defined structs */
395 struct pci_dev *pdev;
396 /* lock for statistics */
397 spinlock_t stats64_lock;
398 struct rtnl_link_stats64 stats64;
399
400 /* structs defined in igc_hw.h */
401 struct igc_hw hw;
402 struct igc_hw_stats stats;
403
404 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
405 u32 eims_enable_mask;
406 u32 eims_other;
407
408 u16 tx_ring_count;
409 u16 rx_ring_count;
410
411 u32 tx_hwtstamp_timeouts;
412 u32 tx_hwtstamp_skipped;
413 u32 rx_hwtstamp_cleared;
414 u32 *shadow_vfta;
415
416 u32 rss_queues;
417 u32 rss_indir_tbl_init;
418
419 /* RX network flow classification support */
420 struct hlist_head nfc_filter_list;
421 struct hlist_head cls_flower_list;
422 unsigned int nfc_filter_count;
423
424 /* lock for RX network flow classification filter */
425 spinlock_t nfc_lock;
426 bool etype_bitmap[MAX_ETYPE_FILTER];
427
428 struct igc_mac_addr *mac_table;
429
430 u8 rss_indir_tbl[IGC_RETA_SIZE];
431
432 unsigned long link_check_timeout;
433 struct igc_info ei;
434};
435
436/* igc_desc_unused - calculate if we have unused descriptors */
437static inline u16 igc_desc_unused(const struct igc_ring *ring)
438{
439 u16 ntc = ring->next_to_clean;
440 u16 ntu = ring->next_to_use;
441
442 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
443}
444
445static inline s32 igc_get_phy_info(struct igc_hw *hw)
446{
447 if (hw->phy.ops.get_phy_info)
448 return hw->phy.ops.get_phy_info(hw);
449
450 return 0;
451}
452
453static inline s32 igc_reset_phy(struct igc_hw *hw)
454{
455 if (hw->phy.ops.reset)
456 return hw->phy.ops.reset(hw);
457
458 return 0;
459}
460
461static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
462{
463 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
464}
465
466enum igc_ring_flags_t {
467 IGC_RING_FLAG_RX_3K_BUFFER,
468 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
469 IGC_RING_FLAG_RX_SCTP_CSUM,
470 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
471 IGC_RING_FLAG_TX_CTX_IDX,
472 IGC_RING_FLAG_TX_DETECT_HANG
473};
474
475#define ring_uses_large_buffer(ring) \
476 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
477
478#define ring_uses_build_skb(ring) \
479 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
480
481static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
482{
483#if (PAGE_SIZE < 8192)
484 if (ring_uses_large_buffer(ring))
485 return IGC_RXBUFFER_3072;
486
487 if (ring_uses_build_skb(ring))
488 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
489#endif
490 return IGC_RXBUFFER_2048;
491}
492
493static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
494{
495#if (PAGE_SIZE < 8192)
496 if (ring_uses_large_buffer(ring))
497 return 1;
498#endif
499 return 0;
500}
501
502static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
503{
504 if (hw->phy.ops.read_reg)
505 return hw->phy.ops.read_reg(hw, offset, data);
506
507 return 0;
508}
509
510/* forward declaration */
511void igc_reinit_locked(struct igc_adapter *);
512int igc_add_filter(struct igc_adapter *adapter,
513 struct igc_nfc_filter *input);
514int igc_erase_filter(struct igc_adapter *adapter,
515 struct igc_nfc_filter *input);
516
517#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
518
519#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
520
521#define IGC_RX_DESC(R, i) \
522 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
523#define IGC_TX_DESC(R, i) \
524 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
525#define IGC_TX_CTXTDESC(R, i) \
526 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
527
528#endif /* _IGC_H_ */