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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */
7
8#include <dt-bindings/clock/sh73a0-clock.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13 compatible = "renesas,sh73a0";
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a9";
25 reg = <0>;
26 clock-frequency = <1196000000>;
27 clocks = <&cpg_clocks SH73A0_CLK_Z>;
28 power-domains = <&pd_a2sl>;
29 next-level-cache = <&L2>;
30 };
31 cpu1: cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 reg = <1>;
35 clock-frequency = <1196000000>;
36 clocks = <&cpg_clocks SH73A0_CLK_Z>;
37 power-domains = <&pd_a2sl>;
38 next-level-cache = <&L2>;
39 };
40 };
41
42 timer@f0000200 {
43 compatible = "arm,cortex-a9-global-timer";
44 reg = <0xf0000200 0x100>;
45 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
46 clocks = <&periph_clk>;
47 };
48
49 timer@f0000600 {
50 compatible = "arm,cortex-a9-twd-timer";
51 reg = <0xf0000600 0x20>;
52 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
53 clocks = <&periph_clk>;
54 };
55
56 gic: interrupt-controller@f0001000 {
57 compatible = "arm,cortex-a9-gic";
58 #interrupt-cells = <3>;
59 interrupt-controller;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
62 };
63
64 L2: cache-controller@f0100000 {
65 compatible = "arm,pl310-cache";
66 reg = <0xf0100000 0x1000>;
67 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
68 power-domains = <&pd_a3sm>;
69 arm,data-latency = <3 3 3>;
70 arm,tag-latency = <2 2 2>;
71 arm,shared-override;
72 cache-unified;
73 cache-level = <2>;
74 };
75
76 sbsc2: memory-controller@fb400000 {
77 compatible = "renesas,sbsc-sh73a0";
78 reg = <0xfb400000 0x400>;
79 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
81 interrupt-names = "sec", "temp";
82 power-domains = <&pd_a4bc1>;
83 };
84
85 sbsc1: memory-controller@fe400000 {
86 compatible = "renesas,sbsc-sh73a0";
87 reg = <0xfe400000 0x400>;
88 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
90 interrupt-names = "sec", "temp";
91 power-domains = <&pd_a4bc0>;
92 };
93
94 pmu {
95 compatible = "arm,cortex-a9-pmu";
96 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
98 interrupt-affinity = <&cpu0>, <&cpu1>;
99 };
100
101 cmt1: timer@e6138000 {
102 compatible = "renesas,sh73a0-cmt1";
103 reg = <0xe6138000 0x200>;
104 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
106 clock-names = "fck";
107 power-domains = <&pd_c5>;
108 status = "disabled";
109 };
110
111 irqpin0: interrupt-controller@e6900000 {
112 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
113 #interrupt-cells = <2>;
114 interrupt-controller;
115 reg = <0xe6900000 4>,
116 <0xe6900010 4>,
117 <0xe6900020 1>,
118 <0xe6900040 1>,
119 <0xe6900060 1>;
120 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
129 power-domains = <&pd_a4s>;
130 control-parent;
131 };
132
133 irqpin1: interrupt-controller@e6900004 {
134 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
135 #interrupt-cells = <2>;
136 interrupt-controller;
137 reg = <0xe6900004 4>,
138 <0xe6900014 4>,
139 <0xe6900024 1>,
140 <0xe6900044 1>,
141 <0xe6900064 1>;
142 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
151 power-domains = <&pd_a4s>;
152 control-parent;
153 };
154
155 irqpin2: interrupt-controller@e6900008 {
156 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 reg = <0xe6900008 4>,
160 <0xe6900018 4>,
161 <0xe6900028 1>,
162 <0xe6900048 1>,
163 <0xe6900068 1>;
164 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
173 power-domains = <&pd_a4s>;
174 control-parent;
175 };
176
177 irqpin3: interrupt-controller@e690000c {
178 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
179 #interrupt-cells = <2>;
180 interrupt-controller;
181 reg = <0xe690000c 4>,
182 <0xe690001c 4>,
183 <0xe690002c 1>,
184 <0xe690004c 1>,
185 <0xe690006c 1>;
186 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
195 power-domains = <&pd_a4s>;
196 control-parent;
197 };
198
199 i2c0: i2c@e6820000 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
203 reg = <0xe6820000 0x425>;
204 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
209 power-domains = <&pd_a3sp>;
210 status = "disabled";
211 };
212
213 i2c1: i2c@e6822000 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
217 reg = <0xe6822000 0x425>;
218 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
223 power-domains = <&pd_a3sp>;
224 status = "disabled";
225 };
226
227 i2c2: i2c@e6824000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
231 reg = <0xe6824000 0x425>;
232 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
237 power-domains = <&pd_a3sp>;
238 status = "disabled";
239 };
240
241 i2c3: i2c@e6826000 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
245 reg = <0xe6826000 0x425>;
246 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
251 power-domains = <&pd_a3sp>;
252 status = "disabled";
253 };
254
255 i2c4: i2c@e6828000 {
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
259 reg = <0xe6828000 0x425>;
260 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
265 power-domains = <&pd_c5>;
266 status = "disabled";
267 };
268
269 mmcif: mmc@e6bd0000 {
270 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
271 reg = <0xe6bd0000 0x100>;
272 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
275 power-domains = <&pd_a3sp>;
276 reg-io-width = <4>;
277 status = "disabled";
278 };
279
280 msiof0: spi@e6e20000 {
281 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
282 reg = <0xe6e20000 0x0064>;
283 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
285 power-domains = <&pd_a3sp>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 status = "disabled";
289 };
290
291 msiof1: spi@e6e10000 {
292 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
293 reg = <0xe6e10000 0x0064>;
294 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
296 power-domains = <&pd_a3sp>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300 };
301
302 msiof2: spi@e6e00000 {
303 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
304 reg = <0xe6e00000 0x0064>;
305 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
307 power-domains = <&pd_a3sp>;
308 #address-cells = <1>;
309 #size-cells = <0>;
310 status = "disabled";
311 };
312
313 msiof3: spi@e6c90000 {
314 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
315 reg = <0xe6c90000 0x0064>;
316 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
318 power-domains = <&pd_a3sp>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 status = "disabled";
322 };
323
324 sdhi0: mmc@ee100000 {
325 compatible = "renesas,sdhi-sh73a0";
326 reg = <0xee100000 0x100>;
327 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
331 power-domains = <&pd_a3sp>;
332 cap-sd-highspeed;
333 status = "disabled";
334 };
335
336 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
337 sdhi1: mmc@ee120000 {
338 compatible = "renesas,sdhi-sh73a0";
339 reg = <0xee120000 0x100>;
340 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
343 power-domains = <&pd_a3sp>;
344 disable-wp;
345 cap-sd-highspeed;
346 status = "disabled";
347 };
348
349 sdhi2: mmc@ee140000 {
350 compatible = "renesas,sdhi-sh73a0";
351 reg = <0xee140000 0x100>;
352 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
355 power-domains = <&pd_a3sp>;
356 disable-wp;
357 cap-sd-highspeed;
358 status = "disabled";
359 };
360
361 scifa0: serial@e6c40000 {
362 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
363 reg = <0xe6c40000 0x100>;
364 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
366 clock-names = "fck";
367 power-domains = <&pd_a3sp>;
368 status = "disabled";
369 };
370
371 scifa1: serial@e6c50000 {
372 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
373 reg = <0xe6c50000 0x100>;
374 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
376 clock-names = "fck";
377 power-domains = <&pd_a3sp>;
378 status = "disabled";
379 };
380
381 scifa2: serial@e6c60000 {
382 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
383 reg = <0xe6c60000 0x100>;
384 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
386 clock-names = "fck";
387 power-domains = <&pd_a3sp>;
388 status = "disabled";
389 };
390
391 scifa3: serial@e6c70000 {
392 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
393 reg = <0xe6c70000 0x100>;
394 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
396 clock-names = "fck";
397 power-domains = <&pd_a3sp>;
398 status = "disabled";
399 };
400
401 scifa4: serial@e6c80000 {
402 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
403 reg = <0xe6c80000 0x100>;
404 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
406 clock-names = "fck";
407 power-domains = <&pd_a3sp>;
408 status = "disabled";
409 };
410
411 scifa5: serial@e6cb0000 {
412 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
413 reg = <0xe6cb0000 0x100>;
414 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
416 clock-names = "fck";
417 power-domains = <&pd_a3sp>;
418 status = "disabled";
419 };
420
421 scifa6: serial@e6cc0000 {
422 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
423 reg = <0xe6cc0000 0x100>;
424 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
426 clock-names = "fck";
427 power-domains = <&pd_a3sp>;
428 status = "disabled";
429 };
430
431 scifa7: serial@e6cd0000 {
432 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
433 reg = <0xe6cd0000 0x100>;
434 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
436 clock-names = "fck";
437 power-domains = <&pd_a3sp>;
438 status = "disabled";
439 };
440
441 scifb: serial@e6c30000 {
442 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
443 reg = <0xe6c30000 0x100>;
444 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
446 clock-names = "fck";
447 power-domains = <&pd_a3sp>;
448 status = "disabled";
449 };
450
451 pfc: pinctrl@e6050000 {
452 compatible = "renesas,pfc-sh73a0";
453 reg = <0xe6050000 0x8000>,
454 <0xe605801c 0x1c>;
455 gpio-controller;
456 #gpio-cells = <2>;
457 gpio-ranges =
458 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
459 <&pfc 288 288 22>;
460 interrupts-extended =
461 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
462 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
463 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
464 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
465 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
466 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
467 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
468 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
469 power-domains = <&pd_c5>;
470 };
471
472 sysc: system-controller@e6180000 {
473 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
474 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
475
476 pm-domains {
477 pd_c5: c5 {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 #power-domain-cells = <0>;
481
482 pd_c4: c4@0 {
483 reg = <0>;
484 #power-domain-cells = <0>;
485 };
486
487 pd_d4: d4@1 {
488 reg = <1>;
489 #power-domain-cells = <0>;
490 };
491
492 pd_a4bc0: a4bc0@4 {
493 reg = <4>;
494 #power-domain-cells = <0>;
495 };
496
497 pd_a4bc1: a4bc1@5 {
498 reg = <5>;
499 #power-domain-cells = <0>;
500 };
501
502 pd_a4lc0: a4lc0@6 {
503 reg = <6>;
504 #power-domain-cells = <0>;
505 };
506
507 pd_a4lc1: a4lc1@7 {
508 reg = <7>;
509 #power-domain-cells = <0>;
510 };
511
512 pd_a4mp: a4mp@8 {
513 reg = <8>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516 #power-domain-cells = <0>;
517
518 pd_a3mp: a3mp@9 {
519 reg = <9>;
520 #power-domain-cells = <0>;
521 };
522
523 pd_a3vc: a3vc@10 {
524 reg = <10>;
525 #power-domain-cells = <0>;
526 };
527 };
528
529 pd_a4rm: a4rm@12 {
530 reg = <12>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 #power-domain-cells = <0>;
534
535 pd_a3r: a3r@13 {
536 reg = <13>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <0>;
540
541 pd_a2rv: a2rv@14 {
542 reg = <14>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 #power-domain-cells = <0>;
546 };
547 };
548 };
549
550 pd_a4s: a4s@16 {
551 reg = <16>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 #power-domain-cells = <0>;
555
556 pd_a3sp: a3sp@17 {
557 reg = <17>;
558 #power-domain-cells = <0>;
559 };
560
561 pd_a3sg: a3sg@18 {
562 reg = <18>;
563 #power-domain-cells = <0>;
564 };
565
566 pd_a3sm: a3sm@19 {
567 reg = <19>;
568 #address-cells = <1>;
569 #size-cells = <0>;
570 #power-domain-cells = <0>;
571
572 pd_a2sl: a2sl@20 {
573 reg = <20>;
574 #power-domain-cells = <0>;
575 };
576 };
577 };
578 };
579 };
580 };
581
582 sh_fsi2: sound@ec230000 {
583 #sound-dai-cells = <1>;
584 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
585 reg = <0xec230000 0x400>;
586 interrupts = <GIC_SPI 146 0x4>;
587 clocks = <&mstp3_clks SH73A0_CLK_FSI>;
588 power-domains = <&pd_a4mp>;
589 status = "disabled";
590 };
591
592 bsc: bus@fec10000 {
593 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
594 "simple-pm-bus";
595 #address-cells = <1>;
596 #size-cells = <1>;
597 ranges = <0 0 0x20000000>;
598 reg = <0xfec10000 0x400>;
599 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&zb_clk>;
601 power-domains = <&pd_a4s>;
602 };
603
604 clocks {
605 #address-cells = <1>;
606 #size-cells = <1>;
607 ranges;
608
609 /* External root clocks */
610 extalr_clk: extalr {
611 compatible = "fixed-clock";
612 #clock-cells = <0>;
613 clock-frequency = <32768>;
614 };
615 extal1_clk: extal1 {
616 compatible = "fixed-clock";
617 #clock-cells = <0>;
618 clock-frequency = <26000000>;
619 };
620 extal2_clk: extal2 {
621 compatible = "fixed-clock";
622 #clock-cells = <0>;
623 /* This value must be overridden by the board. */
624 clock-frequency = <0>;
625 };
626 extcki_clk: extcki {
627 compatible = "fixed-clock";
628 #clock-cells = <0>;
629 /* This value can be overridden by the board. */
630 clock-frequency = <0>;
631 };
632 fsiack_clk: fsiack {
633 compatible = "fixed-clock";
634 #clock-cells = <0>;
635 /* This value can be overridden by the board. */
636 clock-frequency = <0>;
637 };
638 fsibck_clk: fsibck {
639 compatible = "fixed-clock";
640 #clock-cells = <0>;
641 /* This value can be overridden by the board. */
642 clock-frequency = <0>;
643 };
644
645 /* Special CPG clocks */
646 cpg_clocks: cpg_clocks@e6150000 {
647 compatible = "renesas,sh73a0-cpg-clocks";
648 reg = <0xe6150000 0x10000>;
649 clocks = <&extal1_clk>, <&extal2_clk>;
650 #clock-cells = <1>;
651 clock-output-names = "main", "pll0", "pll1", "pll2",
652 "pll3", "dsi0phy", "dsi1phy",
653 "zg", "m3", "b", "m1", "m2",
654 "z", "zx", "hp";
655 };
656
657 /* Variable factor clocks (DIV6) */
658 vclk1_clk: vclk1@e6150008 {
659 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
660 reg = <0xe6150008 4>;
661 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
662 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
663 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
664 <0>;
665 #clock-cells = <0>;
666 };
667 vclk2_clk: vclk2@e615000c {
668 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
669 reg = <0xe615000c 4>;
670 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
671 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
672 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
673 <0>;
674 #clock-cells = <0>;
675 };
676 vclk3_clk: vclk3@e615001c {
677 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
678 reg = <0xe615001c 4>;
679 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
680 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
681 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
682 <0>;
683 #clock-cells = <0>;
684 };
685 zb_clk: zb_clk@e6150010 {
686 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
687 reg = <0xe6150010 4>;
688 clocks = <&pll1_div2_clk>, <0>,
689 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
690 #clock-cells = <0>;
691 clock-output-names = "zb";
692 };
693 flctl_clk: flctlck@e6150014 {
694 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
695 reg = <0xe6150014 4>;
696 clocks = <&pll1_div2_clk>, <0>,
697 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
698 #clock-cells = <0>;
699 };
700 sdhi0_clk: sdhi0ck@e6150074 {
701 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
702 reg = <0xe6150074 4>;
703 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
704 <&pll1_div13_clk>, <0>;
705 #clock-cells = <0>;
706 };
707 sdhi1_clk: sdhi1ck@e6150078 {
708 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
709 reg = <0xe6150078 4>;
710 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
711 <&pll1_div13_clk>, <0>;
712 #clock-cells = <0>;
713 };
714 sdhi2_clk: sdhi2ck@e615007c {
715 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
716 reg = <0xe615007c 4>;
717 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
718 <&pll1_div13_clk>, <0>;
719 #clock-cells = <0>;
720 };
721 fsia_clk: fsia@e6150018 {
722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
723 reg = <0xe6150018 4>;
724 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
725 <&fsiack_clk>, <&fsiack_clk>;
726 #clock-cells = <0>;
727 };
728 fsib_clk: fsib@e6150090 {
729 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
730 reg = <0xe6150090 4>;
731 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
732 <&fsibck_clk>, <&fsibck_clk>;
733 #clock-cells = <0>;
734 };
735 sub_clk: sub@e6150080 {
736 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
737 reg = <0xe6150080 4>;
738 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
739 <&extal2_clk>, <&extal2_clk>;
740 #clock-cells = <0>;
741 };
742 spua_clk: spua@e6150084 {
743 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
744 reg = <0xe6150084 4>;
745 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
746 <&extal2_clk>, <&extal2_clk>;
747 #clock-cells = <0>;
748 };
749 spuv_clk: spuv@e6150094 {
750 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
751 reg = <0xe6150094 4>;
752 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
753 <&extal2_clk>, <&extal2_clk>;
754 #clock-cells = <0>;
755 };
756 msu_clk: msu@e6150088 {
757 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
758 reg = <0xe6150088 4>;
759 clocks = <&pll1_div2_clk>, <0>,
760 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
761 #clock-cells = <0>;
762 };
763 hsi_clk: hsi@e615008c {
764 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
765 reg = <0xe615008c 4>;
766 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
767 <&pll1_div7_clk>, <0>;
768 #clock-cells = <0>;
769 };
770 mfg1_clk: mfg1@e6150098 {
771 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
772 reg = <0xe6150098 4>;
773 clocks = <&pll1_div2_clk>, <0>,
774 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
775 #clock-cells = <0>;
776 };
777 mfg2_clk: mfg2@e615009c {
778 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
779 reg = <0xe615009c 4>;
780 clocks = <&pll1_div2_clk>, <0>,
781 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
782 #clock-cells = <0>;
783 };
784 dsit_clk: dsit@e6150060 {
785 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
786 reg = <0xe6150060 4>;
787 clocks = <&pll1_div2_clk>, <0>,
788 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
789 #clock-cells = <0>;
790 };
791 dsi0p_clk: dsi0pck@e6150064 {
792 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
793 reg = <0xe6150064 4>;
794 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
795 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
796 <&extcki_clk>, <0>, <0>, <0>;
797 #clock-cells = <0>;
798 };
799
800 /* Fixed factor clocks */
801 main_div2_clk: main_div2 {
802 compatible = "fixed-factor-clock";
803 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
804 #clock-cells = <0>;
805 clock-div = <2>;
806 clock-mult = <1>;
807 };
808 pll1_div2_clk: pll1_div2 {
809 compatible = "fixed-factor-clock";
810 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
811 #clock-cells = <0>;
812 clock-div = <2>;
813 clock-mult = <1>;
814 };
815 pll1_div7_clk: pll1_div7 {
816 compatible = "fixed-factor-clock";
817 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
818 #clock-cells = <0>;
819 clock-div = <7>;
820 clock-mult = <1>;
821 };
822 pll1_div13_clk: pll1_div13 {
823 compatible = "fixed-factor-clock";
824 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
825 #clock-cells = <0>;
826 clock-div = <13>;
827 clock-mult = <1>;
828 };
829 periph_clk: periph {
830 compatible = "fixed-factor-clock";
831 clocks = <&cpg_clocks SH73A0_CLK_Z>;
832 #clock-cells = <0>;
833 clock-div = <4>;
834 clock-mult = <1>;
835 };
836
837 /* Gate clocks */
838 mstp0_clks: mstp0_clks@e6150130 {
839 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
840 reg = <0xe6150130 4>, <0xe6150030 4>;
841 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
842 #clock-cells = <1>;
843 clock-indices = <
844 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
845 >;
846 clock-output-names =
847 "iic2", "msiof0";
848 };
849 mstp1_clks: mstp1_clks@e6150134 {
850 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
851 reg = <0xe6150134 4>, <0xe6150038 4>;
852 clocks = <&cpg_clocks SH73A0_CLK_B>,
853 <&cpg_clocks SH73A0_CLK_B>,
854 <&cpg_clocks SH73A0_CLK_B>,
855 <&cpg_clocks SH73A0_CLK_B>,
856 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
857 <&cpg_clocks SH73A0_CLK_HP>,
858 <&cpg_clocks SH73A0_CLK_ZG>,
859 <&cpg_clocks SH73A0_CLK_B>;
860 #clock-cells = <1>;
861 clock-indices = <
862 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
863 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
864 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
865 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
866 SH73A0_CLK_LCDC0
867 >;
868 clock-output-names =
869 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
870 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
871 };
872 mstp2_clks: mstp2_clks@e6150138 {
873 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
874 reg = <0xe6150138 4>, <0xe6150040 4>;
875 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
876 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
877 <&sub_clk>, <&sub_clk>, <&sub_clk>,
878 <&sub_clk>, <&sub_clk>, <&sub_clk>,
879 <&sub_clk>, <&sub_clk>, <&sub_clk>;
880 #clock-cells = <1>;
881 clock-indices = <
882 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
883 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
884 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
885 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
886 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
887 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
888 SH73A0_CLK_SCIFA4
889 >;
890 clock-output-names =
891 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
892 "msiof1", "scifa5", "scifb", "msiof2",
893 "scifa0", "scifa1", "scifa2", "scifa3",
894 "scifa4";
895 };
896 mstp3_clks: mstp3_clks@e615013c {
897 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
898 reg = <0xe615013c 4>, <0xe6150048 4>;
899 clocks = <&sub_clk>, <&extalr_clk>,
900 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
901 <&cpg_clocks SH73A0_CLK_HP>,
902 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
903 <&sdhi0_clk>, <&sdhi1_clk>,
904 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
905 <&main_div2_clk>, <&main_div2_clk>,
906 <&main_div2_clk>, <&main_div2_clk>,
907 <&main_div2_clk>;
908 #clock-cells = <1>;
909 clock-indices = <
910 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
911 SH73A0_CLK_FSI SH73A0_CLK_IRDA
912 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
913 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
914 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
915 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
916 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
917 SH73A0_CLK_TPU4
918 >;
919 clock-output-names =
920 "scifa6", "cmt1", "fsi", "irda", "iic1",
921 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
922 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
923 };
924 mstp4_clks: mstp4_clks@e6150140 {
925 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
926 reg = <0xe6150140 4>, <0xe615004c 4>;
927 clocks = <&cpg_clocks SH73A0_CLK_HP>,
928 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
929 #clock-cells = <1>;
930 clock-indices = <
931 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
932 SH73A0_CLK_KEYSC
933 >;
934 clock-output-names =
935 "iic3", "iic4", "keysc";
936 };
937 mstp5_clks: mstp5_clks@e6150144 {
938 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
939 reg = <0xe6150144 4>, <0xe615003c 4>;
940 clocks = <&cpg_clocks SH73A0_CLK_HP>;
941 #clock-cells = <1>;
942 clock-indices = <
943 SH73A0_CLK_INTCA0
944 >;
945 clock-output-names =
946 "intca0";
947 };
948 };
949};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */
7
8#include <dt-bindings/clock/sh73a0-clock.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13 compatible = "renesas,sh73a0";
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a9";
25 reg = <0>;
26 clock-frequency = <1196000000>;
27 clocks = <&cpg_clocks SH73A0_CLK_Z>;
28 power-domains = <&pd_a2sl>;
29 next-level-cache = <&L2>;
30 };
31 cpu1: cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 reg = <1>;
35 clock-frequency = <1196000000>;
36 clocks = <&cpg_clocks SH73A0_CLK_Z>;
37 power-domains = <&pd_a2sl>;
38 next-level-cache = <&L2>;
39 };
40 };
41
42 timer@f0000600 {
43 compatible = "arm,cortex-a9-twd-timer";
44 reg = <0xf0000600 0x20>;
45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
46 clocks = <&twd_clk>;
47 };
48
49 gic: interrupt-controller@f0001000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
53 reg = <0xf0001000 0x1000>,
54 <0xf0000100 0x100>;
55 };
56
57 L2: cache-controller@f0100000 {
58 compatible = "arm,pl310-cache";
59 reg = <0xf0100000 0x1000>;
60 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
61 power-domains = <&pd_a3sm>;
62 arm,data-latency = <3 3 3>;
63 arm,tag-latency = <2 2 2>;
64 arm,shared-override;
65 cache-unified;
66 cache-level = <2>;
67 };
68
69 sbsc2: memory-controller@fb400000 {
70 compatible = "renesas,sbsc-sh73a0";
71 reg = <0xfb400000 0x400>;
72 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-names = "sec", "temp";
75 power-domains = <&pd_a4bc1>;
76 };
77
78 sbsc1: memory-controller@fe400000 {
79 compatible = "renesas,sbsc-sh73a0";
80 reg = <0xfe400000 0x400>;
81 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-names = "sec", "temp";
84 power-domains = <&pd_a4bc0>;
85 };
86
87 pmu {
88 compatible = "arm,cortex-a9-pmu";
89 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
91 interrupt-affinity = <&cpu0>, <&cpu1>;
92 };
93
94 cmt1: timer@e6138000 {
95 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
96 reg = <0xe6138000 0x200>;
97 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
99 clock-names = "fck";
100 power-domains = <&pd_c5>;
101 status = "disabled";
102 };
103
104 irqpin0: interrupt-controller@e6900000 {
105 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
106 #interrupt-cells = <2>;
107 interrupt-controller;
108 reg = <0xe6900000 4>,
109 <0xe6900010 4>,
110 <0xe6900020 1>,
111 <0xe6900040 1>,
112 <0xe6900060 1>;
113 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
114 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
115 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
116 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
117 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
118 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
122 power-domains = <&pd_a4s>;
123 control-parent;
124 };
125
126 irqpin1: interrupt-controller@e6900004 {
127 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
128 #interrupt-cells = <2>;
129 interrupt-controller;
130 reg = <0xe6900004 4>,
131 <0xe6900014 4>,
132 <0xe6900024 1>,
133 <0xe6900044 1>,
134 <0xe6900064 1>;
135 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
136 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
137 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
138 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
139 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
144 power-domains = <&pd_a4s>;
145 control-parent;
146 };
147
148 irqpin2: interrupt-controller@e6900008 {
149 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
150 #interrupt-cells = <2>;
151 interrupt-controller;
152 reg = <0xe6900008 4>,
153 <0xe6900018 4>,
154 <0xe6900028 1>,
155 <0xe6900048 1>,
156 <0xe6900068 1>;
157 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
158 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
159 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
160 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
161 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
162 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
163 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
164 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
166 power-domains = <&pd_a4s>;
167 control-parent;
168 };
169
170 irqpin3: interrupt-controller@e690000c {
171 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
172 #interrupt-cells = <2>;
173 interrupt-controller;
174 reg = <0xe690000c 4>,
175 <0xe690001c 4>,
176 <0xe690002c 1>,
177 <0xe690004c 1>,
178 <0xe690006c 1>;
179 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
180 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
181 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
182 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
183 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
184 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
185 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
186 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
188 power-domains = <&pd_a4s>;
189 control-parent;
190 };
191
192 i2c0: i2c@e6820000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
196 reg = <0xe6820000 0x425>;
197 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
198 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
199 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
200 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
202 power-domains = <&pd_a3sp>;
203 status = "disabled";
204 };
205
206 i2c1: i2c@e6822000 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
210 reg = <0xe6822000 0x425>;
211 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
212 GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
213 GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
214 GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
216 power-domains = <&pd_a3sp>;
217 status = "disabled";
218 };
219
220 i2c2: i2c@e6824000 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
224 reg = <0xe6824000 0x425>;
225 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
226 GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
227 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
228 GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
230 power-domains = <&pd_a3sp>;
231 status = "disabled";
232 };
233
234 i2c3: i2c@e6826000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
238 reg = <0xe6826000 0x425>;
239 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
240 GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
241 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
244 power-domains = <&pd_a3sp>;
245 status = "disabled";
246 };
247
248 i2c4: i2c@e6828000 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
252 reg = <0xe6828000 0x425>;
253 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
254 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
255 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
256 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
258 power-domains = <&pd_c5>;
259 status = "disabled";
260 };
261
262 mmcif: mmc@e6bd0000 {
263 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
264 reg = <0xe6bd0000 0x100>;
265 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
266 GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
268 power-domains = <&pd_a3sp>;
269 reg-io-width = <4>;
270 status = "disabled";
271 };
272
273 msiof0: spi@e6e20000 {
274 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
275 reg = <0xe6e20000 0x0064>;
276 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
278 power-domains = <&pd_a3sp>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 status = "disabled";
282 };
283
284 msiof1: spi@e6e10000 {
285 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
286 reg = <0xe6e10000 0x0064>;
287 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
289 power-domains = <&pd_a3sp>;
290 #address-cells = <1>;
291 #size-cells = <0>;
292 status = "disabled";
293 };
294
295 msiof2: spi@e6e00000 {
296 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
297 reg = <0xe6e00000 0x0064>;
298 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
300 power-domains = <&pd_a3sp>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 status = "disabled";
304 };
305
306 msiof3: spi@e6c90000 {
307 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
308 reg = <0xe6c90000 0x0064>;
309 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
311 power-domains = <&pd_a3sp>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 status = "disabled";
315 };
316
317 sdhi0: sd@ee100000 {
318 compatible = "renesas,sdhi-sh73a0";
319 reg = <0xee100000 0x100>;
320 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
324 power-domains = <&pd_a3sp>;
325 cap-sd-highspeed;
326 status = "disabled";
327 };
328
329 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
330 sdhi1: sd@ee120000 {
331 compatible = "renesas,sdhi-sh73a0";
332 reg = <0xee120000 0x100>;
333 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
336 power-domains = <&pd_a3sp>;
337 disable-wp;
338 cap-sd-highspeed;
339 status = "disabled";
340 };
341
342 sdhi2: sd@ee140000 {
343 compatible = "renesas,sdhi-sh73a0";
344 reg = <0xee140000 0x100>;
345 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
348 power-domains = <&pd_a3sp>;
349 disable-wp;
350 cap-sd-highspeed;
351 status = "disabled";
352 };
353
354 scifa0: serial@e6c40000 {
355 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
356 reg = <0xe6c40000 0x100>;
357 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
359 clock-names = "fck";
360 power-domains = <&pd_a3sp>;
361 status = "disabled";
362 };
363
364 scifa1: serial@e6c50000 {
365 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
366 reg = <0xe6c50000 0x100>;
367 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
369 clock-names = "fck";
370 power-domains = <&pd_a3sp>;
371 status = "disabled";
372 };
373
374 scifa2: serial@e6c60000 {
375 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
376 reg = <0xe6c60000 0x100>;
377 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
379 clock-names = "fck";
380 power-domains = <&pd_a3sp>;
381 status = "disabled";
382 };
383
384 scifa3: serial@e6c70000 {
385 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
386 reg = <0xe6c70000 0x100>;
387 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
389 clock-names = "fck";
390 power-domains = <&pd_a3sp>;
391 status = "disabled";
392 };
393
394 scifa4: serial@e6c80000 {
395 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
396 reg = <0xe6c80000 0x100>;
397 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
399 clock-names = "fck";
400 power-domains = <&pd_a3sp>;
401 status = "disabled";
402 };
403
404 scifa5: serial@e6cb0000 {
405 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
406 reg = <0xe6cb0000 0x100>;
407 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
409 clock-names = "fck";
410 power-domains = <&pd_a3sp>;
411 status = "disabled";
412 };
413
414 scifa6: serial@e6cc0000 {
415 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
416 reg = <0xe6cc0000 0x100>;
417 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
419 clock-names = "fck";
420 power-domains = <&pd_a3sp>;
421 status = "disabled";
422 };
423
424 scifa7: serial@e6cd0000 {
425 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
426 reg = <0xe6cd0000 0x100>;
427 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
429 clock-names = "fck";
430 power-domains = <&pd_a3sp>;
431 status = "disabled";
432 };
433
434 scifb: serial@e6c30000 {
435 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
436 reg = <0xe6c30000 0x100>;
437 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
439 clock-names = "fck";
440 power-domains = <&pd_a3sp>;
441 status = "disabled";
442 };
443
444 pfc: pin-controller@e6050000 {
445 compatible = "renesas,pfc-sh73a0";
446 reg = <0xe6050000 0x8000>,
447 <0xe605801c 0x1c>;
448 gpio-controller;
449 #gpio-cells = <2>;
450 gpio-ranges =
451 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
452 <&pfc 288 288 22>;
453 interrupts-extended =
454 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
455 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
456 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
457 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
458 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
459 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
460 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
461 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
462 power-domains = <&pd_c5>;
463 };
464
465 sysc: system-controller@e6180000 {
466 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
467 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
468
469 pm-domains {
470 pd_c5: c5 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 #power-domain-cells = <0>;
474
475 pd_c4: c4@0 {
476 reg = <0>;
477 #power-domain-cells = <0>;
478 };
479
480 pd_d4: d4@1 {
481 reg = <1>;
482 #power-domain-cells = <0>;
483 };
484
485 pd_a4bc0: a4bc0@4 {
486 reg = <4>;
487 #power-domain-cells = <0>;
488 };
489
490 pd_a4bc1: a4bc1@5 {
491 reg = <5>;
492 #power-domain-cells = <0>;
493 };
494
495 pd_a4lc0: a4lc0@6 {
496 reg = <6>;
497 #power-domain-cells = <0>;
498 };
499
500 pd_a4lc1: a4lc1@7 {
501 reg = <7>;
502 #power-domain-cells = <0>;
503 };
504
505 pd_a4mp: a4mp@8 {
506 reg = <8>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 #power-domain-cells = <0>;
510
511 pd_a3mp: a3mp@9 {
512 reg = <9>;
513 #power-domain-cells = <0>;
514 };
515
516 pd_a3vc: a3vc@10 {
517 reg = <10>;
518 #power-domain-cells = <0>;
519 };
520 };
521
522 pd_a4rm: a4rm@12 {
523 reg = <12>;
524 #address-cells = <1>;
525 #size-cells = <0>;
526 #power-domain-cells = <0>;
527
528 pd_a3r: a3r@13 {
529 reg = <13>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <0>;
533
534 pd_a2rv: a2rv@14 {
535 reg = <14>;
536 #address-cells = <1>;
537 #size-cells = <0>;
538 #power-domain-cells = <0>;
539 };
540 };
541 };
542
543 pd_a4s: a4s@16 {
544 reg = <16>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 #power-domain-cells = <0>;
548
549 pd_a3sp: a3sp@17 {
550 reg = <17>;
551 #power-domain-cells = <0>;
552 };
553
554 pd_a3sg: a3sg@18 {
555 reg = <18>;
556 #power-domain-cells = <0>;
557 };
558
559 pd_a3sm: a3sm@19 {
560 reg = <19>;
561 #address-cells = <1>;
562 #size-cells = <0>;
563 #power-domain-cells = <0>;
564
565 pd_a2sl: a2sl@20 {
566 reg = <20>;
567 #power-domain-cells = <0>;
568 };
569 };
570 };
571 };
572 };
573 };
574
575 sh_fsi2: sound@ec230000 {
576 #sound-dai-cells = <1>;
577 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
578 reg = <0xec230000 0x400>;
579 interrupts = <GIC_SPI 146 0x4>;
580 power-domains = <&pd_a4mp>;
581 status = "disabled";
582 };
583
584 bsc: bus@fec10000 {
585 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
586 "simple-pm-bus";
587 #address-cells = <1>;
588 #size-cells = <1>;
589 ranges = <0 0 0x20000000>;
590 reg = <0xfec10000 0x400>;
591 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&zb_clk>;
593 power-domains = <&pd_a4s>;
594 };
595
596 clocks {
597 #address-cells = <1>;
598 #size-cells = <1>;
599 ranges;
600
601 /* External root clocks */
602 extalr_clk: extalr {
603 compatible = "fixed-clock";
604 #clock-cells = <0>;
605 clock-frequency = <32768>;
606 };
607 extal1_clk: extal1 {
608 compatible = "fixed-clock";
609 #clock-cells = <0>;
610 clock-frequency = <26000000>;
611 };
612 extal2_clk: extal2 {
613 compatible = "fixed-clock";
614 #clock-cells = <0>;
615 };
616 extcki_clk: extcki {
617 compatible = "fixed-clock";
618 #clock-cells = <0>;
619 };
620 fsiack_clk: fsiack {
621 compatible = "fixed-clock";
622 #clock-cells = <0>;
623 clock-frequency = <0>;
624 };
625 fsibck_clk: fsibck {
626 compatible = "fixed-clock";
627 #clock-cells = <0>;
628 clock-frequency = <0>;
629 };
630
631 /* Special CPG clocks */
632 cpg_clocks: cpg_clocks@e6150000 {
633 compatible = "renesas,sh73a0-cpg-clocks";
634 reg = <0xe6150000 0x10000>;
635 clocks = <&extal1_clk>, <&extal2_clk>;
636 #clock-cells = <1>;
637 clock-output-names = "main", "pll0", "pll1", "pll2",
638 "pll3", "dsi0phy", "dsi1phy",
639 "zg", "m3", "b", "m1", "m2",
640 "z", "zx", "hp";
641 };
642
643 /* Variable factor clocks (DIV6) */
644 vclk1_clk: vclk1@e6150008 {
645 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
646 reg = <0xe6150008 4>;
647 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
648 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
649 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
650 <0>;
651 #clock-cells = <0>;
652 };
653 vclk2_clk: vclk2@e615000c {
654 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
655 reg = <0xe615000c 4>;
656 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
657 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
658 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
659 <0>;
660 #clock-cells = <0>;
661 };
662 vclk3_clk: vclk3@e615001c {
663 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
664 reg = <0xe615001c 4>;
665 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
666 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
667 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
668 <0>;
669 #clock-cells = <0>;
670 };
671 zb_clk: zb_clk@e6150010 {
672 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
673 reg = <0xe6150010 4>;
674 clocks = <&pll1_div2_clk>, <0>,
675 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
676 #clock-cells = <0>;
677 clock-output-names = "zb";
678 };
679 flctl_clk: flctlck@e6150014 {
680 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
681 reg = <0xe6150014 4>;
682 clocks = <&pll1_div2_clk>, <0>,
683 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
684 #clock-cells = <0>;
685 };
686 sdhi0_clk: sdhi0ck@e6150074 {
687 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
688 reg = <0xe6150074 4>;
689 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
690 <&pll1_div13_clk>, <0>;
691 #clock-cells = <0>;
692 };
693 sdhi1_clk: sdhi1ck@e6150078 {
694 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
695 reg = <0xe6150078 4>;
696 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
697 <&pll1_div13_clk>, <0>;
698 #clock-cells = <0>;
699 };
700 sdhi2_clk: sdhi2ck@e615007c {
701 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
702 reg = <0xe615007c 4>;
703 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
704 <&pll1_div13_clk>, <0>;
705 #clock-cells = <0>;
706 };
707 fsia_clk: fsia@e6150018 {
708 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
709 reg = <0xe6150018 4>;
710 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
711 <&fsiack_clk>, <&fsiack_clk>;
712 #clock-cells = <0>;
713 };
714 fsib_clk: fsib@e6150090 {
715 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
716 reg = <0xe6150090 4>;
717 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
718 <&fsibck_clk>, <&fsibck_clk>;
719 #clock-cells = <0>;
720 };
721 sub_clk: sub@e6150080 {
722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
723 reg = <0xe6150080 4>;
724 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
725 <&extal2_clk>, <&extal2_clk>;
726 #clock-cells = <0>;
727 };
728 spua_clk: spua@e6150084 {
729 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
730 reg = <0xe6150084 4>;
731 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
732 <&extal2_clk>, <&extal2_clk>;
733 #clock-cells = <0>;
734 };
735 spuv_clk: spuv@e6150094 {
736 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
737 reg = <0xe6150094 4>;
738 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
739 <&extal2_clk>, <&extal2_clk>;
740 #clock-cells = <0>;
741 };
742 msu_clk: msu@e6150088 {
743 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
744 reg = <0xe6150088 4>;
745 clocks = <&pll1_div2_clk>, <0>,
746 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
747 #clock-cells = <0>;
748 };
749 hsi_clk: hsi@e615008c {
750 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
751 reg = <0xe615008c 4>;
752 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
753 <&pll1_div7_clk>, <0>;
754 #clock-cells = <0>;
755 };
756 mfg1_clk: mfg1@e6150098 {
757 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
758 reg = <0xe6150098 4>;
759 clocks = <&pll1_div2_clk>, <0>,
760 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
761 #clock-cells = <0>;
762 };
763 mfg2_clk: mfg2@e615009c {
764 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
765 reg = <0xe615009c 4>;
766 clocks = <&pll1_div2_clk>, <0>,
767 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
768 #clock-cells = <0>;
769 };
770 dsit_clk: dsit@e6150060 {
771 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
772 reg = <0xe6150060 4>;
773 clocks = <&pll1_div2_clk>, <0>,
774 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
775 #clock-cells = <0>;
776 };
777 dsi0p_clk: dsi0pck@e6150064 {
778 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
779 reg = <0xe6150064 4>;
780 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
781 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
782 <&extcki_clk>, <0>, <0>, <0>;
783 #clock-cells = <0>;
784 };
785
786 /* Fixed factor clocks */
787 main_div2_clk: main_div2 {
788 compatible = "fixed-factor-clock";
789 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
790 #clock-cells = <0>;
791 clock-div = <2>;
792 clock-mult = <1>;
793 };
794 pll1_div2_clk: pll1_div2 {
795 compatible = "fixed-factor-clock";
796 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
797 #clock-cells = <0>;
798 clock-div = <2>;
799 clock-mult = <1>;
800 };
801 pll1_div7_clk: pll1_div7 {
802 compatible = "fixed-factor-clock";
803 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
804 #clock-cells = <0>;
805 clock-div = <7>;
806 clock-mult = <1>;
807 };
808 pll1_div13_clk: pll1_div13 {
809 compatible = "fixed-factor-clock";
810 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
811 #clock-cells = <0>;
812 clock-div = <13>;
813 clock-mult = <1>;
814 };
815 twd_clk: twd {
816 compatible = "fixed-factor-clock";
817 clocks = <&cpg_clocks SH73A0_CLK_Z>;
818 #clock-cells = <0>;
819 clock-div = <4>;
820 clock-mult = <1>;
821 };
822
823 /* Gate clocks */
824 mstp0_clks: mstp0_clks@e6150130 {
825 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
826 reg = <0xe6150130 4>, <0xe6150030 4>;
827 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
828 #clock-cells = <1>;
829 clock-indices = <
830 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
831 >;
832 clock-output-names =
833 "iic2", "msiof0";
834 };
835 mstp1_clks: mstp1_clks@e6150134 {
836 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
837 reg = <0xe6150134 4>, <0xe6150038 4>;
838 clocks = <&cpg_clocks SH73A0_CLK_B>,
839 <&cpg_clocks SH73A0_CLK_B>,
840 <&cpg_clocks SH73A0_CLK_B>,
841 <&cpg_clocks SH73A0_CLK_B>,
842 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
843 <&cpg_clocks SH73A0_CLK_HP>,
844 <&cpg_clocks SH73A0_CLK_ZG>,
845 <&cpg_clocks SH73A0_CLK_B>;
846 #clock-cells = <1>;
847 clock-indices = <
848 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
849 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
850 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
851 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
852 SH73A0_CLK_LCDC0
853 >;
854 clock-output-names =
855 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
856 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
857 };
858 mstp2_clks: mstp2_clks@e6150138 {
859 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
860 reg = <0xe6150138 4>, <0xe6150040 4>;
861 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
862 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
863 <&sub_clk>, <&sub_clk>, <&sub_clk>,
864 <&sub_clk>, <&sub_clk>, <&sub_clk>,
865 <&sub_clk>, <&sub_clk>, <&sub_clk>;
866 #clock-cells = <1>;
867 clock-indices = <
868 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
869 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
870 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
871 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
872 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
873 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
874 SH73A0_CLK_SCIFA4
875 >;
876 clock-output-names =
877 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
878 "msiof1", "scifa5", "scifb", "msiof2",
879 "scifa0", "scifa1", "scifa2", "scifa3",
880 "scifa4";
881 };
882 mstp3_clks: mstp3_clks@e615013c {
883 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
884 reg = <0xe615013c 4>, <0xe6150048 4>;
885 clocks = <&sub_clk>, <&extalr_clk>,
886 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
887 <&cpg_clocks SH73A0_CLK_HP>,
888 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
889 <&sdhi0_clk>, <&sdhi1_clk>,
890 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
891 <&main_div2_clk>, <&main_div2_clk>,
892 <&main_div2_clk>, <&main_div2_clk>,
893 <&main_div2_clk>;
894 #clock-cells = <1>;
895 clock-indices = <
896 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
897 SH73A0_CLK_FSI SH73A0_CLK_IRDA
898 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
899 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
900 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
901 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
902 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
903 SH73A0_CLK_TPU4
904 >;
905 clock-output-names =
906 "scifa6", "cmt1", "fsi", "irda", "iic1",
907 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
908 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
909 };
910 mstp4_clks: mstp4_clks@e6150140 {
911 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
912 reg = <0xe6150140 4>, <0xe615004c 4>;
913 clocks = <&cpg_clocks SH73A0_CLK_HP>,
914 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
915 #clock-cells = <1>;
916 clock-indices = <
917 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
918 SH73A0_CLK_KEYSC
919 >;
920 clock-output-names =
921 "iic3", "iic4", "keysc";
922 };
923 mstp5_clks: mstp5_clks@e6150144 {
924 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
925 reg = <0xe6150144 4>, <0xe615003c 4>;
926 clocks = <&cpg_clocks SH73A0_CLK_HP>;
927 #clock-cells = <1>;
928 clock-indices = <
929 SH73A0_CLK_INTCA0
930 >;
931 clock-output-names =
932 "intca0";
933 };
934 };
935};