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1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2014 Carlo Caione <carlo@caione.org>
4 */
5
6#include <dt-bindings/clock/meson8-ddr-clkc.h>
7#include <dt-bindings/clock/meson8b-clkc.h>
8#include <dt-bindings/gpio/meson8-gpio.h>
9#include <dt-bindings/power/meson8-power.h>
10#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11#include <dt-bindings/reset/amlogic,meson8b-reset.h>
12#include <dt-bindings/thermal/thermal.h>
13#include "meson.dtsi"
14
15/ {
16 model = "Amlogic Meson8 SoC";
17 compatible = "amlogic,meson8";
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu0: cpu@200 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a9";
26 next-level-cache = <&L2>;
27 reg = <0x200>;
28 enable-method = "amlogic,meson8-smp";
29 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
30 operating-points-v2 = <&cpu_opp_table>;
31 clocks = <&clkc CLKID_CPUCLK>;
32 #cooling-cells = <2>; /* min followed by max */
33 };
34
35 cpu1: cpu@201 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 reg = <0x201>;
40 enable-method = "amlogic,meson8-smp";
41 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
42 operating-points-v2 = <&cpu_opp_table>;
43 clocks = <&clkc CLKID_CPUCLK>;
44 #cooling-cells = <2>; /* min followed by max */
45 };
46
47 cpu2: cpu@202 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
51 reg = <0x202>;
52 enable-method = "amlogic,meson8-smp";
53 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
54 operating-points-v2 = <&cpu_opp_table>;
55 clocks = <&clkc CLKID_CPUCLK>;
56 #cooling-cells = <2>; /* min followed by max */
57 };
58
59 cpu3: cpu@203 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
63 reg = <0x203>;
64 enable-method = "amlogic,meson8-smp";
65 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
66 operating-points-v2 = <&cpu_opp_table>;
67 clocks = <&clkc CLKID_CPUCLK>;
68 #cooling-cells = <2>; /* min followed by max */
69 };
70 };
71
72 cpu_opp_table: opp-table {
73 compatible = "operating-points-v2";
74 opp-shared;
75
76 opp-96000000 {
77 opp-hz = /bits/ 64 <96000000>;
78 opp-microvolt = <825000>;
79 };
80 opp-192000000 {
81 opp-hz = /bits/ 64 <192000000>;
82 opp-microvolt = <825000>;
83 };
84 opp-312000000 {
85 opp-hz = /bits/ 64 <312000000>;
86 opp-microvolt = <825000>;
87 };
88 opp-408000000 {
89 opp-hz = /bits/ 64 <408000000>;
90 opp-microvolt = <825000>;
91 };
92 opp-504000000 {
93 opp-hz = /bits/ 64 <504000000>;
94 opp-microvolt = <825000>;
95 };
96 opp-600000000 {
97 opp-hz = /bits/ 64 <600000000>;
98 opp-microvolt = <850000>;
99 };
100 opp-720000000 {
101 opp-hz = /bits/ 64 <720000000>;
102 opp-microvolt = <850000>;
103 };
104 opp-816000000 {
105 opp-hz = /bits/ 64 <816000000>;
106 opp-microvolt = <875000>;
107 };
108 opp-1008000000 {
109 opp-hz = /bits/ 64 <1008000000>;
110 opp-microvolt = <925000>;
111 };
112 opp-1200000000 {
113 opp-hz = /bits/ 64 <1200000000>;
114 opp-microvolt = <975000>;
115 };
116 opp-1416000000 {
117 opp-hz = /bits/ 64 <1416000000>;
118 opp-microvolt = <1025000>;
119 };
120 opp-1608000000 {
121 opp-hz = /bits/ 64 <1608000000>;
122 opp-microvolt = <1100000>;
123 };
124 opp-1800000000 {
125 status = "disabled";
126 opp-hz = /bits/ 64 <1800000000>;
127 opp-microvolt = <1125000>;
128 };
129 opp-1992000000 {
130 status = "disabled";
131 opp-hz = /bits/ 64 <1992000000>;
132 opp-microvolt = <1150000>;
133 };
134 };
135
136 gpu_opp_table: gpu-opp-table {
137 compatible = "operating-points-v2";
138
139 opp-182142857 {
140 opp-hz = /bits/ 64 <182142857>;
141 opp-microvolt = <1150000>;
142 };
143 opp-318750000 {
144 opp-hz = /bits/ 64 <318750000>;
145 opp-microvolt = <1150000>;
146 };
147 opp-425000000 {
148 opp-hz = /bits/ 64 <425000000>;
149 opp-microvolt = <1150000>;
150 };
151 opp-510000000 {
152 opp-hz = /bits/ 64 <510000000>;
153 opp-microvolt = <1150000>;
154 };
155 opp-637500000 {
156 opp-hz = /bits/ 64 <637500000>;
157 opp-microvolt = <1150000>;
158 turbo-mode;
159 };
160 };
161
162 pmu {
163 compatible = "arm,cortex-a9-pmu";
164 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
168 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
169 };
170
171 reserved-memory {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 ranges;
175
176 /* 2 MiB reserved for Hardware ROM Firmware? */
177 hwrom@0 {
178 reg = <0x0 0x200000>;
179 no-map;
180 };
181
182 /*
183 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
184 * code which is responsible for system suspend. It loads a
185 * piece of ARC code ("arc_power" in the vendor u-boot tree)
186 * into SRAM, executes that and shuts down the (last) ARM core.
187 * The arc_power firmware then checks various wakeup sources
188 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
189 * simply the power key) and re-starts the ARM core once it
190 * detects a wakeup request.
191 */
192 power-firmware@4f00000 {
193 reg = <0x4f00000 0x100000>;
194 no-map;
195 };
196 };
197
198 thermal-zones {
199 soc {
200 polling-delay-passive = <250>; /* milliseconds */
201 polling-delay = <1000>; /* milliseconds */
202 thermal-sensors = <&thermal_sensor>;
203
204 cooling-maps {
205 map0 {
206 trip = <&soc_passive>;
207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
210 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
211 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
212 };
213
214 map1 {
215 trip = <&soc_hot>;
216 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
217 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
218 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
219 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
220 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
221 };
222 };
223
224 trips {
225 soc_passive: soc-passive {
226 temperature = <80000>; /* millicelsius */
227 hysteresis = <2000>; /* millicelsius */
228 type = "passive";
229 };
230
231 soc_hot: soc-hot {
232 temperature = <90000>; /* millicelsius */
233 hysteresis = <2000>; /* millicelsius */
234 type = "hot";
235 };
236
237 soc_critical: soc-critical {
238 temperature = <110000>; /* millicelsius */
239 hysteresis = <2000>; /* millicelsius */
240 type = "critical";
241 };
242 };
243 };
244 };
245
246 mmcbus: bus@c8000000 {
247 compatible = "simple-bus";
248 reg = <0xc8000000 0x8000>;
249 #address-cells = <1>;
250 #size-cells = <1>;
251 ranges = <0x0 0xc8000000 0x8000>;
252
253 ddr_clkc: clock-controller@400 {
254 compatible = "amlogic,meson8-ddr-clkc";
255 reg = <0x400 0x20>;
256 clocks = <&xtal>;
257 clock-names = "xtal";
258 #clock-cells = <1>;
259 };
260
261 dmcbus: bus@6000 {
262 compatible = "simple-bus";
263 reg = <0x6000 0x400>;
264 #address-cells = <1>;
265 #size-cells = <1>;
266 ranges = <0x0 0x6000 0x400>;
267
268 canvas: video-lut@20 {
269 compatible = "amlogic,meson8-canvas",
270 "amlogic,canvas";
271 reg = <0x20 0x14>;
272 };
273 };
274 };
275
276 apb: bus@d0000000 {
277 compatible = "simple-bus";
278 reg = <0xd0000000 0x200000>;
279 #address-cells = <1>;
280 #size-cells = <1>;
281 ranges = <0x0 0xd0000000 0x200000>;
282
283 mali: gpu@c0000 {
284 compatible = "amlogic,meson8-mali", "arm,mali-450";
285 reg = <0xc0000 0x40000>;
286 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-names = "gp", "gpmmu", "pp", "pmu",
303 "pp0", "ppmmu0", "pp1", "ppmmu1",
304 "pp2", "ppmmu2", "pp4", "ppmmu4",
305 "pp5", "ppmmu5", "pp6", "ppmmu6";
306 resets = <&reset RESET_MALI>;
307
308 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
309 clock-names = "bus", "core";
310
311 assigned-clocks = <&clkc CLKID_MALI>;
312 assigned-clock-rates = <318750000>;
313
314 operating-points-v2 = <&gpu_opp_table>;
315 #cooling-cells = <2>; /* min followed by max */
316 };
317 };
318}; /* end of / */
319
320&aobus {
321 pmu: pmu@e0 {
322 compatible = "amlogic,meson8-pmu", "syscon";
323 reg = <0xe0 0x18>;
324 };
325
326 pinctrl_aobus: pinctrl@84 {
327 compatible = "amlogic,meson8-aobus-pinctrl";
328 reg = <0x84 0xc>;
329 #address-cells = <1>;
330 #size-cells = <1>;
331 ranges;
332
333 gpio_ao: ao-bank@14 {
334 reg = <0x14 0x4>,
335 <0x2c 0x4>,
336 <0x24 0x8>;
337 reg-names = "mux", "pull", "gpio";
338 gpio-controller;
339 #gpio-cells = <2>;
340 gpio-ranges = <&pinctrl_aobus 0 0 16>;
341 };
342
343 uart_ao_a_pins: uart_ao_a {
344 mux {
345 groups = "uart_tx_ao_a", "uart_rx_ao_a";
346 function = "uart_ao";
347 bias-disable;
348 };
349 };
350
351 i2c_ao_pins: i2c_mst_ao {
352 mux {
353 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
354 function = "i2c_mst_ao";
355 bias-disable;
356 };
357 };
358
359 ir_recv_pins: remote {
360 mux {
361 groups = "remote_input";
362 function = "remote";
363 bias-disable;
364 };
365 };
366
367 pwm_f_ao_pins: pwm-f-ao {
368 mux {
369 groups = "pwm_f_ao";
370 function = "pwm_f_ao";
371 bias-disable;
372 };
373 };
374 };
375};
376
377&ao_arc_rproc {
378 compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
379 amlogic,secbus2 = <&secbus2>;
380 sram = <&ao_arc_sram>;
381 resets = <&reset RESET_MEDIA_CPU>;
382 clocks = <&clkc CLKID_AO_MEDIA_CPU>;
383};
384
385&cbus {
386 reset: reset-controller@4404 {
387 compatible = "amlogic,meson8b-reset";
388 reg = <0x4404 0x9c>;
389 #reset-cells = <1>;
390 };
391
392 analog_top: analog-top@81a8 {
393 compatible = "amlogic,meson8-analog-top", "syscon";
394 reg = <0x81a8 0x14>;
395 };
396
397 pwm_ef: pwm@86c0 {
398 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
399 reg = <0x86c0 0x10>;
400 #pwm-cells = <3>;
401 status = "disabled";
402 };
403
404 clock-measure@8758 {
405 compatible = "amlogic,meson8-clk-measure";
406 reg = <0x8758 0x1c>;
407 };
408
409 pinctrl_cbus: pinctrl@9880 {
410 compatible = "amlogic,meson8-cbus-pinctrl";
411 reg = <0x9880 0x10>;
412 #address-cells = <1>;
413 #size-cells = <1>;
414 ranges;
415
416 gpio: banks@80b0 {
417 reg = <0x80b0 0x28>,
418 <0x80e8 0x18>,
419 <0x8120 0x18>,
420 <0x8030 0x30>;
421 reg-names = "mux", "pull", "pull-enable", "gpio";
422 gpio-controller;
423 #gpio-cells = <2>;
424 gpio-ranges = <&pinctrl_cbus 0 0 120>;
425 };
426
427 sd_a_pins: sd-a {
428 mux {
429 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
430 "sd_d3_a", "sd_clk_a", "sd_cmd_a";
431 function = "sd_a";
432 bias-disable;
433 };
434 };
435
436 sd_b_pins: sd-b {
437 mux {
438 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
439 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
440 function = "sd_b";
441 bias-disable;
442 };
443 };
444
445 sd_c_pins: sd-c {
446 mux {
447 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
448 "sd_d3_c", "sd_clk_c", "sd_cmd_c";
449 function = "sd_c";
450 bias-disable;
451 };
452 };
453
454 sdxc_b_pins: sdxc-b {
455 mux {
456 groups = "sdxc_d0_b", "sdxc_d13_b",
457 "sdxc_clk_b", "sdxc_cmd_b";
458 function = "sdxc_b";
459 bias-pull-up;
460 };
461 };
462
463 spi_nor_pins: nor {
464 mux {
465 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
466 function = "nor";
467 bias-disable;
468 };
469 };
470
471 eth_pins: ethernet {
472 mux {
473 groups = "eth_tx_clk_50m", "eth_tx_en",
474 "eth_txd1", "eth_txd0",
475 "eth_rx_clk_in", "eth_rx_dv",
476 "eth_rxd1", "eth_rxd0", "eth_mdio",
477 "eth_mdc";
478 function = "ethernet";
479 bias-disable;
480 };
481 };
482
483 pwm_e_pins: pwm-e {
484 mux {
485 groups = "pwm_e";
486 function = "pwm_e";
487 bias-disable;
488 };
489 };
490
491 uart_a1_pins: uart-a1 {
492 mux {
493 groups = "uart_tx_a1",
494 "uart_rx_a1";
495 function = "uart_a";
496 bias-disable;
497 };
498 };
499
500 uart_a1_cts_rts_pins: uart-a1-cts-rts {
501 mux {
502 groups = "uart_cts_a1",
503 "uart_rts_a1";
504 function = "uart_a";
505 bias-disable;
506 };
507 };
508 };
509};
510
511&ahb_sram {
512 ao_arc_sram: ao-arc-sram@0 {
513 compatible = "amlogic,meson8-ao-arc-sram";
514 reg = <0x0 0x8000>;
515 pool;
516 };
517
518 smp-sram@1ff80 {
519 compatible = "amlogic,meson8-smp-sram";
520 reg = <0x1ff80 0x8>;
521 };
522};
523
524&efuse {
525 compatible = "amlogic,meson8-efuse";
526 clocks = <&clkc CLKID_EFUSE>;
527 clock-names = "core";
528
529 temperature_calib: calib@1f4 {
530 /* only the upper two bytes are relevant */
531 reg = <0x1f4 0x4>;
532 };
533};
534
535ðmac {
536 clocks = <&clkc CLKID_ETH>;
537 clock-names = "stmmaceth";
538
539 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
540};
541
542&gpio_intc {
543 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
544 status = "okay";
545};
546
547&hhi {
548 clkc: clock-controller {
549 compatible = "amlogic,meson8-clkc";
550 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
551 clock-names = "xtal", "ddr_pll";
552 #clock-cells = <1>;
553 #reset-cells = <1>;
554 };
555
556 pwrc: power-controller {
557 compatible = "amlogic,meson8-pwrc";
558 #power-domain-cells = <1>;
559 amlogic,ao-sysctrl = <&pmu>;
560 clocks = <&clkc CLKID_VPU>;
561 clock-names = "vpu";
562 assigned-clocks = <&clkc CLKID_VPU>;
563 assigned-clock-rates = <364285714>;
564 };
565};
566
567&hwrng {
568 compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
569 clocks = <&clkc CLKID_RNG0>;
570 clock-names = "core";
571};
572
573&i2c_AO {
574 clocks = <&clkc CLKID_CLK81>;
575};
576
577&i2c_A {
578 clocks = <&clkc CLKID_CLK81>;
579};
580
581&i2c_B {
582 clocks = <&clkc CLKID_CLK81>;
583};
584
585&L2 {
586 arm,data-latency = <3 3 3>;
587 arm,tag-latency = <2 2 2>;
588 arm,filter-ranges = <0x100000 0xc0000000>;
589 prefetch-data = <1>;
590 prefetch-instr = <1>;
591 arm,shared-override;
592};
593
594&periph {
595 scu@0 {
596 compatible = "arm,cortex-a9-scu";
597 reg = <0x0 0x100>;
598 };
599
600 timer@200 {
601 compatible = "arm,cortex-a9-global-timer";
602 reg = <0x200 0x20>;
603 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
604 clocks = <&clkc CLKID_PERIPH>;
605
606 /*
607 * the arm_global_timer driver currently does not handle clock
608 * rate changes. Keep it disabled for now.
609 */
610 status = "disabled";
611 };
612
613 timer@600 {
614 compatible = "arm,cortex-a9-twd-timer";
615 reg = <0x600 0x20>;
616 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
617 clocks = <&clkc CLKID_PERIPH>;
618 };
619};
620
621&pwm_ab {
622 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
623};
624
625&pwm_cd {
626 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
627};
628
629&rtc {
630 compatible = "amlogic,meson8-rtc";
631 resets = <&reset RESET_RTC>;
632};
633
634&saradc {
635 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
636 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
637 clock-names = "clkin", "core";
638 amlogic,hhi-sysctrl = <&hhi>;
639 nvmem-cells = <&temperature_calib>;
640 nvmem-cell-names = "temperature_calib";
641};
642
643&sdhc {
644 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
645 clocks = <&xtal>,
646 <&clkc CLKID_FCLK_DIV4>,
647 <&clkc CLKID_FCLK_DIV3>,
648 <&clkc CLKID_FCLK_DIV5>,
649 <&clkc CLKID_SDHC>;
650 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
651};
652
653&secbus {
654 secbus2: system-controller@4000 {
655 compatible = "amlogic,meson8-secbus2", "syscon";
656 reg = <0x4000 0x2000>;
657 };
658};
659
660&sdio {
661 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
662 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
663 clock-names = "core", "clkin";
664};
665
666&spifc {
667 clocks = <&clkc CLKID_CLK81>;
668};
669
670&timer_abcde {
671 clocks = <&xtal>, <&clkc CLKID_CLK81>;
672 clock-names = "xtal", "pclk";
673};
674
675&uart_AO {
676 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
677 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
678 clock-names = "baud", "xtal", "pclk";
679};
680
681&uart_A {
682 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
683 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
684 clock-names = "baud", "xtal", "pclk";
685};
686
687&uart_B {
688 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
689 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
690 clock-names = "baud", "xtal", "pclk";
691};
692
693&uart_C {
694 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
695 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
696 clock-names = "baud", "xtal", "pclk";
697};
698
699&usb0 {
700 compatible = "amlogic,meson8-usb", "snps,dwc2";
701 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
702 clock-names = "otg";
703};
704
705&usb1 {
706 compatible = "amlogic,meson8-usb", "snps,dwc2";
707 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
708 clock-names = "otg";
709};
710
711&usb0_phy {
712 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
713 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
714 clock-names = "usb_general", "usb";
715 resets = <&reset RESET_USB_OTG>;
716};
717
718&usb1_phy {
719 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
720 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
721 clock-names = "usb_general", "usb";
722 resets = <&reset RESET_USB_OTG>;
723};
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2014 Carlo Caione <carlo@caione.org>
4 */
5
6#include <dt-bindings/clock/meson8b-clkc.h>
7#include <dt-bindings/gpio/meson8-gpio.h>
8#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
9#include <dt-bindings/reset/amlogic,meson8b-reset.h>
10#include "meson.dtsi"
11
12/ {
13 model = "Amlogic Meson8 SoC";
14 compatible = "amlogic,meson8";
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu0: cpu@200 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 reg = <0x200>;
25 enable-method = "amlogic,meson8-smp";
26 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
27 operating-points-v2 = <&cpu_opp_table>;
28 clocks = <&clkc CLKID_CPUCLK>;
29 };
30
31 cpu1: cpu@201 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
35 reg = <0x201>;
36 enable-method = "amlogic,meson8-smp";
37 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
38 operating-points-v2 = <&cpu_opp_table>;
39 clocks = <&clkc CLKID_CPUCLK>;
40 };
41
42 cpu2: cpu@202 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 next-level-cache = <&L2>;
46 reg = <0x202>;
47 enable-method = "amlogic,meson8-smp";
48 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
49 operating-points-v2 = <&cpu_opp_table>;
50 clocks = <&clkc CLKID_CPUCLK>;
51 };
52
53 cpu3: cpu@203 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a9";
56 next-level-cache = <&L2>;
57 reg = <0x203>;
58 enable-method = "amlogic,meson8-smp";
59 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
60 operating-points-v2 = <&cpu_opp_table>;
61 clocks = <&clkc CLKID_CPUCLK>;
62 };
63 };
64
65 cpu_opp_table: opp-table {
66 compatible = "operating-points-v2";
67 opp-shared;
68
69 opp-96000000 {
70 opp-hz = /bits/ 64 <96000000>;
71 opp-microvolt = <825000>;
72 };
73 opp-192000000 {
74 opp-hz = /bits/ 64 <192000000>;
75 opp-microvolt = <825000>;
76 };
77 opp-312000000 {
78 opp-hz = /bits/ 64 <312000000>;
79 opp-microvolt = <825000>;
80 };
81 opp-408000000 {
82 opp-hz = /bits/ 64 <408000000>;
83 opp-microvolt = <825000>;
84 };
85 opp-504000000 {
86 opp-hz = /bits/ 64 <504000000>;
87 opp-microvolt = <825000>;
88 };
89 opp-600000000 {
90 opp-hz = /bits/ 64 <600000000>;
91 opp-microvolt = <850000>;
92 };
93 opp-720000000 {
94 opp-hz = /bits/ 64 <720000000>;
95 opp-microvolt = <850000>;
96 };
97 opp-816000000 {
98 opp-hz = /bits/ 64 <816000000>;
99 opp-microvolt = <875000>;
100 };
101 opp-1008000000 {
102 opp-hz = /bits/ 64 <1008000000>;
103 opp-microvolt = <925000>;
104 };
105 opp-1200000000 {
106 opp-hz = /bits/ 64 <1200000000>;
107 opp-microvolt = <975000>;
108 };
109 opp-1416000000 {
110 opp-hz = /bits/ 64 <1416000000>;
111 opp-microvolt = <1025000>;
112 };
113 opp-1608000000 {
114 opp-hz = /bits/ 64 <1608000000>;
115 opp-microvolt = <1100000>;
116 };
117 opp-1800000000 {
118 status = "disabled";
119 opp-hz = /bits/ 64 <1800000000>;
120 opp-microvolt = <1125000>;
121 };
122 opp-1992000000 {
123 status = "disabled";
124 opp-hz = /bits/ 64 <1992000000>;
125 opp-microvolt = <1150000>;
126 };
127 };
128
129 gpu_opp_table: gpu-opp-table {
130 compatible = "operating-points-v2";
131
132 opp-182150000 {
133 opp-hz = /bits/ 64 <182150000>;
134 opp-microvolt = <1150000>;
135 };
136 opp-318750000 {
137 opp-hz = /bits/ 64 <318750000>;
138 opp-microvolt = <1150000>;
139 };
140 opp-425000000 {
141 opp-hz = /bits/ 64 <425000000>;
142 opp-microvolt = <1150000>;
143 };
144 opp-510000000 {
145 opp-hz = /bits/ 64 <510000000>;
146 opp-microvolt = <1150000>;
147 };
148 opp-637500000 {
149 opp-hz = /bits/ 64 <637500000>;
150 opp-microvolt = <1150000>;
151 turbo-mode;
152 };
153 };
154
155 pmu {
156 compatible = "arm,cortex-a9-pmu";
157 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
161 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
162 };
163
164 reserved-memory {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges;
168
169 /* 2 MiB reserved for Hardware ROM Firmware? */
170 hwrom@0 {
171 reg = <0x0 0x200000>;
172 no-map;
173 };
174
175 /*
176 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
177 * code which is responsible for system suspend. It loads a
178 * piece of ARC code ("arc_power" in the vendor u-boot tree)
179 * into SRAM, executes that and shuts down the (last) ARM core.
180 * The arc_power firmware then checks various wakeup sources
181 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
182 * simply the power key) and re-starts the ARM core once it
183 * detects a wakeup request.
184 */
185 power-firmware@4f00000 {
186 reg = <0x4f00000 0x100000>;
187 no-map;
188 };
189 };
190
191 mmcbus: bus@c8000000 {
192 compatible = "simple-bus";
193 reg = <0xc8000000 0x8000>;
194 #address-cells = <1>;
195 #size-cells = <1>;
196 ranges = <0x0 0xc8000000 0x8000>;
197
198 dmcbus: bus@6000 {
199 compatible = "simple-bus";
200 reg = <0x6000 0x400>;
201 #address-cells = <1>;
202 #size-cells = <1>;
203 ranges = <0x0 0x6000 0x400>;
204
205 canvas: video-lut@20 {
206 compatible = "amlogic,meson8-canvas",
207 "amlogic,canvas";
208 reg = <0x20 0x14>;
209 };
210 };
211 };
212
213 apb: bus@d0000000 {
214 compatible = "simple-bus";
215 reg = <0xd0000000 0x200000>;
216 #address-cells = <1>;
217 #size-cells = <1>;
218 ranges = <0x0 0xd0000000 0x200000>;
219
220 mali: gpu@c0000 {
221 compatible = "amlogic,meson8-mali", "arm,mali-450";
222 reg = <0xc0000 0x40000>;
223 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
241 interrupt-names = "gp", "gpmmu", "pp", "pmu",
242 "pp0", "ppmmu0", "pp1", "ppmmu1",
243 "pp2", "ppmmu2", "pp4", "ppmmu4",
244 "pp5", "ppmmu5", "pp6", "ppmmu6";
245 resets = <&reset RESET_MALI>;
246 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
247 clock-names = "bus", "core";
248 operating-points-v2 = <&gpu_opp_table>;
249 };
250 };
251}; /* end of / */
252
253&aobus {
254 pmu: pmu@e0 {
255 compatible = "amlogic,meson8-pmu", "syscon";
256 reg = <0xe0 0x8>;
257 };
258
259 pinctrl_aobus: pinctrl@84 {
260 compatible = "amlogic,meson8-aobus-pinctrl";
261 reg = <0x84 0xc>;
262 #address-cells = <1>;
263 #size-cells = <1>;
264 ranges;
265
266 gpio_ao: ao-bank@14 {
267 reg = <0x14 0x4>,
268 <0x2c 0x4>,
269 <0x24 0x8>;
270 reg-names = "mux", "pull", "gpio";
271 gpio-controller;
272 #gpio-cells = <2>;
273 gpio-ranges = <&pinctrl_aobus 0 0 16>;
274 };
275
276 uart_ao_a_pins: uart_ao_a {
277 mux {
278 groups = "uart_tx_ao_a", "uart_rx_ao_a";
279 function = "uart_ao";
280 bias-disable;
281 };
282 };
283
284 i2c_ao_pins: i2c_mst_ao {
285 mux {
286 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
287 function = "i2c_mst_ao";
288 bias-disable;
289 };
290 };
291
292 ir_recv_pins: remote {
293 mux {
294 groups = "remote_input";
295 function = "remote";
296 bias-disable;
297 };
298 };
299
300 pwm_f_ao_pins: pwm-f-ao {
301 mux {
302 groups = "pwm_f_ao";
303 function = "pwm_f_ao";
304 bias-disable;
305 };
306 };
307 };
308};
309
310&cbus {
311 reset: reset-controller@4404 {
312 compatible = "amlogic,meson8b-reset";
313 reg = <0x4404 0x9c>;
314 #reset-cells = <1>;
315 };
316
317 analog_top: analog-top@81a8 {
318 compatible = "amlogic,meson8-analog-top", "syscon";
319 reg = <0x81a8 0x14>;
320 };
321
322 pwm_ef: pwm@86c0 {
323 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
324 reg = <0x86c0 0x10>;
325 #pwm-cells = <3>;
326 status = "disabled";
327 };
328
329 clock-measure@8758 {
330 compatible = "amlogic,meson8-clk-measure";
331 reg = <0x8758 0x1c>;
332 };
333
334 pinctrl_cbus: pinctrl@9880 {
335 compatible = "amlogic,meson8-cbus-pinctrl";
336 reg = <0x9880 0x10>;
337 #address-cells = <1>;
338 #size-cells = <1>;
339 ranges;
340
341 gpio: banks@80b0 {
342 reg = <0x80b0 0x28>,
343 <0x80e8 0x18>,
344 <0x8120 0x18>,
345 <0x8030 0x30>;
346 reg-names = "mux", "pull", "pull-enable", "gpio";
347 gpio-controller;
348 #gpio-cells = <2>;
349 gpio-ranges = <&pinctrl_cbus 0 0 120>;
350 };
351
352 sd_a_pins: sd-a {
353 mux {
354 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
355 "sd_d3_a", "sd_clk_a", "sd_cmd_a";
356 function = "sd_a";
357 bias-disable;
358 };
359 };
360
361 sd_b_pins: sd-b {
362 mux {
363 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
364 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
365 function = "sd_b";
366 bias-disable;
367 };
368 };
369
370 sd_c_pins: sd-c {
371 mux {
372 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
373 "sd_d3_c", "sd_clk_c", "sd_cmd_c";
374 function = "sd_c";
375 bias-disable;
376 };
377 };
378
379 spi_nor_pins: nor {
380 mux {
381 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
382 function = "nor";
383 bias-disable;
384 };
385 };
386
387 eth_pins: ethernet {
388 mux {
389 groups = "eth_tx_clk_50m", "eth_tx_en",
390 "eth_txd1", "eth_txd0",
391 "eth_rx_clk_in", "eth_rx_dv",
392 "eth_rxd1", "eth_rxd0", "eth_mdio",
393 "eth_mdc";
394 function = "ethernet";
395 bias-disable;
396 };
397 };
398
399 pwm_e_pins: pwm-e {
400 mux {
401 groups = "pwm_e";
402 function = "pwm_e";
403 bias-disable;
404 };
405 };
406
407 uart_a1_pins: uart-a1 {
408 mux {
409 groups = "uart_tx_a1",
410 "uart_rx_a1";
411 function = "uart_a";
412 bias-disable;
413 };
414 };
415
416 uart_a1_cts_rts_pins: uart-a1-cts-rts {
417 mux {
418 groups = "uart_cts_a1",
419 "uart_rts_a1";
420 function = "uart_a";
421 bias-disable;
422 };
423 };
424 };
425};
426
427&ahb_sram {
428 smp-sram@1ff80 {
429 compatible = "amlogic,meson8-smp-sram";
430 reg = <0x1ff80 0x8>;
431 };
432};
433
434&efuse {
435 compatible = "amlogic,meson8-efuse";
436 clocks = <&clkc CLKID_EFUSE>;
437 clock-names = "core";
438
439 temperature_calib: calib@1f4 {
440 /* only the upper two bytes are relevant */
441 reg = <0x1f4 0x4>;
442 };
443};
444
445ðmac {
446 clocks = <&clkc CLKID_ETH>;
447 clock-names = "stmmaceth";
448};
449
450&gpio_intc {
451 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
452 status = "okay";
453};
454
455&hhi {
456 clkc: clock-controller {
457 compatible = "amlogic,meson8-clkc";
458 #clock-cells = <1>;
459 #reset-cells = <1>;
460 };
461};
462
463&hwrng {
464 compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
465 clocks = <&clkc CLKID_RNG0>;
466 clock-names = "core";
467};
468
469&i2c_AO {
470 clocks = <&clkc CLKID_CLK81>;
471};
472
473&i2c_A {
474 clocks = <&clkc CLKID_CLK81>;
475};
476
477&i2c_B {
478 clocks = <&clkc CLKID_CLK81>;
479};
480
481&L2 {
482 arm,data-latency = <3 3 3>;
483 arm,tag-latency = <2 2 2>;
484 arm,filter-ranges = <0x100000 0xc0000000>;
485 prefetch-data = <1>;
486 prefetch-instr = <1>;
487 arm,shared-override;
488};
489
490&periph {
491 scu@0 {
492 compatible = "arm,cortex-a9-scu";
493 reg = <0x0 0x100>;
494 };
495
496 timer@200 {
497 compatible = "arm,cortex-a9-global-timer";
498 reg = <0x200 0x20>;
499 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
500 clocks = <&clkc CLKID_PERIPH>;
501
502 /*
503 * the arm_global_timer driver currently does not handle clock
504 * rate changes. Keep it disabled for now.
505 */
506 status = "disabled";
507 };
508
509 timer@600 {
510 compatible = "arm,cortex-a9-twd-timer";
511 reg = <0x600 0x20>;
512 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
513 clocks = <&clkc CLKID_PERIPH>;
514 };
515};
516
517&pwm_ab {
518 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
519};
520
521&pwm_cd {
522 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
523};
524
525&rtc {
526 compatible = "amlogic,meson8-rtc";
527 resets = <&reset RESET_RTC>;
528};
529
530&saradc {
531 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
532 clocks = <&clkc CLKID_XTAL>,
533 <&clkc CLKID_SAR_ADC>;
534 clock-names = "clkin", "core";
535 amlogic,hhi-sysctrl = <&hhi>;
536 nvmem-cells = <&temperature_calib>;
537 nvmem-cell-names = "temperature_calib";
538};
539
540&sdio {
541 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
542 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
543 clock-names = "core", "clkin";
544};
545
546&spifc {
547 clocks = <&clkc CLKID_CLK81>;
548};
549
550&timer_abcde {
551 clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
552 clock-names = "xtal", "pclk";
553};
554
555&uart_AO {
556 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
557 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
558 clock-names = "baud", "xtal", "pclk";
559};
560
561&uart_A {
562 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
563 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
564 clock-names = "baud", "xtal", "pclk";
565};
566
567&uart_B {
568 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
569 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
570 clock-names = "baud", "xtal", "pclk";
571};
572
573&uart_C {
574 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
575 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
576 clock-names = "baud", "xtal", "pclk";
577};
578
579&usb0 {
580 compatible = "amlogic,meson8-usb", "snps,dwc2";
581 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
582 clock-names = "otg";
583};
584
585&usb1 {
586 compatible = "amlogic,meson8-usb", "snps,dwc2";
587 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
588 clock-names = "otg";
589};
590
591&usb0_phy {
592 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
593 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
594 clock-names = "usb_general", "usb";
595 resets = <&reset RESET_USB_OTG>;
596};
597
598&usb1_phy {
599 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
600 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
601 clock-names = "usb_general", "usb";
602 resets = <&reset RESET_USB_OTG>;
603};