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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * UEFI Common Platform Error Record
4 *
5 * Copyright (C) 2010, Intel Corp.
6 * Author: Huang Ying <ying.huang@intel.com>
7 */
8
9#ifndef LINUX_CPER_H
10#define LINUX_CPER_H
11
12#include <linux/uuid.h>
13#include <linux/trace_seq.h>
14
15/* CPER record signature and the size */
16#define CPER_SIG_RECORD "CPER"
17#define CPER_SIG_SIZE 4
18/* Used in signature_end field in struct cper_record_header */
19#define CPER_SIG_END 0xffffffff
20
21/*
22 * CPER record header revision, used in revision field in struct
23 * cper_record_header
24 */
25#define CPER_RECORD_REV 0x0100
26
27/*
28 * CPER record length contains the CPER fields which are relevant for further
29 * handling of a memory error in userspace (we don't carry all the fields
30 * defined in the UEFI spec because some of them don't make any sense.)
31 * Currently, a length of 256 should be more than enough.
32 */
33#define CPER_REC_LEN 256
34/*
35 * Severity definition for error_severity in struct cper_record_header
36 * and section_severity in struct cper_section_descriptor
37 */
38enum {
39 CPER_SEV_RECOVERABLE,
40 CPER_SEV_FATAL,
41 CPER_SEV_CORRECTED,
42 CPER_SEV_INFORMATIONAL,
43};
44
45/*
46 * Validation bits definition for validation_bits in struct
47 * cper_record_header. If set, corresponding fields in struct
48 * cper_record_header contain valid information.
49 */
50#define CPER_VALID_PLATFORM_ID 0x0001
51#define CPER_VALID_TIMESTAMP 0x0002
52#define CPER_VALID_PARTITION_ID 0x0004
53
54/*
55 * Notification type used to generate error record, used in
56 * notification_type in struct cper_record_header. These UUIDs are defined
57 * in the UEFI spec v2.7, sec N.2.1.
58 */
59
60/* Corrected Machine Check */
61#define CPER_NOTIFY_CMC \
62 GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
63 0xEB, 0xD4, 0xF8, 0x90)
64/* Corrected Platform Error */
65#define CPER_NOTIFY_CPE \
66 GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \
67 0xF2, 0x7E, 0xBE, 0xEE)
68/* Machine Check Exception */
69#define CPER_NOTIFY_MCE \
70 GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
71 0xE1, 0x49, 0x13, 0xBB)
72/* PCI Express Error */
73#define CPER_NOTIFY_PCIE \
74 GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \
75 0xAF, 0x67, 0xC1, 0x04)
76/* INIT Record (for IPF) */
77#define CPER_NOTIFY_INIT \
78 GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \
79 0xD3, 0x9B, 0xC9, 0x8E)
80/* Non-Maskable Interrupt */
81#define CPER_NOTIFY_NMI \
82 GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \
83 0x85, 0xD6, 0xE9, 0x8A)
84/* BOOT Error Record */
85#define CPER_NOTIFY_BOOT \
86 GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
87 0xD4, 0x64, 0xB3, 0x8F)
88/* DMA Remapping Error */
89#define CPER_NOTIFY_DMAR \
90 GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \
91 0x72, 0x2D, 0xEB, 0x41)
92
93/*
94 * Flags bits definitions for flags in struct cper_record_header
95 * If set, the error has been recovered
96 */
97#define CPER_HW_ERROR_FLAGS_RECOVERED 0x1
98/* If set, the error is for previous boot */
99#define CPER_HW_ERROR_FLAGS_PREVERR 0x2
100/* If set, the error is injected for testing */
101#define CPER_HW_ERROR_FLAGS_SIMULATED 0x4
102
103/*
104 * CPER section header revision, used in revision field in struct
105 * cper_section_descriptor
106 */
107#define CPER_SEC_REV 0x0100
108
109/*
110 * Validation bits definition for validation_bits in struct
111 * cper_section_descriptor. If set, corresponding fields in struct
112 * cper_section_descriptor contain valid information.
113 */
114#define CPER_SEC_VALID_FRU_ID 0x1
115#define CPER_SEC_VALID_FRU_TEXT 0x2
116
117/*
118 * Flags bits definitions for flags in struct cper_section_descriptor
119 *
120 * If set, the section is associated with the error condition
121 * directly, and should be focused on
122 */
123#define CPER_SEC_PRIMARY 0x0001
124/*
125 * If set, the error was not contained within the processor or memory
126 * hierarchy and the error may have propagated to persistent storage
127 * or network
128 */
129#define CPER_SEC_CONTAINMENT_WARNING 0x0002
130/* If set, the component must be re-initialized or re-enabled prior to use */
131#define CPER_SEC_RESET 0x0004
132/* If set, Linux may choose to discontinue use of the resource */
133#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008
134/*
135 * If set, resource could not be queried for error information due to
136 * conflicts with other system software or resources. Some fields of
137 * the section will be invalid
138 */
139#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010
140/*
141 * If set, action has been taken to ensure error containment (such as
142 * poisoning data), but the error has not been fully corrected and the
143 * data has not been consumed. Linux may choose to take further
144 * corrective action before the data is consumed
145 */
146#define CPER_SEC_LATENT_ERROR 0x0020
147
148/*
149 * Section type definitions, used in section_type field in struct
150 * cper_section_descriptor. These UUIDs are defined in the UEFI spec
151 * v2.7, sec N.2.2.
152 */
153
154/* Processor Generic */
155#define CPER_SEC_PROC_GENERIC \
156 GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
157 0x93, 0xC4, 0xF3, 0xDB)
158/* Processor Specific: X86/X86_64 */
159#define CPER_SEC_PROC_IA \
160 GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
161 0x24, 0x2B, 0x6E, 0x1D)
162/* Processor Specific: IA64 */
163#define CPER_SEC_PROC_IPF \
164 GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \
165 0x80, 0xC7, 0x3C, 0x88, 0x81)
166/* Processor Specific: ARM */
167#define CPER_SEC_PROC_ARM \
168 GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05, \
169 0x1D, 0x5D, 0x46, 0xB0)
170/* Platform Memory */
171#define CPER_SEC_PLATFORM_MEM \
172 GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
173 0xED, 0x7C, 0x83, 0xB1)
174#define CPER_SEC_PCIE \
175 GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \
176 0xCB, 0x3C, 0x6F, 0x35)
177/* Firmware Error Record Reference */
178#define CPER_SEC_FW_ERR_REC_REF \
179 GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \
180 0x9C, 0x8E, 0x69, 0xED)
181/* PCI/PCI-X Bus */
182#define CPER_SEC_PCI_X_BUS \
183 GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \
184 0xD3, 0xF9, 0xC9, 0xDD)
185/* PCI Component/Device */
186#define CPER_SEC_PCI_DEV \
187 GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \
188 0x8B, 0x00, 0x13, 0x26)
189#define CPER_SEC_DMAR_GENERIC \
190 GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \
191 0xDE, 0x3E, 0x2C, 0x64)
192/* Intel VT for Directed I/O specific DMAr */
193#define CPER_SEC_DMAR_VT \
194 GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \
195 0xDD, 0x93, 0xE8, 0xCF)
196/* IOMMU specific DMAr */
197#define CPER_SEC_DMAR_IOMMU \
198 GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \
199 0xDF, 0xAA, 0x84, 0xEC)
200
201#define CPER_PROC_VALID_TYPE 0x0001
202#define CPER_PROC_VALID_ISA 0x0002
203#define CPER_PROC_VALID_ERROR_TYPE 0x0004
204#define CPER_PROC_VALID_OPERATION 0x0008
205#define CPER_PROC_VALID_FLAGS 0x0010
206#define CPER_PROC_VALID_LEVEL 0x0020
207#define CPER_PROC_VALID_VERSION 0x0040
208#define CPER_PROC_VALID_BRAND_INFO 0x0080
209#define CPER_PROC_VALID_ID 0x0100
210#define CPER_PROC_VALID_TARGET_ADDRESS 0x0200
211#define CPER_PROC_VALID_REQUESTOR_ID 0x0400
212#define CPER_PROC_VALID_RESPONDER_ID 0x0800
213#define CPER_PROC_VALID_IP 0x1000
214
215#define CPER_MEM_VALID_ERROR_STATUS 0x0001
216#define CPER_MEM_VALID_PA 0x0002
217#define CPER_MEM_VALID_PA_MASK 0x0004
218#define CPER_MEM_VALID_NODE 0x0008
219#define CPER_MEM_VALID_CARD 0x0010
220#define CPER_MEM_VALID_MODULE 0x0020
221#define CPER_MEM_VALID_BANK 0x0040
222#define CPER_MEM_VALID_DEVICE 0x0080
223#define CPER_MEM_VALID_ROW 0x0100
224#define CPER_MEM_VALID_COLUMN 0x0200
225#define CPER_MEM_VALID_BIT_POSITION 0x0400
226#define CPER_MEM_VALID_REQUESTOR_ID 0x0800
227#define CPER_MEM_VALID_RESPONDER_ID 0x1000
228#define CPER_MEM_VALID_TARGET_ID 0x2000
229#define CPER_MEM_VALID_ERROR_TYPE 0x4000
230#define CPER_MEM_VALID_RANK_NUMBER 0x8000
231#define CPER_MEM_VALID_CARD_HANDLE 0x10000
232#define CPER_MEM_VALID_MODULE_HANDLE 0x20000
233#define CPER_MEM_VALID_ROW_EXT 0x40000
234#define CPER_MEM_VALID_BANK_GROUP 0x80000
235#define CPER_MEM_VALID_BANK_ADDRESS 0x100000
236#define CPER_MEM_VALID_CHIP_ID 0x200000
237
238#define CPER_MEM_EXT_ROW_MASK 0x3
239#define CPER_MEM_EXT_ROW_SHIFT 16
240
241#define CPER_MEM_BANK_ADDRESS_MASK 0xff
242#define CPER_MEM_BANK_GROUP_SHIFT 8
243
244#define CPER_MEM_CHIP_ID_SHIFT 5
245
246#define CPER_PCIE_VALID_PORT_TYPE 0x0001
247#define CPER_PCIE_VALID_VERSION 0x0002
248#define CPER_PCIE_VALID_COMMAND_STATUS 0x0004
249#define CPER_PCIE_VALID_DEVICE_ID 0x0008
250#define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010
251#define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020
252#define CPER_PCIE_VALID_CAPABILITY 0x0040
253#define CPER_PCIE_VALID_AER_INFO 0x0080
254
255#define CPER_PCIE_SLOT_SHIFT 3
256
257#define CPER_ARM_VALID_MPIDR BIT(0)
258#define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1)
259#define CPER_ARM_VALID_RUNNING_STATE BIT(2)
260#define CPER_ARM_VALID_VENDOR_INFO BIT(3)
261
262#define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0)
263#define CPER_ARM_INFO_VALID_FLAGS BIT(1)
264#define CPER_ARM_INFO_VALID_ERR_INFO BIT(2)
265#define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3)
266#define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4)
267
268#define CPER_ARM_INFO_FLAGS_FIRST BIT(0)
269#define CPER_ARM_INFO_FLAGS_LAST BIT(1)
270#define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2)
271#define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3)
272
273#define CPER_ARM_CACHE_ERROR 0
274#define CPER_ARM_TLB_ERROR 1
275#define CPER_ARM_BUS_ERROR 2
276#define CPER_ARM_VENDOR_ERROR 3
277#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR
278
279#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0)
280#define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1)
281#define CPER_ARM_ERR_VALID_LEVEL BIT(2)
282#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3)
283#define CPER_ARM_ERR_VALID_CORRECTED BIT(4)
284#define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5)
285#define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6)
286#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7)
287#define CPER_ARM_ERR_VALID_TIME_OUT BIT(8)
288#define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9)
289#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10)
290#define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11)
291
292#define CPER_ARM_ERR_TRANSACTION_SHIFT 16
293#define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)
294#define CPER_ARM_ERR_OPERATION_SHIFT 18
295#define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)
296#define CPER_ARM_ERR_LEVEL_SHIFT 22
297#define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)
298#define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25
299#define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)
300#define CPER_ARM_ERR_CORRECTED_SHIFT 26
301#define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)
302#define CPER_ARM_ERR_PRECISE_PC_SHIFT 27
303#define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)
304#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28
305#define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)
306#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29
307#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)
308#define CPER_ARM_ERR_TIME_OUT_SHIFT 31
309#define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)
310#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32
311#define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)
312#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34
313#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0)
314#define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43
315#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)
316
317/*
318 * All tables and structs must be byte-packed to match CPER
319 * specification, since the tables are provided by the system BIOS
320 */
321#pragma pack(1)
322
323/* Record Header, UEFI v2.7 sec N.2.1 */
324struct cper_record_header {
325 char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */
326 u16 revision; /* must be CPER_RECORD_REV */
327 u32 signature_end; /* must be CPER_SIG_END */
328 u16 section_count;
329 u32 error_severity;
330 u32 validation_bits;
331 u32 record_length;
332 u64 timestamp;
333 guid_t platform_id;
334 guid_t partition_id;
335 guid_t creator_id;
336 guid_t notification_type;
337 u64 record_id;
338 u32 flags;
339 u64 persistence_information;
340 u8 reserved[12]; /* must be zero */
341};
342
343/* Section Descriptor, UEFI v2.7 sec N.2.2 */
344struct cper_section_descriptor {
345 u32 section_offset; /* Offset in bytes of the
346 * section body from the base
347 * of the record header */
348 u32 section_length;
349 u16 revision; /* must be CPER_RECORD_REV */
350 u8 validation_bits;
351 u8 reserved; /* must be zero */
352 u32 flags;
353 guid_t section_type;
354 guid_t fru_id;
355 u32 section_severity;
356 u8 fru_text[20];
357};
358
359/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
360struct cper_sec_proc_generic {
361 u64 validation_bits;
362 u8 proc_type;
363 u8 proc_isa;
364 u8 proc_error_type;
365 u8 operation;
366 u8 flags;
367 u8 level;
368 u16 reserved;
369 u64 cpu_version;
370 char cpu_brand[128];
371 u64 proc_id;
372 u64 target_addr;
373 u64 requestor_id;
374 u64 responder_id;
375 u64 ip;
376};
377
378/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
379struct cper_sec_proc_ia {
380 u64 validation_bits;
381 u64 lapic_id;
382 u8 cpuid[48];
383};
384
385/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
386struct cper_ia_err_info {
387 guid_t err_type;
388 u64 validation_bits;
389 u64 check_info;
390 u64 target_id;
391 u64 requestor_id;
392 u64 responder_id;
393 u64 ip;
394};
395
396/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
397struct cper_ia_proc_ctx {
398 u16 reg_ctx_type;
399 u16 reg_arr_size;
400 u32 msr_addr;
401 u64 mm_reg_addr;
402};
403
404/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
405struct cper_sec_proc_arm {
406 u32 validation_bits;
407 u16 err_info_num; /* Number of Processor Error Info */
408 u16 context_info_num; /* Number of Processor Context Info Records*/
409 u32 section_length;
410 u8 affinity_level;
411 u8 reserved[3]; /* must be zero */
412 u64 mpidr;
413 u64 midr;
414 u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
415 u32 psci_state;
416};
417
418/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
419struct cper_arm_err_info {
420 u8 version;
421 u8 length;
422 u16 validation_bits;
423 u8 type;
424 u16 multiple_error;
425 u8 flags;
426 u64 error_info;
427 u64 virt_fault_addr;
428 u64 physical_fault_addr;
429};
430
431/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
432struct cper_arm_ctx_info {
433 u16 version;
434 u16 type;
435 u32 size;
436};
437
438/* Old Memory Error Section, UEFI v2.1, v2.2 */
439struct cper_sec_mem_err_old {
440 u64 validation_bits;
441 u64 error_status;
442 u64 physical_addr;
443 u64 physical_addr_mask;
444 u16 node;
445 u16 card;
446 u16 module;
447 u16 bank;
448 u16 device;
449 u16 row;
450 u16 column;
451 u16 bit_pos;
452 u64 requestor_id;
453 u64 responder_id;
454 u64 target_id;
455 u8 error_type;
456};
457
458/* Memory Error Section (UEFI >= v2.3), UEFI v2.8 sec N.2.5 */
459struct cper_sec_mem_err {
460 u64 validation_bits;
461 u64 error_status;
462 u64 physical_addr;
463 u64 physical_addr_mask;
464 u16 node;
465 u16 card;
466 u16 module;
467 u16 bank;
468 u16 device;
469 u16 row;
470 u16 column;
471 u16 bit_pos;
472 u64 requestor_id;
473 u64 responder_id;
474 u64 target_id;
475 u8 error_type;
476 u8 extended;
477 u16 rank;
478 u16 mem_array_handle; /* "card handle" in UEFI 2.4 */
479 u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */
480};
481
482struct cper_mem_err_compact {
483 u64 validation_bits;
484 u16 node;
485 u16 card;
486 u16 module;
487 u16 bank;
488 u16 device;
489 u16 row;
490 u16 column;
491 u16 bit_pos;
492 u64 requestor_id;
493 u64 responder_id;
494 u64 target_id;
495 u16 rank;
496 u16 mem_array_handle;
497 u16 mem_dev_handle;
498 u8 extended;
499};
500
501static inline u32 cper_get_mem_extension(u64 mem_valid, u8 mem_extended)
502{
503 if (!(mem_valid & CPER_MEM_VALID_ROW_EXT))
504 return 0;
505 return (mem_extended & CPER_MEM_EXT_ROW_MASK) << CPER_MEM_EXT_ROW_SHIFT;
506}
507
508/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
509struct cper_sec_pcie {
510 u64 validation_bits;
511 u32 port_type;
512 struct {
513 u8 minor;
514 u8 major;
515 u8 reserved[2];
516 } version;
517 u16 command;
518 u16 status;
519 u32 reserved;
520 struct {
521 u16 vendor_id;
522 u16 device_id;
523 u8 class_code[3];
524 u8 function;
525 u8 device;
526 u16 segment;
527 u8 bus;
528 u8 secondary_bus;
529 u16 slot;
530 u8 reserved;
531 } device_id;
532 struct {
533 u32 lower;
534 u32 upper;
535 } serial_number;
536 struct {
537 u16 secondary_status;
538 u16 control;
539 } bridge;
540 u8 capability[60];
541 u8 aer_info[96];
542};
543
544/* Firmware Error Record Reference, UEFI v2.7 sec N.2.10 */
545struct cper_sec_fw_err_rec_ref {
546 u8 record_type;
547 u8 revision;
548 u8 reserved[6];
549 u64 record_identifier;
550 guid_t record_identifier_guid;
551};
552
553/* Reset to default packing */
554#pragma pack()
555
556extern const char *const cper_proc_error_type_strs[4];
557
558u64 cper_next_record_id(void);
559const char *cper_severity_str(unsigned int);
560const char *cper_mem_err_type_str(unsigned int);
561void cper_print_bits(const char *prefix, unsigned int bits,
562 const char * const strs[], unsigned int strs_size);
563void cper_mem_err_pack(const struct cper_sec_mem_err *,
564 struct cper_mem_err_compact *);
565const char *cper_mem_err_unpack(struct trace_seq *,
566 struct cper_mem_err_compact *);
567void cper_print_proc_arm(const char *pfx,
568 const struct cper_sec_proc_arm *proc);
569void cper_print_proc_ia(const char *pfx,
570 const struct cper_sec_proc_ia *proc);
571
572#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * UEFI Common Platform Error Record
4 *
5 * Copyright (C) 2010, Intel Corp.
6 * Author: Huang Ying <ying.huang@intel.com>
7 */
8
9#ifndef LINUX_CPER_H
10#define LINUX_CPER_H
11
12#include <linux/uuid.h>
13#include <linux/trace_seq.h>
14
15/* CPER record signature and the size */
16#define CPER_SIG_RECORD "CPER"
17#define CPER_SIG_SIZE 4
18/* Used in signature_end field in struct cper_record_header */
19#define CPER_SIG_END 0xffffffff
20
21/*
22 * CPER record header revision, used in revision field in struct
23 * cper_record_header
24 */
25#define CPER_RECORD_REV 0x0100
26
27/*
28 * CPER record length contains the CPER fields which are relevant for further
29 * handling of a memory error in userspace (we don't carry all the fields
30 * defined in the UEFI spec because some of them don't make any sense.)
31 * Currently, a length of 256 should be more than enough.
32 */
33#define CPER_REC_LEN 256
34/*
35 * Severity definition for error_severity in struct cper_record_header
36 * and section_severity in struct cper_section_descriptor
37 */
38enum {
39 CPER_SEV_RECOVERABLE,
40 CPER_SEV_FATAL,
41 CPER_SEV_CORRECTED,
42 CPER_SEV_INFORMATIONAL,
43};
44
45/*
46 * Validation bits definition for validation_bits in struct
47 * cper_record_header. If set, corresponding fields in struct
48 * cper_record_header contain valid information.
49 */
50#define CPER_VALID_PLATFORM_ID 0x0001
51#define CPER_VALID_TIMESTAMP 0x0002
52#define CPER_VALID_PARTITION_ID 0x0004
53
54/*
55 * Notification type used to generate error record, used in
56 * notification_type in struct cper_record_header. These UUIDs are defined
57 * in the UEFI spec v2.7, sec N.2.1.
58 */
59
60/* Corrected Machine Check */
61#define CPER_NOTIFY_CMC \
62 GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
63 0xEB, 0xD4, 0xF8, 0x90)
64/* Corrected Platform Error */
65#define CPER_NOTIFY_CPE \
66 GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \
67 0xF2, 0x7E, 0xBE, 0xEE)
68/* Machine Check Exception */
69#define CPER_NOTIFY_MCE \
70 GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
71 0xE1, 0x49, 0x13, 0xBB)
72/* PCI Express Error */
73#define CPER_NOTIFY_PCIE \
74 GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \
75 0xAF, 0x67, 0xC1, 0x04)
76/* INIT Record (for IPF) */
77#define CPER_NOTIFY_INIT \
78 GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \
79 0xD3, 0x9B, 0xC9, 0x8E)
80/* Non-Maskable Interrupt */
81#define CPER_NOTIFY_NMI \
82 GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \
83 0x85, 0xD6, 0xE9, 0x8A)
84/* BOOT Error Record */
85#define CPER_NOTIFY_BOOT \
86 GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
87 0xD4, 0x64, 0xB3, 0x8F)
88/* DMA Remapping Error */
89#define CPER_NOTIFY_DMAR \
90 GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \
91 0x72, 0x2D, 0xEB, 0x41)
92
93/*
94 * Flags bits definitions for flags in struct cper_record_header
95 * If set, the error has been recovered
96 */
97#define CPER_HW_ERROR_FLAGS_RECOVERED 0x1
98/* If set, the error is for previous boot */
99#define CPER_HW_ERROR_FLAGS_PREVERR 0x2
100/* If set, the error is injected for testing */
101#define CPER_HW_ERROR_FLAGS_SIMULATED 0x4
102
103/*
104 * CPER section header revision, used in revision field in struct
105 * cper_section_descriptor
106 */
107#define CPER_SEC_REV 0x0100
108
109/*
110 * Validation bits definition for validation_bits in struct
111 * cper_section_descriptor. If set, corresponding fields in struct
112 * cper_section_descriptor contain valid information.
113 */
114#define CPER_SEC_VALID_FRU_ID 0x1
115#define CPER_SEC_VALID_FRU_TEXT 0x2
116
117/*
118 * Flags bits definitions for flags in struct cper_section_descriptor
119 *
120 * If set, the section is associated with the error condition
121 * directly, and should be focused on
122 */
123#define CPER_SEC_PRIMARY 0x0001
124/*
125 * If set, the error was not contained within the processor or memory
126 * hierarchy and the error may have propagated to persistent storage
127 * or network
128 */
129#define CPER_SEC_CONTAINMENT_WARNING 0x0002
130/* If set, the component must be re-initialized or re-enabled prior to use */
131#define CPER_SEC_RESET 0x0004
132/* If set, Linux may choose to discontinue use of the resource */
133#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008
134/*
135 * If set, resource could not be queried for error information due to
136 * conflicts with other system software or resources. Some fields of
137 * the section will be invalid
138 */
139#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010
140/*
141 * If set, action has been taken to ensure error containment (such as
142 * poisoning data), but the error has not been fully corrected and the
143 * data has not been consumed. Linux may choose to take further
144 * corrective action before the data is consumed
145 */
146#define CPER_SEC_LATENT_ERROR 0x0020
147
148/*
149 * Section type definitions, used in section_type field in struct
150 * cper_section_descriptor. These UUIDs are defined in the UEFI spec
151 * v2.7, sec N.2.2.
152 */
153
154/* Processor Generic */
155#define CPER_SEC_PROC_GENERIC \
156 GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
157 0x93, 0xC4, 0xF3, 0xDB)
158/* Processor Specific: X86/X86_64 */
159#define CPER_SEC_PROC_IA \
160 GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
161 0x24, 0x2B, 0x6E, 0x1D)
162/* Processor Specific: IA64 */
163#define CPER_SEC_PROC_IPF \
164 GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \
165 0x80, 0xC7, 0x3C, 0x88, 0x81)
166/* Processor Specific: ARM */
167#define CPER_SEC_PROC_ARM \
168 GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05, \
169 0x1D, 0x5D, 0x46, 0xB0)
170/* Platform Memory */
171#define CPER_SEC_PLATFORM_MEM \
172 GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
173 0xED, 0x7C, 0x83, 0xB1)
174#define CPER_SEC_PCIE \
175 GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \
176 0xCB, 0x3C, 0x6F, 0x35)
177/* Firmware Error Record Reference */
178#define CPER_SEC_FW_ERR_REC_REF \
179 GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \
180 0x9C, 0x8E, 0x69, 0xED)
181/* PCI/PCI-X Bus */
182#define CPER_SEC_PCI_X_BUS \
183 GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \
184 0xD3, 0xF9, 0xC9, 0xDD)
185/* PCI Component/Device */
186#define CPER_SEC_PCI_DEV \
187 GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \
188 0x8B, 0x00, 0x13, 0x26)
189#define CPER_SEC_DMAR_GENERIC \
190 GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \
191 0xDE, 0x3E, 0x2C, 0x64)
192/* Intel VT for Directed I/O specific DMAr */
193#define CPER_SEC_DMAR_VT \
194 GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \
195 0xDD, 0x93, 0xE8, 0xCF)
196/* IOMMU specific DMAr */
197#define CPER_SEC_DMAR_IOMMU \
198 GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \
199 0xDF, 0xAA, 0x84, 0xEC)
200
201#define CPER_PROC_VALID_TYPE 0x0001
202#define CPER_PROC_VALID_ISA 0x0002
203#define CPER_PROC_VALID_ERROR_TYPE 0x0004
204#define CPER_PROC_VALID_OPERATION 0x0008
205#define CPER_PROC_VALID_FLAGS 0x0010
206#define CPER_PROC_VALID_LEVEL 0x0020
207#define CPER_PROC_VALID_VERSION 0x0040
208#define CPER_PROC_VALID_BRAND_INFO 0x0080
209#define CPER_PROC_VALID_ID 0x0100
210#define CPER_PROC_VALID_TARGET_ADDRESS 0x0200
211#define CPER_PROC_VALID_REQUESTOR_ID 0x0400
212#define CPER_PROC_VALID_RESPONDER_ID 0x0800
213#define CPER_PROC_VALID_IP 0x1000
214
215#define CPER_MEM_VALID_ERROR_STATUS 0x0001
216#define CPER_MEM_VALID_PA 0x0002
217#define CPER_MEM_VALID_PA_MASK 0x0004
218#define CPER_MEM_VALID_NODE 0x0008
219#define CPER_MEM_VALID_CARD 0x0010
220#define CPER_MEM_VALID_MODULE 0x0020
221#define CPER_MEM_VALID_BANK 0x0040
222#define CPER_MEM_VALID_DEVICE 0x0080
223#define CPER_MEM_VALID_ROW 0x0100
224#define CPER_MEM_VALID_COLUMN 0x0200
225#define CPER_MEM_VALID_BIT_POSITION 0x0400
226#define CPER_MEM_VALID_REQUESTOR_ID 0x0800
227#define CPER_MEM_VALID_RESPONDER_ID 0x1000
228#define CPER_MEM_VALID_TARGET_ID 0x2000
229#define CPER_MEM_VALID_ERROR_TYPE 0x4000
230#define CPER_MEM_VALID_RANK_NUMBER 0x8000
231#define CPER_MEM_VALID_CARD_HANDLE 0x10000
232#define CPER_MEM_VALID_MODULE_HANDLE 0x20000
233
234#define CPER_PCIE_VALID_PORT_TYPE 0x0001
235#define CPER_PCIE_VALID_VERSION 0x0002
236#define CPER_PCIE_VALID_COMMAND_STATUS 0x0004
237#define CPER_PCIE_VALID_DEVICE_ID 0x0008
238#define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010
239#define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020
240#define CPER_PCIE_VALID_CAPABILITY 0x0040
241#define CPER_PCIE_VALID_AER_INFO 0x0080
242
243#define CPER_PCIE_SLOT_SHIFT 3
244
245#define CPER_ARM_VALID_MPIDR BIT(0)
246#define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1)
247#define CPER_ARM_VALID_RUNNING_STATE BIT(2)
248#define CPER_ARM_VALID_VENDOR_INFO BIT(3)
249
250#define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0)
251#define CPER_ARM_INFO_VALID_FLAGS BIT(1)
252#define CPER_ARM_INFO_VALID_ERR_INFO BIT(2)
253#define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3)
254#define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4)
255
256#define CPER_ARM_INFO_FLAGS_FIRST BIT(0)
257#define CPER_ARM_INFO_FLAGS_LAST BIT(1)
258#define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2)
259#define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3)
260
261#define CPER_ARM_CACHE_ERROR 0
262#define CPER_ARM_TLB_ERROR 1
263#define CPER_ARM_BUS_ERROR 2
264#define CPER_ARM_VENDOR_ERROR 3
265#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR
266
267#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0)
268#define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1)
269#define CPER_ARM_ERR_VALID_LEVEL BIT(2)
270#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3)
271#define CPER_ARM_ERR_VALID_CORRECTED BIT(4)
272#define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5)
273#define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6)
274#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7)
275#define CPER_ARM_ERR_VALID_TIME_OUT BIT(8)
276#define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9)
277#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10)
278#define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11)
279
280#define CPER_ARM_ERR_TRANSACTION_SHIFT 16
281#define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)
282#define CPER_ARM_ERR_OPERATION_SHIFT 18
283#define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)
284#define CPER_ARM_ERR_LEVEL_SHIFT 22
285#define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)
286#define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25
287#define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)
288#define CPER_ARM_ERR_CORRECTED_SHIFT 26
289#define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)
290#define CPER_ARM_ERR_PRECISE_PC_SHIFT 27
291#define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)
292#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28
293#define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)
294#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29
295#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)
296#define CPER_ARM_ERR_TIME_OUT_SHIFT 31
297#define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)
298#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32
299#define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)
300#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34
301#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0)
302#define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43
303#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)
304
305/*
306 * All tables and structs must be byte-packed to match CPER
307 * specification, since the tables are provided by the system BIOS
308 */
309#pragma pack(1)
310
311/* Record Header, UEFI v2.7 sec N.2.1 */
312struct cper_record_header {
313 char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */
314 u16 revision; /* must be CPER_RECORD_REV */
315 u32 signature_end; /* must be CPER_SIG_END */
316 u16 section_count;
317 u32 error_severity;
318 u32 validation_bits;
319 u32 record_length;
320 u64 timestamp;
321 guid_t platform_id;
322 guid_t partition_id;
323 guid_t creator_id;
324 guid_t notification_type;
325 u64 record_id;
326 u32 flags;
327 u64 persistence_information;
328 u8 reserved[12]; /* must be zero */
329};
330
331/* Section Descriptor, UEFI v2.7 sec N.2.2 */
332struct cper_section_descriptor {
333 u32 section_offset; /* Offset in bytes of the
334 * section body from the base
335 * of the record header */
336 u32 section_length;
337 u16 revision; /* must be CPER_RECORD_REV */
338 u8 validation_bits;
339 u8 reserved; /* must be zero */
340 u32 flags;
341 guid_t section_type;
342 guid_t fru_id;
343 u32 section_severity;
344 u8 fru_text[20];
345};
346
347/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
348struct cper_sec_proc_generic {
349 u64 validation_bits;
350 u8 proc_type;
351 u8 proc_isa;
352 u8 proc_error_type;
353 u8 operation;
354 u8 flags;
355 u8 level;
356 u16 reserved;
357 u64 cpu_version;
358 char cpu_brand[128];
359 u64 proc_id;
360 u64 target_addr;
361 u64 requestor_id;
362 u64 responder_id;
363 u64 ip;
364};
365
366/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
367struct cper_sec_proc_ia {
368 u64 validation_bits;
369 u64 lapic_id;
370 u8 cpuid[48];
371};
372
373/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
374struct cper_ia_err_info {
375 guid_t err_type;
376 u64 validation_bits;
377 u64 check_info;
378 u64 target_id;
379 u64 requestor_id;
380 u64 responder_id;
381 u64 ip;
382};
383
384/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
385struct cper_ia_proc_ctx {
386 u16 reg_ctx_type;
387 u16 reg_arr_size;
388 u32 msr_addr;
389 u64 mm_reg_addr;
390};
391
392/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
393struct cper_sec_proc_arm {
394 u32 validation_bits;
395 u16 err_info_num; /* Number of Processor Error Info */
396 u16 context_info_num; /* Number of Processor Context Info Records*/
397 u32 section_length;
398 u8 affinity_level;
399 u8 reserved[3]; /* must be zero */
400 u64 mpidr;
401 u64 midr;
402 u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
403 u32 psci_state;
404};
405
406/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
407struct cper_arm_err_info {
408 u8 version;
409 u8 length;
410 u16 validation_bits;
411 u8 type;
412 u16 multiple_error;
413 u8 flags;
414 u64 error_info;
415 u64 virt_fault_addr;
416 u64 physical_fault_addr;
417};
418
419/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
420struct cper_arm_ctx_info {
421 u16 version;
422 u16 type;
423 u32 size;
424};
425
426/* Old Memory Error Section, UEFI v2.1, v2.2 */
427struct cper_sec_mem_err_old {
428 u64 validation_bits;
429 u64 error_status;
430 u64 physical_addr;
431 u64 physical_addr_mask;
432 u16 node;
433 u16 card;
434 u16 module;
435 u16 bank;
436 u16 device;
437 u16 row;
438 u16 column;
439 u16 bit_pos;
440 u64 requestor_id;
441 u64 responder_id;
442 u64 target_id;
443 u8 error_type;
444};
445
446/* Memory Error Section (UEFI >= v2.3), UEFI v2.7 sec N.2.5 */
447struct cper_sec_mem_err {
448 u64 validation_bits;
449 u64 error_status;
450 u64 physical_addr;
451 u64 physical_addr_mask;
452 u16 node;
453 u16 card;
454 u16 module;
455 u16 bank;
456 u16 device;
457 u16 row;
458 u16 column;
459 u16 bit_pos;
460 u64 requestor_id;
461 u64 responder_id;
462 u64 target_id;
463 u8 error_type;
464 u8 reserved;
465 u16 rank;
466 u16 mem_array_handle; /* "card handle" in UEFI 2.4 */
467 u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */
468};
469
470struct cper_mem_err_compact {
471 u64 validation_bits;
472 u16 node;
473 u16 card;
474 u16 module;
475 u16 bank;
476 u16 device;
477 u16 row;
478 u16 column;
479 u16 bit_pos;
480 u64 requestor_id;
481 u64 responder_id;
482 u64 target_id;
483 u16 rank;
484 u16 mem_array_handle;
485 u16 mem_dev_handle;
486};
487
488/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
489struct cper_sec_pcie {
490 u64 validation_bits;
491 u32 port_type;
492 struct {
493 u8 minor;
494 u8 major;
495 u8 reserved[2];
496 } version;
497 u16 command;
498 u16 status;
499 u32 reserved;
500 struct {
501 u16 vendor_id;
502 u16 device_id;
503 u8 class_code[3];
504 u8 function;
505 u8 device;
506 u16 segment;
507 u8 bus;
508 u8 secondary_bus;
509 u16 slot;
510 u8 reserved;
511 } device_id;
512 struct {
513 u32 lower;
514 u32 upper;
515 } serial_number;
516 struct {
517 u16 secondary_status;
518 u16 control;
519 } bridge;
520 u8 capability[60];
521 u8 aer_info[96];
522};
523
524/* Reset to default packing */
525#pragma pack()
526
527extern const char *const cper_proc_error_type_strs[4];
528
529u64 cper_next_record_id(void);
530const char *cper_severity_str(unsigned int);
531const char *cper_mem_err_type_str(unsigned int);
532void cper_print_bits(const char *prefix, unsigned int bits,
533 const char * const strs[], unsigned int strs_size);
534void cper_mem_err_pack(const struct cper_sec_mem_err *,
535 struct cper_mem_err_compact *);
536const char *cper_mem_err_unpack(struct trace_seq *,
537 struct cper_mem_err_compact *);
538void cper_print_proc_arm(const char *pfx,
539 const struct cper_sec_proc_arm *proc);
540void cper_print_proc_ia(const char *pfx,
541 const struct cper_sec_proc_ia *proc);
542
543#endif