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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * This file is part of AD5686 DAC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7
8#ifndef __DRIVERS_IIO_DAC_AD5686_H__
9#define __DRIVERS_IIO_DAC_AD5686_H__
10
11#include <linux/types.h>
12#include <linux/cache.h>
13#include <linux/mutex.h>
14#include <linux/kernel.h>
15
16#define AD5310_CMD(x) ((x) << 12)
17
18#define AD5683_DATA(x) ((x) << 4)
19
20#define AD5686_ADDR(x) ((x) << 16)
21#define AD5686_CMD(x) ((x) << 20)
22
23#define AD5686_ADDR_DAC(chan) (0x1 << (chan))
24#define AD5686_ADDR_ALL_DAC 0xF
25
26#define AD5686_CMD_NOOP 0x0
27#define AD5686_CMD_WRITE_INPUT_N 0x1
28#define AD5686_CMD_UPDATE_DAC_N 0x2
29#define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3
30#define AD5686_CMD_POWERDOWN_DAC 0x4
31#define AD5686_CMD_LDAC_MASK 0x5
32#define AD5686_CMD_RESET 0x6
33#define AD5686_CMD_INTERNAL_REFER_SETUP 0x7
34#define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8
35#define AD5686_CMD_READBACK_ENABLE 0x9
36
37#define AD5686_LDAC_PWRDN_NONE 0x0
38#define AD5686_LDAC_PWRDN_1K 0x1
39#define AD5686_LDAC_PWRDN_100K 0x2
40#define AD5686_LDAC_PWRDN_3STATE 0x3
41
42#define AD5686_CMD_CONTROL_REG 0x4
43#define AD5686_CMD_READBACK_ENABLE_V2 0x5
44
45#define AD5310_REF_BIT_MSK BIT(8)
46#define AD5683_REF_BIT_MSK BIT(12)
47#define AD5693_REF_BIT_MSK BIT(12)
48
49/**
50 * ad5686_supported_device_ids:
51 */
52enum ad5686_supported_device_ids {
53 ID_AD5310R,
54 ID_AD5311R,
55 ID_AD5338R,
56 ID_AD5671R,
57 ID_AD5672R,
58 ID_AD5673R,
59 ID_AD5674R,
60 ID_AD5675R,
61 ID_AD5676,
62 ID_AD5676R,
63 ID_AD5677R,
64 ID_AD5679R,
65 ID_AD5681R,
66 ID_AD5682R,
67 ID_AD5683,
68 ID_AD5683R,
69 ID_AD5684,
70 ID_AD5684R,
71 ID_AD5685R,
72 ID_AD5686,
73 ID_AD5686R,
74 ID_AD5691R,
75 ID_AD5692R,
76 ID_AD5693,
77 ID_AD5693R,
78 ID_AD5694,
79 ID_AD5694R,
80 ID_AD5695R,
81 ID_AD5696,
82 ID_AD5696R,
83};
84
85enum ad5686_regmap_type {
86 AD5310_REGMAP,
87 AD5683_REGMAP,
88 AD5686_REGMAP,
89 AD5693_REGMAP
90};
91
92struct ad5686_state;
93
94typedef int (*ad5686_write_func)(struct ad5686_state *st,
95 u8 cmd, u8 addr, u16 val);
96
97typedef int (*ad5686_read_func)(struct ad5686_state *st, u8 addr);
98
99/**
100 * struct ad5686_chip_info - chip specific information
101 * @int_vref_mv: AD5620/40/60: the internal reference voltage
102 * @num_channels: number of channels
103 * @channel: channel specification
104 * @regmap_type: register map layout variant
105 */
106
107struct ad5686_chip_info {
108 u16 int_vref_mv;
109 unsigned int num_channels;
110 const struct iio_chan_spec *channels;
111 enum ad5686_regmap_type regmap_type;
112};
113
114/**
115 * struct ad5446_state - driver instance specific data
116 * @spi: spi_device
117 * @chip_info: chip model specific constants, available modes etc
118 * @reg: supply regulator
119 * @vref_mv: actual reference voltage used
120 * @pwr_down_mask: power down mask
121 * @pwr_down_mode: current power down mode
122 * @use_internal_vref: set to true if the internal reference voltage is used
123 * @lock lock to protect the data buffer during regmap ops
124 * @data: spi transfer buffers
125 */
126
127struct ad5686_state {
128 struct device *dev;
129 const struct ad5686_chip_info *chip_info;
130 struct regulator *reg;
131 unsigned short vref_mv;
132 unsigned int pwr_down_mask;
133 unsigned int pwr_down_mode;
134 ad5686_write_func write;
135 ad5686_read_func read;
136 bool use_internal_vref;
137 struct mutex lock;
138
139 /*
140 * DMA (thus cache coherency maintenance) requires the
141 * transfer buffers to live in their own cache lines.
142 */
143
144 union {
145 __be32 d32;
146 __be16 d16;
147 u8 d8[4];
148 } data[3] ____cacheline_aligned;
149};
150
151
152int ad5686_probe(struct device *dev,
153 enum ad5686_supported_device_ids chip_type,
154 const char *name, ad5686_write_func write,
155 ad5686_read_func read);
156
157int ad5686_remove(struct device *dev);
158
159
160#endif /* __DRIVERS_IIO_DAC_AD5686_H__ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * This file is part of AD5686 DAC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7
8#ifndef __DRIVERS_IIO_DAC_AD5686_H__
9#define __DRIVERS_IIO_DAC_AD5686_H__
10
11#include <linux/types.h>
12#include <linux/cache.h>
13#include <linux/mutex.h>
14#include <linux/kernel.h>
15
16#define AD5310_CMD(x) ((x) << 12)
17
18#define AD5683_DATA(x) ((x) << 4)
19
20#define AD5686_ADDR(x) ((x) << 16)
21#define AD5686_CMD(x) ((x) << 20)
22
23#define AD5686_ADDR_DAC(chan) (0x1 << (chan))
24#define AD5686_ADDR_ALL_DAC 0xF
25
26#define AD5686_CMD_NOOP 0x0
27#define AD5686_CMD_WRITE_INPUT_N 0x1
28#define AD5686_CMD_UPDATE_DAC_N 0x2
29#define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3
30#define AD5686_CMD_POWERDOWN_DAC 0x4
31#define AD5686_CMD_LDAC_MASK 0x5
32#define AD5686_CMD_RESET 0x6
33#define AD5686_CMD_INTERNAL_REFER_SETUP 0x7
34#define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8
35#define AD5686_CMD_READBACK_ENABLE 0x9
36
37#define AD5686_LDAC_PWRDN_NONE 0x0
38#define AD5686_LDAC_PWRDN_1K 0x1
39#define AD5686_LDAC_PWRDN_100K 0x2
40#define AD5686_LDAC_PWRDN_3STATE 0x3
41
42#define AD5686_CMD_CONTROL_REG 0x4
43#define AD5686_CMD_READBACK_ENABLE_V2 0x5
44
45#define AD5310_REF_BIT_MSK BIT(8)
46#define AD5683_REF_BIT_MSK BIT(12)
47#define AD5693_REF_BIT_MSK BIT(12)
48
49/**
50 * ad5686_supported_device_ids:
51 */
52enum ad5686_supported_device_ids {
53 ID_AD5310R,
54 ID_AD5311R,
55 ID_AD5671R,
56 ID_AD5672R,
57 ID_AD5674R,
58 ID_AD5675R,
59 ID_AD5676,
60 ID_AD5676R,
61 ID_AD5679R,
62 ID_AD5681R,
63 ID_AD5682R,
64 ID_AD5683,
65 ID_AD5683R,
66 ID_AD5684,
67 ID_AD5684R,
68 ID_AD5685R,
69 ID_AD5686,
70 ID_AD5686R,
71 ID_AD5691R,
72 ID_AD5692R,
73 ID_AD5693,
74 ID_AD5693R,
75 ID_AD5694,
76 ID_AD5694R,
77 ID_AD5695R,
78 ID_AD5696,
79 ID_AD5696R,
80};
81
82enum ad5686_regmap_type {
83 AD5310_REGMAP,
84 AD5683_REGMAP,
85 AD5686_REGMAP,
86 AD5693_REGMAP
87};
88
89struct ad5686_state;
90
91typedef int (*ad5686_write_func)(struct ad5686_state *st,
92 u8 cmd, u8 addr, u16 val);
93
94typedef int (*ad5686_read_func)(struct ad5686_state *st, u8 addr);
95
96/**
97 * struct ad5686_chip_info - chip specific information
98 * @int_vref_mv: AD5620/40/60: the internal reference voltage
99 * @num_channels: number of channels
100 * @channel: channel specification
101 * @regmap_type: register map layout variant
102 */
103
104struct ad5686_chip_info {
105 u16 int_vref_mv;
106 unsigned int num_channels;
107 struct iio_chan_spec *channels;
108 enum ad5686_regmap_type regmap_type;
109};
110
111/**
112 * struct ad5446_state - driver instance specific data
113 * @spi: spi_device
114 * @chip_info: chip model specific constants, available modes etc
115 * @reg: supply regulator
116 * @vref_mv: actual reference voltage used
117 * @pwr_down_mask: power down mask
118 * @pwr_down_mode: current power down mode
119 * @use_internal_vref: set to true if the internal reference voltage is used
120 * @data: spi transfer buffers
121 */
122
123struct ad5686_state {
124 struct device *dev;
125 const struct ad5686_chip_info *chip_info;
126 struct regulator *reg;
127 unsigned short vref_mv;
128 unsigned int pwr_down_mask;
129 unsigned int pwr_down_mode;
130 ad5686_write_func write;
131 ad5686_read_func read;
132 bool use_internal_vref;
133
134 /*
135 * DMA (thus cache coherency maintenance) requires the
136 * transfer buffers to live in their own cache lines.
137 */
138
139 union {
140 __be32 d32;
141 __be16 d16;
142 u8 d8[4];
143 } data[3] ____cacheline_aligned;
144};
145
146
147int ad5686_probe(struct device *dev,
148 enum ad5686_supported_device_ids chip_type,
149 const char *name, ad5686_write_func write,
150 ad5686_read_func read);
151
152int ad5686_remove(struct device *dev);
153
154
155#endif /* __DRIVERS_IIO_DAC_AD5686_H__ */