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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 */
6
7#define DSS_SUBSYS_NAME "DSI"
8
9#include <linux/kernel.h>
10#include <linux/mfd/syscon.h>
11#include <linux/regmap.h>
12#include <linux/io.h>
13#include <linux/clk.h>
14#include <linux/device.h>
15#include <linux/err.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/delay.h>
19#include <linux/gpio/consumer.h>
20#include <linux/mutex.h>
21#include <linux/module.h>
22#include <linux/semaphore.h>
23#include <linux/seq_file.h>
24#include <linux/platform_device.h>
25#include <linux/regulator/consumer.h>
26#include <linux/wait.h>
27#include <linux/workqueue.h>
28#include <linux/sched.h>
29#include <linux/slab.h>
30#include <linux/debugfs.h>
31#include <linux/pm_runtime.h>
32#include <linux/of.h>
33#include <linux/of_graph.h>
34#include <linux/of_platform.h>
35#include <linux/component.h>
36#include <linux/sys_soc.h>
37
38#include <drm/drm_bridge.h>
39#include <drm/drm_mipi_dsi.h>
40#include <drm/drm_panel.h>
41#include <video/mipi_display.h>
42
43#include "omapdss.h"
44#include "dss.h"
45
46#define DSI_CATCH_MISSING_TE
47
48#include "dsi.h"
49
50#define REG_GET(dsi, idx, start, end) \
51 FLD_GET(dsi_read_reg(dsi, idx), start, end)
52
53#define REG_FLD_MOD(dsi, idx, val, start, end) \
54 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
55
56static int dsi_init_dispc(struct dsi_data *dsi);
57static void dsi_uninit_dispc(struct dsi_data *dsi);
58
59static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel);
60
61static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc,
62 const struct mipi_dsi_msg *msg);
63
64#ifdef DSI_PERF_MEASURE
65static bool dsi_perf;
66module_param(dsi_perf, bool, 0644);
67#endif
68
69/* Note: for some reason video mode seems to work only if VC_VIDEO is 0 */
70#define VC_VIDEO 0
71#define VC_CMD 1
72
73#define drm_bridge_to_dsi(bridge) \
74 container_of(bridge, struct dsi_data, bridge)
75
76static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev)
77{
78 return dev_get_drvdata(dssdev->dev);
79}
80
81static inline struct dsi_data *host_to_omap(struct mipi_dsi_host *host)
82{
83 return container_of(host, struct dsi_data, host);
84}
85
86static inline void dsi_write_reg(struct dsi_data *dsi,
87 const struct dsi_reg idx, u32 val)
88{
89 void __iomem *base;
90
91 switch(idx.module) {
92 case DSI_PROTO: base = dsi->proto_base; break;
93 case DSI_PHY: base = dsi->phy_base; break;
94 case DSI_PLL: base = dsi->pll_base; break;
95 default: return;
96 }
97
98 __raw_writel(val, base + idx.idx);
99}
100
101static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx)
102{
103 void __iomem *base;
104
105 switch(idx.module) {
106 case DSI_PROTO: base = dsi->proto_base; break;
107 case DSI_PHY: base = dsi->phy_base; break;
108 case DSI_PLL: base = dsi->pll_base; break;
109 default: return 0;
110 }
111
112 return __raw_readl(base + idx.idx);
113}
114
115static void dsi_bus_lock(struct dsi_data *dsi)
116{
117 down(&dsi->bus_lock);
118}
119
120static void dsi_bus_unlock(struct dsi_data *dsi)
121{
122 up(&dsi->bus_lock);
123}
124
125static bool dsi_bus_is_locked(struct dsi_data *dsi)
126{
127 return dsi->bus_lock.count == 0;
128}
129
130static void dsi_completion_handler(void *data, u32 mask)
131{
132 complete((struct completion *)data);
133}
134
135static inline bool wait_for_bit_change(struct dsi_data *dsi,
136 const struct dsi_reg idx,
137 int bitnum, int value)
138{
139 unsigned long timeout;
140 ktime_t wait;
141 int t;
142
143 /* first busyloop to see if the bit changes right away */
144 t = 100;
145 while (t-- > 0) {
146 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
147 return true;
148 }
149
150 /* then loop for 500ms, sleeping for 1ms in between */
151 timeout = jiffies + msecs_to_jiffies(500);
152 while (time_before(jiffies, timeout)) {
153 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
154 return true;
155
156 wait = ns_to_ktime(1000 * 1000);
157 set_current_state(TASK_UNINTERRUPTIBLE);
158 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
159 }
160
161 return false;
162}
163
164#ifdef DSI_PERF_MEASURE
165static void dsi_perf_mark_setup(struct dsi_data *dsi)
166{
167 dsi->perf_setup_time = ktime_get();
168}
169
170static void dsi_perf_mark_start(struct dsi_data *dsi)
171{
172 dsi->perf_start_time = ktime_get();
173}
174
175static void dsi_perf_show(struct dsi_data *dsi, const char *name)
176{
177 ktime_t t, setup_time, trans_time;
178 u32 total_bytes;
179 u32 setup_us, trans_us, total_us;
180
181 if (!dsi_perf)
182 return;
183
184 t = ktime_get();
185
186 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
187 setup_us = (u32)ktime_to_us(setup_time);
188 if (setup_us == 0)
189 setup_us = 1;
190
191 trans_time = ktime_sub(t, dsi->perf_start_time);
192 trans_us = (u32)ktime_to_us(trans_time);
193 if (trans_us == 0)
194 trans_us = 1;
195
196 total_us = setup_us + trans_us;
197
198 total_bytes = dsi->update_bytes;
199
200 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n",
201 name,
202 setup_us,
203 trans_us,
204 total_us,
205 1000 * 1000 / total_us,
206 total_bytes,
207 total_bytes * 1000 / total_us);
208}
209#else
210static inline void dsi_perf_mark_setup(struct dsi_data *dsi)
211{
212}
213
214static inline void dsi_perf_mark_start(struct dsi_data *dsi)
215{
216}
217
218static inline void dsi_perf_show(struct dsi_data *dsi, const char *name)
219{
220}
221#endif
222
223static int verbose_irq;
224
225static void print_irq_status(u32 status)
226{
227 if (status == 0)
228 return;
229
230 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
231 return;
232
233#define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
234
235 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
236 status,
237 verbose_irq ? PIS(VC0) : "",
238 verbose_irq ? PIS(VC1) : "",
239 verbose_irq ? PIS(VC2) : "",
240 verbose_irq ? PIS(VC3) : "",
241 PIS(WAKEUP),
242 PIS(RESYNC),
243 PIS(PLL_LOCK),
244 PIS(PLL_UNLOCK),
245 PIS(PLL_RECALL),
246 PIS(COMPLEXIO_ERR),
247 PIS(HS_TX_TIMEOUT),
248 PIS(LP_RX_TIMEOUT),
249 PIS(TE_TRIGGER),
250 PIS(ACK_TRIGGER),
251 PIS(SYNC_LOST),
252 PIS(LDO_POWER_GOOD),
253 PIS(TA_TIMEOUT));
254#undef PIS
255}
256
257static void print_irq_status_vc(int vc, u32 status)
258{
259 if (status == 0)
260 return;
261
262 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
263 return;
264
265#define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
266
267 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
268 vc,
269 status,
270 PIS(CS),
271 PIS(ECC_CORR),
272 PIS(ECC_NO_CORR),
273 verbose_irq ? PIS(PACKET_SENT) : "",
274 PIS(BTA),
275 PIS(FIFO_TX_OVF),
276 PIS(FIFO_RX_OVF),
277 PIS(FIFO_TX_UDF),
278 PIS(PP_BUSY_CHANGE));
279#undef PIS
280}
281
282static void print_irq_status_cio(u32 status)
283{
284 if (status == 0)
285 return;
286
287#define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
288
289 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
290 status,
291 PIS(ERRSYNCESC1),
292 PIS(ERRSYNCESC2),
293 PIS(ERRSYNCESC3),
294 PIS(ERRESC1),
295 PIS(ERRESC2),
296 PIS(ERRESC3),
297 PIS(ERRCONTROL1),
298 PIS(ERRCONTROL2),
299 PIS(ERRCONTROL3),
300 PIS(STATEULPS1),
301 PIS(STATEULPS2),
302 PIS(STATEULPS3),
303 PIS(ERRCONTENTIONLP0_1),
304 PIS(ERRCONTENTIONLP1_1),
305 PIS(ERRCONTENTIONLP0_2),
306 PIS(ERRCONTENTIONLP1_2),
307 PIS(ERRCONTENTIONLP0_3),
308 PIS(ERRCONTENTIONLP1_3),
309 PIS(ULPSACTIVENOT_ALL0),
310 PIS(ULPSACTIVENOT_ALL1));
311#undef PIS
312}
313
314#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
315static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus,
316 u32 *vcstatus, u32 ciostatus)
317{
318 int i;
319
320 spin_lock(&dsi->irq_stats_lock);
321
322 dsi->irq_stats.irq_count++;
323 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
324
325 for (i = 0; i < 4; ++i)
326 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
327
328 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
329
330 spin_unlock(&dsi->irq_stats_lock);
331}
332#else
333#define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus)
334#endif
335
336static int debug_irq;
337
338static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus,
339 u32 *vcstatus, u32 ciostatus)
340{
341 int i;
342
343 if (irqstatus & DSI_IRQ_ERROR_MASK) {
344 DSSERR("DSI error, irqstatus %x\n", irqstatus);
345 print_irq_status(irqstatus);
346 spin_lock(&dsi->errors_lock);
347 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
348 spin_unlock(&dsi->errors_lock);
349 } else if (debug_irq) {
350 print_irq_status(irqstatus);
351 }
352
353 for (i = 0; i < 4; ++i) {
354 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
355 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
356 i, vcstatus[i]);
357 print_irq_status_vc(i, vcstatus[i]);
358 } else if (debug_irq) {
359 print_irq_status_vc(i, vcstatus[i]);
360 }
361 }
362
363 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
364 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
365 print_irq_status_cio(ciostatus);
366 } else if (debug_irq) {
367 print_irq_status_cio(ciostatus);
368 }
369}
370
371static void dsi_call_isrs(struct dsi_isr_data *isr_array,
372 unsigned int isr_array_size, u32 irqstatus)
373{
374 struct dsi_isr_data *isr_data;
375 int i;
376
377 for (i = 0; i < isr_array_size; i++) {
378 isr_data = &isr_array[i];
379 if (isr_data->isr && isr_data->mask & irqstatus)
380 isr_data->isr(isr_data->arg, irqstatus);
381 }
382}
383
384static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
385 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
386{
387 int i;
388
389 dsi_call_isrs(isr_tables->isr_table,
390 ARRAY_SIZE(isr_tables->isr_table),
391 irqstatus);
392
393 for (i = 0; i < 4; ++i) {
394 if (vcstatus[i] == 0)
395 continue;
396 dsi_call_isrs(isr_tables->isr_table_vc[i],
397 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
398 vcstatus[i]);
399 }
400
401 if (ciostatus != 0)
402 dsi_call_isrs(isr_tables->isr_table_cio,
403 ARRAY_SIZE(isr_tables->isr_table_cio),
404 ciostatus);
405}
406
407static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
408{
409 struct dsi_data *dsi = arg;
410 u32 irqstatus, vcstatus[4], ciostatus;
411 int i;
412
413 if (!dsi->is_enabled)
414 return IRQ_NONE;
415
416 spin_lock(&dsi->irq_lock);
417
418 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS);
419
420 /* IRQ is not for us */
421 if (!irqstatus) {
422 spin_unlock(&dsi->irq_lock);
423 return IRQ_NONE;
424 }
425
426 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
427 /* flush posted write */
428 dsi_read_reg(dsi, DSI_IRQSTATUS);
429
430 for (i = 0; i < 4; ++i) {
431 if ((irqstatus & (1 << i)) == 0) {
432 vcstatus[i] = 0;
433 continue;
434 }
435
436 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
437
438 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]);
439 /* flush posted write */
440 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
441 }
442
443 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
444 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
445
446 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
447 /* flush posted write */
448 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
449 } else {
450 ciostatus = 0;
451 }
452
453#ifdef DSI_CATCH_MISSING_TE
454 if (irqstatus & DSI_IRQ_TE_TRIGGER)
455 del_timer(&dsi->te_timer);
456#endif
457
458 /* make a copy and unlock, so that isrs can unregister
459 * themselves */
460 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
461 sizeof(dsi->isr_tables));
462
463 spin_unlock(&dsi->irq_lock);
464
465 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
466
467 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus);
468
469 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus);
470
471 return IRQ_HANDLED;
472}
473
474/* dsi->irq_lock has to be locked by the caller */
475static void _omap_dsi_configure_irqs(struct dsi_data *dsi,
476 struct dsi_isr_data *isr_array,
477 unsigned int isr_array_size,
478 u32 default_mask,
479 const struct dsi_reg enable_reg,
480 const struct dsi_reg status_reg)
481{
482 struct dsi_isr_data *isr_data;
483 u32 mask;
484 u32 old_mask;
485 int i;
486
487 mask = default_mask;
488
489 for (i = 0; i < isr_array_size; i++) {
490 isr_data = &isr_array[i];
491
492 if (isr_data->isr == NULL)
493 continue;
494
495 mask |= isr_data->mask;
496 }
497
498 old_mask = dsi_read_reg(dsi, enable_reg);
499 /* clear the irqstatus for newly enabled irqs */
500 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask);
501 dsi_write_reg(dsi, enable_reg, mask);
502
503 /* flush posted writes */
504 dsi_read_reg(dsi, enable_reg);
505 dsi_read_reg(dsi, status_reg);
506}
507
508/* dsi->irq_lock has to be locked by the caller */
509static void _omap_dsi_set_irqs(struct dsi_data *dsi)
510{
511 u32 mask = DSI_IRQ_ERROR_MASK;
512#ifdef DSI_CATCH_MISSING_TE
513 mask |= DSI_IRQ_TE_TRIGGER;
514#endif
515 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table,
516 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
517 DSI_IRQENABLE, DSI_IRQSTATUS);
518}
519
520/* dsi->irq_lock has to be locked by the caller */
521static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc)
522{
523 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc],
524 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
525 DSI_VC_IRQ_ERROR_MASK,
526 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
527}
528
529/* dsi->irq_lock has to be locked by the caller */
530static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi)
531{
532 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio,
533 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
534 DSI_CIO_IRQ_ERROR_MASK,
535 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
536}
537
538static void _dsi_initialize_irq(struct dsi_data *dsi)
539{
540 unsigned long flags;
541 int vc;
542
543 spin_lock_irqsave(&dsi->irq_lock, flags);
544
545 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
546
547 _omap_dsi_set_irqs(dsi);
548 for (vc = 0; vc < 4; ++vc)
549 _omap_dsi_set_irqs_vc(dsi, vc);
550 _omap_dsi_set_irqs_cio(dsi);
551
552 spin_unlock_irqrestore(&dsi->irq_lock, flags);
553}
554
555static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
556 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
557{
558 struct dsi_isr_data *isr_data;
559 int free_idx;
560 int i;
561
562 BUG_ON(isr == NULL);
563
564 /* check for duplicate entry and find a free slot */
565 free_idx = -1;
566 for (i = 0; i < isr_array_size; i++) {
567 isr_data = &isr_array[i];
568
569 if (isr_data->isr == isr && isr_data->arg == arg &&
570 isr_data->mask == mask) {
571 return -EINVAL;
572 }
573
574 if (isr_data->isr == NULL && free_idx == -1)
575 free_idx = i;
576 }
577
578 if (free_idx == -1)
579 return -EBUSY;
580
581 isr_data = &isr_array[free_idx];
582 isr_data->isr = isr;
583 isr_data->arg = arg;
584 isr_data->mask = mask;
585
586 return 0;
587}
588
589static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
590 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
591{
592 struct dsi_isr_data *isr_data;
593 int i;
594
595 for (i = 0; i < isr_array_size; i++) {
596 isr_data = &isr_array[i];
597 if (isr_data->isr != isr || isr_data->arg != arg ||
598 isr_data->mask != mask)
599 continue;
600
601 isr_data->isr = NULL;
602 isr_data->arg = NULL;
603 isr_data->mask = 0;
604
605 return 0;
606 }
607
608 return -EINVAL;
609}
610
611static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
612 void *arg, u32 mask)
613{
614 unsigned long flags;
615 int r;
616
617 spin_lock_irqsave(&dsi->irq_lock, flags);
618
619 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
620 ARRAY_SIZE(dsi->isr_tables.isr_table));
621
622 if (r == 0)
623 _omap_dsi_set_irqs(dsi);
624
625 spin_unlock_irqrestore(&dsi->irq_lock, flags);
626
627 return r;
628}
629
630static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
631 void *arg, u32 mask)
632{
633 unsigned long flags;
634 int r;
635
636 spin_lock_irqsave(&dsi->irq_lock, flags);
637
638 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
639 ARRAY_SIZE(dsi->isr_tables.isr_table));
640
641 if (r == 0)
642 _omap_dsi_set_irqs(dsi);
643
644 spin_unlock_irqrestore(&dsi->irq_lock, flags);
645
646 return r;
647}
648
649static int dsi_register_isr_vc(struct dsi_data *dsi, int vc,
650 omap_dsi_isr_t isr, void *arg, u32 mask)
651{
652 unsigned long flags;
653 int r;
654
655 spin_lock_irqsave(&dsi->irq_lock, flags);
656
657 r = _dsi_register_isr(isr, arg, mask,
658 dsi->isr_tables.isr_table_vc[vc],
659 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]));
660
661 if (r == 0)
662 _omap_dsi_set_irqs_vc(dsi, vc);
663
664 spin_unlock_irqrestore(&dsi->irq_lock, flags);
665
666 return r;
667}
668
669static int dsi_unregister_isr_vc(struct dsi_data *dsi, int vc,
670 omap_dsi_isr_t isr, void *arg, u32 mask)
671{
672 unsigned long flags;
673 int r;
674
675 spin_lock_irqsave(&dsi->irq_lock, flags);
676
677 r = _dsi_unregister_isr(isr, arg, mask,
678 dsi->isr_tables.isr_table_vc[vc],
679 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]));
680
681 if (r == 0)
682 _omap_dsi_set_irqs_vc(dsi, vc);
683
684 spin_unlock_irqrestore(&dsi->irq_lock, flags);
685
686 return r;
687}
688
689static u32 dsi_get_errors(struct dsi_data *dsi)
690{
691 unsigned long flags;
692 u32 e;
693
694 spin_lock_irqsave(&dsi->errors_lock, flags);
695 e = dsi->errors;
696 dsi->errors = 0;
697 spin_unlock_irqrestore(&dsi->errors_lock, flags);
698 return e;
699}
700
701static int dsi_runtime_get(struct dsi_data *dsi)
702{
703 int r;
704
705 DSSDBG("dsi_runtime_get\n");
706
707 r = pm_runtime_get_sync(dsi->dev);
708 if (WARN_ON(r < 0)) {
709 pm_runtime_put_noidle(dsi->dev);
710 return r;
711 }
712 return 0;
713}
714
715static void dsi_runtime_put(struct dsi_data *dsi)
716{
717 int r;
718
719 DSSDBG("dsi_runtime_put\n");
720
721 r = pm_runtime_put_sync(dsi->dev);
722 WARN_ON(r < 0 && r != -ENOSYS);
723}
724
725static void _dsi_print_reset_status(struct dsi_data *dsi)
726{
727 int b0, b1, b2;
728
729 /* A dummy read using the SCP interface to any DSIPHY register is
730 * required after DSIPHY reset to complete the reset of the DSI complex
731 * I/O. */
732 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
733
734 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
735 b0 = 28;
736 b1 = 27;
737 b2 = 26;
738 } else {
739 b0 = 24;
740 b1 = 25;
741 b2 = 26;
742 }
743
744#define DSI_FLD_GET(fld, start, end)\
745 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end)
746
747 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
748 DSI_FLD_GET(PLL_STATUS, 0, 0),
749 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
750 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
751 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
752 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
753 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
754 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
755 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
756
757#undef DSI_FLD_GET
758}
759
760static inline int dsi_if_enable(struct dsi_data *dsi, bool enable)
761{
762 DSSDBG("dsi_if_enable(%d)\n", enable);
763
764 enable = enable ? 1 : 0;
765 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */
766
767 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) {
768 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
769 return -EIO;
770 }
771
772 return 0;
773}
774
775static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi)
776{
777 return dsi->pll.cinfo.clkout[HSDIV_DISPC];
778}
779
780static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi)
781{
782 return dsi->pll.cinfo.clkout[HSDIV_DSI];
783}
784
785static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi)
786{
787 return dsi->pll.cinfo.clkdco / 16;
788}
789
790static unsigned long dsi_fclk_rate(struct dsi_data *dsi)
791{
792 unsigned long r;
793 enum dss_clk_source source;
794
795 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id);
796 if (source == DSS_CLK_SRC_FCK) {
797 /* DSI FCLK source is DSS_CLK_FCK */
798 r = clk_get_rate(dsi->dss_clk);
799 } else {
800 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
801 r = dsi_get_pll_hsdiv_dsi_rate(dsi);
802 }
803
804 return r;
805}
806
807static int dsi_lp_clock_calc(unsigned long dsi_fclk,
808 unsigned long lp_clk_min, unsigned long lp_clk_max,
809 struct dsi_lp_clock_info *lp_cinfo)
810{
811 unsigned int lp_clk_div;
812 unsigned long lp_clk;
813
814 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
815 lp_clk = dsi_fclk / 2 / lp_clk_div;
816
817 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
818 return -EINVAL;
819
820 lp_cinfo->lp_clk_div = lp_clk_div;
821 lp_cinfo->lp_clk = lp_clk;
822
823 return 0;
824}
825
826static int dsi_set_lp_clk_divisor(struct dsi_data *dsi)
827{
828 unsigned long dsi_fclk;
829 unsigned int lp_clk_div;
830 unsigned long lp_clk;
831 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv;
832
833
834 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
835
836 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
837 return -EINVAL;
838
839 dsi_fclk = dsi_fclk_rate(dsi);
840
841 lp_clk = dsi_fclk / 2 / lp_clk_div;
842
843 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
844 dsi->current_lp_cinfo.lp_clk = lp_clk;
845 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
846
847 /* LP_CLK_DIVISOR */
848 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0);
849
850 /* LP_RX_SYNCHRO_ENABLE */
851 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
852
853 return 0;
854}
855
856static void dsi_enable_scp_clk(struct dsi_data *dsi)
857{
858 if (dsi->scp_clk_refcount++ == 0)
859 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
860}
861
862static void dsi_disable_scp_clk(struct dsi_data *dsi)
863{
864 WARN_ON(dsi->scp_clk_refcount == 0);
865 if (--dsi->scp_clk_refcount == 0)
866 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
867}
868
869enum dsi_pll_power_state {
870 DSI_PLL_POWER_OFF = 0x0,
871 DSI_PLL_POWER_ON_HSCLK = 0x1,
872 DSI_PLL_POWER_ON_ALL = 0x2,
873 DSI_PLL_POWER_ON_DIV = 0x3,
874};
875
876static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state)
877{
878 int t = 0;
879
880 /* DSI-PLL power command 0x3 is not working */
881 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) &&
882 state == DSI_PLL_POWER_ON_DIV)
883 state = DSI_PLL_POWER_ON_ALL;
884
885 /* PLL_PWR_CMD */
886 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30);
887
888 /* PLL_PWR_STATUS */
889 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) {
890 if (++t > 1000) {
891 DSSERR("Failed to set DSI PLL power mode to %d\n",
892 state);
893 return -ENODEV;
894 }
895 udelay(1);
896 }
897
898 return 0;
899}
900
901
902static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi,
903 struct dss_pll_clock_info *cinfo)
904{
905 unsigned long max_dsi_fck;
906
907 max_dsi_fck = dsi->data->max_fck_freq;
908
909 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
910 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
911}
912
913static int dsi_pll_enable(struct dss_pll *pll)
914{
915 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
916 int r = 0;
917
918 DSSDBG("PLL init\n");
919
920 r = dsi_runtime_get(dsi);
921 if (r)
922 return r;
923
924 /*
925 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
926 */
927 dsi_enable_scp_clk(dsi);
928
929 r = regulator_enable(dsi->vdds_dsi_reg);
930 if (r)
931 goto err0;
932
933 /* XXX PLL does not come out of reset without this... */
934 dispc_pck_free_enable(dsi->dss->dispc, 1);
935
936 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) {
937 DSSERR("PLL not coming out of reset.\n");
938 r = -ENODEV;
939 dispc_pck_free_enable(dsi->dss->dispc, 0);
940 goto err1;
941 }
942
943 /* XXX ... but if left on, we get problems when planes do not
944 * fill the whole display. No idea about this */
945 dispc_pck_free_enable(dsi->dss->dispc, 0);
946
947 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL);
948
949 if (r)
950 goto err1;
951
952 DSSDBG("PLL init done\n");
953
954 return 0;
955err1:
956 regulator_disable(dsi->vdds_dsi_reg);
957err0:
958 dsi_disable_scp_clk(dsi);
959 dsi_runtime_put(dsi);
960 return r;
961}
962
963static void dsi_pll_disable(struct dss_pll *pll)
964{
965 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
966
967 dsi_pll_power(dsi, DSI_PLL_POWER_OFF);
968
969 regulator_disable(dsi->vdds_dsi_reg);
970
971 dsi_disable_scp_clk(dsi);
972 dsi_runtime_put(dsi);
973
974 DSSDBG("PLL disable done\n");
975}
976
977static int dsi_dump_dsi_clocks(struct seq_file *s, void *p)
978{
979 struct dsi_data *dsi = s->private;
980 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
981 enum dss_clk_source dispc_clk_src, dsi_clk_src;
982 int dsi_module = dsi->module_id;
983 struct dss_pll *pll = &dsi->pll;
984
985 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss);
986 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module);
987
988 if (dsi_runtime_get(dsi))
989 return 0;
990
991 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
992
993 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
994
995 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
996
997 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n",
998 cinfo->clkdco, cinfo->m);
999
1000 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1001 dss_get_clk_source_name(dsi_module == 0 ?
1002 DSS_CLK_SRC_PLL1_1 :
1003 DSS_CLK_SRC_PLL2_1),
1004 cinfo->clkout[HSDIV_DISPC],
1005 cinfo->mX[HSDIV_DISPC],
1006 dispc_clk_src == DSS_CLK_SRC_FCK ?
1007 "off" : "on");
1008
1009 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1010 dss_get_clk_source_name(dsi_module == 0 ?
1011 DSS_CLK_SRC_PLL1_2 :
1012 DSS_CLK_SRC_PLL2_2),
1013 cinfo->clkout[HSDIV_DSI],
1014 cinfo->mX[HSDIV_DSI],
1015 dsi_clk_src == DSS_CLK_SRC_FCK ?
1016 "off" : "on");
1017
1018 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1019
1020 seq_printf(s, "dsi fclk source = %s\n",
1021 dss_get_clk_source_name(dsi_clk_src));
1022
1023 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi));
1024
1025 seq_printf(s, "DDR_CLK\t\t%lu\n",
1026 cinfo->clkdco / 4);
1027
1028 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi));
1029
1030 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1031
1032 dsi_runtime_put(dsi);
1033
1034 return 0;
1035}
1036
1037#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1038static int dsi_dump_dsi_irqs(struct seq_file *s, void *p)
1039{
1040 struct dsi_data *dsi = s->private;
1041 unsigned long flags;
1042 struct dsi_irq_stats stats;
1043
1044 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1045
1046 stats = dsi->irq_stats;
1047 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1048 dsi->irq_stats.last_reset = jiffies;
1049
1050 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1051
1052 seq_printf(s, "period %u ms\n",
1053 jiffies_to_msecs(jiffies - stats.last_reset));
1054
1055 seq_printf(s, "irqs %d\n", stats.irq_count);
1056#define PIS(x) \
1057 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1058
1059 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1060 PIS(VC0);
1061 PIS(VC1);
1062 PIS(VC2);
1063 PIS(VC3);
1064 PIS(WAKEUP);
1065 PIS(RESYNC);
1066 PIS(PLL_LOCK);
1067 PIS(PLL_UNLOCK);
1068 PIS(PLL_RECALL);
1069 PIS(COMPLEXIO_ERR);
1070 PIS(HS_TX_TIMEOUT);
1071 PIS(LP_RX_TIMEOUT);
1072 PIS(TE_TRIGGER);
1073 PIS(ACK_TRIGGER);
1074 PIS(SYNC_LOST);
1075 PIS(LDO_POWER_GOOD);
1076 PIS(TA_TIMEOUT);
1077#undef PIS
1078
1079#define PIS(x) \
1080 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1081 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1082 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1083 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1084 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1085
1086 seq_printf(s, "-- VC interrupts --\n");
1087 PIS(CS);
1088 PIS(ECC_CORR);
1089 PIS(PACKET_SENT);
1090 PIS(FIFO_TX_OVF);
1091 PIS(FIFO_RX_OVF);
1092 PIS(BTA);
1093 PIS(ECC_NO_CORR);
1094 PIS(FIFO_TX_UDF);
1095 PIS(PP_BUSY_CHANGE);
1096#undef PIS
1097
1098#define PIS(x) \
1099 seq_printf(s, "%-20s %10d\n", #x, \
1100 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1101
1102 seq_printf(s, "-- CIO interrupts --\n");
1103 PIS(ERRSYNCESC1);
1104 PIS(ERRSYNCESC2);
1105 PIS(ERRSYNCESC3);
1106 PIS(ERRESC1);
1107 PIS(ERRESC2);
1108 PIS(ERRESC3);
1109 PIS(ERRCONTROL1);
1110 PIS(ERRCONTROL2);
1111 PIS(ERRCONTROL3);
1112 PIS(STATEULPS1);
1113 PIS(STATEULPS2);
1114 PIS(STATEULPS3);
1115 PIS(ERRCONTENTIONLP0_1);
1116 PIS(ERRCONTENTIONLP1_1);
1117 PIS(ERRCONTENTIONLP0_2);
1118 PIS(ERRCONTENTIONLP1_2);
1119 PIS(ERRCONTENTIONLP0_3);
1120 PIS(ERRCONTENTIONLP1_3);
1121 PIS(ULPSACTIVENOT_ALL0);
1122 PIS(ULPSACTIVENOT_ALL1);
1123#undef PIS
1124
1125 return 0;
1126}
1127#endif
1128
1129static int dsi_dump_dsi_regs(struct seq_file *s, void *p)
1130{
1131 struct dsi_data *dsi = s->private;
1132
1133 if (dsi_runtime_get(dsi))
1134 return 0;
1135 dsi_enable_scp_clk(dsi);
1136
1137#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r))
1138 DUMPREG(DSI_REVISION);
1139 DUMPREG(DSI_SYSCONFIG);
1140 DUMPREG(DSI_SYSSTATUS);
1141 DUMPREG(DSI_IRQSTATUS);
1142 DUMPREG(DSI_IRQENABLE);
1143 DUMPREG(DSI_CTRL);
1144 DUMPREG(DSI_COMPLEXIO_CFG1);
1145 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1146 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1147 DUMPREG(DSI_CLK_CTRL);
1148 DUMPREG(DSI_TIMING1);
1149 DUMPREG(DSI_TIMING2);
1150 DUMPREG(DSI_VM_TIMING1);
1151 DUMPREG(DSI_VM_TIMING2);
1152 DUMPREG(DSI_VM_TIMING3);
1153 DUMPREG(DSI_CLK_TIMING);
1154 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1155 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1156 DUMPREG(DSI_COMPLEXIO_CFG2);
1157 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1158 DUMPREG(DSI_VM_TIMING4);
1159 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1160 DUMPREG(DSI_VM_TIMING5);
1161 DUMPREG(DSI_VM_TIMING6);
1162 DUMPREG(DSI_VM_TIMING7);
1163 DUMPREG(DSI_STOPCLK_TIMING);
1164
1165 DUMPREG(DSI_VC_CTRL(0));
1166 DUMPREG(DSI_VC_TE(0));
1167 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1168 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1169 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1170 DUMPREG(DSI_VC_IRQSTATUS(0));
1171 DUMPREG(DSI_VC_IRQENABLE(0));
1172
1173 DUMPREG(DSI_VC_CTRL(1));
1174 DUMPREG(DSI_VC_TE(1));
1175 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1176 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1177 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1178 DUMPREG(DSI_VC_IRQSTATUS(1));
1179 DUMPREG(DSI_VC_IRQENABLE(1));
1180
1181 DUMPREG(DSI_VC_CTRL(2));
1182 DUMPREG(DSI_VC_TE(2));
1183 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1184 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1185 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1186 DUMPREG(DSI_VC_IRQSTATUS(2));
1187 DUMPREG(DSI_VC_IRQENABLE(2));
1188
1189 DUMPREG(DSI_VC_CTRL(3));
1190 DUMPREG(DSI_VC_TE(3));
1191 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1192 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1193 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1194 DUMPREG(DSI_VC_IRQSTATUS(3));
1195 DUMPREG(DSI_VC_IRQENABLE(3));
1196
1197 DUMPREG(DSI_DSIPHY_CFG0);
1198 DUMPREG(DSI_DSIPHY_CFG1);
1199 DUMPREG(DSI_DSIPHY_CFG2);
1200 DUMPREG(DSI_DSIPHY_CFG5);
1201
1202 DUMPREG(DSI_PLL_CONTROL);
1203 DUMPREG(DSI_PLL_STATUS);
1204 DUMPREG(DSI_PLL_GO);
1205 DUMPREG(DSI_PLL_CONFIGURATION1);
1206 DUMPREG(DSI_PLL_CONFIGURATION2);
1207#undef DUMPREG
1208
1209 dsi_disable_scp_clk(dsi);
1210 dsi_runtime_put(dsi);
1211
1212 return 0;
1213}
1214
1215enum dsi_cio_power_state {
1216 DSI_COMPLEXIO_POWER_OFF = 0x0,
1217 DSI_COMPLEXIO_POWER_ON = 0x1,
1218 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1219};
1220
1221static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state)
1222{
1223 int t = 0;
1224
1225 /* PWR_CMD */
1226 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27);
1227
1228 /* PWR_STATUS */
1229 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1),
1230 26, 25) != state) {
1231 if (++t > 1000) {
1232 DSSERR("failed to set complexio power state to "
1233 "%d\n", state);
1234 return -ENODEV;
1235 }
1236 udelay(1);
1237 }
1238
1239 return 0;
1240}
1241
1242static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi)
1243{
1244 int val;
1245
1246 /* line buffer on OMAP3 is 1024 x 24bits */
1247 /* XXX: for some reason using full buffer size causes
1248 * considerable TX slowdown with update sizes that fill the
1249 * whole buffer */
1250 if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1251 return 1023 * 3;
1252
1253 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1254
1255 switch (val) {
1256 case 1:
1257 return 512 * 3; /* 512x24 bits */
1258 case 2:
1259 return 682 * 3; /* 682x24 bits */
1260 case 3:
1261 return 853 * 3; /* 853x24 bits */
1262 case 4:
1263 return 1024 * 3; /* 1024x24 bits */
1264 case 5:
1265 return 1194 * 3; /* 1194x24 bits */
1266 case 6:
1267 return 1365 * 3; /* 1365x24 bits */
1268 case 7:
1269 return 1920 * 3; /* 1920x24 bits */
1270 default:
1271 BUG();
1272 return 0;
1273 }
1274}
1275
1276static int dsi_set_lane_config(struct dsi_data *dsi)
1277{
1278 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1279 static const enum dsi_lane_function functions[] = {
1280 DSI_LANE_CLK,
1281 DSI_LANE_DATA1,
1282 DSI_LANE_DATA2,
1283 DSI_LANE_DATA3,
1284 DSI_LANE_DATA4,
1285 };
1286 u32 r;
1287 int i;
1288
1289 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1);
1290
1291 for (i = 0; i < dsi->num_lanes_used; ++i) {
1292 unsigned int offset = offsets[i];
1293 unsigned int polarity, lane_number;
1294 unsigned int t;
1295
1296 for (t = 0; t < dsi->num_lanes_supported; ++t)
1297 if (dsi->lanes[t].function == functions[i])
1298 break;
1299
1300 if (t == dsi->num_lanes_supported)
1301 return -EINVAL;
1302
1303 lane_number = t;
1304 polarity = dsi->lanes[t].polarity;
1305
1306 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1307 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1308 }
1309
1310 /* clear the unused lanes */
1311 for (; i < dsi->num_lanes_supported; ++i) {
1312 unsigned int offset = offsets[i];
1313
1314 r = FLD_MOD(r, 0, offset + 2, offset);
1315 r = FLD_MOD(r, 0, offset + 3, offset + 3);
1316 }
1317
1318 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r);
1319
1320 return 0;
1321}
1322
1323static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns)
1324{
1325 /* convert time in ns to ddr ticks, rounding up */
1326 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1327
1328 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1329}
1330
1331static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr)
1332{
1333 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1334
1335 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1336}
1337
1338static void dsi_cio_timings(struct dsi_data *dsi)
1339{
1340 u32 r;
1341 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1342 u32 tlpx_half, tclk_trail, tclk_zero;
1343 u32 tclk_prepare;
1344
1345 /* calculate timings */
1346
1347 /* 1 * DDR_CLK = 2 * UI */
1348
1349 /* min 40ns + 4*UI max 85ns + 6*UI */
1350 ths_prepare = ns2ddr(dsi, 70) + 2;
1351
1352 /* min 145ns + 10*UI */
1353 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2;
1354
1355 /* min max(8*UI, 60ns+4*UI) */
1356 ths_trail = ns2ddr(dsi, 60) + 5;
1357
1358 /* min 100ns */
1359 ths_exit = ns2ddr(dsi, 145);
1360
1361 /* tlpx min 50n */
1362 tlpx_half = ns2ddr(dsi, 25);
1363
1364 /* min 60ns */
1365 tclk_trail = ns2ddr(dsi, 60) + 2;
1366
1367 /* min 38ns, max 95ns */
1368 tclk_prepare = ns2ddr(dsi, 65);
1369
1370 /* min tclk-prepare + tclk-zero = 300ns */
1371 tclk_zero = ns2ddr(dsi, 260);
1372
1373 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1374 ths_prepare, ddr2ns(dsi, ths_prepare),
1375 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero));
1376 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1377 ths_trail, ddr2ns(dsi, ths_trail),
1378 ths_exit, ddr2ns(dsi, ths_exit));
1379
1380 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1381 "tclk_zero %u (%uns)\n",
1382 tlpx_half, ddr2ns(dsi, tlpx_half),
1383 tclk_trail, ddr2ns(dsi, tclk_trail),
1384 tclk_zero, ddr2ns(dsi, tclk_zero));
1385 DSSDBG("tclk_prepare %u (%uns)\n",
1386 tclk_prepare, ddr2ns(dsi, tclk_prepare));
1387
1388 /* program timings */
1389
1390 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
1391 r = FLD_MOD(r, ths_prepare, 31, 24);
1392 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1393 r = FLD_MOD(r, ths_trail, 15, 8);
1394 r = FLD_MOD(r, ths_exit, 7, 0);
1395 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r);
1396
1397 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
1398 r = FLD_MOD(r, tlpx_half, 20, 16);
1399 r = FLD_MOD(r, tclk_trail, 15, 8);
1400 r = FLD_MOD(r, tclk_zero, 7, 0);
1401
1402 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) {
1403 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
1404 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
1405 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
1406 }
1407
1408 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r);
1409
1410 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
1411 r = FLD_MOD(r, tclk_prepare, 7, 0);
1412 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r);
1413}
1414
1415static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi)
1416{
1417 int t, i;
1418 bool in_use[DSI_MAX_NR_LANES];
1419 static const u8 offsets_old[] = { 28, 27, 26 };
1420 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
1421 const u8 *offsets;
1422
1423 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC)
1424 offsets = offsets_old;
1425 else
1426 offsets = offsets_new;
1427
1428 for (i = 0; i < dsi->num_lanes_supported; ++i)
1429 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
1430
1431 t = 100000;
1432 while (true) {
1433 u32 l;
1434 int ok;
1435
1436 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1437
1438 ok = 0;
1439 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1440 if (!in_use[i] || (l & (1 << offsets[i])))
1441 ok++;
1442 }
1443
1444 if (ok == dsi->num_lanes_supported)
1445 break;
1446
1447 if (--t == 0) {
1448 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1449 if (!in_use[i] || (l & (1 << offsets[i])))
1450 continue;
1451
1452 DSSERR("CIO TXCLKESC%d domain not coming " \
1453 "out of reset\n", i);
1454 }
1455 return -EIO;
1456 }
1457 }
1458
1459 return 0;
1460}
1461
1462/* return bitmask of enabled lanes, lane0 being the lsb */
1463static unsigned int dsi_get_lane_mask(struct dsi_data *dsi)
1464{
1465 unsigned int mask = 0;
1466 int i;
1467
1468 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1469 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
1470 mask |= 1 << i;
1471 }
1472
1473 return mask;
1474}
1475
1476/* OMAP4 CONTROL_DSIPHY */
1477#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
1478
1479#define OMAP4_DSI2_LANEENABLE_SHIFT 29
1480#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
1481#define OMAP4_DSI1_LANEENABLE_SHIFT 24
1482#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
1483#define OMAP4_DSI1_PIPD_SHIFT 19
1484#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
1485#define OMAP4_DSI2_PIPD_SHIFT 14
1486#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
1487
1488static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1489{
1490 u32 enable_mask, enable_shift;
1491 u32 pipd_mask, pipd_shift;
1492
1493 if (dsi->module_id == 0) {
1494 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
1495 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
1496 pipd_mask = OMAP4_DSI1_PIPD_MASK;
1497 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
1498 } else if (dsi->module_id == 1) {
1499 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
1500 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
1501 pipd_mask = OMAP4_DSI2_PIPD_MASK;
1502 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
1503 } else {
1504 return -ENODEV;
1505 }
1506
1507 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET,
1508 enable_mask | pipd_mask,
1509 (lanes << enable_shift) | (lanes << pipd_shift));
1510}
1511
1512/* OMAP5 CONTROL_DSIPHY */
1513
1514#define OMAP5_DSIPHY_SYSCON_OFFSET 0x74
1515
1516#define OMAP5_DSI1_LANEENABLE_SHIFT 24
1517#define OMAP5_DSI2_LANEENABLE_SHIFT 19
1518#define OMAP5_DSI_LANEENABLE_MASK 0x1f
1519
1520static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1521{
1522 u32 enable_shift;
1523
1524 if (dsi->module_id == 0)
1525 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT;
1526 else if (dsi->module_id == 1)
1527 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT;
1528 else
1529 return -ENODEV;
1530
1531 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET,
1532 OMAP5_DSI_LANEENABLE_MASK << enable_shift,
1533 lanes << enable_shift);
1534}
1535
1536static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask)
1537{
1538 if (dsi->data->model == DSI_MODEL_OMAP4)
1539 return dsi_omap4_mux_pads(dsi, lane_mask);
1540 if (dsi->data->model == DSI_MODEL_OMAP5)
1541 return dsi_omap5_mux_pads(dsi, lane_mask);
1542 return 0;
1543}
1544
1545static void dsi_disable_pads(struct dsi_data *dsi)
1546{
1547 if (dsi->data->model == DSI_MODEL_OMAP4)
1548 dsi_omap4_mux_pads(dsi, 0);
1549 else if (dsi->data->model == DSI_MODEL_OMAP5)
1550 dsi_omap5_mux_pads(dsi, 0);
1551}
1552
1553static int dsi_cio_init(struct dsi_data *dsi)
1554{
1555 int r;
1556 u32 l;
1557
1558 DSSDBG("DSI CIO init starts");
1559
1560 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi));
1561 if (r)
1562 return r;
1563
1564 dsi_enable_scp_clk(dsi);
1565
1566 /* A dummy read using the SCP interface to any DSIPHY register is
1567 * required after DSIPHY reset to complete the reset of the DSI complex
1568 * I/O. */
1569 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1570
1571 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) {
1572 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
1573 r = -EIO;
1574 goto err_scp_clk_dom;
1575 }
1576
1577 r = dsi_set_lane_config(dsi);
1578 if (r)
1579 goto err_scp_clk_dom;
1580
1581 /* set TX STOP MODE timer to maximum for this operation */
1582 l = dsi_read_reg(dsi, DSI_TIMING1);
1583 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1584 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
1585 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
1586 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
1587 dsi_write_reg(dsi, DSI_TIMING1, l);
1588
1589 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON);
1590 if (r)
1591 goto err_cio_pwr;
1592
1593 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) {
1594 DSSERR("CIO PWR clock domain not coming out of reset.\n");
1595 r = -ENODEV;
1596 goto err_cio_pwr_dom;
1597 }
1598
1599 dsi_if_enable(dsi, true);
1600 dsi_if_enable(dsi, false);
1601 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1602
1603 r = dsi_cio_wait_tx_clk_esc_reset(dsi);
1604 if (r)
1605 goto err_tx_clk_esc_rst;
1606
1607 /* FORCE_TX_STOP_MODE_IO */
1608 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15);
1609
1610 dsi_cio_timings(dsi);
1611
1612 /* DDR_CLK_ALWAYS_ON */
1613 REG_FLD_MOD(dsi, DSI_CLK_CTRL,
1614 !(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS),
1615 13, 13);
1616
1617 DSSDBG("CIO init done\n");
1618
1619 return 0;
1620
1621err_tx_clk_esc_rst:
1622 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
1623err_cio_pwr_dom:
1624 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
1625err_cio_pwr:
1626err_scp_clk_dom:
1627 dsi_disable_scp_clk(dsi);
1628 dsi_disable_pads(dsi);
1629 return r;
1630}
1631
1632static void dsi_cio_uninit(struct dsi_data *dsi)
1633{
1634 /* DDR_CLK_ALWAYS_ON */
1635 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
1636
1637 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
1638 dsi_disable_scp_clk(dsi);
1639 dsi_disable_pads(dsi);
1640}
1641
1642static void dsi_config_tx_fifo(struct dsi_data *dsi,
1643 enum fifo_size size1, enum fifo_size size2,
1644 enum fifo_size size3, enum fifo_size size4)
1645{
1646 u32 r = 0;
1647 int add = 0;
1648 int i;
1649
1650 dsi->vc[0].tx_fifo_size = size1;
1651 dsi->vc[1].tx_fifo_size = size2;
1652 dsi->vc[2].tx_fifo_size = size3;
1653 dsi->vc[3].tx_fifo_size = size4;
1654
1655 for (i = 0; i < 4; i++) {
1656 u8 v;
1657 int size = dsi->vc[i].tx_fifo_size;
1658
1659 if (add + size > 4) {
1660 DSSERR("Illegal FIFO configuration\n");
1661 BUG();
1662 return;
1663 }
1664
1665 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1666 r |= v << (8 * i);
1667 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1668 add += size;
1669 }
1670
1671 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r);
1672}
1673
1674static void dsi_config_rx_fifo(struct dsi_data *dsi,
1675 enum fifo_size size1, enum fifo_size size2,
1676 enum fifo_size size3, enum fifo_size size4)
1677{
1678 u32 r = 0;
1679 int add = 0;
1680 int i;
1681
1682 dsi->vc[0].rx_fifo_size = size1;
1683 dsi->vc[1].rx_fifo_size = size2;
1684 dsi->vc[2].rx_fifo_size = size3;
1685 dsi->vc[3].rx_fifo_size = size4;
1686
1687 for (i = 0; i < 4; i++) {
1688 u8 v;
1689 int size = dsi->vc[i].rx_fifo_size;
1690
1691 if (add + size > 4) {
1692 DSSERR("Illegal FIFO configuration\n");
1693 BUG();
1694 return;
1695 }
1696
1697 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1698 r |= v << (8 * i);
1699 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1700 add += size;
1701 }
1702
1703 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r);
1704}
1705
1706static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi)
1707{
1708 u32 r;
1709
1710 r = dsi_read_reg(dsi, DSI_TIMING1);
1711 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1712 dsi_write_reg(dsi, DSI_TIMING1, r);
1713
1714 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) {
1715 DSSERR("TX_STOP bit not going down\n");
1716 return -EIO;
1717 }
1718
1719 return 0;
1720}
1721
1722static bool dsi_vc_is_enabled(struct dsi_data *dsi, int vc)
1723{
1724 return REG_GET(dsi, DSI_VC_CTRL(vc), 0, 0);
1725}
1726
1727static void dsi_packet_sent_handler_vp(void *data, u32 mask)
1728{
1729 struct dsi_packet_sent_handler_data *vp_data =
1730 (struct dsi_packet_sent_handler_data *) data;
1731 struct dsi_data *dsi = vp_data->dsi;
1732 const int vc = dsi->update_vc;
1733 u8 bit = dsi->te_enabled ? 30 : 31;
1734
1735 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit) == 0)
1736 complete(vp_data->completion);
1737}
1738
1739static int dsi_sync_vc_vp(struct dsi_data *dsi, int vc)
1740{
1741 DECLARE_COMPLETION_ONSTACK(completion);
1742 struct dsi_packet_sent_handler_data vp_data = {
1743 .dsi = dsi,
1744 .completion = &completion
1745 };
1746 int r = 0;
1747 u8 bit;
1748
1749 bit = dsi->te_enabled ? 30 : 31;
1750
1751 r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_vp,
1752 &vp_data, DSI_VC_IRQ_PACKET_SENT);
1753 if (r)
1754 goto err0;
1755
1756 /* Wait for completion only if TE_EN/TE_START is still set */
1757 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit)) {
1758 if (wait_for_completion_timeout(&completion,
1759 msecs_to_jiffies(10)) == 0) {
1760 DSSERR("Failed to complete previous frame transfer\n");
1761 r = -EIO;
1762 goto err1;
1763 }
1764 }
1765
1766 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp,
1767 &vp_data, DSI_VC_IRQ_PACKET_SENT);
1768
1769 return 0;
1770err1:
1771 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp,
1772 &vp_data, DSI_VC_IRQ_PACKET_SENT);
1773err0:
1774 return r;
1775}
1776
1777static void dsi_packet_sent_handler_l4(void *data, u32 mask)
1778{
1779 struct dsi_packet_sent_handler_data *l4_data =
1780 (struct dsi_packet_sent_handler_data *) data;
1781 struct dsi_data *dsi = l4_data->dsi;
1782 const int vc = dsi->update_vc;
1783
1784 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5) == 0)
1785 complete(l4_data->completion);
1786}
1787
1788static int dsi_sync_vc_l4(struct dsi_data *dsi, int vc)
1789{
1790 DECLARE_COMPLETION_ONSTACK(completion);
1791 struct dsi_packet_sent_handler_data l4_data = {
1792 .dsi = dsi,
1793 .completion = &completion
1794 };
1795 int r = 0;
1796
1797 r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_l4,
1798 &l4_data, DSI_VC_IRQ_PACKET_SENT);
1799 if (r)
1800 goto err0;
1801
1802 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
1803 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5)) {
1804 if (wait_for_completion_timeout(&completion,
1805 msecs_to_jiffies(10)) == 0) {
1806 DSSERR("Failed to complete previous l4 transfer\n");
1807 r = -EIO;
1808 goto err1;
1809 }
1810 }
1811
1812 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4,
1813 &l4_data, DSI_VC_IRQ_PACKET_SENT);
1814
1815 return 0;
1816err1:
1817 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4,
1818 &l4_data, DSI_VC_IRQ_PACKET_SENT);
1819err0:
1820 return r;
1821}
1822
1823static int dsi_sync_vc(struct dsi_data *dsi, int vc)
1824{
1825 WARN_ON(!dsi_bus_is_locked(dsi));
1826
1827 WARN_ON(in_interrupt());
1828
1829 if (!dsi_vc_is_enabled(dsi, vc))
1830 return 0;
1831
1832 switch (dsi->vc[vc].source) {
1833 case DSI_VC_SOURCE_VP:
1834 return dsi_sync_vc_vp(dsi, vc);
1835 case DSI_VC_SOURCE_L4:
1836 return dsi_sync_vc_l4(dsi, vc);
1837 default:
1838 BUG();
1839 return -EINVAL;
1840 }
1841}
1842
1843static int dsi_vc_enable(struct dsi_data *dsi, int vc, bool enable)
1844{
1845 DSSDBG("dsi_vc_enable vc %d, enable %d\n",
1846 vc, enable);
1847
1848 enable = enable ? 1 : 0;
1849
1850 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 0, 0);
1851
1852 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(vc), 0, enable)) {
1853 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1854 return -EIO;
1855 }
1856
1857 return 0;
1858}
1859
1860static void dsi_vc_initial_config(struct dsi_data *dsi, int vc)
1861{
1862 u32 r;
1863
1864 DSSDBG("Initial config of VC %d", vc);
1865
1866 r = dsi_read_reg(dsi, DSI_VC_CTRL(vc));
1867
1868 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1869 DSSERR("VC(%d) busy when trying to configure it!\n",
1870 vc);
1871
1872 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1873 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1874 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1875 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1876 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1877 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1878 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1879 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH)
1880 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
1881
1882 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1883 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1884
1885 dsi_write_reg(dsi, DSI_VC_CTRL(vc), r);
1886
1887 dsi->vc[vc].source = DSI_VC_SOURCE_L4;
1888}
1889
1890static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int vc,
1891 bool enable)
1892{
1893 struct dsi_data *dsi = to_dsi_data(dssdev);
1894
1895 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", vc, enable);
1896
1897 if (REG_GET(dsi, DSI_VC_CTRL(vc), 9, 9) == enable)
1898 return;
1899
1900 WARN_ON(!dsi_bus_is_locked(dsi));
1901
1902 dsi_vc_enable(dsi, vc, 0);
1903 dsi_if_enable(dsi, 0);
1904
1905 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 9, 9);
1906
1907 dsi_vc_enable(dsi, vc, 1);
1908 dsi_if_enable(dsi, 1);
1909
1910 dsi_force_tx_stop_mode_io(dsi);
1911}
1912
1913static void dsi_vc_flush_long_data(struct dsi_data *dsi, int vc)
1914{
1915 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
1916 u32 val;
1917 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc));
1918 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1919 (val >> 0) & 0xff,
1920 (val >> 8) & 0xff,
1921 (val >> 16) & 0xff,
1922 (val >> 24) & 0xff);
1923 }
1924}
1925
1926static void dsi_show_rx_ack_with_err(u16 err)
1927{
1928 DSSERR("\tACK with ERROR (%#x):\n", err);
1929 if (err & (1 << 0))
1930 DSSERR("\t\tSoT Error\n");
1931 if (err & (1 << 1))
1932 DSSERR("\t\tSoT Sync Error\n");
1933 if (err & (1 << 2))
1934 DSSERR("\t\tEoT Sync Error\n");
1935 if (err & (1 << 3))
1936 DSSERR("\t\tEscape Mode Entry Command Error\n");
1937 if (err & (1 << 4))
1938 DSSERR("\t\tLP Transmit Sync Error\n");
1939 if (err & (1 << 5))
1940 DSSERR("\t\tHS Receive Timeout Error\n");
1941 if (err & (1 << 6))
1942 DSSERR("\t\tFalse Control Error\n");
1943 if (err & (1 << 7))
1944 DSSERR("\t\t(reserved7)\n");
1945 if (err & (1 << 8))
1946 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1947 if (err & (1 << 9))
1948 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1949 if (err & (1 << 10))
1950 DSSERR("\t\tChecksum Error\n");
1951 if (err & (1 << 11))
1952 DSSERR("\t\tData type not recognized\n");
1953 if (err & (1 << 12))
1954 DSSERR("\t\tInvalid VC ID\n");
1955 if (err & (1 << 13))
1956 DSSERR("\t\tInvalid Transmission Length\n");
1957 if (err & (1 << 14))
1958 DSSERR("\t\t(reserved14)\n");
1959 if (err & (1 << 15))
1960 DSSERR("\t\tDSI Protocol Violation\n");
1961}
1962
1963static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int vc)
1964{
1965 /* RX_FIFO_NOT_EMPTY */
1966 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
1967 u32 val;
1968 u8 dt;
1969 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc));
1970 DSSERR("\trawval %#08x\n", val);
1971 dt = FLD_GET(val, 5, 0);
1972 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
1973 u16 err = FLD_GET(val, 23, 8);
1974 dsi_show_rx_ack_with_err(err);
1975 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
1976 DSSERR("\tDCS short response, 1 byte: %#x\n",
1977 FLD_GET(val, 23, 8));
1978 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
1979 DSSERR("\tDCS short response, 2 byte: %#x\n",
1980 FLD_GET(val, 23, 8));
1981 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
1982 DSSERR("\tDCS long response, len %d\n",
1983 FLD_GET(val, 23, 8));
1984 dsi_vc_flush_long_data(dsi, vc);
1985 } else {
1986 DSSERR("\tunknown datatype 0x%02x\n", dt);
1987 }
1988 }
1989 return 0;
1990}
1991
1992static int dsi_vc_send_bta(struct dsi_data *dsi, int vc)
1993{
1994 if (dsi->debug_write || dsi->debug_read)
1995 DSSDBG("dsi_vc_send_bta %d\n", vc);
1996
1997 WARN_ON(!dsi_bus_is_locked(dsi));
1998
1999 /* RX_FIFO_NOT_EMPTY */
2000 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
2001 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2002 dsi_vc_flush_receive_data(dsi, vc);
2003 }
2004
2005 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 6, 6); /* BTA_EN */
2006
2007 /* flush posted write */
2008 dsi_read_reg(dsi, DSI_VC_CTRL(vc));
2009
2010 return 0;
2011}
2012
2013static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int vc)
2014{
2015 struct dsi_data *dsi = to_dsi_data(dssdev);
2016 DECLARE_COMPLETION_ONSTACK(completion);
2017 int r = 0;
2018 u32 err;
2019
2020 r = dsi_register_isr_vc(dsi, vc, dsi_completion_handler,
2021 &completion, DSI_VC_IRQ_BTA);
2022 if (r)
2023 goto err0;
2024
2025 r = dsi_register_isr(dsi, dsi_completion_handler, &completion,
2026 DSI_IRQ_ERROR_MASK);
2027 if (r)
2028 goto err1;
2029
2030 r = dsi_vc_send_bta(dsi, vc);
2031 if (r)
2032 goto err2;
2033
2034 if (wait_for_completion_timeout(&completion,
2035 msecs_to_jiffies(500)) == 0) {
2036 DSSERR("Failed to receive BTA\n");
2037 r = -EIO;
2038 goto err2;
2039 }
2040
2041 err = dsi_get_errors(dsi);
2042 if (err) {
2043 DSSERR("Error while sending BTA: %x\n", err);
2044 r = -EIO;
2045 goto err2;
2046 }
2047err2:
2048 dsi_unregister_isr(dsi, dsi_completion_handler, &completion,
2049 DSI_IRQ_ERROR_MASK);
2050err1:
2051 dsi_unregister_isr_vc(dsi, vc, dsi_completion_handler,
2052 &completion, DSI_VC_IRQ_BTA);
2053err0:
2054 return r;
2055}
2056
2057static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int vc,
2058 int channel, u8 data_type, u16 len,
2059 u8 ecc)
2060{
2061 u32 val;
2062 u8 data_id;
2063
2064 WARN_ON(!dsi_bus_is_locked(dsi));
2065
2066 data_id = data_type | channel << 6;
2067
2068 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2069 FLD_VAL(ecc, 31, 24);
2070
2071 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(vc), val);
2072}
2073
2074static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int vc,
2075 u8 b1, u8 b2, u8 b3, u8 b4)
2076{
2077 u32 val;
2078
2079 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2080
2081/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2082 b1, b2, b3, b4, val); */
2083
2084 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(vc), val);
2085}
2086
2087static int dsi_vc_send_long(struct dsi_data *dsi, int vc,
2088 const struct mipi_dsi_msg *msg)
2089{
2090 /*u32 val; */
2091 int i;
2092 const u8 *p;
2093 int r = 0;
2094 u8 b1, b2, b3, b4;
2095
2096 if (dsi->debug_write)
2097 DSSDBG("dsi_vc_send_long, %d bytes\n", msg->tx_len);
2098
2099 /* len + header */
2100 if (dsi->vc[vc].tx_fifo_size * 32 * 4 < msg->tx_len + 4) {
2101 DSSERR("unable to send long packet: packet too long.\n");
2102 return -EINVAL;
2103 }
2104
2105 dsi_vc_write_long_header(dsi, vc, msg->channel, msg->type, msg->tx_len, 0);
2106
2107 p = msg->tx_buf;
2108 for (i = 0; i < msg->tx_len >> 2; i++) {
2109 if (dsi->debug_write)
2110 DSSDBG("\tsending full packet %d\n", i);
2111
2112 b1 = *p++;
2113 b2 = *p++;
2114 b3 = *p++;
2115 b4 = *p++;
2116
2117 dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, b4);
2118 }
2119
2120 i = msg->tx_len % 4;
2121 if (i) {
2122 b1 = 0; b2 = 0; b3 = 0;
2123
2124 if (dsi->debug_write)
2125 DSSDBG("\tsending remainder bytes %d\n", i);
2126
2127 switch (i) {
2128 case 3:
2129 b1 = *p++;
2130 b2 = *p++;
2131 b3 = *p++;
2132 break;
2133 case 2:
2134 b1 = *p++;
2135 b2 = *p++;
2136 break;
2137 case 1:
2138 b1 = *p++;
2139 break;
2140 }
2141
2142 dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, 0);
2143 }
2144
2145 return r;
2146}
2147
2148static int dsi_vc_send_short(struct dsi_data *dsi, int vc,
2149 const struct mipi_dsi_msg *msg)
2150{
2151 struct mipi_dsi_packet pkt;
2152 int ret;
2153 u32 r;
2154
2155 ret = mipi_dsi_create_packet(&pkt, msg);
2156 if (ret < 0)
2157 return ret;
2158
2159 WARN_ON(!dsi_bus_is_locked(dsi));
2160
2161 if (dsi->debug_write)
2162 DSSDBG("dsi_vc_send_short(vc%d, dt %#x, b1 %#x, b2 %#x)\n",
2163 vc, msg->type, pkt.header[1], pkt.header[2]);
2164
2165 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(vc)), 16, 16)) {
2166 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2167 return -EINVAL;
2168 }
2169
2170 r = pkt.header[3] << 24 | pkt.header[2] << 16 | pkt.header[1] << 8 |
2171 pkt.header[0];
2172
2173 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc), r);
2174
2175 return 0;
2176}
2177
2178static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel)
2179{
2180 const struct mipi_dsi_msg msg = {
2181 .channel = channel,
2182 .type = MIPI_DSI_NULL_PACKET,
2183 };
2184
2185 return dsi_vc_send_long(dsi, vc, &msg);
2186}
2187
2188static int dsi_vc_write_common(struct omap_dss_device *dssdev, int vc,
2189 const struct mipi_dsi_msg *msg)
2190{
2191 struct dsi_data *dsi = to_dsi_data(dssdev);
2192 int r;
2193
2194 if (mipi_dsi_packet_format_is_short(msg->type))
2195 r = dsi_vc_send_short(dsi, vc, msg);
2196 else
2197 r = dsi_vc_send_long(dsi, vc, msg);
2198
2199 if (r < 0)
2200 return r;
2201
2202 /*
2203 * TODO: we do not always have to do the BTA sync, for example
2204 * we can improve performance by setting the update window
2205 * information without sending BTA sync between the commands.
2206 * In that case we can return early.
2207 */
2208
2209 r = dsi_vc_send_bta_sync(dssdev, vc);
2210 if (r) {
2211 DSSERR("bta sync failed\n");
2212 return r;
2213 }
2214
2215 /* RX_FIFO_NOT_EMPTY */
2216 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
2217 DSSERR("rx fifo not empty after write, dumping data:\n");
2218 dsi_vc_flush_receive_data(dsi, vc);
2219 return -EIO;
2220 }
2221
2222 return 0;
2223}
2224
2225static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int vc, u8 *buf,
2226 int buflen, enum dss_dsi_content_type type)
2227{
2228 u32 val;
2229 u8 dt;
2230 int r;
2231
2232 /* RX_FIFO_NOT_EMPTY */
2233 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20) == 0) {
2234 DSSERR("RX fifo empty when trying to read.\n");
2235 r = -EIO;
2236 goto err;
2237 }
2238
2239 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc));
2240 if (dsi->debug_read)
2241 DSSDBG("\theader: %08x\n", val);
2242 dt = FLD_GET(val, 5, 0);
2243 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2244 u16 err = FLD_GET(val, 23, 8);
2245 dsi_show_rx_ack_with_err(err);
2246 r = -EIO;
2247 goto err;
2248
2249 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2250 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2251 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2252 u8 data = FLD_GET(val, 15, 8);
2253 if (dsi->debug_read)
2254 DSSDBG("\t%s short response, 1 byte: %02x\n",
2255 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2256 "DCS", data);
2257
2258 if (buflen < 1) {
2259 r = -EIO;
2260 goto err;
2261 }
2262
2263 buf[0] = data;
2264
2265 return 1;
2266 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2267 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2268 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2269 u16 data = FLD_GET(val, 23, 8);
2270 if (dsi->debug_read)
2271 DSSDBG("\t%s short response, 2 byte: %04x\n",
2272 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2273 "DCS", data);
2274
2275 if (buflen < 2) {
2276 r = -EIO;
2277 goto err;
2278 }
2279
2280 buf[0] = data & 0xff;
2281 buf[1] = (data >> 8) & 0xff;
2282
2283 return 2;
2284 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2285 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
2286 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
2287 int w;
2288 int len = FLD_GET(val, 23, 8);
2289 if (dsi->debug_read)
2290 DSSDBG("\t%s long response, len %d\n",
2291 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2292 "DCS", len);
2293
2294 if (len > buflen) {
2295 r = -EIO;
2296 goto err;
2297 }
2298
2299 /* two byte checksum ends the packet, not included in len */
2300 for (w = 0; w < len + 2;) {
2301 int b;
2302 val = dsi_read_reg(dsi,
2303 DSI_VC_SHORT_PACKET_HEADER(vc));
2304 if (dsi->debug_read)
2305 DSSDBG("\t\t%02x %02x %02x %02x\n",
2306 (val >> 0) & 0xff,
2307 (val >> 8) & 0xff,
2308 (val >> 16) & 0xff,
2309 (val >> 24) & 0xff);
2310
2311 for (b = 0; b < 4; ++b) {
2312 if (w < len)
2313 buf[w] = (val >> (b * 8)) & 0xff;
2314 /* we discard the 2 byte checksum */
2315 ++w;
2316 }
2317 }
2318
2319 return len;
2320 } else {
2321 DSSERR("\tunknown datatype 0x%02x\n", dt);
2322 r = -EIO;
2323 goto err;
2324 }
2325
2326err:
2327 DSSERR("dsi_vc_read_rx_fifo(vc %d type %s) failed\n", vc,
2328 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
2329
2330 return r;
2331}
2332
2333static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int vc,
2334 const struct mipi_dsi_msg *msg)
2335{
2336 struct dsi_data *dsi = to_dsi_data(dssdev);
2337 u8 cmd = ((u8 *)msg->tx_buf)[0];
2338 int r;
2339
2340 if (dsi->debug_read)
2341 DSSDBG("%s(vc %d, cmd %x)\n", __func__, vc, cmd);
2342
2343 r = dsi_vc_send_short(dsi, vc, msg);
2344 if (r)
2345 goto err;
2346
2347 r = dsi_vc_send_bta_sync(dssdev, vc);
2348 if (r)
2349 goto err;
2350
2351 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len,
2352 DSS_DSI_CONTENT_DCS);
2353 if (r < 0)
2354 goto err;
2355
2356 if (r != msg->rx_len) {
2357 r = -EIO;
2358 goto err;
2359 }
2360
2361 return 0;
2362err:
2363 DSSERR("%s(vc %d, cmd 0x%02x) failed\n", __func__, vc, cmd);
2364 return r;
2365}
2366
2367static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int vc,
2368 const struct mipi_dsi_msg *msg)
2369{
2370 struct dsi_data *dsi = to_dsi_data(dssdev);
2371 int r;
2372
2373 r = dsi_vc_send_short(dsi, vc, msg);
2374 if (r)
2375 goto err;
2376
2377 r = dsi_vc_send_bta_sync(dssdev, vc);
2378 if (r)
2379 goto err;
2380
2381 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len,
2382 DSS_DSI_CONTENT_GENERIC);
2383 if (r < 0)
2384 goto err;
2385
2386 if (r != msg->rx_len) {
2387 r = -EIO;
2388 goto err;
2389 }
2390
2391 return 0;
2392err:
2393 DSSERR("%s(vc %d, reqlen %d) failed\n", __func__, vc, msg->tx_len);
2394 return r;
2395}
2396
2397static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks,
2398 bool x4, bool x16)
2399{
2400 unsigned long fck;
2401 unsigned long total_ticks;
2402 u32 r;
2403
2404 BUG_ON(ticks > 0x1fff);
2405
2406 /* ticks in DSI_FCK */
2407 fck = dsi_fclk_rate(dsi);
2408
2409 r = dsi_read_reg(dsi, DSI_TIMING2);
2410 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2411 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2412 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
2413 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2414 dsi_write_reg(dsi, DSI_TIMING2, r);
2415
2416 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2417
2418 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2419 total_ticks,
2420 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2421 (total_ticks * 1000) / (fck / 1000 / 1000));
2422}
2423
2424static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks,
2425 bool x8, bool x16)
2426{
2427 unsigned long fck;
2428 unsigned long total_ticks;
2429 u32 r;
2430
2431 BUG_ON(ticks > 0x1fff);
2432
2433 /* ticks in DSI_FCK */
2434 fck = dsi_fclk_rate(dsi);
2435
2436 r = dsi_read_reg(dsi, DSI_TIMING1);
2437 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2438 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
2439 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
2440 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2441 dsi_write_reg(dsi, DSI_TIMING1, r);
2442
2443 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
2444
2445 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2446 total_ticks,
2447 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
2448 (total_ticks * 1000) / (fck / 1000 / 1000));
2449}
2450
2451static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks,
2452 bool x4, bool x16)
2453{
2454 unsigned long fck;
2455 unsigned long total_ticks;
2456 u32 r;
2457
2458 BUG_ON(ticks > 0x1fff);
2459
2460 /* ticks in DSI_FCK */
2461 fck = dsi_fclk_rate(dsi);
2462
2463 r = dsi_read_reg(dsi, DSI_TIMING1);
2464 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2465 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2466 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
2467 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2468 dsi_write_reg(dsi, DSI_TIMING1, r);
2469
2470 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2471
2472 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2473 total_ticks,
2474 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2475 (total_ticks * 1000) / (fck / 1000 / 1000));
2476}
2477
2478static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks,
2479 bool x4, bool x16)
2480{
2481 unsigned long fck;
2482 unsigned long total_ticks;
2483 u32 r;
2484
2485 BUG_ON(ticks > 0x1fff);
2486
2487 /* ticks in TxByteClkHS */
2488 fck = dsi_get_txbyteclkhs(dsi);
2489
2490 r = dsi_read_reg(dsi, DSI_TIMING2);
2491 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2492 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2493 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
2494 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2495 dsi_write_reg(dsi, DSI_TIMING2, r);
2496
2497 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2498
2499 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2500 total_ticks,
2501 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2502 (total_ticks * 1000) / (fck / 1000 / 1000));
2503}
2504
2505static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi)
2506{
2507 int num_line_buffers;
2508
2509 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2510 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
2511 const struct videomode *vm = &dsi->vm;
2512 /*
2513 * Don't use line buffers if width is greater than the video
2514 * port's line buffer size
2515 */
2516 if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
2517 num_line_buffers = 0;
2518 else
2519 num_line_buffers = 2;
2520 } else {
2521 /* Use maximum number of line buffers in command mode */
2522 num_line_buffers = 2;
2523 }
2524
2525 /* LINE_BUFFER */
2526 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12);
2527}
2528
2529static void dsi_config_vp_sync_events(struct dsi_data *dsi)
2530{
2531 bool sync_end;
2532 u32 r;
2533
2534 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
2535 sync_end = true;
2536 else
2537 sync_end = false;
2538
2539 r = dsi_read_reg(dsi, DSI_CTRL);
2540 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
2541 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
2542 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
2543 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
2544 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
2545 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
2546 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
2547 dsi_write_reg(dsi, DSI_CTRL, r);
2548}
2549
2550static void dsi_config_blanking_modes(struct dsi_data *dsi)
2551{
2552 int blanking_mode = dsi->vm_timings.blanking_mode;
2553 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
2554 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
2555 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
2556 u32 r;
2557
2558 /*
2559 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
2560 * 1 = Long blanking packets are sent in corresponding blanking periods
2561 */
2562 r = dsi_read_reg(dsi, DSI_CTRL);
2563 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
2564 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
2565 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
2566 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
2567 dsi_write_reg(dsi, DSI_CTRL, r);
2568}
2569
2570/*
2571 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
2572 * results in maximum transition time for data and clock lanes to enter and
2573 * exit HS mode. Hence, this is the scenario where the least amount of command
2574 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
2575 * clock cycles that can be used to interleave command mode data in HS so that
2576 * all scenarios are satisfied.
2577 */
2578static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
2579 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
2580{
2581 int transition;
2582
2583 /*
2584 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
2585 * time of data lanes only, if it isn't set, we need to consider HS
2586 * transition time of both data and clock lanes. HS transition time
2587 * of Scenario 3 is considered.
2588 */
2589 if (ddr_alwon) {
2590 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
2591 } else {
2592 int trans1, trans2;
2593 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
2594 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
2595 enter_hs + 1;
2596 transition = max(trans1, trans2);
2597 }
2598
2599 return blank > transition ? blank - transition : 0;
2600}
2601
2602/*
2603 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
2604 * results in maximum transition time for data lanes to enter and exit LP mode.
2605 * Hence, this is the scenario where the least amount of command mode data can
2606 * be interleaved. We program the minimum amount of bytes that can be
2607 * interleaved in LP so that all scenarios are satisfied.
2608 */
2609static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
2610 int lp_clk_div, int tdsi_fclk)
2611{
2612 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
2613 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
2614 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
2615 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
2616 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
2617
2618 /* maximum LP transition time according to Scenario 1 */
2619 trans_lp = exit_hs + max(enter_hs, 2) + 1;
2620
2621 /* CLKIN4DDR = 16 * TXBYTECLKHS */
2622 tlp_avail = thsbyte_clk * (blank - trans_lp);
2623
2624 ttxclkesc = tdsi_fclk * lp_clk_div;
2625
2626 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
2627 26) / 16;
2628
2629 return max(lp_inter, 0);
2630}
2631
2632static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi)
2633{
2634 int blanking_mode;
2635 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
2636 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
2637 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
2638 int tclk_trail, ths_exit, exiths_clk;
2639 bool ddr_alwon;
2640 const struct videomode *vm = &dsi->vm;
2641 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
2642 int ndl = dsi->num_lanes_used - 1;
2643 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
2644 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
2645 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
2646 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
2647 int bl_interleave_hs = 0, bl_interleave_lp = 0;
2648 u32 r;
2649
2650 r = dsi_read_reg(dsi, DSI_CTRL);
2651 blanking_mode = FLD_GET(r, 20, 20);
2652 hfp_blanking_mode = FLD_GET(r, 21, 21);
2653 hbp_blanking_mode = FLD_GET(r, 22, 22);
2654 hsa_blanking_mode = FLD_GET(r, 23, 23);
2655
2656 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
2657 hbp = FLD_GET(r, 11, 0);
2658 hfp = FLD_GET(r, 23, 12);
2659 hsa = FLD_GET(r, 31, 24);
2660
2661 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
2662 ddr_clk_post = FLD_GET(r, 7, 0);
2663 ddr_clk_pre = FLD_GET(r, 15, 8);
2664
2665 r = dsi_read_reg(dsi, DSI_VM_TIMING7);
2666 exit_hs_mode_lat = FLD_GET(r, 15, 0);
2667 enter_hs_mode_lat = FLD_GET(r, 31, 16);
2668
2669 r = dsi_read_reg(dsi, DSI_CLK_CTRL);
2670 lp_clk_div = FLD_GET(r, 12, 0);
2671 ddr_alwon = FLD_GET(r, 13, 13);
2672
2673 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
2674 ths_exit = FLD_GET(r, 7, 0);
2675
2676 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
2677 tclk_trail = FLD_GET(r, 15, 8);
2678
2679 exiths_clk = ths_exit + tclk_trail;
2680
2681 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
2682 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
2683
2684 if (!hsa_blanking_mode) {
2685 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
2686 enter_hs_mode_lat, exit_hs_mode_lat,
2687 exiths_clk, ddr_clk_pre, ddr_clk_post);
2688 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
2689 enter_hs_mode_lat, exit_hs_mode_lat,
2690 lp_clk_div, dsi_fclk_hsdiv);
2691 }
2692
2693 if (!hfp_blanking_mode) {
2694 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
2695 enter_hs_mode_lat, exit_hs_mode_lat,
2696 exiths_clk, ddr_clk_pre, ddr_clk_post);
2697 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
2698 enter_hs_mode_lat, exit_hs_mode_lat,
2699 lp_clk_div, dsi_fclk_hsdiv);
2700 }
2701
2702 if (!hbp_blanking_mode) {
2703 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
2704 enter_hs_mode_lat, exit_hs_mode_lat,
2705 exiths_clk, ddr_clk_pre, ddr_clk_post);
2706
2707 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
2708 enter_hs_mode_lat, exit_hs_mode_lat,
2709 lp_clk_div, dsi_fclk_hsdiv);
2710 }
2711
2712 if (!blanking_mode) {
2713 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
2714 enter_hs_mode_lat, exit_hs_mode_lat,
2715 exiths_clk, ddr_clk_pre, ddr_clk_post);
2716
2717 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
2718 enter_hs_mode_lat, exit_hs_mode_lat,
2719 lp_clk_div, dsi_fclk_hsdiv);
2720 }
2721
2722 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
2723 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
2724 bl_interleave_hs);
2725
2726 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
2727 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
2728 bl_interleave_lp);
2729
2730 r = dsi_read_reg(dsi, DSI_VM_TIMING4);
2731 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
2732 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
2733 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
2734 dsi_write_reg(dsi, DSI_VM_TIMING4, r);
2735
2736 r = dsi_read_reg(dsi, DSI_VM_TIMING5);
2737 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
2738 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
2739 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
2740 dsi_write_reg(dsi, DSI_VM_TIMING5, r);
2741
2742 r = dsi_read_reg(dsi, DSI_VM_TIMING6);
2743 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
2744 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
2745 dsi_write_reg(dsi, DSI_VM_TIMING6, r);
2746}
2747
2748static int dsi_proto_config(struct dsi_data *dsi)
2749{
2750 u32 r;
2751 int buswidth = 0;
2752
2753 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32,
2754 DSI_FIFO_SIZE_32,
2755 DSI_FIFO_SIZE_32,
2756 DSI_FIFO_SIZE_32);
2757
2758 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32,
2759 DSI_FIFO_SIZE_32,
2760 DSI_FIFO_SIZE_32,
2761 DSI_FIFO_SIZE_32);
2762
2763 /* XXX what values for the timeouts? */
2764 dsi_set_stop_state_counter(dsi, 0x1000, false, false);
2765 dsi_set_ta_timeout(dsi, 0x1fff, true, true);
2766 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true);
2767 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true);
2768
2769 switch (mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt)) {
2770 case 16:
2771 buswidth = 0;
2772 break;
2773 case 18:
2774 buswidth = 1;
2775 break;
2776 case 24:
2777 buswidth = 2;
2778 break;
2779 default:
2780 BUG();
2781 return -EINVAL;
2782 }
2783
2784 r = dsi_read_reg(dsi, DSI_CTRL);
2785 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2786 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2787 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2788 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2789 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2790 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2791 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2792 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2793 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) {
2794 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2795 /* DCS_CMD_CODE, 1=start, 0=continue */
2796 r = FLD_MOD(r, 0, 25, 25);
2797 }
2798
2799 dsi_write_reg(dsi, DSI_CTRL, r);
2800
2801 dsi_config_vp_num_line_buffers(dsi);
2802
2803 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2804 dsi_config_vp_sync_events(dsi);
2805 dsi_config_blanking_modes(dsi);
2806 dsi_config_cmd_mode_interleaving(dsi);
2807 }
2808
2809 dsi_vc_initial_config(dsi, 0);
2810 dsi_vc_initial_config(dsi, 1);
2811 dsi_vc_initial_config(dsi, 2);
2812 dsi_vc_initial_config(dsi, 3);
2813
2814 return 0;
2815}
2816
2817static void dsi_proto_timings(struct dsi_data *dsi)
2818{
2819 unsigned int tlpx, tclk_zero, tclk_prepare;
2820 unsigned int tclk_pre, tclk_post;
2821 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero;
2822 unsigned int ths_trail, ths_exit;
2823 unsigned int ddr_clk_pre, ddr_clk_post;
2824 unsigned int enter_hs_mode_lat, exit_hs_mode_lat;
2825 unsigned int ths_eot;
2826 int ndl = dsi->num_lanes_used - 1;
2827 u32 r;
2828
2829 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
2830 ths_prepare = FLD_GET(r, 31, 24);
2831 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2832 ths_zero = ths_prepare_ths_zero - ths_prepare;
2833 ths_trail = FLD_GET(r, 15, 8);
2834 ths_exit = FLD_GET(r, 7, 0);
2835
2836 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
2837 tlpx = FLD_GET(r, 20, 16) * 2;
2838 tclk_zero = FLD_GET(r, 7, 0);
2839
2840 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
2841 tclk_prepare = FLD_GET(r, 7, 0);
2842
2843 /* min 8*UI */
2844 tclk_pre = 20;
2845 /* min 60ns + 52*UI */
2846 tclk_post = ns2ddr(dsi, 60) + 26;
2847
2848 ths_eot = DIV_ROUND_UP(4, ndl);
2849
2850 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2851 4);
2852 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2853
2854 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2855 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2856
2857 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
2858 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2859 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2860 dsi_write_reg(dsi, DSI_CLK_TIMING, r);
2861
2862 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2863 ddr_clk_pre,
2864 ddr_clk_post);
2865
2866 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2867 DIV_ROUND_UP(ths_prepare, 4) +
2868 DIV_ROUND_UP(ths_zero + 3, 4);
2869
2870 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2871
2872 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2873 FLD_VAL(exit_hs_mode_lat, 15, 0);
2874 dsi_write_reg(dsi, DSI_VM_TIMING7, r);
2875
2876 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2877 enter_hs_mode_lat, exit_hs_mode_lat);
2878
2879 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2880 /* TODO: Implement a video mode check_timings function */
2881 int hsa = dsi->vm_timings.hsa;
2882 int hfp = dsi->vm_timings.hfp;
2883 int hbp = dsi->vm_timings.hbp;
2884 int vsa = dsi->vm_timings.vsa;
2885 int vfp = dsi->vm_timings.vfp;
2886 int vbp = dsi->vm_timings.vbp;
2887 int window_sync = dsi->vm_timings.window_sync;
2888 bool hsync_end;
2889 const struct videomode *vm = &dsi->vm;
2890 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
2891 int tl, t_he, width_bytes;
2892
2893 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
2894 t_he = hsync_end ?
2895 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
2896
2897 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
2898
2899 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
2900 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
2901 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
2902
2903 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
2904 hfp, hsync_end ? hsa : 0, tl);
2905 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
2906 vsa, vm->vactive);
2907
2908 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
2909 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
2910 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
2911 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
2912 dsi_write_reg(dsi, DSI_VM_TIMING1, r);
2913
2914 r = dsi_read_reg(dsi, DSI_VM_TIMING2);
2915 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
2916 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
2917 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
2918 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
2919 dsi_write_reg(dsi, DSI_VM_TIMING2, r);
2920
2921 r = dsi_read_reg(dsi, DSI_VM_TIMING3);
2922 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */
2923 r = FLD_MOD(r, tl, 31, 16); /* TL */
2924 dsi_write_reg(dsi, DSI_VM_TIMING3, r);
2925 }
2926}
2927
2928static int dsi_configure_pins(struct dsi_data *dsi,
2929 int num_pins, const u32 *pins)
2930{
2931 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
2932 int num_lanes;
2933 int i;
2934
2935 static const enum dsi_lane_function functions[] = {
2936 DSI_LANE_CLK,
2937 DSI_LANE_DATA1,
2938 DSI_LANE_DATA2,
2939 DSI_LANE_DATA3,
2940 DSI_LANE_DATA4,
2941 };
2942
2943 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
2944 || num_pins % 2 != 0)
2945 return -EINVAL;
2946
2947 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
2948 lanes[i].function = DSI_LANE_UNUSED;
2949
2950 num_lanes = 0;
2951
2952 for (i = 0; i < num_pins; i += 2) {
2953 u8 lane, pol;
2954 u32 dx, dy;
2955
2956 dx = pins[i];
2957 dy = pins[i + 1];
2958
2959 if (dx >= dsi->num_lanes_supported * 2)
2960 return -EINVAL;
2961
2962 if (dy >= dsi->num_lanes_supported * 2)
2963 return -EINVAL;
2964
2965 if (dx & 1) {
2966 if (dy != dx - 1)
2967 return -EINVAL;
2968 pol = 1;
2969 } else {
2970 if (dy != dx + 1)
2971 return -EINVAL;
2972 pol = 0;
2973 }
2974
2975 lane = dx / 2;
2976
2977 lanes[lane].function = functions[i / 2];
2978 lanes[lane].polarity = pol;
2979 num_lanes++;
2980 }
2981
2982 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
2983 dsi->num_lanes_used = num_lanes;
2984
2985 return 0;
2986}
2987
2988static int dsi_enable_video_mode(struct dsi_data *dsi, int vc)
2989{
2990 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
2991 u8 data_type;
2992 u16 word_count;
2993
2994 switch (dsi->pix_fmt) {
2995 case MIPI_DSI_FMT_RGB888:
2996 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
2997 break;
2998 case MIPI_DSI_FMT_RGB666:
2999 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3000 break;
3001 case MIPI_DSI_FMT_RGB666_PACKED:
3002 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3003 break;
3004 case MIPI_DSI_FMT_RGB565:
3005 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3006 break;
3007 default:
3008 return -EINVAL;
3009 }
3010
3011 dsi_if_enable(dsi, false);
3012 dsi_vc_enable(dsi, vc, false);
3013
3014 /* MODE, 1 = video mode */
3015 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 4, 4);
3016
3017 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3018
3019 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, data_type,
3020 word_count, 0);
3021
3022 dsi_vc_enable(dsi, vc, true);
3023 dsi_if_enable(dsi, true);
3024
3025 return 0;
3026}
3027
3028static void dsi_disable_video_mode(struct dsi_data *dsi, int vc)
3029{
3030 dsi_if_enable(dsi, false);
3031 dsi_vc_enable(dsi, vc, false);
3032
3033 /* MODE, 0 = command mode */
3034 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 0, 4, 4);
3035
3036 dsi_vc_enable(dsi, vc, true);
3037 dsi_if_enable(dsi, true);
3038}
3039
3040static void dsi_enable_video_output(struct omap_dss_device *dssdev, int vc)
3041{
3042 struct dsi_data *dsi = to_dsi_data(dssdev);
3043 int r;
3044
3045 r = dsi_init_dispc(dsi);
3046 if (r) {
3047 dev_err(dsi->dev, "failed to init dispc!\n");
3048 return;
3049 }
3050
3051 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3052 r = dsi_enable_video_mode(dsi, vc);
3053 if (r)
3054 goto err_video_mode;
3055 }
3056
3057 r = dss_mgr_enable(&dsi->output);
3058 if (r)
3059 goto err_mgr_enable;
3060
3061 return;
3062
3063err_mgr_enable:
3064 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3065 dsi_if_enable(dsi, false);
3066 dsi_vc_enable(dsi, vc, false);
3067 }
3068err_video_mode:
3069 dsi_uninit_dispc(dsi);
3070 dev_err(dsi->dev, "failed to enable DSI encoder!\n");
3071 return;
3072}
3073
3074static void dsi_disable_video_output(struct omap_dss_device *dssdev, int vc)
3075{
3076 struct dsi_data *dsi = to_dsi_data(dssdev);
3077
3078 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE)
3079 dsi_disable_video_mode(dsi, vc);
3080
3081 dss_mgr_disable(&dsi->output);
3082
3083 dsi_uninit_dispc(dsi);
3084}
3085
3086static void dsi_update_screen_dispc(struct dsi_data *dsi)
3087{
3088 unsigned int bytespp;
3089 unsigned int bytespl;
3090 unsigned int bytespf;
3091 unsigned int total_len;
3092 unsigned int packet_payload;
3093 unsigned int packet_len;
3094 u32 l;
3095 int r;
3096 const unsigned vc = dsi->update_vc;
3097 const unsigned int line_buf_size = dsi->line_buffer_size;
3098 u16 w = dsi->vm.hactive;
3099 u16 h = dsi->vm.vactive;
3100
3101 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3102
3103 bytespp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8;
3104 bytespl = w * bytespp;
3105 bytespf = bytespl * h;
3106
3107 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3108 * number of lines in a packet. See errata about VP_CLK_RATIO */
3109
3110 if (bytespf < line_buf_size)
3111 packet_payload = bytespf;
3112 else
3113 packet_payload = (line_buf_size) / bytespl * bytespl;
3114
3115 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3116 total_len = (bytespf / packet_payload) * packet_len;
3117
3118 if (bytespf % packet_payload)
3119 total_len += (bytespf % packet_payload) + 1;
3120
3121 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3122 dsi_write_reg(dsi, DSI_VC_TE(vc), l);
3123
3124 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, MIPI_DSI_DCS_LONG_WRITE,
3125 packet_len, 0);
3126
3127 if (dsi->te_enabled)
3128 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3129 else
3130 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3131 dsi_write_reg(dsi, DSI_VC_TE(vc), l);
3132
3133 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3134 * because DSS interrupts are not capable of waking up the CPU and the
3135 * framedone interrupt could be delayed for quite a long time. I think
3136 * the same goes for any DSS interrupts, but for some reason I have not
3137 * seen the problem anywhere else than here.
3138 */
3139 dispc_disable_sidle(dsi->dss->dispc);
3140
3141 dsi_perf_mark_start(dsi);
3142
3143 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3144 msecs_to_jiffies(250));
3145 BUG_ON(r == 0);
3146
3147 dss_mgr_start_update(&dsi->output);
3148
3149 if (dsi->te_enabled) {
3150 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3151 * for TE is longer than the timer allows */
3152 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3153
3154 dsi_vc_send_bta(dsi, vc);
3155
3156#ifdef DSI_CATCH_MISSING_TE
3157 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3158#endif
3159 }
3160}
3161
3162#ifdef DSI_CATCH_MISSING_TE
3163static void dsi_te_timeout(struct timer_list *unused)
3164{
3165 DSSERR("TE not received for 250ms!\n");
3166}
3167#endif
3168
3169static void dsi_handle_framedone(struct dsi_data *dsi, int error)
3170{
3171 /* SIDLEMODE back to smart-idle */
3172 dispc_enable_sidle(dsi->dss->dispc);
3173
3174 if (dsi->te_enabled) {
3175 /* enable LP_RX_TO again after the TE */
3176 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3177 }
3178
3179 dsi_bus_unlock(dsi);
3180
3181 if (!error)
3182 dsi_perf_show(dsi, "DISPC");
3183}
3184
3185static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3186{
3187 struct dsi_data *dsi = container_of(work, struct dsi_data,
3188 framedone_timeout_work.work);
3189 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3190 * 250ms which would conflict with this timeout work. What should be
3191 * done is first cancel the transfer on the HW, and then cancel the
3192 * possibly scheduled framedone work. However, cancelling the transfer
3193 * on the HW is buggy, and would probably require resetting the whole
3194 * DSI */
3195
3196 DSSERR("Framedone not received for 250ms!\n");
3197
3198 dsi_handle_framedone(dsi, -ETIMEDOUT);
3199}
3200
3201static void dsi_framedone_irq_callback(void *data)
3202{
3203 struct dsi_data *dsi = data;
3204
3205 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3206 * turns itself off. However, DSI still has the pixels in its buffers,
3207 * and is sending the data.
3208 */
3209
3210 cancel_delayed_work(&dsi->framedone_timeout_work);
3211
3212 DSSDBG("Framedone received!\n");
3213
3214 dsi_handle_framedone(dsi, 0);
3215}
3216
3217static int _dsi_update(struct dsi_data *dsi)
3218{
3219 dsi_perf_mark_setup(dsi);
3220
3221#ifdef DSI_PERF_MEASURE
3222 dsi->update_bytes = dsi->vm.hactive * dsi->vm.vactive *
3223 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8;
3224#endif
3225 dsi_update_screen_dispc(dsi);
3226
3227 return 0;
3228}
3229
3230static int _dsi_send_nop(struct dsi_data *dsi, int vc, int channel)
3231{
3232 const u8 payload[] = { MIPI_DCS_NOP };
3233 const struct mipi_dsi_msg msg = {
3234 .channel = channel,
3235 .type = MIPI_DSI_DCS_SHORT_WRITE,
3236 .tx_len = 1,
3237 .tx_buf = payload,
3238 };
3239
3240 WARN_ON(!dsi_bus_is_locked(dsi));
3241
3242 return _omap_dsi_host_transfer(dsi, vc, &msg);
3243}
3244
3245static int dsi_update_channel(struct omap_dss_device *dssdev, int vc)
3246{
3247 struct dsi_data *dsi = to_dsi_data(dssdev);
3248 int r;
3249
3250 dsi_bus_lock(dsi);
3251
3252 if (!dsi->video_enabled) {
3253 r = -EIO;
3254 goto err;
3255 }
3256
3257 if (dsi->vm.hactive == 0 || dsi->vm.vactive == 0) {
3258 r = -EINVAL;
3259 goto err;
3260 }
3261
3262 DSSDBG("dsi_update_channel: %d", vc);
3263
3264 /*
3265 * Send NOP between the frames. If we don't send something here, the
3266 * updates stop working. This is probably related to DSI spec stating
3267 * that the DSI host should transition to LP at least once per frame.
3268 */
3269 r = _dsi_send_nop(dsi, VC_CMD, dsi->dsidev->channel);
3270 if (r < 0) {
3271 DSSWARN("failed to send nop between frames: %d\n", r);
3272 goto err;
3273 }
3274
3275 dsi->update_vc = vc;
3276
3277 if (dsi->te_enabled && dsi->te_gpio) {
3278 schedule_delayed_work(&dsi->te_timeout_work,
3279 msecs_to_jiffies(250));
3280 atomic_set(&dsi->do_ext_te_update, 1);
3281 } else {
3282 _dsi_update(dsi);
3283 }
3284
3285 return 0;
3286
3287err:
3288 dsi_bus_unlock(dsi);
3289 return r;
3290}
3291
3292static int dsi_update_all(struct omap_dss_device *dssdev)
3293{
3294 return dsi_update_channel(dssdev, VC_VIDEO);
3295}
3296
3297/* Display funcs */
3298
3299static int dsi_configure_dispc_clocks(struct dsi_data *dsi)
3300{
3301 struct dispc_clock_info dispc_cinfo;
3302 int r;
3303 unsigned long fck;
3304
3305 fck = dsi_get_pll_hsdiv_dispc_rate(dsi);
3306
3307 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
3308 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
3309
3310 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo);
3311 if (r) {
3312 DSSERR("Failed to calc dispc clocks\n");
3313 return r;
3314 }
3315
3316 dsi->mgr_config.clock_info = dispc_cinfo;
3317
3318 return 0;
3319}
3320
3321static int dsi_init_dispc(struct dsi_data *dsi)
3322{
3323 enum omap_channel dispc_channel = dsi->output.dispc_channel;
3324 int r;
3325
3326 dss_select_lcd_clk_source(dsi->dss, dispc_channel, dsi->module_id == 0 ?
3327 DSS_CLK_SRC_PLL1_1 :
3328 DSS_CLK_SRC_PLL2_1);
3329
3330 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
3331 r = dss_mgr_register_framedone_handler(&dsi->output,
3332 dsi_framedone_irq_callback, dsi);
3333 if (r) {
3334 DSSERR("can't register FRAMEDONE handler\n");
3335 goto err;
3336 }
3337
3338 dsi->mgr_config.stallmode = true;
3339 dsi->mgr_config.fifohandcheck = true;
3340 } else {
3341 dsi->mgr_config.stallmode = false;
3342 dsi->mgr_config.fifohandcheck = false;
3343 }
3344
3345 r = dsi_configure_dispc_clocks(dsi);
3346 if (r)
3347 goto err1;
3348
3349 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
3350 dsi->mgr_config.video_port_width =
3351 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
3352 dsi->mgr_config.lcden_sig_polarity = 0;
3353
3354 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config);
3355
3356 return 0;
3357err1:
3358 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
3359 dss_mgr_unregister_framedone_handler(&dsi->output,
3360 dsi_framedone_irq_callback, dsi);
3361err:
3362 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK);
3363 return r;
3364}
3365
3366static void dsi_uninit_dispc(struct dsi_data *dsi)
3367{
3368 enum omap_channel dispc_channel = dsi->output.dispc_channel;
3369
3370 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
3371 dss_mgr_unregister_framedone_handler(&dsi->output,
3372 dsi_framedone_irq_callback, dsi);
3373
3374 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK);
3375}
3376
3377static int dsi_configure_dsi_clocks(struct dsi_data *dsi)
3378{
3379 struct dss_pll_clock_info cinfo;
3380 int r;
3381
3382 cinfo = dsi->user_dsi_cinfo;
3383
3384 r = dss_pll_set_config(&dsi->pll, &cinfo);
3385 if (r) {
3386 DSSERR("Failed to set dsi clocks\n");
3387 return r;
3388 }
3389
3390 return 0;
3391}
3392
3393static void dsi_setup_dsi_vcs(struct dsi_data *dsi)
3394{
3395 /* Setup VC_CMD for LP and cpu transfers */
3396 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 9, 9); /* LP */
3397
3398 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 1, 1); /* SOURCE_L4 */
3399 dsi->vc[VC_CMD].source = DSI_VC_SOURCE_L4;
3400
3401 /* Setup VC_VIDEO for HS and dispc transfers */
3402 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 9, 9); /* HS */
3403
3404 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 1, 1); /* SOURCE_VP */
3405 dsi->vc[VC_VIDEO].source = DSI_VC_SOURCE_VP;
3406
3407 if ((dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) &&
3408 !(dsi->dsidev->mode_flags & MIPI_DSI_MODE_VIDEO))
3409 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 30, 30); /* DCS_CMD_ENABLE */
3410
3411 dsi_vc_enable(dsi, VC_CMD, 1);
3412 dsi_vc_enable(dsi, VC_VIDEO, 1);
3413
3414 dsi_if_enable(dsi, 1);
3415
3416 dsi_force_tx_stop_mode_io(dsi);
3417
3418 /* start the DDR clock by sending a NULL packet */
3419 if (!(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
3420 dsi_vc_send_null(dsi, VC_CMD, dsi->dsidev->channel);
3421}
3422
3423static int dsi_init_dsi(struct dsi_data *dsi)
3424{
3425 int r;
3426
3427 r = dss_pll_enable(&dsi->pll);
3428 if (r)
3429 return r;
3430
3431 r = dsi_configure_dsi_clocks(dsi);
3432 if (r)
3433 goto err0;
3434
3435 dss_select_dsi_clk_source(dsi->dss, dsi->module_id,
3436 dsi->module_id == 0 ?
3437 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2);
3438
3439 DSSDBG("PLL OK\n");
3440
3441 if (!dsi->vdds_dsi_enabled) {
3442 r = regulator_enable(dsi->vdds_dsi_reg);
3443 if (r)
3444 goto err1;
3445
3446 dsi->vdds_dsi_enabled = true;
3447 }
3448
3449 r = dsi_cio_init(dsi);
3450 if (r)
3451 goto err2;
3452
3453 _dsi_print_reset_status(dsi);
3454
3455 dsi_proto_timings(dsi);
3456 dsi_set_lp_clk_divisor(dsi);
3457
3458 if (1)
3459 _dsi_print_reset_status(dsi);
3460
3461 r = dsi_proto_config(dsi);
3462 if (r)
3463 goto err3;
3464
3465 dsi_setup_dsi_vcs(dsi);
3466
3467 return 0;
3468err3:
3469 dsi_cio_uninit(dsi);
3470err2:
3471 regulator_disable(dsi->vdds_dsi_reg);
3472 dsi->vdds_dsi_enabled = false;
3473err1:
3474 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
3475err0:
3476 dss_pll_disable(&dsi->pll);
3477
3478 return r;
3479}
3480
3481static void dsi_uninit_dsi(struct dsi_data *dsi)
3482{
3483 /* disable interface */
3484 dsi_if_enable(dsi, 0);
3485 dsi_vc_enable(dsi, 0, 0);
3486 dsi_vc_enable(dsi, 1, 0);
3487 dsi_vc_enable(dsi, 2, 0);
3488 dsi_vc_enable(dsi, 3, 0);
3489
3490 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
3491 dsi_cio_uninit(dsi);
3492 dss_pll_disable(&dsi->pll);
3493
3494 regulator_disable(dsi->vdds_dsi_reg);
3495 dsi->vdds_dsi_enabled = false;
3496}
3497
3498static void dsi_enable(struct dsi_data *dsi)
3499{
3500 int r;
3501
3502 WARN_ON(!dsi_bus_is_locked(dsi));
3503
3504 if (WARN_ON(dsi->iface_enabled))
3505 return;
3506
3507 mutex_lock(&dsi->lock);
3508
3509 r = dsi_runtime_get(dsi);
3510 if (r)
3511 goto err_get_dsi;
3512
3513 _dsi_initialize_irq(dsi);
3514
3515 r = dsi_init_dsi(dsi);
3516 if (r)
3517 goto err_init_dsi;
3518
3519 dsi->iface_enabled = true;
3520
3521 mutex_unlock(&dsi->lock);
3522
3523 return;
3524
3525err_init_dsi:
3526 dsi_runtime_put(dsi);
3527err_get_dsi:
3528 mutex_unlock(&dsi->lock);
3529 DSSDBG("dsi_enable FAILED\n");
3530}
3531
3532static void dsi_disable(struct dsi_data *dsi)
3533{
3534 WARN_ON(!dsi_bus_is_locked(dsi));
3535
3536 if (WARN_ON(!dsi->iface_enabled))
3537 return;
3538
3539 mutex_lock(&dsi->lock);
3540
3541 dsi_sync_vc(dsi, 0);
3542 dsi_sync_vc(dsi, 1);
3543 dsi_sync_vc(dsi, 2);
3544 dsi_sync_vc(dsi, 3);
3545
3546 dsi_uninit_dsi(dsi);
3547
3548 dsi_runtime_put(dsi);
3549
3550 dsi->iface_enabled = false;
3551
3552 mutex_unlock(&dsi->lock);
3553}
3554
3555static int dsi_enable_te(struct dsi_data *dsi, bool enable)
3556{
3557 dsi->te_enabled = enable;
3558
3559 if (dsi->te_gpio) {
3560 if (enable)
3561 enable_irq(dsi->te_irq);
3562 else
3563 disable_irq(dsi->te_irq);
3564 }
3565
3566 return 0;
3567}
3568
3569#ifdef PRINT_VERBOSE_VM_TIMINGS
3570static void print_dsi_vm(const char *str,
3571 const struct omap_dss_dsi_videomode_timings *t)
3572{
3573 unsigned long byteclk = t->hsclk / 4;
3574 int bl, wc, pps, tot;
3575
3576 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
3577 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
3578 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
3579 tot = bl + pps;
3580
3581#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
3582
3583 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
3584 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
3585 str,
3586 byteclk,
3587 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
3588 bl, pps, tot,
3589 TO_DSI_T(t->hss),
3590 TO_DSI_T(t->hsa),
3591 TO_DSI_T(t->hse),
3592 TO_DSI_T(t->hbp),
3593 TO_DSI_T(pps),
3594 TO_DSI_T(t->hfp),
3595
3596 TO_DSI_T(bl),
3597 TO_DSI_T(pps),
3598
3599 TO_DSI_T(tot));
3600#undef TO_DSI_T
3601}
3602
3603static void print_dispc_vm(const char *str, const struct videomode *vm)
3604{
3605 unsigned long pck = vm->pixelclock;
3606 int hact, bl, tot;
3607
3608 hact = vm->hactive;
3609 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch;
3610 tot = hact + bl;
3611
3612#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
3613
3614 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
3615 "%u/%u/%u/%u = %u + %u = %u\n",
3616 str,
3617 pck,
3618 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch,
3619 bl, hact, tot,
3620 TO_DISPC_T(vm->hsync_len),
3621 TO_DISPC_T(vm->hback_porch),
3622 TO_DISPC_T(hact),
3623 TO_DISPC_T(vm->hfront_porch),
3624 TO_DISPC_T(bl),
3625 TO_DISPC_T(hact),
3626 TO_DISPC_T(tot));
3627#undef TO_DISPC_T
3628}
3629
3630/* note: this is not quite accurate */
3631static void print_dsi_dispc_vm(const char *str,
3632 const struct omap_dss_dsi_videomode_timings *t)
3633{
3634 struct videomode vm = { 0 };
3635 unsigned long byteclk = t->hsclk / 4;
3636 unsigned long pck;
3637 u64 dsi_tput;
3638 int dsi_hact, dsi_htot;
3639
3640 dsi_tput = (u64)byteclk * t->ndl * 8;
3641 pck = (u32)div64_u64(dsi_tput, t->bitspp);
3642 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
3643 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
3644
3645 vm.pixelclock = pck;
3646 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
3647 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk);
3648 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk);
3649 vm.hactive = t->hact;
3650
3651 print_dispc_vm(str, &vm);
3652}
3653#endif /* PRINT_VERBOSE_VM_TIMINGS */
3654
3655static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
3656 unsigned long pck, void *data)
3657{
3658 struct dsi_clk_calc_ctx *ctx = data;
3659 struct videomode *vm = &ctx->vm;
3660
3661 ctx->dispc_cinfo.lck_div = lckd;
3662 ctx->dispc_cinfo.pck_div = pckd;
3663 ctx->dispc_cinfo.lck = lck;
3664 ctx->dispc_cinfo.pck = pck;
3665
3666 *vm = *ctx->config->vm;
3667 vm->pixelclock = pck;
3668 vm->hactive = ctx->config->vm->hactive;
3669 vm->vactive = ctx->config->vm->vactive;
3670 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1;
3671 vm->vfront_porch = vm->vback_porch = 0;
3672
3673 return true;
3674}
3675
3676static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
3677 void *data)
3678{
3679 struct dsi_clk_calc_ctx *ctx = data;
3680
3681 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
3682 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
3683
3684 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
3685 ctx->req_pck_min, ctx->req_pck_max,
3686 dsi_cm_calc_dispc_cb, ctx);
3687}
3688
3689static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
3690 unsigned long clkdco, void *data)
3691{
3692 struct dsi_clk_calc_ctx *ctx = data;
3693 struct dsi_data *dsi = ctx->dsi;
3694
3695 ctx->dsi_cinfo.n = n;
3696 ctx->dsi_cinfo.m = m;
3697 ctx->dsi_cinfo.fint = fint;
3698 ctx->dsi_cinfo.clkdco = clkdco;
3699
3700 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
3701 dsi->data->max_fck_freq,
3702 dsi_cm_calc_hsdiv_cb, ctx);
3703}
3704
3705static bool dsi_cm_calc(struct dsi_data *dsi,
3706 const struct omap_dss_dsi_config *cfg,
3707 struct dsi_clk_calc_ctx *ctx)
3708{
3709 unsigned long clkin;
3710 int bitspp, ndl;
3711 unsigned long pll_min, pll_max;
3712 unsigned long pck, txbyteclk;
3713
3714 clkin = clk_get_rate(dsi->pll.clkin);
3715 bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format);
3716 ndl = dsi->num_lanes_used - 1;
3717
3718 /*
3719 * Here we should calculate minimum txbyteclk to be able to send the
3720 * frame in time, and also to handle TE. That's not very simple, though,
3721 * especially as we go to LP between each pixel packet due to HW
3722 * "feature". So let's just estimate very roughly and multiply by 1.5.
3723 */
3724 pck = cfg->vm->pixelclock;
3725 pck = pck * 3 / 2;
3726 txbyteclk = pck * bitspp / 8 / ndl;
3727
3728 memset(ctx, 0, sizeof(*ctx));
3729 ctx->dsi = dsi;
3730 ctx->pll = &dsi->pll;
3731 ctx->config = cfg;
3732 ctx->req_pck_min = pck;
3733 ctx->req_pck_nom = pck;
3734 ctx->req_pck_max = pck * 3 / 2;
3735
3736 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
3737 pll_max = cfg->hs_clk_max * 4;
3738
3739 return dss_pll_calc_a(ctx->pll, clkin,
3740 pll_min, pll_max,
3741 dsi_cm_calc_pll_cb, ctx);
3742}
3743
3744static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
3745{
3746 struct dsi_data *dsi = ctx->dsi;
3747 const struct omap_dss_dsi_config *cfg = ctx->config;
3748 int bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format);
3749 int ndl = dsi->num_lanes_used - 1;
3750 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
3751 unsigned long byteclk = hsclk / 4;
3752
3753 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
3754 int xres;
3755 int panel_htot, panel_hbl; /* pixels */
3756 int dispc_htot, dispc_hbl; /* pixels */
3757 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
3758 int hfp, hsa, hbp;
3759 const struct videomode *req_vm;
3760 struct videomode *dispc_vm;
3761 struct omap_dss_dsi_videomode_timings *dsi_vm;
3762 u64 dsi_tput, dispc_tput;
3763
3764 dsi_tput = (u64)byteclk * ndl * 8;
3765
3766 req_vm = cfg->vm;
3767 req_pck_min = ctx->req_pck_min;
3768 req_pck_max = ctx->req_pck_max;
3769 req_pck_nom = ctx->req_pck_nom;
3770
3771 dispc_pck = ctx->dispc_cinfo.pck;
3772 dispc_tput = (u64)dispc_pck * bitspp;
3773
3774 xres = req_vm->hactive;
3775
3776 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch +
3777 req_vm->hsync_len;
3778 panel_htot = xres + panel_hbl;
3779
3780 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
3781
3782 /*
3783 * When there are no line buffers, DISPC and DSI must have the
3784 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
3785 */
3786 if (dsi->line_buffer_size < xres * bitspp / 8) {
3787 if (dispc_tput != dsi_tput)
3788 return false;
3789 } else {
3790 if (dispc_tput < dsi_tput)
3791 return false;
3792 }
3793
3794 /* DSI tput must be over the min requirement */
3795 if (dsi_tput < (u64)bitspp * req_pck_min)
3796 return false;
3797
3798 /* When non-burst mode, DSI tput must be below max requirement. */
3799 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
3800 if (dsi_tput > (u64)bitspp * req_pck_max)
3801 return false;
3802 }
3803
3804 hss = DIV_ROUND_UP(4, ndl);
3805
3806 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
3807 if (ndl == 3 && req_vm->hsync_len == 0)
3808 hse = 1;
3809 else
3810 hse = DIV_ROUND_UP(4, ndl);
3811 } else {
3812 hse = 0;
3813 }
3814
3815 /* DSI htot to match the panel's nominal pck */
3816 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
3817
3818 /* fail if there would be no time for blanking */
3819 if (dsi_htot < hss + hse + dsi_hact)
3820 return false;
3821
3822 /* total DSI blanking needed to achieve panel's TL */
3823 dsi_hbl = dsi_htot - dsi_hact;
3824
3825 /* DISPC htot to match the DSI TL */
3826 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
3827
3828 /* verify that the DSI and DISPC TLs are the same */
3829 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
3830 return false;
3831
3832 dispc_hbl = dispc_htot - xres;
3833
3834 /* setup DSI videomode */
3835
3836 dsi_vm = &ctx->dsi_vm;
3837 memset(dsi_vm, 0, sizeof(*dsi_vm));
3838
3839 dsi_vm->hsclk = hsclk;
3840
3841 dsi_vm->ndl = ndl;
3842 dsi_vm->bitspp = bitspp;
3843
3844 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
3845 hsa = 0;
3846 } else if (ndl == 3 && req_vm->hsync_len == 0) {
3847 hsa = 0;
3848 } else {
3849 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
3850 hsa = max(hsa - hse, 1);
3851 }
3852
3853 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom);
3854 hbp = max(hbp, 1);
3855
3856 hfp = dsi_hbl - (hss + hsa + hse + hbp);
3857 if (hfp < 1) {
3858 int t;
3859 /* we need to take cycles from hbp */
3860
3861 t = 1 - hfp;
3862 hbp = max(hbp - t, 1);
3863 hfp = dsi_hbl - (hss + hsa + hse + hbp);
3864
3865 if (hfp < 1 && hsa > 0) {
3866 /* we need to take cycles from hsa */
3867 t = 1 - hfp;
3868 hsa = max(hsa - t, 1);
3869 hfp = dsi_hbl - (hss + hsa + hse + hbp);
3870 }
3871 }
3872
3873 if (hfp < 1)
3874 return false;
3875
3876 dsi_vm->hss = hss;
3877 dsi_vm->hsa = hsa;
3878 dsi_vm->hse = hse;
3879 dsi_vm->hbp = hbp;
3880 dsi_vm->hact = xres;
3881 dsi_vm->hfp = hfp;
3882
3883 dsi_vm->vsa = req_vm->vsync_len;
3884 dsi_vm->vbp = req_vm->vback_porch;
3885 dsi_vm->vact = req_vm->vactive;
3886 dsi_vm->vfp = req_vm->vfront_porch;
3887
3888 dsi_vm->trans_mode = cfg->trans_mode;
3889
3890 dsi_vm->blanking_mode = 0;
3891 dsi_vm->hsa_blanking_mode = 1;
3892 dsi_vm->hfp_blanking_mode = 1;
3893 dsi_vm->hbp_blanking_mode = 1;
3894
3895 dsi_vm->window_sync = 4;
3896
3897 /* setup DISPC videomode */
3898
3899 dispc_vm = &ctx->vm;
3900 *dispc_vm = *req_vm;
3901 dispc_vm->pixelclock = dispc_pck;
3902
3903 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
3904 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
3905 req_pck_nom);
3906 hsa = max(hsa, 1);
3907 } else {
3908 hsa = 1;
3909 }
3910
3911 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom);
3912 hbp = max(hbp, 1);
3913
3914 hfp = dispc_hbl - hsa - hbp;
3915 if (hfp < 1) {
3916 int t;
3917 /* we need to take cycles from hbp */
3918
3919 t = 1 - hfp;
3920 hbp = max(hbp - t, 1);
3921 hfp = dispc_hbl - hsa - hbp;
3922
3923 if (hfp < 1) {
3924 /* we need to take cycles from hsa */
3925 t = 1 - hfp;
3926 hsa = max(hsa - t, 1);
3927 hfp = dispc_hbl - hsa - hbp;
3928 }
3929 }
3930
3931 if (hfp < 1)
3932 return false;
3933
3934 dispc_vm->hfront_porch = hfp;
3935 dispc_vm->hsync_len = hsa;
3936 dispc_vm->hback_porch = hbp;
3937
3938 return true;
3939}
3940
3941
3942static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
3943 unsigned long pck, void *data)
3944{
3945 struct dsi_clk_calc_ctx *ctx = data;
3946
3947 ctx->dispc_cinfo.lck_div = lckd;
3948 ctx->dispc_cinfo.pck_div = pckd;
3949 ctx->dispc_cinfo.lck = lck;
3950 ctx->dispc_cinfo.pck = pck;
3951
3952 if (dsi_vm_calc_blanking(ctx) == false)
3953 return false;
3954
3955#ifdef PRINT_VERBOSE_VM_TIMINGS
3956 print_dispc_vm("dispc", &ctx->vm);
3957 print_dsi_vm("dsi ", &ctx->dsi_vm);
3958 print_dispc_vm("req ", ctx->config->vm);
3959 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
3960#endif
3961
3962 return true;
3963}
3964
3965static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
3966 void *data)
3967{
3968 struct dsi_clk_calc_ctx *ctx = data;
3969 unsigned long pck_max;
3970
3971 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
3972 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
3973
3974 /*
3975 * In burst mode we can let the dispc pck be arbitrarily high, but it
3976 * limits our scaling abilities. So for now, don't aim too high.
3977 */
3978
3979 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
3980 pck_max = ctx->req_pck_max + 10000000;
3981 else
3982 pck_max = ctx->req_pck_max;
3983
3984 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
3985 ctx->req_pck_min, pck_max,
3986 dsi_vm_calc_dispc_cb, ctx);
3987}
3988
3989static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
3990 unsigned long clkdco, void *data)
3991{
3992 struct dsi_clk_calc_ctx *ctx = data;
3993 struct dsi_data *dsi = ctx->dsi;
3994
3995 ctx->dsi_cinfo.n = n;
3996 ctx->dsi_cinfo.m = m;
3997 ctx->dsi_cinfo.fint = fint;
3998 ctx->dsi_cinfo.clkdco = clkdco;
3999
4000 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4001 dsi->data->max_fck_freq,
4002 dsi_vm_calc_hsdiv_cb, ctx);
4003}
4004
4005static bool dsi_vm_calc(struct dsi_data *dsi,
4006 const struct omap_dss_dsi_config *cfg,
4007 struct dsi_clk_calc_ctx *ctx)
4008{
4009 const struct videomode *vm = cfg->vm;
4010 unsigned long clkin;
4011 unsigned long pll_min;
4012 unsigned long pll_max;
4013 int ndl = dsi->num_lanes_used - 1;
4014 int bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format);
4015 unsigned long byteclk_min;
4016
4017 clkin = clk_get_rate(dsi->pll.clkin);
4018
4019 memset(ctx, 0, sizeof(*ctx));
4020 ctx->dsi = dsi;
4021 ctx->pll = &dsi->pll;
4022 ctx->config = cfg;
4023
4024 /* these limits should come from the panel driver */
4025 ctx->req_pck_min = vm->pixelclock - 1000;
4026 ctx->req_pck_nom = vm->pixelclock;
4027 ctx->req_pck_max = vm->pixelclock + 1000;
4028
4029 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4030 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4031
4032 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4033 pll_max = cfg->hs_clk_max * 4;
4034 } else {
4035 unsigned long byteclk_max;
4036 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4037 ndl * 8);
4038
4039 pll_max = byteclk_max * 4 * 4;
4040 }
4041
4042 return dss_pll_calc_a(ctx->pll, clkin,
4043 pll_min, pll_max,
4044 dsi_vm_calc_pll_cb, ctx);
4045}
4046
4047static bool dsi_is_video_mode(struct omap_dss_device *dssdev)
4048{
4049 struct dsi_data *dsi = to_dsi_data(dssdev);
4050
4051 return dsi->mode == OMAP_DSS_DSI_VIDEO_MODE;
4052}
4053
4054static int __dsi_calc_config(struct dsi_data *dsi,
4055 const struct drm_display_mode *mode,
4056 struct dsi_clk_calc_ctx *ctx)
4057{
4058 struct omap_dss_dsi_config cfg = dsi->config;
4059 struct videomode vm;
4060 bool ok;
4061 int r;
4062
4063 drm_display_mode_to_videomode(mode, &vm);
4064
4065 cfg.vm = &vm;
4066 cfg.mode = dsi->mode;
4067 cfg.pixel_format = dsi->pix_fmt;
4068
4069 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE)
4070 ok = dsi_vm_calc(dsi, &cfg, ctx);
4071 else
4072 ok = dsi_cm_calc(dsi, &cfg, ctx);
4073
4074 if (!ok)
4075 return -EINVAL;
4076
4077 dsi_pll_calc_dsi_fck(dsi, &ctx->dsi_cinfo);
4078
4079 r = dsi_lp_clock_calc(ctx->dsi_cinfo.clkout[HSDIV_DSI],
4080 cfg.lp_clk_min, cfg.lp_clk_max, &ctx->lp_cinfo);
4081 if (r)
4082 return r;
4083
4084 return 0;
4085}
4086
4087static int dsi_set_config(struct omap_dss_device *dssdev,
4088 const struct drm_display_mode *mode)
4089{
4090 struct dsi_data *dsi = to_dsi_data(dssdev);
4091 struct dsi_clk_calc_ctx ctx;
4092 int r;
4093
4094 mutex_lock(&dsi->lock);
4095
4096 r = __dsi_calc_config(dsi, mode, &ctx);
4097 if (r) {
4098 DSSERR("failed to find suitable DSI clock settings\n");
4099 goto err;
4100 }
4101
4102 dsi->user_lp_cinfo = ctx.lp_cinfo;
4103 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4104 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4105
4106 dsi->vm = ctx.vm;
4107
4108 /*
4109 * override interlace, logic level and edge related parameters in
4110 * videomode with default values
4111 */
4112 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4113 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4114 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4115 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4116 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4117 /*
4118 * HACK: These flags should be handled through the omap_dss_device bus
4119 * flags, but this will only be possible when the DSI encoder will be
4120 * converted to the omapdrm-managed encoder model.
4121 */
4122 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4123 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4124 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4125 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4126 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4127 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4128
4129 dss_mgr_set_timings(&dsi->output, &dsi->vm);
4130
4131 dsi->vm_timings = ctx.dsi_vm;
4132
4133 mutex_unlock(&dsi->lock);
4134
4135 return 0;
4136err:
4137 mutex_unlock(&dsi->lock);
4138
4139 return r;
4140}
4141
4142/*
4143 * Return a hardcoded dispc channel for the DSI output. This should work for
4144 * current use cases, but this can be later expanded to either resolve
4145 * the channel in some more dynamic manner, or get the channel as a user
4146 * parameter.
4147 */
4148static enum omap_channel dsi_get_dispc_channel(struct dsi_data *dsi)
4149{
4150 switch (dsi->data->model) {
4151 case DSI_MODEL_OMAP3:
4152 return OMAP_DSS_CHANNEL_LCD;
4153
4154 case DSI_MODEL_OMAP4:
4155 switch (dsi->module_id) {
4156 case 0:
4157 return OMAP_DSS_CHANNEL_LCD;
4158 case 1:
4159 return OMAP_DSS_CHANNEL_LCD2;
4160 default:
4161 DSSWARN("unsupported module id\n");
4162 return OMAP_DSS_CHANNEL_LCD;
4163 }
4164
4165 case DSI_MODEL_OMAP5:
4166 switch (dsi->module_id) {
4167 case 0:
4168 return OMAP_DSS_CHANNEL_LCD;
4169 case 1:
4170 return OMAP_DSS_CHANNEL_LCD3;
4171 default:
4172 DSSWARN("unsupported module id\n");
4173 return OMAP_DSS_CHANNEL_LCD;
4174 }
4175
4176 default:
4177 DSSWARN("unsupported DSS version\n");
4178 return OMAP_DSS_CHANNEL_LCD;
4179 }
4180}
4181
4182static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc,
4183 const struct mipi_dsi_msg *msg)
4184{
4185 struct omap_dss_device *dssdev = &dsi->output;
4186 int r;
4187
4188 dsi_vc_enable_hs(dssdev, vc, !(msg->flags & MIPI_DSI_MSG_USE_LPM));
4189
4190 switch (msg->type) {
4191 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
4192 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
4193 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
4194 case MIPI_DSI_GENERIC_LONG_WRITE:
4195 case MIPI_DSI_DCS_SHORT_WRITE:
4196 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
4197 case MIPI_DSI_DCS_LONG_WRITE:
4198 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
4199 case MIPI_DSI_NULL_PACKET:
4200 r = dsi_vc_write_common(dssdev, vc, msg);
4201 break;
4202 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
4203 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
4204 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
4205 r = dsi_vc_generic_read(dssdev, vc, msg);
4206 break;
4207 case MIPI_DSI_DCS_READ:
4208 r = dsi_vc_dcs_read(dssdev, vc, msg);
4209 break;
4210 default:
4211 r = -EINVAL;
4212 break;
4213 }
4214
4215 if (r < 0)
4216 return r;
4217
4218 if (msg->type == MIPI_DSI_DCS_SHORT_WRITE ||
4219 msg->type == MIPI_DSI_DCS_SHORT_WRITE_PARAM) {
4220 u8 cmd = ((u8 *)msg->tx_buf)[0];
4221
4222 if (cmd == MIPI_DCS_SET_TEAR_OFF)
4223 dsi_enable_te(dsi, false);
4224 else if (cmd == MIPI_DCS_SET_TEAR_ON)
4225 dsi_enable_te(dsi, true);
4226 }
4227
4228 return 0;
4229}
4230
4231static ssize_t omap_dsi_host_transfer(struct mipi_dsi_host *host,
4232 const struct mipi_dsi_msg *msg)
4233{
4234 struct dsi_data *dsi = host_to_omap(host);
4235 int r;
4236 int vc = VC_CMD;
4237
4238 dsi_bus_lock(dsi);
4239
4240 if (!dsi->iface_enabled) {
4241 dsi_enable(dsi);
4242 schedule_delayed_work(&dsi->dsi_disable_work, msecs_to_jiffies(2000));
4243 }
4244
4245 r = _omap_dsi_host_transfer(dsi, vc, msg);
4246
4247 dsi_bus_unlock(dsi);
4248
4249 return r;
4250}
4251
4252static int dsi_get_clocks(struct dsi_data *dsi)
4253{
4254 struct clk *clk;
4255
4256 clk = devm_clk_get(dsi->dev, "fck");
4257 if (IS_ERR(clk)) {
4258 DSSERR("can't get fck\n");
4259 return PTR_ERR(clk);
4260 }
4261
4262 dsi->dss_clk = clk;
4263
4264 return 0;
4265}
4266
4267static const struct omapdss_dsi_ops dsi_ops = {
4268 .update = dsi_update_all,
4269 .is_video_mode = dsi_is_video_mode,
4270};
4271
4272static irqreturn_t omap_dsi_te_irq_handler(int irq, void *dev_id)
4273{
4274 struct dsi_data *dsi = (struct dsi_data *)dev_id;
4275 int old;
4276
4277 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0);
4278 if (old) {
4279 cancel_delayed_work(&dsi->te_timeout_work);
4280 _dsi_update(dsi);
4281 }
4282
4283 return IRQ_HANDLED;
4284}
4285
4286static void omap_dsi_te_timeout_work_callback(struct work_struct *work)
4287{
4288 struct dsi_data *dsi =
4289 container_of(work, struct dsi_data, te_timeout_work.work);
4290 int old;
4291
4292 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0);
4293 if (old) {
4294 dev_err(dsi->dev, "TE not received for 250ms!\n");
4295 _dsi_update(dsi);
4296 }
4297}
4298
4299static int omap_dsi_register_te_irq(struct dsi_data *dsi,
4300 struct mipi_dsi_device *client)
4301{
4302 int err;
4303 int te_irq;
4304
4305 dsi->te_gpio = gpiod_get(&client->dev, "te-gpios", GPIOD_IN);
4306 if (IS_ERR(dsi->te_gpio)) {
4307 err = PTR_ERR(dsi->te_gpio);
4308
4309 if (err == -ENOENT) {
4310 dsi->te_gpio = NULL;
4311 return 0;
4312 }
4313
4314 dev_err(dsi->dev, "Could not get TE gpio: %d\n", err);
4315 return err;
4316 }
4317
4318 te_irq = gpiod_to_irq(dsi->te_gpio);
4319 if (te_irq < 0) {
4320 gpiod_put(dsi->te_gpio);
4321 dsi->te_gpio = NULL;
4322 return -EINVAL;
4323 }
4324
4325 dsi->te_irq = te_irq;
4326
4327 irq_set_status_flags(te_irq, IRQ_NOAUTOEN);
4328
4329 err = request_threaded_irq(te_irq, NULL, omap_dsi_te_irq_handler,
4330 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
4331 "TE", dsi);
4332 if (err) {
4333 dev_err(dsi->dev, "request irq failed with %d\n", err);
4334 gpiod_put(dsi->te_gpio);
4335 dsi->te_gpio = NULL;
4336 return err;
4337 }
4338
4339 INIT_DEFERRABLE_WORK(&dsi->te_timeout_work,
4340 omap_dsi_te_timeout_work_callback);
4341
4342 dev_dbg(dsi->dev, "Using GPIO TE\n");
4343
4344 return 0;
4345}
4346
4347static void omap_dsi_unregister_te_irq(struct dsi_data *dsi)
4348{
4349 if (dsi->te_gpio) {
4350 free_irq(dsi->te_irq, dsi);
4351 cancel_delayed_work(&dsi->te_timeout_work);
4352 gpiod_put(dsi->te_gpio);
4353 dsi->te_gpio = NULL;
4354 }
4355}
4356
4357static int omap_dsi_host_attach(struct mipi_dsi_host *host,
4358 struct mipi_dsi_device *client)
4359{
4360 struct dsi_data *dsi = host_to_omap(host);
4361 int r;
4362
4363 if (dsi->dsidev) {
4364 DSSERR("dsi client already attached\n");
4365 return -EBUSY;
4366 }
4367
4368 if (mipi_dsi_pixel_format_to_bpp(client->format) < 0) {
4369 DSSERR("invalid pixel format\n");
4370 return -EINVAL;
4371 }
4372
4373 atomic_set(&dsi->do_ext_te_update, 0);
4374
4375 if (client->mode_flags & MIPI_DSI_MODE_VIDEO) {
4376 dsi->mode = OMAP_DSS_DSI_VIDEO_MODE;
4377 } else {
4378 r = omap_dsi_register_te_irq(dsi, client);
4379 if (r)
4380 return r;
4381
4382 dsi->mode = OMAP_DSS_DSI_CMD_MODE;
4383 }
4384
4385 dsi->dsidev = client;
4386 dsi->pix_fmt = client->format;
4387
4388 dsi->config.hs_clk_min = 150000000; // TODO: get from client?
4389 dsi->config.hs_clk_max = client->hs_rate;
4390 dsi->config.lp_clk_min = 7000000; // TODO: get from client?
4391 dsi->config.lp_clk_max = client->lp_rate;
4392
4393 if (client->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
4394 dsi->config.trans_mode = OMAP_DSS_DSI_BURST_MODE;
4395 else if (client->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
4396 dsi->config.trans_mode = OMAP_DSS_DSI_PULSE_MODE;
4397 else
4398 dsi->config.trans_mode = OMAP_DSS_DSI_EVENT_MODE;
4399
4400 return 0;
4401}
4402
4403static int omap_dsi_host_detach(struct mipi_dsi_host *host,
4404 struct mipi_dsi_device *client)
4405{
4406 struct dsi_data *dsi = host_to_omap(host);
4407
4408 if (WARN_ON(dsi->dsidev != client))
4409 return -EINVAL;
4410
4411 cancel_delayed_work_sync(&dsi->dsi_disable_work);
4412
4413 dsi_bus_lock(dsi);
4414
4415 if (dsi->iface_enabled)
4416 dsi_disable(dsi);
4417
4418 dsi_bus_unlock(dsi);
4419
4420 omap_dsi_unregister_te_irq(dsi);
4421 dsi->dsidev = NULL;
4422 return 0;
4423}
4424
4425static const struct mipi_dsi_host_ops omap_dsi_host_ops = {
4426 .attach = omap_dsi_host_attach,
4427 .detach = omap_dsi_host_detach,
4428 .transfer = omap_dsi_host_transfer,
4429};
4430
4431/* -----------------------------------------------------------------------------
4432 * PLL
4433 */
4434
4435static const struct dss_pll_ops dsi_pll_ops = {
4436 .enable = dsi_pll_enable,
4437 .disable = dsi_pll_disable,
4438 .set_config = dss_pll_write_config_type_a,
4439};
4440
4441static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
4442 .type = DSS_PLL_TYPE_A,
4443
4444 .n_max = (1 << 7) - 1,
4445 .m_max = (1 << 11) - 1,
4446 .mX_max = (1 << 4) - 1,
4447 .fint_min = 750000,
4448 .fint_max = 2100000,
4449 .clkdco_low = 1000000000,
4450 .clkdco_max = 1800000000,
4451
4452 .n_msb = 7,
4453 .n_lsb = 1,
4454 .m_msb = 18,
4455 .m_lsb = 8,
4456
4457 .mX_msb[0] = 22,
4458 .mX_lsb[0] = 19,
4459 .mX_msb[1] = 26,
4460 .mX_lsb[1] = 23,
4461
4462 .has_stopmode = true,
4463 .has_freqsel = true,
4464 .has_selfreqdco = false,
4465 .has_refsel = false,
4466};
4467
4468static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
4469 .type = DSS_PLL_TYPE_A,
4470
4471 .n_max = (1 << 8) - 1,
4472 .m_max = (1 << 12) - 1,
4473 .mX_max = (1 << 5) - 1,
4474 .fint_min = 500000,
4475 .fint_max = 2500000,
4476 .clkdco_low = 1000000000,
4477 .clkdco_max = 1800000000,
4478
4479 .n_msb = 8,
4480 .n_lsb = 1,
4481 .m_msb = 20,
4482 .m_lsb = 9,
4483
4484 .mX_msb[0] = 25,
4485 .mX_lsb[0] = 21,
4486 .mX_msb[1] = 30,
4487 .mX_lsb[1] = 26,
4488
4489 .has_stopmode = true,
4490 .has_freqsel = false,
4491 .has_selfreqdco = false,
4492 .has_refsel = false,
4493};
4494
4495static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
4496 .type = DSS_PLL_TYPE_A,
4497
4498 .n_max = (1 << 8) - 1,
4499 .m_max = (1 << 12) - 1,
4500 .mX_max = (1 << 5) - 1,
4501 .fint_min = 150000,
4502 .fint_max = 52000000,
4503 .clkdco_low = 1000000000,
4504 .clkdco_max = 1800000000,
4505
4506 .n_msb = 8,
4507 .n_lsb = 1,
4508 .m_msb = 20,
4509 .m_lsb = 9,
4510
4511 .mX_msb[0] = 25,
4512 .mX_lsb[0] = 21,
4513 .mX_msb[1] = 30,
4514 .mX_lsb[1] = 26,
4515
4516 .has_stopmode = true,
4517 .has_freqsel = false,
4518 .has_selfreqdco = true,
4519 .has_refsel = true,
4520};
4521
4522static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi)
4523{
4524 struct dss_pll *pll = &dsi->pll;
4525 struct clk *clk;
4526 int r;
4527
4528 clk = devm_clk_get(dsi->dev, "sys_clk");
4529 if (IS_ERR(clk)) {
4530 DSSERR("can't get sys_clk\n");
4531 return PTR_ERR(clk);
4532 }
4533
4534 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
4535 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
4536 pll->clkin = clk;
4537 pll->base = dsi->pll_base;
4538 pll->hw = dsi->data->pll_hw;
4539 pll->ops = &dsi_pll_ops;
4540
4541 r = dss_pll_register(dss, pll);
4542 if (r)
4543 return r;
4544
4545 return 0;
4546}
4547
4548/* -----------------------------------------------------------------------------
4549 * Component Bind & Unbind
4550 */
4551
4552static int dsi_bind(struct device *dev, struct device *master, void *data)
4553{
4554 struct dss_device *dss = dss_get_device(master);
4555 struct dsi_data *dsi = dev_get_drvdata(dev);
4556 char name[10];
4557 u32 rev;
4558 int r;
4559
4560 dsi->dss = dss;
4561
4562 dsi_init_pll_data(dss, dsi);
4563
4564 r = dsi_runtime_get(dsi);
4565 if (r)
4566 return r;
4567
4568 rev = dsi_read_reg(dsi, DSI_REVISION);
4569 dev_dbg(dev, "OMAP DSI rev %d.%d\n",
4570 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4571
4572 dsi->line_buffer_size = dsi_get_line_buf_size(dsi);
4573
4574 dsi_runtime_put(dsi);
4575
4576 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1);
4577 dsi->debugfs.regs = dss_debugfs_create_file(dss, name,
4578 dsi_dump_dsi_regs, dsi);
4579#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4580 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1);
4581 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name,
4582 dsi_dump_dsi_irqs, dsi);
4583#endif
4584 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1);
4585 dsi->debugfs.clks = dss_debugfs_create_file(dss, name,
4586 dsi_dump_dsi_clocks, dsi);
4587
4588 return 0;
4589}
4590
4591static void dsi_unbind(struct device *dev, struct device *master, void *data)
4592{
4593 struct dsi_data *dsi = dev_get_drvdata(dev);
4594
4595 dss_debugfs_remove_file(dsi->debugfs.clks);
4596 dss_debugfs_remove_file(dsi->debugfs.irqs);
4597 dss_debugfs_remove_file(dsi->debugfs.regs);
4598
4599 WARN_ON(dsi->scp_clk_refcount > 0);
4600
4601 dss_pll_unregister(&dsi->pll);
4602}
4603
4604static const struct component_ops dsi_component_ops = {
4605 .bind = dsi_bind,
4606 .unbind = dsi_unbind,
4607};
4608
4609/* -----------------------------------------------------------------------------
4610 * DRM Bridge Operations
4611 */
4612
4613static int dsi_bridge_attach(struct drm_bridge *bridge,
4614 enum drm_bridge_attach_flags flags)
4615{
4616 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4617
4618 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
4619 return -EINVAL;
4620
4621 return drm_bridge_attach(bridge->encoder, dsi->output.next_bridge,
4622 bridge, flags);
4623}
4624
4625static enum drm_mode_status
4626dsi_bridge_mode_valid(struct drm_bridge *bridge,
4627 const struct drm_display_info *info,
4628 const struct drm_display_mode *mode)
4629{
4630 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4631 struct dsi_clk_calc_ctx ctx;
4632 int r;
4633
4634 mutex_lock(&dsi->lock);
4635 r = __dsi_calc_config(dsi, mode, &ctx);
4636 mutex_unlock(&dsi->lock);
4637
4638 return r ? MODE_CLOCK_RANGE : MODE_OK;
4639}
4640
4641static void dsi_bridge_mode_set(struct drm_bridge *bridge,
4642 const struct drm_display_mode *mode,
4643 const struct drm_display_mode *adjusted_mode)
4644{
4645 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4646
4647 dsi_set_config(&dsi->output, adjusted_mode);
4648}
4649
4650static void dsi_bridge_enable(struct drm_bridge *bridge)
4651{
4652 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4653 struct omap_dss_device *dssdev = &dsi->output;
4654
4655 cancel_delayed_work_sync(&dsi->dsi_disable_work);
4656
4657 dsi_bus_lock(dsi);
4658
4659 if (!dsi->iface_enabled)
4660 dsi_enable(dsi);
4661
4662 dsi_enable_video_output(dssdev, VC_VIDEO);
4663
4664 dsi->video_enabled = true;
4665
4666 dsi_bus_unlock(dsi);
4667}
4668
4669static void dsi_bridge_disable(struct drm_bridge *bridge)
4670{
4671 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4672 struct omap_dss_device *dssdev = &dsi->output;
4673
4674 cancel_delayed_work_sync(&dsi->dsi_disable_work);
4675
4676 dsi_bus_lock(dsi);
4677
4678 dsi->video_enabled = false;
4679
4680 dsi_disable_video_output(dssdev, VC_VIDEO);
4681
4682 dsi_disable(dsi);
4683
4684 dsi_bus_unlock(dsi);
4685}
4686
4687static const struct drm_bridge_funcs dsi_bridge_funcs = {
4688 .attach = dsi_bridge_attach,
4689 .mode_valid = dsi_bridge_mode_valid,
4690 .mode_set = dsi_bridge_mode_set,
4691 .enable = dsi_bridge_enable,
4692 .disable = dsi_bridge_disable,
4693};
4694
4695static void dsi_bridge_init(struct dsi_data *dsi)
4696{
4697 dsi->bridge.funcs = &dsi_bridge_funcs;
4698 dsi->bridge.of_node = dsi->host.dev->of_node;
4699 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
4700
4701 drm_bridge_add(&dsi->bridge);
4702}
4703
4704static void dsi_bridge_cleanup(struct dsi_data *dsi)
4705{
4706 drm_bridge_remove(&dsi->bridge);
4707}
4708
4709/* -----------------------------------------------------------------------------
4710 * Probe & Remove, Suspend & Resume
4711 */
4712
4713static int dsi_init_output(struct dsi_data *dsi)
4714{
4715 struct omap_dss_device *out = &dsi->output;
4716 int r;
4717
4718 dsi_bridge_init(dsi);
4719
4720 out->dev = dsi->dev;
4721 out->id = dsi->module_id == 0 ?
4722 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
4723
4724 out->type = OMAP_DISPLAY_TYPE_DSI;
4725 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
4726 out->dispc_channel = dsi_get_dispc_channel(dsi);
4727 out->dsi_ops = &dsi_ops;
4728 out->of_port = 0;
4729 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
4730 | DRM_BUS_FLAG_DE_HIGH
4731 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
4732
4733 r = omapdss_device_init_output(out, &dsi->bridge);
4734 if (r < 0) {
4735 dsi_bridge_cleanup(dsi);
4736 return r;
4737 }
4738
4739 omapdss_device_register(out);
4740
4741 return 0;
4742}
4743
4744static void dsi_uninit_output(struct dsi_data *dsi)
4745{
4746 struct omap_dss_device *out = &dsi->output;
4747
4748 omapdss_device_unregister(out);
4749 omapdss_device_cleanup_output(out);
4750 dsi_bridge_cleanup(dsi);
4751}
4752
4753static int dsi_probe_of(struct dsi_data *dsi)
4754{
4755 struct device_node *node = dsi->dev->of_node;
4756 struct property *prop;
4757 u32 lane_arr[10];
4758 int len, num_pins;
4759 int r;
4760 struct device_node *ep;
4761
4762 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
4763 if (!ep)
4764 return 0;
4765
4766 prop = of_find_property(ep, "lanes", &len);
4767 if (prop == NULL) {
4768 dev_err(dsi->dev, "failed to find lane data\n");
4769 r = -EINVAL;
4770 goto err;
4771 }
4772
4773 num_pins = len / sizeof(u32);
4774
4775 if (num_pins < 4 || num_pins % 2 != 0 ||
4776 num_pins > dsi->num_lanes_supported * 2) {
4777 dev_err(dsi->dev, "bad number of lanes\n");
4778 r = -EINVAL;
4779 goto err;
4780 }
4781
4782 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
4783 if (r) {
4784 dev_err(dsi->dev, "failed to read lane data\n");
4785 goto err;
4786 }
4787
4788 r = dsi_configure_pins(dsi, num_pins, lane_arr);
4789 if (r) {
4790 dev_err(dsi->dev, "failed to configure pins");
4791 goto err;
4792 }
4793
4794 of_node_put(ep);
4795
4796 return 0;
4797
4798err:
4799 of_node_put(ep);
4800 return r;
4801}
4802
4803static const struct dsi_of_data dsi_of_data_omap34xx = {
4804 .model = DSI_MODEL_OMAP3,
4805 .pll_hw = &dss_omap3_dsi_pll_hw,
4806 .modules = (const struct dsi_module_id_data[]) {
4807 { .address = 0x4804fc00, .id = 0, },
4808 { },
4809 },
4810 .max_fck_freq = 173000000,
4811 .max_pll_lpdiv = (1 << 13) - 1,
4812 .quirks = DSI_QUIRK_REVERSE_TXCLKESC,
4813};
4814
4815static const struct dsi_of_data dsi_of_data_omap36xx = {
4816 .model = DSI_MODEL_OMAP3,
4817 .pll_hw = &dss_omap3_dsi_pll_hw,
4818 .modules = (const struct dsi_module_id_data[]) {
4819 { .address = 0x4804fc00, .id = 0, },
4820 { },
4821 },
4822 .max_fck_freq = 173000000,
4823 .max_pll_lpdiv = (1 << 13) - 1,
4824 .quirks = DSI_QUIRK_PLL_PWR_BUG,
4825};
4826
4827static const struct dsi_of_data dsi_of_data_omap4 = {
4828 .model = DSI_MODEL_OMAP4,
4829 .pll_hw = &dss_omap4_dsi_pll_hw,
4830 .modules = (const struct dsi_module_id_data[]) {
4831 { .address = 0x58004000, .id = 0, },
4832 { .address = 0x58005000, .id = 1, },
4833 { },
4834 },
4835 .max_fck_freq = 170000000,
4836 .max_pll_lpdiv = (1 << 13) - 1,
4837 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
4838 | DSI_QUIRK_GNQ,
4839};
4840
4841static const struct dsi_of_data dsi_of_data_omap5 = {
4842 .model = DSI_MODEL_OMAP5,
4843 .pll_hw = &dss_omap5_dsi_pll_hw,
4844 .modules = (const struct dsi_module_id_data[]) {
4845 { .address = 0x58004000, .id = 0, },
4846 { .address = 0x58009000, .id = 1, },
4847 { },
4848 },
4849 .max_fck_freq = 209250000,
4850 .max_pll_lpdiv = (1 << 13) - 1,
4851 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
4852 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC,
4853};
4854
4855static const struct of_device_id dsi_of_match[] = {
4856 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
4857 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
4858 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
4859 {},
4860};
4861
4862static const struct soc_device_attribute dsi_soc_devices[] = {
4863 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx },
4864 { .machine = "AM35*", .data = &dsi_of_data_omap34xx },
4865 { /* sentinel */ }
4866};
4867
4868static void omap_dsi_disable_work_callback(struct work_struct *work)
4869{
4870 struct dsi_data *dsi = container_of(work, struct dsi_data, dsi_disable_work.work);
4871
4872 dsi_bus_lock(dsi);
4873
4874 if (dsi->iface_enabled && !dsi->video_enabled)
4875 dsi_disable(dsi);
4876
4877 dsi_bus_unlock(dsi);
4878}
4879
4880static int dsi_probe(struct platform_device *pdev)
4881{
4882 const struct soc_device_attribute *soc;
4883 const struct dsi_module_id_data *d;
4884 struct device *dev = &pdev->dev;
4885 struct dsi_data *dsi;
4886 struct resource *dsi_mem;
4887 struct resource *res;
4888 unsigned int i;
4889 int r;
4890
4891 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
4892 if (!dsi)
4893 return -ENOMEM;
4894
4895 dsi->dev = dev;
4896 dev_set_drvdata(dev, dsi);
4897
4898 spin_lock_init(&dsi->irq_lock);
4899 spin_lock_init(&dsi->errors_lock);
4900 dsi->errors = 0;
4901
4902#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4903 spin_lock_init(&dsi->irq_stats_lock);
4904 dsi->irq_stats.last_reset = jiffies;
4905#endif
4906
4907 mutex_init(&dsi->lock);
4908 sema_init(&dsi->bus_lock, 1);
4909
4910 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
4911 dsi_framedone_timeout_work_callback);
4912
4913 INIT_DEFERRABLE_WORK(&dsi->dsi_disable_work, omap_dsi_disable_work_callback);
4914
4915#ifdef DSI_CATCH_MISSING_TE
4916 timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
4917#endif
4918
4919 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto");
4920 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem);
4921 if (IS_ERR(dsi->proto_base))
4922 return PTR_ERR(dsi->proto_base);
4923
4924 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
4925 dsi->phy_base = devm_ioremap_resource(dev, res);
4926 if (IS_ERR(dsi->phy_base))
4927 return PTR_ERR(dsi->phy_base);
4928
4929 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
4930 dsi->pll_base = devm_ioremap_resource(dev, res);
4931 if (IS_ERR(dsi->pll_base))
4932 return PTR_ERR(dsi->pll_base);
4933
4934 dsi->irq = platform_get_irq(pdev, 0);
4935 if (dsi->irq < 0) {
4936 DSSERR("platform_get_irq failed\n");
4937 return -ENODEV;
4938 }
4939
4940 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler,
4941 IRQF_SHARED, dev_name(dev), dsi);
4942 if (r < 0) {
4943 DSSERR("request_irq failed\n");
4944 return r;
4945 }
4946
4947 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd");
4948 if (IS_ERR(dsi->vdds_dsi_reg)) {
4949 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER)
4950 DSSERR("can't get DSI VDD regulator\n");
4951 return PTR_ERR(dsi->vdds_dsi_reg);
4952 }
4953
4954 soc = soc_device_match(dsi_soc_devices);
4955 if (soc)
4956 dsi->data = soc->data;
4957 else
4958 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data;
4959
4960 d = dsi->data->modules;
4961 while (d->address != 0 && d->address != dsi_mem->start)
4962 d++;
4963
4964 if (d->address == 0) {
4965 DSSERR("unsupported DSI module\n");
4966 return -ENODEV;
4967 }
4968
4969 dsi->module_id = d->id;
4970
4971 if (dsi->data->model == DSI_MODEL_OMAP4 ||
4972 dsi->data->model == DSI_MODEL_OMAP5) {
4973 struct device_node *np;
4974
4975 /*
4976 * The OMAP4/5 display DT bindings don't reference the padconf
4977 * syscon. Our only option to retrieve it is to find it by name.
4978 */
4979 np = of_find_node_by_name(NULL,
4980 dsi->data->model == DSI_MODEL_OMAP4 ?
4981 "omap4_padconf_global" : "omap5_padconf_global");
4982 if (!np)
4983 return -ENODEV;
4984
4985 dsi->syscon = syscon_node_to_regmap(np);
4986 of_node_put(np);
4987 }
4988
4989 /* DSI VCs initialization */
4990 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++)
4991 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4992
4993 r = dsi_get_clocks(dsi);
4994 if (r)
4995 return r;
4996
4997 pm_runtime_enable(dev);
4998
4999 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5000 * of data to 3 by default */
5001 if (dsi->data->quirks & DSI_QUIRK_GNQ) {
5002 dsi_runtime_get(dsi);
5003 /* NB_DATA_LANES */
5004 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9);
5005 dsi_runtime_put(dsi);
5006 } else {
5007 dsi->num_lanes_supported = 3;
5008 }
5009
5010 dsi->host.ops = &omap_dsi_host_ops;
5011 dsi->host.dev = &pdev->dev;
5012
5013 r = dsi_probe_of(dsi);
5014 if (r) {
5015 DSSERR("Invalid DSI DT data\n");
5016 goto err_pm_disable;
5017 }
5018
5019 r = mipi_dsi_host_register(&dsi->host);
5020 if (r < 0) {
5021 dev_err(&pdev->dev, "failed to register DSI host: %d\n", r);
5022 goto err_pm_disable;
5023 }
5024
5025 r = dsi_init_output(dsi);
5026 if (r)
5027 goto err_dsi_host_unregister;
5028
5029 r = component_add(&pdev->dev, &dsi_component_ops);
5030 if (r)
5031 goto err_uninit_output;
5032
5033 return 0;
5034
5035err_uninit_output:
5036 dsi_uninit_output(dsi);
5037err_dsi_host_unregister:
5038 mipi_dsi_host_unregister(&dsi->host);
5039err_pm_disable:
5040 pm_runtime_disable(dev);
5041 return r;
5042}
5043
5044static int dsi_remove(struct platform_device *pdev)
5045{
5046 struct dsi_data *dsi = platform_get_drvdata(pdev);
5047
5048 component_del(&pdev->dev, &dsi_component_ops);
5049
5050 dsi_uninit_output(dsi);
5051
5052 mipi_dsi_host_unregister(&dsi->host);
5053
5054 pm_runtime_disable(&pdev->dev);
5055
5056 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5057 regulator_disable(dsi->vdds_dsi_reg);
5058 dsi->vdds_dsi_enabled = false;
5059 }
5060
5061 return 0;
5062}
5063
5064static int dsi_runtime_suspend(struct device *dev)
5065{
5066 struct dsi_data *dsi = dev_get_drvdata(dev);
5067
5068 dsi->is_enabled = false;
5069 /* ensure the irq handler sees the is_enabled value */
5070 smp_wmb();
5071 /* wait for current handler to finish before turning the DSI off */
5072 synchronize_irq(dsi->irq);
5073
5074 return 0;
5075}
5076
5077static int dsi_runtime_resume(struct device *dev)
5078{
5079 struct dsi_data *dsi = dev_get_drvdata(dev);
5080
5081 dsi->is_enabled = true;
5082 /* ensure the irq handler sees the is_enabled value */
5083 smp_wmb();
5084
5085 return 0;
5086}
5087
5088static const struct dev_pm_ops dsi_pm_ops = {
5089 .runtime_suspend = dsi_runtime_suspend,
5090 .runtime_resume = dsi_runtime_resume,
5091 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
5092};
5093
5094struct platform_driver omap_dsihw_driver = {
5095 .probe = dsi_probe,
5096 .remove = dsi_remove,
5097 .driver = {
5098 .name = "omapdss_dsi",
5099 .pm = &dsi_pm_ops,
5100 .of_match_table = dsi_of_match,
5101 .suppress_bind_attrs = true,
5102 },
5103};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 */
6
7#define DSS_SUBSYS_NAME "DSI"
8
9#include <linux/kernel.h>
10#include <linux/mfd/syscon.h>
11#include <linux/regmap.h>
12#include <linux/io.h>
13#include <linux/clk.h>
14#include <linux/device.h>
15#include <linux/err.h>
16#include <linux/interrupt.h>
17#include <linux/delay.h>
18#include <linux/mutex.h>
19#include <linux/module.h>
20#include <linux/semaphore.h>
21#include <linux/seq_file.h>
22#include <linux/platform_device.h>
23#include <linux/regulator/consumer.h>
24#include <linux/wait.h>
25#include <linux/workqueue.h>
26#include <linux/sched.h>
27#include <linux/slab.h>
28#include <linux/debugfs.h>
29#include <linux/pm_runtime.h>
30#include <linux/of.h>
31#include <linux/of_graph.h>
32#include <linux/of_platform.h>
33#include <linux/component.h>
34#include <linux/sys_soc.h>
35
36#include <video/mipi_display.h>
37
38#include "omapdss.h"
39#include "dss.h"
40
41#define DSI_CATCH_MISSING_TE
42
43struct dsi_reg { u16 module; u16 idx; };
44
45#define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
46
47/* DSI Protocol Engine */
48
49#define DSI_PROTO 0
50#define DSI_PROTO_SZ 0x200
51
52#define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
53#define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
54#define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
55#define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
56#define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
57#define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
58#define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
59#define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
60#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
61#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
62#define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
63#define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
64#define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
65#define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
66#define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
67#define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
68#define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
69#define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
70#define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
71#define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
72#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
73#define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
74#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
75#define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
76#define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
77#define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
78#define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
79#define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
80#define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
81#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
82#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
83#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
84#define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
85#define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
86
87/* DSIPHY_SCP */
88
89#define DSI_PHY 1
90#define DSI_PHY_OFFSET 0x200
91#define DSI_PHY_SZ 0x40
92
93#define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
94#define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
95#define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
96#define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
97#define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
98
99/* DSI_PLL_CTRL_SCP */
100
101#define DSI_PLL 2
102#define DSI_PLL_OFFSET 0x300
103#define DSI_PLL_SZ 0x20
104
105#define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
106#define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
107#define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
108#define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
109#define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
110
111#define REG_GET(dsi, idx, start, end) \
112 FLD_GET(dsi_read_reg(dsi, idx), start, end)
113
114#define REG_FLD_MOD(dsi, idx, val, start, end) \
115 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
116
117/* Global interrupts */
118#define DSI_IRQ_VC0 (1 << 0)
119#define DSI_IRQ_VC1 (1 << 1)
120#define DSI_IRQ_VC2 (1 << 2)
121#define DSI_IRQ_VC3 (1 << 3)
122#define DSI_IRQ_WAKEUP (1 << 4)
123#define DSI_IRQ_RESYNC (1 << 5)
124#define DSI_IRQ_PLL_LOCK (1 << 7)
125#define DSI_IRQ_PLL_UNLOCK (1 << 8)
126#define DSI_IRQ_PLL_RECALL (1 << 9)
127#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
128#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
129#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
130#define DSI_IRQ_TE_TRIGGER (1 << 16)
131#define DSI_IRQ_ACK_TRIGGER (1 << 17)
132#define DSI_IRQ_SYNC_LOST (1 << 18)
133#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
134#define DSI_IRQ_TA_TIMEOUT (1 << 20)
135#define DSI_IRQ_ERROR_MASK \
136 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
137 DSI_IRQ_TA_TIMEOUT)
138#define DSI_IRQ_CHANNEL_MASK 0xf
139
140/* Virtual channel interrupts */
141#define DSI_VC_IRQ_CS (1 << 0)
142#define DSI_VC_IRQ_ECC_CORR (1 << 1)
143#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
144#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
145#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
146#define DSI_VC_IRQ_BTA (1 << 5)
147#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
148#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
149#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
150#define DSI_VC_IRQ_ERROR_MASK \
151 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
152 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
153 DSI_VC_IRQ_FIFO_TX_UDF)
154
155/* ComplexIO interrupts */
156#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
157#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
158#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
159#define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
160#define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
161#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
162#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
163#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
164#define DSI_CIO_IRQ_ERRESC4 (1 << 8)
165#define DSI_CIO_IRQ_ERRESC5 (1 << 9)
166#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
167#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
168#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
169#define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
170#define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
171#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
172#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
173#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
174#define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
175#define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
176#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
177#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
178#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
179#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
180#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
181#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
182#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
183#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
184#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
185#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
186#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
187#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
188#define DSI_CIO_IRQ_ERROR_MASK \
189 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
190 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
191 DSI_CIO_IRQ_ERRSYNCESC5 | \
192 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
193 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
194 DSI_CIO_IRQ_ERRESC5 | \
195 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
196 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
197 DSI_CIO_IRQ_ERRCONTROL5 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
202 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
203
204typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
205struct dsi_data;
206
207static int dsi_display_init_dispc(struct dsi_data *dsi);
208static void dsi_display_uninit_dispc(struct dsi_data *dsi);
209
210static int dsi_vc_send_null(struct dsi_data *dsi, int channel);
211
212/* DSI PLL HSDIV indices */
213#define HSDIV_DISPC 0
214#define HSDIV_DSI 1
215
216#define DSI_MAX_NR_ISRS 2
217#define DSI_MAX_NR_LANES 5
218
219enum dsi_model {
220 DSI_MODEL_OMAP3,
221 DSI_MODEL_OMAP4,
222 DSI_MODEL_OMAP5,
223};
224
225enum dsi_lane_function {
226 DSI_LANE_UNUSED = 0,
227 DSI_LANE_CLK,
228 DSI_LANE_DATA1,
229 DSI_LANE_DATA2,
230 DSI_LANE_DATA3,
231 DSI_LANE_DATA4,
232};
233
234struct dsi_lane_config {
235 enum dsi_lane_function function;
236 u8 polarity;
237};
238
239struct dsi_isr_data {
240 omap_dsi_isr_t isr;
241 void *arg;
242 u32 mask;
243};
244
245enum fifo_size {
246 DSI_FIFO_SIZE_0 = 0,
247 DSI_FIFO_SIZE_32 = 1,
248 DSI_FIFO_SIZE_64 = 2,
249 DSI_FIFO_SIZE_96 = 3,
250 DSI_FIFO_SIZE_128 = 4,
251};
252
253enum dsi_vc_source {
254 DSI_VC_SOURCE_L4 = 0,
255 DSI_VC_SOURCE_VP,
256};
257
258struct dsi_irq_stats {
259 unsigned long last_reset;
260 unsigned int irq_count;
261 unsigned int dsi_irqs[32];
262 unsigned int vc_irqs[4][32];
263 unsigned int cio_irqs[32];
264};
265
266struct dsi_isr_tables {
267 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
268 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
269 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
270};
271
272struct dsi_clk_calc_ctx {
273 struct dsi_data *dsi;
274 struct dss_pll *pll;
275
276 /* inputs */
277
278 const struct omap_dss_dsi_config *config;
279
280 unsigned long req_pck_min, req_pck_nom, req_pck_max;
281
282 /* outputs */
283
284 struct dss_pll_clock_info dsi_cinfo;
285 struct dispc_clock_info dispc_cinfo;
286
287 struct videomode vm;
288 struct omap_dss_dsi_videomode_timings dsi_vm;
289};
290
291struct dsi_lp_clock_info {
292 unsigned long lp_clk;
293 u16 lp_clk_div;
294};
295
296struct dsi_module_id_data {
297 u32 address;
298 int id;
299};
300
301enum dsi_quirks {
302 DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */
303 DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1),
304 DSI_QUIRK_VC_OCP_WIDTH = (1 << 2),
305 DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3),
306 DSI_QUIRK_GNQ = (1 << 4),
307 DSI_QUIRK_PHY_DCC = (1 << 5),
308};
309
310struct dsi_of_data {
311 enum dsi_model model;
312 const struct dss_pll_hw *pll_hw;
313 const struct dsi_module_id_data *modules;
314 unsigned int max_fck_freq;
315 unsigned int max_pll_lpdiv;
316 enum dsi_quirks quirks;
317};
318
319struct dsi_data {
320 struct device *dev;
321 void __iomem *proto_base;
322 void __iomem *phy_base;
323 void __iomem *pll_base;
324
325 const struct dsi_of_data *data;
326 int module_id;
327
328 int irq;
329
330 bool is_enabled;
331
332 struct clk *dss_clk;
333 struct regmap *syscon;
334 struct dss_device *dss;
335
336 struct dispc_clock_info user_dispc_cinfo;
337 struct dss_pll_clock_info user_dsi_cinfo;
338
339 struct dsi_lp_clock_info user_lp_cinfo;
340 struct dsi_lp_clock_info current_lp_cinfo;
341
342 struct dss_pll pll;
343
344 bool vdds_dsi_enabled;
345 struct regulator *vdds_dsi_reg;
346
347 struct {
348 enum dsi_vc_source source;
349 struct omap_dss_device *dssdev;
350 enum fifo_size tx_fifo_size;
351 enum fifo_size rx_fifo_size;
352 int vc_id;
353 } vc[4];
354
355 struct mutex lock;
356 struct semaphore bus_lock;
357
358 spinlock_t irq_lock;
359 struct dsi_isr_tables isr_tables;
360 /* space for a copy used by the interrupt handler */
361 struct dsi_isr_tables isr_tables_copy;
362
363 int update_channel;
364#ifdef DSI_PERF_MEASURE
365 unsigned int update_bytes;
366#endif
367
368 bool te_enabled;
369 bool ulps_enabled;
370
371 void (*framedone_callback)(int, void *);
372 void *framedone_data;
373
374 struct delayed_work framedone_timeout_work;
375
376#ifdef DSI_CATCH_MISSING_TE
377 struct timer_list te_timer;
378#endif
379
380 unsigned long cache_req_pck;
381 unsigned long cache_clk_freq;
382 struct dss_pll_clock_info cache_cinfo;
383
384 u32 errors;
385 spinlock_t errors_lock;
386#ifdef DSI_PERF_MEASURE
387 ktime_t perf_setup_time;
388 ktime_t perf_start_time;
389#endif
390 int debug_read;
391 int debug_write;
392 struct {
393 struct dss_debugfs_entry *irqs;
394 struct dss_debugfs_entry *regs;
395 struct dss_debugfs_entry *clks;
396 } debugfs;
397
398#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
399 spinlock_t irq_stats_lock;
400 struct dsi_irq_stats irq_stats;
401#endif
402
403 unsigned int num_lanes_supported;
404 unsigned int line_buffer_size;
405
406 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
407 unsigned int num_lanes_used;
408
409 unsigned int scp_clk_refcount;
410
411 struct dss_lcd_mgr_config mgr_config;
412 struct videomode vm;
413 enum omap_dss_dsi_pixel_format pix_fmt;
414 enum omap_dss_dsi_mode mode;
415 struct omap_dss_dsi_videomode_timings vm_timings;
416
417 struct omap_dss_device output;
418};
419
420struct dsi_packet_sent_handler_data {
421 struct dsi_data *dsi;
422 struct completion *completion;
423};
424
425#ifdef DSI_PERF_MEASURE
426static bool dsi_perf;
427module_param(dsi_perf, bool, 0644);
428#endif
429
430static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev)
431{
432 return dev_get_drvdata(dssdev->dev);
433}
434
435static inline void dsi_write_reg(struct dsi_data *dsi,
436 const struct dsi_reg idx, u32 val)
437{
438 void __iomem *base;
439
440 switch(idx.module) {
441 case DSI_PROTO: base = dsi->proto_base; break;
442 case DSI_PHY: base = dsi->phy_base; break;
443 case DSI_PLL: base = dsi->pll_base; break;
444 default: return;
445 }
446
447 __raw_writel(val, base + idx.idx);
448}
449
450static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx)
451{
452 void __iomem *base;
453
454 switch(idx.module) {
455 case DSI_PROTO: base = dsi->proto_base; break;
456 case DSI_PHY: base = dsi->phy_base; break;
457 case DSI_PLL: base = dsi->pll_base; break;
458 default: return 0;
459 }
460
461 return __raw_readl(base + idx.idx);
462}
463
464static void dsi_bus_lock(struct omap_dss_device *dssdev)
465{
466 struct dsi_data *dsi = to_dsi_data(dssdev);
467
468 down(&dsi->bus_lock);
469}
470
471static void dsi_bus_unlock(struct omap_dss_device *dssdev)
472{
473 struct dsi_data *dsi = to_dsi_data(dssdev);
474
475 up(&dsi->bus_lock);
476}
477
478static bool dsi_bus_is_locked(struct dsi_data *dsi)
479{
480 return dsi->bus_lock.count == 0;
481}
482
483static void dsi_completion_handler(void *data, u32 mask)
484{
485 complete((struct completion *)data);
486}
487
488static inline bool wait_for_bit_change(struct dsi_data *dsi,
489 const struct dsi_reg idx,
490 int bitnum, int value)
491{
492 unsigned long timeout;
493 ktime_t wait;
494 int t;
495
496 /* first busyloop to see if the bit changes right away */
497 t = 100;
498 while (t-- > 0) {
499 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
500 return true;
501 }
502
503 /* then loop for 500ms, sleeping for 1ms in between */
504 timeout = jiffies + msecs_to_jiffies(500);
505 while (time_before(jiffies, timeout)) {
506 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
507 return true;
508
509 wait = ns_to_ktime(1000 * 1000);
510 set_current_state(TASK_UNINTERRUPTIBLE);
511 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
512 }
513
514 return false;
515}
516
517static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
518{
519 switch (fmt) {
520 case OMAP_DSS_DSI_FMT_RGB888:
521 case OMAP_DSS_DSI_FMT_RGB666:
522 return 24;
523 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
524 return 18;
525 case OMAP_DSS_DSI_FMT_RGB565:
526 return 16;
527 default:
528 BUG();
529 return 0;
530 }
531}
532
533#ifdef DSI_PERF_MEASURE
534static void dsi_perf_mark_setup(struct dsi_data *dsi)
535{
536 dsi->perf_setup_time = ktime_get();
537}
538
539static void dsi_perf_mark_start(struct dsi_data *dsi)
540{
541 dsi->perf_start_time = ktime_get();
542}
543
544static void dsi_perf_show(struct dsi_data *dsi, const char *name)
545{
546 ktime_t t, setup_time, trans_time;
547 u32 total_bytes;
548 u32 setup_us, trans_us, total_us;
549
550 if (!dsi_perf)
551 return;
552
553 t = ktime_get();
554
555 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
556 setup_us = (u32)ktime_to_us(setup_time);
557 if (setup_us == 0)
558 setup_us = 1;
559
560 trans_time = ktime_sub(t, dsi->perf_start_time);
561 trans_us = (u32)ktime_to_us(trans_time);
562 if (trans_us == 0)
563 trans_us = 1;
564
565 total_us = setup_us + trans_us;
566
567 total_bytes = dsi->update_bytes;
568
569 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n",
570 name,
571 setup_us,
572 trans_us,
573 total_us,
574 1000 * 1000 / total_us,
575 total_bytes,
576 total_bytes * 1000 / total_us);
577}
578#else
579static inline void dsi_perf_mark_setup(struct dsi_data *dsi)
580{
581}
582
583static inline void dsi_perf_mark_start(struct dsi_data *dsi)
584{
585}
586
587static inline void dsi_perf_show(struct dsi_data *dsi, const char *name)
588{
589}
590#endif
591
592static int verbose_irq;
593
594static void print_irq_status(u32 status)
595{
596 if (status == 0)
597 return;
598
599 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
600 return;
601
602#define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
603
604 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
605 status,
606 verbose_irq ? PIS(VC0) : "",
607 verbose_irq ? PIS(VC1) : "",
608 verbose_irq ? PIS(VC2) : "",
609 verbose_irq ? PIS(VC3) : "",
610 PIS(WAKEUP),
611 PIS(RESYNC),
612 PIS(PLL_LOCK),
613 PIS(PLL_UNLOCK),
614 PIS(PLL_RECALL),
615 PIS(COMPLEXIO_ERR),
616 PIS(HS_TX_TIMEOUT),
617 PIS(LP_RX_TIMEOUT),
618 PIS(TE_TRIGGER),
619 PIS(ACK_TRIGGER),
620 PIS(SYNC_LOST),
621 PIS(LDO_POWER_GOOD),
622 PIS(TA_TIMEOUT));
623#undef PIS
624}
625
626static void print_irq_status_vc(int channel, u32 status)
627{
628 if (status == 0)
629 return;
630
631 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
632 return;
633
634#define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
635
636 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
637 channel,
638 status,
639 PIS(CS),
640 PIS(ECC_CORR),
641 PIS(ECC_NO_CORR),
642 verbose_irq ? PIS(PACKET_SENT) : "",
643 PIS(BTA),
644 PIS(FIFO_TX_OVF),
645 PIS(FIFO_RX_OVF),
646 PIS(FIFO_TX_UDF),
647 PIS(PP_BUSY_CHANGE));
648#undef PIS
649}
650
651static void print_irq_status_cio(u32 status)
652{
653 if (status == 0)
654 return;
655
656#define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
657
658 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
659 status,
660 PIS(ERRSYNCESC1),
661 PIS(ERRSYNCESC2),
662 PIS(ERRSYNCESC3),
663 PIS(ERRESC1),
664 PIS(ERRESC2),
665 PIS(ERRESC3),
666 PIS(ERRCONTROL1),
667 PIS(ERRCONTROL2),
668 PIS(ERRCONTROL3),
669 PIS(STATEULPS1),
670 PIS(STATEULPS2),
671 PIS(STATEULPS3),
672 PIS(ERRCONTENTIONLP0_1),
673 PIS(ERRCONTENTIONLP1_1),
674 PIS(ERRCONTENTIONLP0_2),
675 PIS(ERRCONTENTIONLP1_2),
676 PIS(ERRCONTENTIONLP0_3),
677 PIS(ERRCONTENTIONLP1_3),
678 PIS(ULPSACTIVENOT_ALL0),
679 PIS(ULPSACTIVENOT_ALL1));
680#undef PIS
681}
682
683#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
684static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus,
685 u32 *vcstatus, u32 ciostatus)
686{
687 int i;
688
689 spin_lock(&dsi->irq_stats_lock);
690
691 dsi->irq_stats.irq_count++;
692 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
693
694 for (i = 0; i < 4; ++i)
695 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
696
697 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
698
699 spin_unlock(&dsi->irq_stats_lock);
700}
701#else
702#define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus)
703#endif
704
705static int debug_irq;
706
707static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus,
708 u32 *vcstatus, u32 ciostatus)
709{
710 int i;
711
712 if (irqstatus & DSI_IRQ_ERROR_MASK) {
713 DSSERR("DSI error, irqstatus %x\n", irqstatus);
714 print_irq_status(irqstatus);
715 spin_lock(&dsi->errors_lock);
716 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
717 spin_unlock(&dsi->errors_lock);
718 } else if (debug_irq) {
719 print_irq_status(irqstatus);
720 }
721
722 for (i = 0; i < 4; ++i) {
723 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
724 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
725 i, vcstatus[i]);
726 print_irq_status_vc(i, vcstatus[i]);
727 } else if (debug_irq) {
728 print_irq_status_vc(i, vcstatus[i]);
729 }
730 }
731
732 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
733 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
734 print_irq_status_cio(ciostatus);
735 } else if (debug_irq) {
736 print_irq_status_cio(ciostatus);
737 }
738}
739
740static void dsi_call_isrs(struct dsi_isr_data *isr_array,
741 unsigned int isr_array_size, u32 irqstatus)
742{
743 struct dsi_isr_data *isr_data;
744 int i;
745
746 for (i = 0; i < isr_array_size; i++) {
747 isr_data = &isr_array[i];
748 if (isr_data->isr && isr_data->mask & irqstatus)
749 isr_data->isr(isr_data->arg, irqstatus);
750 }
751}
752
753static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
754 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
755{
756 int i;
757
758 dsi_call_isrs(isr_tables->isr_table,
759 ARRAY_SIZE(isr_tables->isr_table),
760 irqstatus);
761
762 for (i = 0; i < 4; ++i) {
763 if (vcstatus[i] == 0)
764 continue;
765 dsi_call_isrs(isr_tables->isr_table_vc[i],
766 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
767 vcstatus[i]);
768 }
769
770 if (ciostatus != 0)
771 dsi_call_isrs(isr_tables->isr_table_cio,
772 ARRAY_SIZE(isr_tables->isr_table_cio),
773 ciostatus);
774}
775
776static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
777{
778 struct dsi_data *dsi = arg;
779 u32 irqstatus, vcstatus[4], ciostatus;
780 int i;
781
782 if (!dsi->is_enabled)
783 return IRQ_NONE;
784
785 spin_lock(&dsi->irq_lock);
786
787 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS);
788
789 /* IRQ is not for us */
790 if (!irqstatus) {
791 spin_unlock(&dsi->irq_lock);
792 return IRQ_NONE;
793 }
794
795 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
796 /* flush posted write */
797 dsi_read_reg(dsi, DSI_IRQSTATUS);
798
799 for (i = 0; i < 4; ++i) {
800 if ((irqstatus & (1 << i)) == 0) {
801 vcstatus[i] = 0;
802 continue;
803 }
804
805 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
806
807 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]);
808 /* flush posted write */
809 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
810 }
811
812 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
813 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
814
815 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
816 /* flush posted write */
817 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
818 } else {
819 ciostatus = 0;
820 }
821
822#ifdef DSI_CATCH_MISSING_TE
823 if (irqstatus & DSI_IRQ_TE_TRIGGER)
824 del_timer(&dsi->te_timer);
825#endif
826
827 /* make a copy and unlock, so that isrs can unregister
828 * themselves */
829 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
830 sizeof(dsi->isr_tables));
831
832 spin_unlock(&dsi->irq_lock);
833
834 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
835
836 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus);
837
838 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus);
839
840 return IRQ_HANDLED;
841}
842
843/* dsi->irq_lock has to be locked by the caller */
844static void _omap_dsi_configure_irqs(struct dsi_data *dsi,
845 struct dsi_isr_data *isr_array,
846 unsigned int isr_array_size,
847 u32 default_mask,
848 const struct dsi_reg enable_reg,
849 const struct dsi_reg status_reg)
850{
851 struct dsi_isr_data *isr_data;
852 u32 mask;
853 u32 old_mask;
854 int i;
855
856 mask = default_mask;
857
858 for (i = 0; i < isr_array_size; i++) {
859 isr_data = &isr_array[i];
860
861 if (isr_data->isr == NULL)
862 continue;
863
864 mask |= isr_data->mask;
865 }
866
867 old_mask = dsi_read_reg(dsi, enable_reg);
868 /* clear the irqstatus for newly enabled irqs */
869 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask);
870 dsi_write_reg(dsi, enable_reg, mask);
871
872 /* flush posted writes */
873 dsi_read_reg(dsi, enable_reg);
874 dsi_read_reg(dsi, status_reg);
875}
876
877/* dsi->irq_lock has to be locked by the caller */
878static void _omap_dsi_set_irqs(struct dsi_data *dsi)
879{
880 u32 mask = DSI_IRQ_ERROR_MASK;
881#ifdef DSI_CATCH_MISSING_TE
882 mask |= DSI_IRQ_TE_TRIGGER;
883#endif
884 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table,
885 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
886 DSI_IRQENABLE, DSI_IRQSTATUS);
887}
888
889/* dsi->irq_lock has to be locked by the caller */
890static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc)
891{
892 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc],
893 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
894 DSI_VC_IRQ_ERROR_MASK,
895 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
896}
897
898/* dsi->irq_lock has to be locked by the caller */
899static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi)
900{
901 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio,
902 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
903 DSI_CIO_IRQ_ERROR_MASK,
904 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
905}
906
907static void _dsi_initialize_irq(struct dsi_data *dsi)
908{
909 unsigned long flags;
910 int vc;
911
912 spin_lock_irqsave(&dsi->irq_lock, flags);
913
914 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
915
916 _omap_dsi_set_irqs(dsi);
917 for (vc = 0; vc < 4; ++vc)
918 _omap_dsi_set_irqs_vc(dsi, vc);
919 _omap_dsi_set_irqs_cio(dsi);
920
921 spin_unlock_irqrestore(&dsi->irq_lock, flags);
922}
923
924static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
925 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
926{
927 struct dsi_isr_data *isr_data;
928 int free_idx;
929 int i;
930
931 BUG_ON(isr == NULL);
932
933 /* check for duplicate entry and find a free slot */
934 free_idx = -1;
935 for (i = 0; i < isr_array_size; i++) {
936 isr_data = &isr_array[i];
937
938 if (isr_data->isr == isr && isr_data->arg == arg &&
939 isr_data->mask == mask) {
940 return -EINVAL;
941 }
942
943 if (isr_data->isr == NULL && free_idx == -1)
944 free_idx = i;
945 }
946
947 if (free_idx == -1)
948 return -EBUSY;
949
950 isr_data = &isr_array[free_idx];
951 isr_data->isr = isr;
952 isr_data->arg = arg;
953 isr_data->mask = mask;
954
955 return 0;
956}
957
958static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
959 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
960{
961 struct dsi_isr_data *isr_data;
962 int i;
963
964 for (i = 0; i < isr_array_size; i++) {
965 isr_data = &isr_array[i];
966 if (isr_data->isr != isr || isr_data->arg != arg ||
967 isr_data->mask != mask)
968 continue;
969
970 isr_data->isr = NULL;
971 isr_data->arg = NULL;
972 isr_data->mask = 0;
973
974 return 0;
975 }
976
977 return -EINVAL;
978}
979
980static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
981 void *arg, u32 mask)
982{
983 unsigned long flags;
984 int r;
985
986 spin_lock_irqsave(&dsi->irq_lock, flags);
987
988 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
989 ARRAY_SIZE(dsi->isr_tables.isr_table));
990
991 if (r == 0)
992 _omap_dsi_set_irqs(dsi);
993
994 spin_unlock_irqrestore(&dsi->irq_lock, flags);
995
996 return r;
997}
998
999static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
1000 void *arg, u32 mask)
1001{
1002 unsigned long flags;
1003 int r;
1004
1005 spin_lock_irqsave(&dsi->irq_lock, flags);
1006
1007 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1008 ARRAY_SIZE(dsi->isr_tables.isr_table));
1009
1010 if (r == 0)
1011 _omap_dsi_set_irqs(dsi);
1012
1013 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1014
1015 return r;
1016}
1017
1018static int dsi_register_isr_vc(struct dsi_data *dsi, int channel,
1019 omap_dsi_isr_t isr, void *arg, u32 mask)
1020{
1021 unsigned long flags;
1022 int r;
1023
1024 spin_lock_irqsave(&dsi->irq_lock, flags);
1025
1026 r = _dsi_register_isr(isr, arg, mask,
1027 dsi->isr_tables.isr_table_vc[channel],
1028 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1029
1030 if (r == 0)
1031 _omap_dsi_set_irqs_vc(dsi, channel);
1032
1033 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1034
1035 return r;
1036}
1037
1038static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel,
1039 omap_dsi_isr_t isr, void *arg, u32 mask)
1040{
1041 unsigned long flags;
1042 int r;
1043
1044 spin_lock_irqsave(&dsi->irq_lock, flags);
1045
1046 r = _dsi_unregister_isr(isr, arg, mask,
1047 dsi->isr_tables.isr_table_vc[channel],
1048 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1049
1050 if (r == 0)
1051 _omap_dsi_set_irqs_vc(dsi, channel);
1052
1053 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1054
1055 return r;
1056}
1057
1058static int dsi_register_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1059 void *arg, u32 mask)
1060{
1061 unsigned long flags;
1062 int r;
1063
1064 spin_lock_irqsave(&dsi->irq_lock, flags);
1065
1066 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1067 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1068
1069 if (r == 0)
1070 _omap_dsi_set_irqs_cio(dsi);
1071
1072 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1073
1074 return r;
1075}
1076
1077static int dsi_unregister_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1078 void *arg, u32 mask)
1079{
1080 unsigned long flags;
1081 int r;
1082
1083 spin_lock_irqsave(&dsi->irq_lock, flags);
1084
1085 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1086 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1087
1088 if (r == 0)
1089 _omap_dsi_set_irqs_cio(dsi);
1090
1091 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1092
1093 return r;
1094}
1095
1096static u32 dsi_get_errors(struct dsi_data *dsi)
1097{
1098 unsigned long flags;
1099 u32 e;
1100
1101 spin_lock_irqsave(&dsi->errors_lock, flags);
1102 e = dsi->errors;
1103 dsi->errors = 0;
1104 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1105 return e;
1106}
1107
1108static int dsi_runtime_get(struct dsi_data *dsi)
1109{
1110 int r;
1111
1112 DSSDBG("dsi_runtime_get\n");
1113
1114 r = pm_runtime_get_sync(dsi->dev);
1115 WARN_ON(r < 0);
1116 return r < 0 ? r : 0;
1117}
1118
1119static void dsi_runtime_put(struct dsi_data *dsi)
1120{
1121 int r;
1122
1123 DSSDBG("dsi_runtime_put\n");
1124
1125 r = pm_runtime_put_sync(dsi->dev);
1126 WARN_ON(r < 0 && r != -ENOSYS);
1127}
1128
1129static void _dsi_print_reset_status(struct dsi_data *dsi)
1130{
1131 u32 l;
1132 int b0, b1, b2;
1133
1134 /* A dummy read using the SCP interface to any DSIPHY register is
1135 * required after DSIPHY reset to complete the reset of the DSI complex
1136 * I/O. */
1137 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1138
1139 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
1140 b0 = 28;
1141 b1 = 27;
1142 b2 = 26;
1143 } else {
1144 b0 = 24;
1145 b1 = 25;
1146 b2 = 26;
1147 }
1148
1149#define DSI_FLD_GET(fld, start, end)\
1150 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end)
1151
1152 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1153 DSI_FLD_GET(PLL_STATUS, 0, 0),
1154 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1155 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1156 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1157 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1158 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1159 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1160 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1161
1162#undef DSI_FLD_GET
1163}
1164
1165static inline int dsi_if_enable(struct dsi_data *dsi, bool enable)
1166{
1167 DSSDBG("dsi_if_enable(%d)\n", enable);
1168
1169 enable = enable ? 1 : 0;
1170 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */
1171
1172 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) {
1173 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1174 return -EIO;
1175 }
1176
1177 return 0;
1178}
1179
1180static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi)
1181{
1182 return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1183}
1184
1185static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi)
1186{
1187 return dsi->pll.cinfo.clkout[HSDIV_DSI];
1188}
1189
1190static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi)
1191{
1192 return dsi->pll.cinfo.clkdco / 16;
1193}
1194
1195static unsigned long dsi_fclk_rate(struct dsi_data *dsi)
1196{
1197 unsigned long r;
1198 enum dss_clk_source source;
1199
1200 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id);
1201 if (source == DSS_CLK_SRC_FCK) {
1202 /* DSI FCLK source is DSS_CLK_FCK */
1203 r = clk_get_rate(dsi->dss_clk);
1204 } else {
1205 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1206 r = dsi_get_pll_hsdiv_dsi_rate(dsi);
1207 }
1208
1209 return r;
1210}
1211
1212static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1213 unsigned long lp_clk_min, unsigned long lp_clk_max,
1214 struct dsi_lp_clock_info *lp_cinfo)
1215{
1216 unsigned int lp_clk_div;
1217 unsigned long lp_clk;
1218
1219 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1220 lp_clk = dsi_fclk / 2 / lp_clk_div;
1221
1222 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1223 return -EINVAL;
1224
1225 lp_cinfo->lp_clk_div = lp_clk_div;
1226 lp_cinfo->lp_clk = lp_clk;
1227
1228 return 0;
1229}
1230
1231static int dsi_set_lp_clk_divisor(struct dsi_data *dsi)
1232{
1233 unsigned long dsi_fclk;
1234 unsigned int lp_clk_div;
1235 unsigned long lp_clk;
1236 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv;
1237
1238
1239 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1240
1241 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1242 return -EINVAL;
1243
1244 dsi_fclk = dsi_fclk_rate(dsi);
1245
1246 lp_clk = dsi_fclk / 2 / lp_clk_div;
1247
1248 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1249 dsi->current_lp_cinfo.lp_clk = lp_clk;
1250 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1251
1252 /* LP_CLK_DIVISOR */
1253 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1254
1255 /* LP_RX_SYNCHRO_ENABLE */
1256 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1257
1258 return 0;
1259}
1260
1261static void dsi_enable_scp_clk(struct dsi_data *dsi)
1262{
1263 if (dsi->scp_clk_refcount++ == 0)
1264 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1265}
1266
1267static void dsi_disable_scp_clk(struct dsi_data *dsi)
1268{
1269 WARN_ON(dsi->scp_clk_refcount == 0);
1270 if (--dsi->scp_clk_refcount == 0)
1271 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1272}
1273
1274enum dsi_pll_power_state {
1275 DSI_PLL_POWER_OFF = 0x0,
1276 DSI_PLL_POWER_ON_HSCLK = 0x1,
1277 DSI_PLL_POWER_ON_ALL = 0x2,
1278 DSI_PLL_POWER_ON_DIV = 0x3,
1279};
1280
1281static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state)
1282{
1283 int t = 0;
1284
1285 /* DSI-PLL power command 0x3 is not working */
1286 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) &&
1287 state == DSI_PLL_POWER_ON_DIV)
1288 state = DSI_PLL_POWER_ON_ALL;
1289
1290 /* PLL_PWR_CMD */
1291 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30);
1292
1293 /* PLL_PWR_STATUS */
1294 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) {
1295 if (++t > 1000) {
1296 DSSERR("Failed to set DSI PLL power mode to %d\n",
1297 state);
1298 return -ENODEV;
1299 }
1300 udelay(1);
1301 }
1302
1303 return 0;
1304}
1305
1306
1307static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi,
1308 struct dss_pll_clock_info *cinfo)
1309{
1310 unsigned long max_dsi_fck;
1311
1312 max_dsi_fck = dsi->data->max_fck_freq;
1313
1314 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1315 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1316}
1317
1318static int dsi_pll_enable(struct dss_pll *pll)
1319{
1320 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1321 int r = 0;
1322
1323 DSSDBG("PLL init\n");
1324
1325 r = dsi_runtime_get(dsi);
1326 if (r)
1327 return r;
1328
1329 /*
1330 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1331 */
1332 dsi_enable_scp_clk(dsi);
1333
1334 r = regulator_enable(dsi->vdds_dsi_reg);
1335 if (r)
1336 goto err0;
1337
1338 /* XXX PLL does not come out of reset without this... */
1339 dispc_pck_free_enable(dsi->dss->dispc, 1);
1340
1341 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) {
1342 DSSERR("PLL not coming out of reset.\n");
1343 r = -ENODEV;
1344 dispc_pck_free_enable(dsi->dss->dispc, 0);
1345 goto err1;
1346 }
1347
1348 /* XXX ... but if left on, we get problems when planes do not
1349 * fill the whole display. No idea about this */
1350 dispc_pck_free_enable(dsi->dss->dispc, 0);
1351
1352 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL);
1353
1354 if (r)
1355 goto err1;
1356
1357 DSSDBG("PLL init done\n");
1358
1359 return 0;
1360err1:
1361 regulator_disable(dsi->vdds_dsi_reg);
1362err0:
1363 dsi_disable_scp_clk(dsi);
1364 dsi_runtime_put(dsi);
1365 return r;
1366}
1367
1368static void dsi_pll_disable(struct dss_pll *pll)
1369{
1370 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1371
1372 dsi_pll_power(dsi, DSI_PLL_POWER_OFF);
1373
1374 regulator_disable(dsi->vdds_dsi_reg);
1375
1376 dsi_disable_scp_clk(dsi);
1377 dsi_runtime_put(dsi);
1378
1379 DSSDBG("PLL disable done\n");
1380}
1381
1382static int dsi_dump_dsi_clocks(struct seq_file *s, void *p)
1383{
1384 struct dsi_data *dsi = s->private;
1385 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1386 enum dss_clk_source dispc_clk_src, dsi_clk_src;
1387 int dsi_module = dsi->module_id;
1388 struct dss_pll *pll = &dsi->pll;
1389
1390 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss);
1391 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module);
1392
1393 if (dsi_runtime_get(dsi))
1394 return 0;
1395
1396 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1397
1398 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1399
1400 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1401
1402 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n",
1403 cinfo->clkdco, cinfo->m);
1404
1405 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1406 dss_get_clk_source_name(dsi_module == 0 ?
1407 DSS_CLK_SRC_PLL1_1 :
1408 DSS_CLK_SRC_PLL2_1),
1409 cinfo->clkout[HSDIV_DISPC],
1410 cinfo->mX[HSDIV_DISPC],
1411 dispc_clk_src == DSS_CLK_SRC_FCK ?
1412 "off" : "on");
1413
1414 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1415 dss_get_clk_source_name(dsi_module == 0 ?
1416 DSS_CLK_SRC_PLL1_2 :
1417 DSS_CLK_SRC_PLL2_2),
1418 cinfo->clkout[HSDIV_DSI],
1419 cinfo->mX[HSDIV_DSI],
1420 dsi_clk_src == DSS_CLK_SRC_FCK ?
1421 "off" : "on");
1422
1423 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1424
1425 seq_printf(s, "dsi fclk source = %s\n",
1426 dss_get_clk_source_name(dsi_clk_src));
1427
1428 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi));
1429
1430 seq_printf(s, "DDR_CLK\t\t%lu\n",
1431 cinfo->clkdco / 4);
1432
1433 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi));
1434
1435 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1436
1437 dsi_runtime_put(dsi);
1438
1439 return 0;
1440}
1441
1442#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1443static int dsi_dump_dsi_irqs(struct seq_file *s, void *p)
1444{
1445 struct dsi_data *dsi = s->private;
1446 unsigned long flags;
1447 struct dsi_irq_stats stats;
1448
1449 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1450
1451 stats = dsi->irq_stats;
1452 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1453 dsi->irq_stats.last_reset = jiffies;
1454
1455 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1456
1457 seq_printf(s, "period %u ms\n",
1458 jiffies_to_msecs(jiffies - stats.last_reset));
1459
1460 seq_printf(s, "irqs %d\n", stats.irq_count);
1461#define PIS(x) \
1462 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1463
1464 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1465 PIS(VC0);
1466 PIS(VC1);
1467 PIS(VC2);
1468 PIS(VC3);
1469 PIS(WAKEUP);
1470 PIS(RESYNC);
1471 PIS(PLL_LOCK);
1472 PIS(PLL_UNLOCK);
1473 PIS(PLL_RECALL);
1474 PIS(COMPLEXIO_ERR);
1475 PIS(HS_TX_TIMEOUT);
1476 PIS(LP_RX_TIMEOUT);
1477 PIS(TE_TRIGGER);
1478 PIS(ACK_TRIGGER);
1479 PIS(SYNC_LOST);
1480 PIS(LDO_POWER_GOOD);
1481 PIS(TA_TIMEOUT);
1482#undef PIS
1483
1484#define PIS(x) \
1485 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1486 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1487 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1488 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1489 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1490
1491 seq_printf(s, "-- VC interrupts --\n");
1492 PIS(CS);
1493 PIS(ECC_CORR);
1494 PIS(PACKET_SENT);
1495 PIS(FIFO_TX_OVF);
1496 PIS(FIFO_RX_OVF);
1497 PIS(BTA);
1498 PIS(ECC_NO_CORR);
1499 PIS(FIFO_TX_UDF);
1500 PIS(PP_BUSY_CHANGE);
1501#undef PIS
1502
1503#define PIS(x) \
1504 seq_printf(s, "%-20s %10d\n", #x, \
1505 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1506
1507 seq_printf(s, "-- CIO interrupts --\n");
1508 PIS(ERRSYNCESC1);
1509 PIS(ERRSYNCESC2);
1510 PIS(ERRSYNCESC3);
1511 PIS(ERRESC1);
1512 PIS(ERRESC2);
1513 PIS(ERRESC3);
1514 PIS(ERRCONTROL1);
1515 PIS(ERRCONTROL2);
1516 PIS(ERRCONTROL3);
1517 PIS(STATEULPS1);
1518 PIS(STATEULPS2);
1519 PIS(STATEULPS3);
1520 PIS(ERRCONTENTIONLP0_1);
1521 PIS(ERRCONTENTIONLP1_1);
1522 PIS(ERRCONTENTIONLP0_2);
1523 PIS(ERRCONTENTIONLP1_2);
1524 PIS(ERRCONTENTIONLP0_3);
1525 PIS(ERRCONTENTIONLP1_3);
1526 PIS(ULPSACTIVENOT_ALL0);
1527 PIS(ULPSACTIVENOT_ALL1);
1528#undef PIS
1529
1530 return 0;
1531}
1532#endif
1533
1534static int dsi_dump_dsi_regs(struct seq_file *s, void *p)
1535{
1536 struct dsi_data *dsi = s->private;
1537
1538 if (dsi_runtime_get(dsi))
1539 return 0;
1540 dsi_enable_scp_clk(dsi);
1541
1542#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r))
1543 DUMPREG(DSI_REVISION);
1544 DUMPREG(DSI_SYSCONFIG);
1545 DUMPREG(DSI_SYSSTATUS);
1546 DUMPREG(DSI_IRQSTATUS);
1547 DUMPREG(DSI_IRQENABLE);
1548 DUMPREG(DSI_CTRL);
1549 DUMPREG(DSI_COMPLEXIO_CFG1);
1550 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1551 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1552 DUMPREG(DSI_CLK_CTRL);
1553 DUMPREG(DSI_TIMING1);
1554 DUMPREG(DSI_TIMING2);
1555 DUMPREG(DSI_VM_TIMING1);
1556 DUMPREG(DSI_VM_TIMING2);
1557 DUMPREG(DSI_VM_TIMING3);
1558 DUMPREG(DSI_CLK_TIMING);
1559 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1560 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1561 DUMPREG(DSI_COMPLEXIO_CFG2);
1562 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1563 DUMPREG(DSI_VM_TIMING4);
1564 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1565 DUMPREG(DSI_VM_TIMING5);
1566 DUMPREG(DSI_VM_TIMING6);
1567 DUMPREG(DSI_VM_TIMING7);
1568 DUMPREG(DSI_STOPCLK_TIMING);
1569
1570 DUMPREG(DSI_VC_CTRL(0));
1571 DUMPREG(DSI_VC_TE(0));
1572 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1573 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1574 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1575 DUMPREG(DSI_VC_IRQSTATUS(0));
1576 DUMPREG(DSI_VC_IRQENABLE(0));
1577
1578 DUMPREG(DSI_VC_CTRL(1));
1579 DUMPREG(DSI_VC_TE(1));
1580 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1581 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1582 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1583 DUMPREG(DSI_VC_IRQSTATUS(1));
1584 DUMPREG(DSI_VC_IRQENABLE(1));
1585
1586 DUMPREG(DSI_VC_CTRL(2));
1587 DUMPREG(DSI_VC_TE(2));
1588 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1589 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1590 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1591 DUMPREG(DSI_VC_IRQSTATUS(2));
1592 DUMPREG(DSI_VC_IRQENABLE(2));
1593
1594 DUMPREG(DSI_VC_CTRL(3));
1595 DUMPREG(DSI_VC_TE(3));
1596 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1597 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1598 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1599 DUMPREG(DSI_VC_IRQSTATUS(3));
1600 DUMPREG(DSI_VC_IRQENABLE(3));
1601
1602 DUMPREG(DSI_DSIPHY_CFG0);
1603 DUMPREG(DSI_DSIPHY_CFG1);
1604 DUMPREG(DSI_DSIPHY_CFG2);
1605 DUMPREG(DSI_DSIPHY_CFG5);
1606
1607 DUMPREG(DSI_PLL_CONTROL);
1608 DUMPREG(DSI_PLL_STATUS);
1609 DUMPREG(DSI_PLL_GO);
1610 DUMPREG(DSI_PLL_CONFIGURATION1);
1611 DUMPREG(DSI_PLL_CONFIGURATION2);
1612#undef DUMPREG
1613
1614 dsi_disable_scp_clk(dsi);
1615 dsi_runtime_put(dsi);
1616
1617 return 0;
1618}
1619
1620enum dsi_cio_power_state {
1621 DSI_COMPLEXIO_POWER_OFF = 0x0,
1622 DSI_COMPLEXIO_POWER_ON = 0x1,
1623 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1624};
1625
1626static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state)
1627{
1628 int t = 0;
1629
1630 /* PWR_CMD */
1631 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27);
1632
1633 /* PWR_STATUS */
1634 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1),
1635 26, 25) != state) {
1636 if (++t > 1000) {
1637 DSSERR("failed to set complexio power state to "
1638 "%d\n", state);
1639 return -ENODEV;
1640 }
1641 udelay(1);
1642 }
1643
1644 return 0;
1645}
1646
1647static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi)
1648{
1649 int val;
1650
1651 /* line buffer on OMAP3 is 1024 x 24bits */
1652 /* XXX: for some reason using full buffer size causes
1653 * considerable TX slowdown with update sizes that fill the
1654 * whole buffer */
1655 if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1656 return 1023 * 3;
1657
1658 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1659
1660 switch (val) {
1661 case 1:
1662 return 512 * 3; /* 512x24 bits */
1663 case 2:
1664 return 682 * 3; /* 682x24 bits */
1665 case 3:
1666 return 853 * 3; /* 853x24 bits */
1667 case 4:
1668 return 1024 * 3; /* 1024x24 bits */
1669 case 5:
1670 return 1194 * 3; /* 1194x24 bits */
1671 case 6:
1672 return 1365 * 3; /* 1365x24 bits */
1673 case 7:
1674 return 1920 * 3; /* 1920x24 bits */
1675 default:
1676 BUG();
1677 return 0;
1678 }
1679}
1680
1681static int dsi_set_lane_config(struct dsi_data *dsi)
1682{
1683 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1684 static const enum dsi_lane_function functions[] = {
1685 DSI_LANE_CLK,
1686 DSI_LANE_DATA1,
1687 DSI_LANE_DATA2,
1688 DSI_LANE_DATA3,
1689 DSI_LANE_DATA4,
1690 };
1691 u32 r;
1692 int i;
1693
1694 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1);
1695
1696 for (i = 0; i < dsi->num_lanes_used; ++i) {
1697 unsigned int offset = offsets[i];
1698 unsigned int polarity, lane_number;
1699 unsigned int t;
1700
1701 for (t = 0; t < dsi->num_lanes_supported; ++t)
1702 if (dsi->lanes[t].function == functions[i])
1703 break;
1704
1705 if (t == dsi->num_lanes_supported)
1706 return -EINVAL;
1707
1708 lane_number = t;
1709 polarity = dsi->lanes[t].polarity;
1710
1711 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1712 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1713 }
1714
1715 /* clear the unused lanes */
1716 for (; i < dsi->num_lanes_supported; ++i) {
1717 unsigned int offset = offsets[i];
1718
1719 r = FLD_MOD(r, 0, offset + 2, offset);
1720 r = FLD_MOD(r, 0, offset + 3, offset + 3);
1721 }
1722
1723 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r);
1724
1725 return 0;
1726}
1727
1728static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns)
1729{
1730 /* convert time in ns to ddr ticks, rounding up */
1731 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1732
1733 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1734}
1735
1736static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr)
1737{
1738 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1739
1740 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1741}
1742
1743static void dsi_cio_timings(struct dsi_data *dsi)
1744{
1745 u32 r;
1746 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1747 u32 tlpx_half, tclk_trail, tclk_zero;
1748 u32 tclk_prepare;
1749
1750 /* calculate timings */
1751
1752 /* 1 * DDR_CLK = 2 * UI */
1753
1754 /* min 40ns + 4*UI max 85ns + 6*UI */
1755 ths_prepare = ns2ddr(dsi, 70) + 2;
1756
1757 /* min 145ns + 10*UI */
1758 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2;
1759
1760 /* min max(8*UI, 60ns+4*UI) */
1761 ths_trail = ns2ddr(dsi, 60) + 5;
1762
1763 /* min 100ns */
1764 ths_exit = ns2ddr(dsi, 145);
1765
1766 /* tlpx min 50n */
1767 tlpx_half = ns2ddr(dsi, 25);
1768
1769 /* min 60ns */
1770 tclk_trail = ns2ddr(dsi, 60) + 2;
1771
1772 /* min 38ns, max 95ns */
1773 tclk_prepare = ns2ddr(dsi, 65);
1774
1775 /* min tclk-prepare + tclk-zero = 300ns */
1776 tclk_zero = ns2ddr(dsi, 260);
1777
1778 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1779 ths_prepare, ddr2ns(dsi, ths_prepare),
1780 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero));
1781 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1782 ths_trail, ddr2ns(dsi, ths_trail),
1783 ths_exit, ddr2ns(dsi, ths_exit));
1784
1785 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1786 "tclk_zero %u (%uns)\n",
1787 tlpx_half, ddr2ns(dsi, tlpx_half),
1788 tclk_trail, ddr2ns(dsi, tclk_trail),
1789 tclk_zero, ddr2ns(dsi, tclk_zero));
1790 DSSDBG("tclk_prepare %u (%uns)\n",
1791 tclk_prepare, ddr2ns(dsi, tclk_prepare));
1792
1793 /* program timings */
1794
1795 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
1796 r = FLD_MOD(r, ths_prepare, 31, 24);
1797 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1798 r = FLD_MOD(r, ths_trail, 15, 8);
1799 r = FLD_MOD(r, ths_exit, 7, 0);
1800 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r);
1801
1802 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
1803 r = FLD_MOD(r, tlpx_half, 20, 16);
1804 r = FLD_MOD(r, tclk_trail, 15, 8);
1805 r = FLD_MOD(r, tclk_zero, 7, 0);
1806
1807 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) {
1808 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
1809 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
1810 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
1811 }
1812
1813 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r);
1814
1815 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
1816 r = FLD_MOD(r, tclk_prepare, 7, 0);
1817 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r);
1818}
1819
1820/* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1821static void dsi_cio_enable_lane_override(struct dsi_data *dsi,
1822 unsigned int mask_p,
1823 unsigned int mask_n)
1824{
1825 int i;
1826 u32 l;
1827 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1828
1829 l = 0;
1830
1831 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1832 unsigned int p = dsi->lanes[i].polarity;
1833
1834 if (mask_p & (1 << i))
1835 l |= 1 << (i * 2 + (p ? 0 : 1));
1836
1837 if (mask_n & (1 << i))
1838 l |= 1 << (i * 2 + (p ? 1 : 0));
1839 }
1840
1841 /*
1842 * Bits in REGLPTXSCPDAT4TO0DXDY:
1843 * 17: DY0 18: DX0
1844 * 19: DY1 20: DX1
1845 * 21: DY2 22: DX2
1846 * 23: DY3 24: DX3
1847 * 25: DY4 26: DX4
1848 */
1849
1850 /* Set the lane override configuration */
1851
1852 /* REGLPTXSCPDAT4TO0DXDY */
1853 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1854
1855 /* Enable lane override */
1856
1857 /* ENLPTXSCPDAT */
1858 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27);
1859}
1860
1861static void dsi_cio_disable_lane_override(struct dsi_data *dsi)
1862{
1863 /* Disable lane override */
1864 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1865 /* Reset the lane override configuration */
1866 /* REGLPTXSCPDAT4TO0DXDY */
1867 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 22, 17);
1868}
1869
1870static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi)
1871{
1872 int t, i;
1873 bool in_use[DSI_MAX_NR_LANES];
1874 static const u8 offsets_old[] = { 28, 27, 26 };
1875 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
1876 const u8 *offsets;
1877
1878 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC)
1879 offsets = offsets_old;
1880 else
1881 offsets = offsets_new;
1882
1883 for (i = 0; i < dsi->num_lanes_supported; ++i)
1884 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
1885
1886 t = 100000;
1887 while (true) {
1888 u32 l;
1889 int ok;
1890
1891 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1892
1893 ok = 0;
1894 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1895 if (!in_use[i] || (l & (1 << offsets[i])))
1896 ok++;
1897 }
1898
1899 if (ok == dsi->num_lanes_supported)
1900 break;
1901
1902 if (--t == 0) {
1903 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1904 if (!in_use[i] || (l & (1 << offsets[i])))
1905 continue;
1906
1907 DSSERR("CIO TXCLKESC%d domain not coming " \
1908 "out of reset\n", i);
1909 }
1910 return -EIO;
1911 }
1912 }
1913
1914 return 0;
1915}
1916
1917/* return bitmask of enabled lanes, lane0 being the lsb */
1918static unsigned int dsi_get_lane_mask(struct dsi_data *dsi)
1919{
1920 unsigned int mask = 0;
1921 int i;
1922
1923 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1924 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
1925 mask |= 1 << i;
1926 }
1927
1928 return mask;
1929}
1930
1931/* OMAP4 CONTROL_DSIPHY */
1932#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
1933
1934#define OMAP4_DSI2_LANEENABLE_SHIFT 29
1935#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
1936#define OMAP4_DSI1_LANEENABLE_SHIFT 24
1937#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
1938#define OMAP4_DSI1_PIPD_SHIFT 19
1939#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
1940#define OMAP4_DSI2_PIPD_SHIFT 14
1941#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
1942
1943static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1944{
1945 u32 enable_mask, enable_shift;
1946 u32 pipd_mask, pipd_shift;
1947
1948 if (dsi->module_id == 0) {
1949 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
1950 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
1951 pipd_mask = OMAP4_DSI1_PIPD_MASK;
1952 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
1953 } else if (dsi->module_id == 1) {
1954 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
1955 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
1956 pipd_mask = OMAP4_DSI2_PIPD_MASK;
1957 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
1958 } else {
1959 return -ENODEV;
1960 }
1961
1962 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET,
1963 enable_mask | pipd_mask,
1964 (lanes << enable_shift) | (lanes << pipd_shift));
1965}
1966
1967/* OMAP5 CONTROL_DSIPHY */
1968
1969#define OMAP5_DSIPHY_SYSCON_OFFSET 0x74
1970
1971#define OMAP5_DSI1_LANEENABLE_SHIFT 24
1972#define OMAP5_DSI2_LANEENABLE_SHIFT 19
1973#define OMAP5_DSI_LANEENABLE_MASK 0x1f
1974
1975static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1976{
1977 u32 enable_shift;
1978
1979 if (dsi->module_id == 0)
1980 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT;
1981 else if (dsi->module_id == 1)
1982 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT;
1983 else
1984 return -ENODEV;
1985
1986 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET,
1987 OMAP5_DSI_LANEENABLE_MASK << enable_shift,
1988 lanes << enable_shift);
1989}
1990
1991static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask)
1992{
1993 if (dsi->data->model == DSI_MODEL_OMAP4)
1994 return dsi_omap4_mux_pads(dsi, lane_mask);
1995 if (dsi->data->model == DSI_MODEL_OMAP5)
1996 return dsi_omap5_mux_pads(dsi, lane_mask);
1997 return 0;
1998}
1999
2000static void dsi_disable_pads(struct dsi_data *dsi)
2001{
2002 if (dsi->data->model == DSI_MODEL_OMAP4)
2003 dsi_omap4_mux_pads(dsi, 0);
2004 else if (dsi->data->model == DSI_MODEL_OMAP5)
2005 dsi_omap5_mux_pads(dsi, 0);
2006}
2007
2008static int dsi_cio_init(struct dsi_data *dsi)
2009{
2010 int r;
2011 u32 l;
2012
2013 DSSDBG("DSI CIO init starts");
2014
2015 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi));
2016 if (r)
2017 return r;
2018
2019 dsi_enable_scp_clk(dsi);
2020
2021 /* A dummy read using the SCP interface to any DSIPHY register is
2022 * required after DSIPHY reset to complete the reset of the DSI complex
2023 * I/O. */
2024 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
2025
2026 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) {
2027 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2028 r = -EIO;
2029 goto err_scp_clk_dom;
2030 }
2031
2032 r = dsi_set_lane_config(dsi);
2033 if (r)
2034 goto err_scp_clk_dom;
2035
2036 /* set TX STOP MODE timer to maximum for this operation */
2037 l = dsi_read_reg(dsi, DSI_TIMING1);
2038 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2039 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2040 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2041 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2042 dsi_write_reg(dsi, DSI_TIMING1, l);
2043
2044 if (dsi->ulps_enabled) {
2045 unsigned int mask_p;
2046 int i;
2047
2048 DSSDBG("manual ulps exit\n");
2049
2050 /* ULPS is exited by Mark-1 state for 1ms, followed by
2051 * stop state. DSS HW cannot do this via the normal
2052 * ULPS exit sequence, as after reset the DSS HW thinks
2053 * that we are not in ULPS mode, and refuses to send the
2054 * sequence. So we need to send the ULPS exit sequence
2055 * manually by setting positive lines high and negative lines
2056 * low for 1ms.
2057 */
2058
2059 mask_p = 0;
2060
2061 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2062 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2063 continue;
2064 mask_p |= 1 << i;
2065 }
2066
2067 dsi_cio_enable_lane_override(dsi, mask_p, 0);
2068 }
2069
2070 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON);
2071 if (r)
2072 goto err_cio_pwr;
2073
2074 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) {
2075 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2076 r = -ENODEV;
2077 goto err_cio_pwr_dom;
2078 }
2079
2080 dsi_if_enable(dsi, true);
2081 dsi_if_enable(dsi, false);
2082 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2083
2084 r = dsi_cio_wait_tx_clk_esc_reset(dsi);
2085 if (r)
2086 goto err_tx_clk_esc_rst;
2087
2088 if (dsi->ulps_enabled) {
2089 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2090 ktime_t wait = ns_to_ktime(1000 * 1000);
2091 set_current_state(TASK_UNINTERRUPTIBLE);
2092 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2093
2094 /* Disable the override. The lanes should be set to Mark-11
2095 * state by the HW */
2096 dsi_cio_disable_lane_override(dsi);
2097 }
2098
2099 /* FORCE_TX_STOP_MODE_IO */
2100 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15);
2101
2102 dsi_cio_timings(dsi);
2103
2104 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2105 /* DDR_CLK_ALWAYS_ON */
2106 REG_FLD_MOD(dsi, DSI_CLK_CTRL,
2107 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2108 }
2109
2110 dsi->ulps_enabled = false;
2111
2112 DSSDBG("CIO init done\n");
2113
2114 return 0;
2115
2116err_tx_clk_esc_rst:
2117 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2118err_cio_pwr_dom:
2119 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2120err_cio_pwr:
2121 if (dsi->ulps_enabled)
2122 dsi_cio_disable_lane_override(dsi);
2123err_scp_clk_dom:
2124 dsi_disable_scp_clk(dsi);
2125 dsi_disable_pads(dsi);
2126 return r;
2127}
2128
2129static void dsi_cio_uninit(struct dsi_data *dsi)
2130{
2131 /* DDR_CLK_ALWAYS_ON */
2132 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
2133
2134 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2135 dsi_disable_scp_clk(dsi);
2136 dsi_disable_pads(dsi);
2137}
2138
2139static void dsi_config_tx_fifo(struct dsi_data *dsi,
2140 enum fifo_size size1, enum fifo_size size2,
2141 enum fifo_size size3, enum fifo_size size4)
2142{
2143 u32 r = 0;
2144 int add = 0;
2145 int i;
2146
2147 dsi->vc[0].tx_fifo_size = size1;
2148 dsi->vc[1].tx_fifo_size = size2;
2149 dsi->vc[2].tx_fifo_size = size3;
2150 dsi->vc[3].tx_fifo_size = size4;
2151
2152 for (i = 0; i < 4; i++) {
2153 u8 v;
2154 int size = dsi->vc[i].tx_fifo_size;
2155
2156 if (add + size > 4) {
2157 DSSERR("Illegal FIFO configuration\n");
2158 BUG();
2159 return;
2160 }
2161
2162 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2163 r |= v << (8 * i);
2164 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2165 add += size;
2166 }
2167
2168 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r);
2169}
2170
2171static void dsi_config_rx_fifo(struct dsi_data *dsi,
2172 enum fifo_size size1, enum fifo_size size2,
2173 enum fifo_size size3, enum fifo_size size4)
2174{
2175 u32 r = 0;
2176 int add = 0;
2177 int i;
2178
2179 dsi->vc[0].rx_fifo_size = size1;
2180 dsi->vc[1].rx_fifo_size = size2;
2181 dsi->vc[2].rx_fifo_size = size3;
2182 dsi->vc[3].rx_fifo_size = size4;
2183
2184 for (i = 0; i < 4; i++) {
2185 u8 v;
2186 int size = dsi->vc[i].rx_fifo_size;
2187
2188 if (add + size > 4) {
2189 DSSERR("Illegal FIFO configuration\n");
2190 BUG();
2191 return;
2192 }
2193
2194 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2195 r |= v << (8 * i);
2196 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2197 add += size;
2198 }
2199
2200 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r);
2201}
2202
2203static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi)
2204{
2205 u32 r;
2206
2207 r = dsi_read_reg(dsi, DSI_TIMING1);
2208 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2209 dsi_write_reg(dsi, DSI_TIMING1, r);
2210
2211 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) {
2212 DSSERR("TX_STOP bit not going down\n");
2213 return -EIO;
2214 }
2215
2216 return 0;
2217}
2218
2219static bool dsi_vc_is_enabled(struct dsi_data *dsi, int channel)
2220{
2221 return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0);
2222}
2223
2224static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2225{
2226 struct dsi_packet_sent_handler_data *vp_data =
2227 (struct dsi_packet_sent_handler_data *) data;
2228 struct dsi_data *dsi = vp_data->dsi;
2229 const int channel = dsi->update_channel;
2230 u8 bit = dsi->te_enabled ? 30 : 31;
2231
2232 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0)
2233 complete(vp_data->completion);
2234}
2235
2236static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel)
2237{
2238 DECLARE_COMPLETION_ONSTACK(completion);
2239 struct dsi_packet_sent_handler_data vp_data = {
2240 .dsi = dsi,
2241 .completion = &completion
2242 };
2243 int r = 0;
2244 u8 bit;
2245
2246 bit = dsi->te_enabled ? 30 : 31;
2247
2248 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2249 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2250 if (r)
2251 goto err0;
2252
2253 /* Wait for completion only if TE_EN/TE_START is still set */
2254 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) {
2255 if (wait_for_completion_timeout(&completion,
2256 msecs_to_jiffies(10)) == 0) {
2257 DSSERR("Failed to complete previous frame transfer\n");
2258 r = -EIO;
2259 goto err1;
2260 }
2261 }
2262
2263 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2264 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2265
2266 return 0;
2267err1:
2268 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2269 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2270err0:
2271 return r;
2272}
2273
2274static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2275{
2276 struct dsi_packet_sent_handler_data *l4_data =
2277 (struct dsi_packet_sent_handler_data *) data;
2278 struct dsi_data *dsi = l4_data->dsi;
2279 const int channel = dsi->update_channel;
2280
2281 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0)
2282 complete(l4_data->completion);
2283}
2284
2285static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel)
2286{
2287 DECLARE_COMPLETION_ONSTACK(completion);
2288 struct dsi_packet_sent_handler_data l4_data = {
2289 .dsi = dsi,
2290 .completion = &completion
2291 };
2292 int r = 0;
2293
2294 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2295 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2296 if (r)
2297 goto err0;
2298
2299 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2300 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) {
2301 if (wait_for_completion_timeout(&completion,
2302 msecs_to_jiffies(10)) == 0) {
2303 DSSERR("Failed to complete previous l4 transfer\n");
2304 r = -EIO;
2305 goto err1;
2306 }
2307 }
2308
2309 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2310 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2311
2312 return 0;
2313err1:
2314 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2315 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2316err0:
2317 return r;
2318}
2319
2320static int dsi_sync_vc(struct dsi_data *dsi, int channel)
2321{
2322 WARN_ON(!dsi_bus_is_locked(dsi));
2323
2324 WARN_ON(in_interrupt());
2325
2326 if (!dsi_vc_is_enabled(dsi, channel))
2327 return 0;
2328
2329 switch (dsi->vc[channel].source) {
2330 case DSI_VC_SOURCE_VP:
2331 return dsi_sync_vc_vp(dsi, channel);
2332 case DSI_VC_SOURCE_L4:
2333 return dsi_sync_vc_l4(dsi, channel);
2334 default:
2335 BUG();
2336 return -EINVAL;
2337 }
2338}
2339
2340static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable)
2341{
2342 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2343 channel, enable);
2344
2345 enable = enable ? 1 : 0;
2346
2347 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0);
2348
2349 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 0, enable)) {
2350 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2351 return -EIO;
2352 }
2353
2354 return 0;
2355}
2356
2357static void dsi_vc_initial_config(struct dsi_data *dsi, int channel)
2358{
2359 u32 r;
2360
2361 DSSDBG("Initial config of virtual channel %d", channel);
2362
2363 r = dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2364
2365 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2366 DSSERR("VC(%d) busy when trying to configure it!\n",
2367 channel);
2368
2369 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2370 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2371 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2372 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2373 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2374 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2375 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2376 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH)
2377 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2378
2379 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2380 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2381
2382 dsi_write_reg(dsi, DSI_VC_CTRL(channel), r);
2383
2384 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2385}
2386
2387static int dsi_vc_config_source(struct dsi_data *dsi, int channel,
2388 enum dsi_vc_source source)
2389{
2390 if (dsi->vc[channel].source == source)
2391 return 0;
2392
2393 DSSDBG("Source config of virtual channel %d", channel);
2394
2395 dsi_sync_vc(dsi, channel);
2396
2397 dsi_vc_enable(dsi, channel, 0);
2398
2399 /* VC_BUSY */
2400 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 15, 0)) {
2401 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2402 return -EIO;
2403 }
2404
2405 /* SOURCE, 0 = L4, 1 = video port */
2406 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1);
2407
2408 /* DCS_CMD_ENABLE */
2409 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) {
2410 bool enable = source == DSI_VC_SOURCE_VP;
2411 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30);
2412 }
2413
2414 dsi_vc_enable(dsi, channel, 1);
2415
2416 dsi->vc[channel].source = source;
2417
2418 return 0;
2419}
2420
2421static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2422 bool enable)
2423{
2424 struct dsi_data *dsi = to_dsi_data(dssdev);
2425
2426 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2427
2428 WARN_ON(!dsi_bus_is_locked(dsi));
2429
2430 dsi_vc_enable(dsi, channel, 0);
2431 dsi_if_enable(dsi, 0);
2432
2433 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9);
2434
2435 dsi_vc_enable(dsi, channel, 1);
2436 dsi_if_enable(dsi, 1);
2437
2438 dsi_force_tx_stop_mode_io(dsi);
2439
2440 /* start the DDR clock by sending a NULL packet */
2441 if (dsi->vm_timings.ddr_clk_always_on && enable)
2442 dsi_vc_send_null(dsi, channel);
2443}
2444
2445static void dsi_vc_flush_long_data(struct dsi_data *dsi, int channel)
2446{
2447 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2448 u32 val;
2449 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2450 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2451 (val >> 0) & 0xff,
2452 (val >> 8) & 0xff,
2453 (val >> 16) & 0xff,
2454 (val >> 24) & 0xff);
2455 }
2456}
2457
2458static void dsi_show_rx_ack_with_err(u16 err)
2459{
2460 DSSERR("\tACK with ERROR (%#x):\n", err);
2461 if (err & (1 << 0))
2462 DSSERR("\t\tSoT Error\n");
2463 if (err & (1 << 1))
2464 DSSERR("\t\tSoT Sync Error\n");
2465 if (err & (1 << 2))
2466 DSSERR("\t\tEoT Sync Error\n");
2467 if (err & (1 << 3))
2468 DSSERR("\t\tEscape Mode Entry Command Error\n");
2469 if (err & (1 << 4))
2470 DSSERR("\t\tLP Transmit Sync Error\n");
2471 if (err & (1 << 5))
2472 DSSERR("\t\tHS Receive Timeout Error\n");
2473 if (err & (1 << 6))
2474 DSSERR("\t\tFalse Control Error\n");
2475 if (err & (1 << 7))
2476 DSSERR("\t\t(reserved7)\n");
2477 if (err & (1 << 8))
2478 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2479 if (err & (1 << 9))
2480 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2481 if (err & (1 << 10))
2482 DSSERR("\t\tChecksum Error\n");
2483 if (err & (1 << 11))
2484 DSSERR("\t\tData type not recognized\n");
2485 if (err & (1 << 12))
2486 DSSERR("\t\tInvalid VC ID\n");
2487 if (err & (1 << 13))
2488 DSSERR("\t\tInvalid Transmission Length\n");
2489 if (err & (1 << 14))
2490 DSSERR("\t\t(reserved14)\n");
2491 if (err & (1 << 15))
2492 DSSERR("\t\tDSI Protocol Violation\n");
2493}
2494
2495static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel)
2496{
2497 /* RX_FIFO_NOT_EMPTY */
2498 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2499 u32 val;
2500 u8 dt;
2501 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2502 DSSERR("\trawval %#08x\n", val);
2503 dt = FLD_GET(val, 5, 0);
2504 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2505 u16 err = FLD_GET(val, 23, 8);
2506 dsi_show_rx_ack_with_err(err);
2507 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2508 DSSERR("\tDCS short response, 1 byte: %#x\n",
2509 FLD_GET(val, 23, 8));
2510 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2511 DSSERR("\tDCS short response, 2 byte: %#x\n",
2512 FLD_GET(val, 23, 8));
2513 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2514 DSSERR("\tDCS long response, len %d\n",
2515 FLD_GET(val, 23, 8));
2516 dsi_vc_flush_long_data(dsi, channel);
2517 } else {
2518 DSSERR("\tunknown datatype 0x%02x\n", dt);
2519 }
2520 }
2521 return 0;
2522}
2523
2524static int dsi_vc_send_bta(struct dsi_data *dsi, int channel)
2525{
2526 if (dsi->debug_write || dsi->debug_read)
2527 DSSDBG("dsi_vc_send_bta %d\n", channel);
2528
2529 WARN_ON(!dsi_bus_is_locked(dsi));
2530
2531 /* RX_FIFO_NOT_EMPTY */
2532 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2533 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2534 dsi_vc_flush_receive_data(dsi, channel);
2535 }
2536
2537 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2538
2539 /* flush posted write */
2540 dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2541
2542 return 0;
2543}
2544
2545static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2546{
2547 struct dsi_data *dsi = to_dsi_data(dssdev);
2548 DECLARE_COMPLETION_ONSTACK(completion);
2549 int r = 0;
2550 u32 err;
2551
2552 r = dsi_register_isr_vc(dsi, channel, dsi_completion_handler,
2553 &completion, DSI_VC_IRQ_BTA);
2554 if (r)
2555 goto err0;
2556
2557 r = dsi_register_isr(dsi, dsi_completion_handler, &completion,
2558 DSI_IRQ_ERROR_MASK);
2559 if (r)
2560 goto err1;
2561
2562 r = dsi_vc_send_bta(dsi, channel);
2563 if (r)
2564 goto err2;
2565
2566 if (wait_for_completion_timeout(&completion,
2567 msecs_to_jiffies(500)) == 0) {
2568 DSSERR("Failed to receive BTA\n");
2569 r = -EIO;
2570 goto err2;
2571 }
2572
2573 err = dsi_get_errors(dsi);
2574 if (err) {
2575 DSSERR("Error while sending BTA: %x\n", err);
2576 r = -EIO;
2577 goto err2;
2578 }
2579err2:
2580 dsi_unregister_isr(dsi, dsi_completion_handler, &completion,
2581 DSI_IRQ_ERROR_MASK);
2582err1:
2583 dsi_unregister_isr_vc(dsi, channel, dsi_completion_handler,
2584 &completion, DSI_VC_IRQ_BTA);
2585err0:
2586 return r;
2587}
2588
2589static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel,
2590 u8 data_type, u16 len, u8 ecc)
2591{
2592 u32 val;
2593 u8 data_id;
2594
2595 WARN_ON(!dsi_bus_is_locked(dsi));
2596
2597 data_id = data_type | dsi->vc[channel].vc_id << 6;
2598
2599 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2600 FLD_VAL(ecc, 31, 24);
2601
2602 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val);
2603}
2604
2605static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel,
2606 u8 b1, u8 b2, u8 b3, u8 b4)
2607{
2608 u32 val;
2609
2610 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2611
2612/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2613 b1, b2, b3, b4, val); */
2614
2615 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2616}
2617
2618static int dsi_vc_send_long(struct dsi_data *dsi, int channel, u8 data_type,
2619 u8 *data, u16 len, u8 ecc)
2620{
2621 /*u32 val; */
2622 int i;
2623 u8 *p;
2624 int r = 0;
2625 u8 b1, b2, b3, b4;
2626
2627 if (dsi->debug_write)
2628 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2629
2630 /* len + header */
2631 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2632 DSSERR("unable to send long packet: packet too long.\n");
2633 return -EINVAL;
2634 }
2635
2636 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2637
2638 dsi_vc_write_long_header(dsi, channel, data_type, len, ecc);
2639
2640 p = data;
2641 for (i = 0; i < len >> 2; i++) {
2642 if (dsi->debug_write)
2643 DSSDBG("\tsending full packet %d\n", i);
2644
2645 b1 = *p++;
2646 b2 = *p++;
2647 b3 = *p++;
2648 b4 = *p++;
2649
2650 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, b4);
2651 }
2652
2653 i = len % 4;
2654 if (i) {
2655 b1 = 0; b2 = 0; b3 = 0;
2656
2657 if (dsi->debug_write)
2658 DSSDBG("\tsending remainder bytes %d\n", i);
2659
2660 switch (i) {
2661 case 3:
2662 b1 = *p++;
2663 b2 = *p++;
2664 b3 = *p++;
2665 break;
2666 case 2:
2667 b1 = *p++;
2668 b2 = *p++;
2669 break;
2670 case 1:
2671 b1 = *p++;
2672 break;
2673 }
2674
2675 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, 0);
2676 }
2677
2678 return r;
2679}
2680
2681static int dsi_vc_send_short(struct dsi_data *dsi, int channel, u8 data_type,
2682 u16 data, u8 ecc)
2683{
2684 u32 r;
2685 u8 data_id;
2686
2687 WARN_ON(!dsi_bus_is_locked(dsi));
2688
2689 if (dsi->debug_write)
2690 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2691 channel,
2692 data_type, data & 0xff, (data >> 8) & 0xff);
2693
2694 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2695
2696 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(channel)), 16, 16)) {
2697 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2698 return -EINVAL;
2699 }
2700
2701 data_id = data_type | dsi->vc[channel].vc_id << 6;
2702
2703 r = (data_id << 0) | (data << 8) | (ecc << 24);
2704
2705 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2706
2707 return 0;
2708}
2709
2710static int dsi_vc_send_null(struct dsi_data *dsi, int channel)
2711{
2712 return dsi_vc_send_long(dsi, channel, MIPI_DSI_NULL_PACKET, NULL, 0, 0);
2713}
2714
2715static int dsi_vc_write_nosync_common(struct dsi_data *dsi, int channel,
2716 u8 *data, int len,
2717 enum dss_dsi_content_type type)
2718{
2719 int r;
2720
2721 if (len == 0) {
2722 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2723 r = dsi_vc_send_short(dsi, channel,
2724 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2725 } else if (len == 1) {
2726 r = dsi_vc_send_short(dsi, channel,
2727 type == DSS_DSI_CONTENT_GENERIC ?
2728 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2729 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2730 } else if (len == 2) {
2731 r = dsi_vc_send_short(dsi, channel,
2732 type == DSS_DSI_CONTENT_GENERIC ?
2733 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2734 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2735 data[0] | (data[1] << 8), 0);
2736 } else {
2737 r = dsi_vc_send_long(dsi, channel,
2738 type == DSS_DSI_CONTENT_GENERIC ?
2739 MIPI_DSI_GENERIC_LONG_WRITE :
2740 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2741 }
2742
2743 return r;
2744}
2745
2746static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2747 u8 *data, int len)
2748{
2749 struct dsi_data *dsi = to_dsi_data(dssdev);
2750
2751 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2752 DSS_DSI_CONTENT_DCS);
2753}
2754
2755static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2756 u8 *data, int len)
2757{
2758 struct dsi_data *dsi = to_dsi_data(dssdev);
2759
2760 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2761 DSS_DSI_CONTENT_GENERIC);
2762}
2763
2764static int dsi_vc_write_common(struct omap_dss_device *dssdev,
2765 int channel, u8 *data, int len,
2766 enum dss_dsi_content_type type)
2767{
2768 struct dsi_data *dsi = to_dsi_data(dssdev);
2769 int r;
2770
2771 r = dsi_vc_write_nosync_common(dsi, channel, data, len, type);
2772 if (r)
2773 goto err;
2774
2775 r = dsi_vc_send_bta_sync(dssdev, channel);
2776 if (r)
2777 goto err;
2778
2779 /* RX_FIFO_NOT_EMPTY */
2780 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2781 DSSERR("rx fifo not empty after write, dumping data:\n");
2782 dsi_vc_flush_receive_data(dsi, channel);
2783 r = -EIO;
2784 goto err;
2785 }
2786
2787 return 0;
2788err:
2789 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2790 channel, data[0], len);
2791 return r;
2792}
2793
2794static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2795 int len)
2796{
2797 return dsi_vc_write_common(dssdev, channel, data, len,
2798 DSS_DSI_CONTENT_DCS);
2799}
2800
2801static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2802 int len)
2803{
2804 return dsi_vc_write_common(dssdev, channel, data, len,
2805 DSS_DSI_CONTENT_GENERIC);
2806}
2807
2808static int dsi_vc_dcs_send_read_request(struct dsi_data *dsi, int channel,
2809 u8 dcs_cmd)
2810{
2811 int r;
2812
2813 if (dsi->debug_read)
2814 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2815 channel, dcs_cmd);
2816
2817 r = dsi_vc_send_short(dsi, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2818 if (r) {
2819 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2820 " failed\n", channel, dcs_cmd);
2821 return r;
2822 }
2823
2824 return 0;
2825}
2826
2827static int dsi_vc_generic_send_read_request(struct dsi_data *dsi, int channel,
2828 u8 *reqdata, int reqlen)
2829{
2830 u16 data;
2831 u8 data_type;
2832 int r;
2833
2834 if (dsi->debug_read)
2835 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2836 channel, reqlen);
2837
2838 if (reqlen == 0) {
2839 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2840 data = 0;
2841 } else if (reqlen == 1) {
2842 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2843 data = reqdata[0];
2844 } else if (reqlen == 2) {
2845 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2846 data = reqdata[0] | (reqdata[1] << 8);
2847 } else {
2848 BUG();
2849 return -EINVAL;
2850 }
2851
2852 r = dsi_vc_send_short(dsi, channel, data_type, data, 0);
2853 if (r) {
2854 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2855 " failed\n", channel, reqlen);
2856 return r;
2857 }
2858
2859 return 0;
2860}
2861
2862static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf,
2863 int buflen, enum dss_dsi_content_type type)
2864{
2865 u32 val;
2866 u8 dt;
2867 int r;
2868
2869 /* RX_FIFO_NOT_EMPTY */
2870 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) {
2871 DSSERR("RX fifo empty when trying to read.\n");
2872 r = -EIO;
2873 goto err;
2874 }
2875
2876 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2877 if (dsi->debug_read)
2878 DSSDBG("\theader: %08x\n", val);
2879 dt = FLD_GET(val, 5, 0);
2880 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2881 u16 err = FLD_GET(val, 23, 8);
2882 dsi_show_rx_ack_with_err(err);
2883 r = -EIO;
2884 goto err;
2885
2886 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2887 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2888 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2889 u8 data = FLD_GET(val, 15, 8);
2890 if (dsi->debug_read)
2891 DSSDBG("\t%s short response, 1 byte: %02x\n",
2892 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2893 "DCS", data);
2894
2895 if (buflen < 1) {
2896 r = -EIO;
2897 goto err;
2898 }
2899
2900 buf[0] = data;
2901
2902 return 1;
2903 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2904 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2905 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2906 u16 data = FLD_GET(val, 23, 8);
2907 if (dsi->debug_read)
2908 DSSDBG("\t%s short response, 2 byte: %04x\n",
2909 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2910 "DCS", data);
2911
2912 if (buflen < 2) {
2913 r = -EIO;
2914 goto err;
2915 }
2916
2917 buf[0] = data & 0xff;
2918 buf[1] = (data >> 8) & 0xff;
2919
2920 return 2;
2921 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2922 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
2923 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
2924 int w;
2925 int len = FLD_GET(val, 23, 8);
2926 if (dsi->debug_read)
2927 DSSDBG("\t%s long response, len %d\n",
2928 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2929 "DCS", len);
2930
2931 if (len > buflen) {
2932 r = -EIO;
2933 goto err;
2934 }
2935
2936 /* two byte checksum ends the packet, not included in len */
2937 for (w = 0; w < len + 2;) {
2938 int b;
2939 val = dsi_read_reg(dsi,
2940 DSI_VC_SHORT_PACKET_HEADER(channel));
2941 if (dsi->debug_read)
2942 DSSDBG("\t\t%02x %02x %02x %02x\n",
2943 (val >> 0) & 0xff,
2944 (val >> 8) & 0xff,
2945 (val >> 16) & 0xff,
2946 (val >> 24) & 0xff);
2947
2948 for (b = 0; b < 4; ++b) {
2949 if (w < len)
2950 buf[w] = (val >> (b * 8)) & 0xff;
2951 /* we discard the 2 byte checksum */
2952 ++w;
2953 }
2954 }
2955
2956 return len;
2957 } else {
2958 DSSERR("\tunknown datatype 0x%02x\n", dt);
2959 r = -EIO;
2960 goto err;
2961 }
2962
2963err:
2964 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
2965 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
2966
2967 return r;
2968}
2969
2970static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
2971 u8 *buf, int buflen)
2972{
2973 struct dsi_data *dsi = to_dsi_data(dssdev);
2974 int r;
2975
2976 r = dsi_vc_dcs_send_read_request(dsi, channel, dcs_cmd);
2977 if (r)
2978 goto err;
2979
2980 r = dsi_vc_send_bta_sync(dssdev, channel);
2981 if (r)
2982 goto err;
2983
2984 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
2985 DSS_DSI_CONTENT_DCS);
2986 if (r < 0)
2987 goto err;
2988
2989 if (r != buflen) {
2990 r = -EIO;
2991 goto err;
2992 }
2993
2994 return 0;
2995err:
2996 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
2997 return r;
2998}
2999
3000static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3001 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3002{
3003 struct dsi_data *dsi = to_dsi_data(dssdev);
3004 int r;
3005
3006 r = dsi_vc_generic_send_read_request(dsi, channel, reqdata, reqlen);
3007 if (r)
3008 return r;
3009
3010 r = dsi_vc_send_bta_sync(dssdev, channel);
3011 if (r)
3012 return r;
3013
3014 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
3015 DSS_DSI_CONTENT_GENERIC);
3016 if (r < 0)
3017 return r;
3018
3019 if (r != buflen) {
3020 r = -EIO;
3021 return r;
3022 }
3023
3024 return 0;
3025}
3026
3027static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3028 u16 len)
3029{
3030 struct dsi_data *dsi = to_dsi_data(dssdev);
3031
3032 return dsi_vc_send_short(dsi, channel,
3033 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3034}
3035
3036static int dsi_enter_ulps(struct dsi_data *dsi)
3037{
3038 DECLARE_COMPLETION_ONSTACK(completion);
3039 int r, i;
3040 unsigned int mask;
3041
3042 DSSDBG("Entering ULPS");
3043
3044 WARN_ON(!dsi_bus_is_locked(dsi));
3045
3046 WARN_ON(dsi->ulps_enabled);
3047
3048 if (dsi->ulps_enabled)
3049 return 0;
3050
3051 /* DDR_CLK_ALWAYS_ON */
3052 if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) {
3053 dsi_if_enable(dsi, 0);
3054 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
3055 dsi_if_enable(dsi, 1);
3056 }
3057
3058 dsi_sync_vc(dsi, 0);
3059 dsi_sync_vc(dsi, 1);
3060 dsi_sync_vc(dsi, 2);
3061 dsi_sync_vc(dsi, 3);
3062
3063 dsi_force_tx_stop_mode_io(dsi);
3064
3065 dsi_vc_enable(dsi, 0, false);
3066 dsi_vc_enable(dsi, 1, false);
3067 dsi_vc_enable(dsi, 2, false);
3068 dsi_vc_enable(dsi, 3, false);
3069
3070 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3071 DSSERR("HS busy when enabling ULPS\n");
3072 return -EIO;
3073 }
3074
3075 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3076 DSSERR("LP busy when enabling ULPS\n");
3077 return -EIO;
3078 }
3079
3080 r = dsi_register_isr_cio(dsi, dsi_completion_handler, &completion,
3081 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3082 if (r)
3083 return r;
3084
3085 mask = 0;
3086
3087 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3088 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3089 continue;
3090 mask |= 1 << i;
3091 }
3092 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3093 /* LANEx_ULPS_SIG2 */
3094 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3095
3096 /* flush posted write and wait for SCP interface to finish the write */
3097 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3098
3099 if (wait_for_completion_timeout(&completion,
3100 msecs_to_jiffies(1000)) == 0) {
3101 DSSERR("ULPS enable timeout\n");
3102 r = -EIO;
3103 goto err;
3104 }
3105
3106 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3107 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3108
3109 /* Reset LANEx_ULPS_SIG2 */
3110 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3111
3112 /* flush posted write and wait for SCP interface to finish the write */
3113 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3114
3115 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ULPS);
3116
3117 dsi_if_enable(dsi, false);
3118
3119 dsi->ulps_enabled = true;
3120
3121 return 0;
3122
3123err:
3124 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3125 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3126 return r;
3127}
3128
3129static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks,
3130 bool x4, bool x16)
3131{
3132 unsigned long fck;
3133 unsigned long total_ticks;
3134 u32 r;
3135
3136 BUG_ON(ticks > 0x1fff);
3137
3138 /* ticks in DSI_FCK */
3139 fck = dsi_fclk_rate(dsi);
3140
3141 r = dsi_read_reg(dsi, DSI_TIMING2);
3142 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3143 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3144 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3145 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3146 dsi_write_reg(dsi, DSI_TIMING2, r);
3147
3148 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3149
3150 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3151 total_ticks,
3152 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3153 (total_ticks * 1000) / (fck / 1000 / 1000));
3154}
3155
3156static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks,
3157 bool x8, bool x16)
3158{
3159 unsigned long fck;
3160 unsigned long total_ticks;
3161 u32 r;
3162
3163 BUG_ON(ticks > 0x1fff);
3164
3165 /* ticks in DSI_FCK */
3166 fck = dsi_fclk_rate(dsi);
3167
3168 r = dsi_read_reg(dsi, DSI_TIMING1);
3169 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3170 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3171 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3172 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3173 dsi_write_reg(dsi, DSI_TIMING1, r);
3174
3175 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3176
3177 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3178 total_ticks,
3179 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3180 (total_ticks * 1000) / (fck / 1000 / 1000));
3181}
3182
3183static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks,
3184 bool x4, bool x16)
3185{
3186 unsigned long fck;
3187 unsigned long total_ticks;
3188 u32 r;
3189
3190 BUG_ON(ticks > 0x1fff);
3191
3192 /* ticks in DSI_FCK */
3193 fck = dsi_fclk_rate(dsi);
3194
3195 r = dsi_read_reg(dsi, DSI_TIMING1);
3196 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3197 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3198 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3199 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3200 dsi_write_reg(dsi, DSI_TIMING1, r);
3201
3202 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3203
3204 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3205 total_ticks,
3206 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3207 (total_ticks * 1000) / (fck / 1000 / 1000));
3208}
3209
3210static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks,
3211 bool x4, bool x16)
3212{
3213 unsigned long fck;
3214 unsigned long total_ticks;
3215 u32 r;
3216
3217 BUG_ON(ticks > 0x1fff);
3218
3219 /* ticks in TxByteClkHS */
3220 fck = dsi_get_txbyteclkhs(dsi);
3221
3222 r = dsi_read_reg(dsi, DSI_TIMING2);
3223 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3224 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3225 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3226 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3227 dsi_write_reg(dsi, DSI_TIMING2, r);
3228
3229 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3230
3231 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3232 total_ticks,
3233 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3234 (total_ticks * 1000) / (fck / 1000 / 1000));
3235}
3236
3237static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi)
3238{
3239 int num_line_buffers;
3240
3241 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3242 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3243 const struct videomode *vm = &dsi->vm;
3244 /*
3245 * Don't use line buffers if width is greater than the video
3246 * port's line buffer size
3247 */
3248 if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
3249 num_line_buffers = 0;
3250 else
3251 num_line_buffers = 2;
3252 } else {
3253 /* Use maximum number of line buffers in command mode */
3254 num_line_buffers = 2;
3255 }
3256
3257 /* LINE_BUFFER */
3258 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12);
3259}
3260
3261static void dsi_config_vp_sync_events(struct dsi_data *dsi)
3262{
3263 bool sync_end;
3264 u32 r;
3265
3266 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3267 sync_end = true;
3268 else
3269 sync_end = false;
3270
3271 r = dsi_read_reg(dsi, DSI_CTRL);
3272 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3273 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3274 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3275 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3276 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3277 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3278 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3279 dsi_write_reg(dsi, DSI_CTRL, r);
3280}
3281
3282static void dsi_config_blanking_modes(struct dsi_data *dsi)
3283{
3284 int blanking_mode = dsi->vm_timings.blanking_mode;
3285 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3286 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3287 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3288 u32 r;
3289
3290 /*
3291 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3292 * 1 = Long blanking packets are sent in corresponding blanking periods
3293 */
3294 r = dsi_read_reg(dsi, DSI_CTRL);
3295 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3296 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3297 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3298 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3299 dsi_write_reg(dsi, DSI_CTRL, r);
3300}
3301
3302/*
3303 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3304 * results in maximum transition time for data and clock lanes to enter and
3305 * exit HS mode. Hence, this is the scenario where the least amount of command
3306 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3307 * clock cycles that can be used to interleave command mode data in HS so that
3308 * all scenarios are satisfied.
3309 */
3310static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3311 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3312{
3313 int transition;
3314
3315 /*
3316 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3317 * time of data lanes only, if it isn't set, we need to consider HS
3318 * transition time of both data and clock lanes. HS transition time
3319 * of Scenario 3 is considered.
3320 */
3321 if (ddr_alwon) {
3322 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3323 } else {
3324 int trans1, trans2;
3325 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3326 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3327 enter_hs + 1;
3328 transition = max(trans1, trans2);
3329 }
3330
3331 return blank > transition ? blank - transition : 0;
3332}
3333
3334/*
3335 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3336 * results in maximum transition time for data lanes to enter and exit LP mode.
3337 * Hence, this is the scenario where the least amount of command mode data can
3338 * be interleaved. We program the minimum amount of bytes that can be
3339 * interleaved in LP so that all scenarios are satisfied.
3340 */
3341static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3342 int lp_clk_div, int tdsi_fclk)
3343{
3344 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3345 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3346 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3347 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3348 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3349
3350 /* maximum LP transition time according to Scenario 1 */
3351 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3352
3353 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3354 tlp_avail = thsbyte_clk * (blank - trans_lp);
3355
3356 ttxclkesc = tdsi_fclk * lp_clk_div;
3357
3358 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3359 26) / 16;
3360
3361 return max(lp_inter, 0);
3362}
3363
3364static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi)
3365{
3366 int blanking_mode;
3367 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3368 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3369 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3370 int tclk_trail, ths_exit, exiths_clk;
3371 bool ddr_alwon;
3372 const struct videomode *vm = &dsi->vm;
3373 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3374 int ndl = dsi->num_lanes_used - 1;
3375 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3376 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3377 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3378 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3379 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3380 u32 r;
3381
3382 r = dsi_read_reg(dsi, DSI_CTRL);
3383 blanking_mode = FLD_GET(r, 20, 20);
3384 hfp_blanking_mode = FLD_GET(r, 21, 21);
3385 hbp_blanking_mode = FLD_GET(r, 22, 22);
3386 hsa_blanking_mode = FLD_GET(r, 23, 23);
3387
3388 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3389 hbp = FLD_GET(r, 11, 0);
3390 hfp = FLD_GET(r, 23, 12);
3391 hsa = FLD_GET(r, 31, 24);
3392
3393 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3394 ddr_clk_post = FLD_GET(r, 7, 0);
3395 ddr_clk_pre = FLD_GET(r, 15, 8);
3396
3397 r = dsi_read_reg(dsi, DSI_VM_TIMING7);
3398 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3399 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3400
3401 r = dsi_read_reg(dsi, DSI_CLK_CTRL);
3402 lp_clk_div = FLD_GET(r, 12, 0);
3403 ddr_alwon = FLD_GET(r, 13, 13);
3404
3405 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3406 ths_exit = FLD_GET(r, 7, 0);
3407
3408 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3409 tclk_trail = FLD_GET(r, 15, 8);
3410
3411 exiths_clk = ths_exit + tclk_trail;
3412
3413 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3414 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3415
3416 if (!hsa_blanking_mode) {
3417 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3418 enter_hs_mode_lat, exit_hs_mode_lat,
3419 exiths_clk, ddr_clk_pre, ddr_clk_post);
3420 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3421 enter_hs_mode_lat, exit_hs_mode_lat,
3422 lp_clk_div, dsi_fclk_hsdiv);
3423 }
3424
3425 if (!hfp_blanking_mode) {
3426 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3427 enter_hs_mode_lat, exit_hs_mode_lat,
3428 exiths_clk, ddr_clk_pre, ddr_clk_post);
3429 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3430 enter_hs_mode_lat, exit_hs_mode_lat,
3431 lp_clk_div, dsi_fclk_hsdiv);
3432 }
3433
3434 if (!hbp_blanking_mode) {
3435 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3436 enter_hs_mode_lat, exit_hs_mode_lat,
3437 exiths_clk, ddr_clk_pre, ddr_clk_post);
3438
3439 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3440 enter_hs_mode_lat, exit_hs_mode_lat,
3441 lp_clk_div, dsi_fclk_hsdiv);
3442 }
3443
3444 if (!blanking_mode) {
3445 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3446 enter_hs_mode_lat, exit_hs_mode_lat,
3447 exiths_clk, ddr_clk_pre, ddr_clk_post);
3448
3449 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3450 enter_hs_mode_lat, exit_hs_mode_lat,
3451 lp_clk_div, dsi_fclk_hsdiv);
3452 }
3453
3454 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3455 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3456 bl_interleave_hs);
3457
3458 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3459 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3460 bl_interleave_lp);
3461
3462 r = dsi_read_reg(dsi, DSI_VM_TIMING4);
3463 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3464 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3465 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3466 dsi_write_reg(dsi, DSI_VM_TIMING4, r);
3467
3468 r = dsi_read_reg(dsi, DSI_VM_TIMING5);
3469 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3470 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3471 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3472 dsi_write_reg(dsi, DSI_VM_TIMING5, r);
3473
3474 r = dsi_read_reg(dsi, DSI_VM_TIMING6);
3475 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3476 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3477 dsi_write_reg(dsi, DSI_VM_TIMING6, r);
3478}
3479
3480static int dsi_proto_config(struct dsi_data *dsi)
3481{
3482 u32 r;
3483 int buswidth = 0;
3484
3485 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32,
3486 DSI_FIFO_SIZE_32,
3487 DSI_FIFO_SIZE_32,
3488 DSI_FIFO_SIZE_32);
3489
3490 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32,
3491 DSI_FIFO_SIZE_32,
3492 DSI_FIFO_SIZE_32,
3493 DSI_FIFO_SIZE_32);
3494
3495 /* XXX what values for the timeouts? */
3496 dsi_set_stop_state_counter(dsi, 0x1000, false, false);
3497 dsi_set_ta_timeout(dsi, 0x1fff, true, true);
3498 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true);
3499 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true);
3500
3501 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3502 case 16:
3503 buswidth = 0;
3504 break;
3505 case 18:
3506 buswidth = 1;
3507 break;
3508 case 24:
3509 buswidth = 2;
3510 break;
3511 default:
3512 BUG();
3513 return -EINVAL;
3514 }
3515
3516 r = dsi_read_reg(dsi, DSI_CTRL);
3517 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3518 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3519 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3520 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3521 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3522 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3523 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3524 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3525 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) {
3526 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3527 /* DCS_CMD_CODE, 1=start, 0=continue */
3528 r = FLD_MOD(r, 0, 25, 25);
3529 }
3530
3531 dsi_write_reg(dsi, DSI_CTRL, r);
3532
3533 dsi_config_vp_num_line_buffers(dsi);
3534
3535 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3536 dsi_config_vp_sync_events(dsi);
3537 dsi_config_blanking_modes(dsi);
3538 dsi_config_cmd_mode_interleaving(dsi);
3539 }
3540
3541 dsi_vc_initial_config(dsi, 0);
3542 dsi_vc_initial_config(dsi, 1);
3543 dsi_vc_initial_config(dsi, 2);
3544 dsi_vc_initial_config(dsi, 3);
3545
3546 return 0;
3547}
3548
3549static void dsi_proto_timings(struct dsi_data *dsi)
3550{
3551 unsigned int tlpx, tclk_zero, tclk_prepare, tclk_trail;
3552 unsigned int tclk_pre, tclk_post;
3553 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero;
3554 unsigned int ths_trail, ths_exit;
3555 unsigned int ddr_clk_pre, ddr_clk_post;
3556 unsigned int enter_hs_mode_lat, exit_hs_mode_lat;
3557 unsigned int ths_eot;
3558 int ndl = dsi->num_lanes_used - 1;
3559 u32 r;
3560
3561 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3562 ths_prepare = FLD_GET(r, 31, 24);
3563 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3564 ths_zero = ths_prepare_ths_zero - ths_prepare;
3565 ths_trail = FLD_GET(r, 15, 8);
3566 ths_exit = FLD_GET(r, 7, 0);
3567
3568 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3569 tlpx = FLD_GET(r, 20, 16) * 2;
3570 tclk_trail = FLD_GET(r, 15, 8);
3571 tclk_zero = FLD_GET(r, 7, 0);
3572
3573 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
3574 tclk_prepare = FLD_GET(r, 7, 0);
3575
3576 /* min 8*UI */
3577 tclk_pre = 20;
3578 /* min 60ns + 52*UI */
3579 tclk_post = ns2ddr(dsi, 60) + 26;
3580
3581 ths_eot = DIV_ROUND_UP(4, ndl);
3582
3583 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3584 4);
3585 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3586
3587 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3588 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3589
3590 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3591 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3592 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3593 dsi_write_reg(dsi, DSI_CLK_TIMING, r);
3594
3595 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3596 ddr_clk_pre,
3597 ddr_clk_post);
3598
3599 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3600 DIV_ROUND_UP(ths_prepare, 4) +
3601 DIV_ROUND_UP(ths_zero + 3, 4);
3602
3603 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3604
3605 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3606 FLD_VAL(exit_hs_mode_lat, 15, 0);
3607 dsi_write_reg(dsi, DSI_VM_TIMING7, r);
3608
3609 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3610 enter_hs_mode_lat, exit_hs_mode_lat);
3611
3612 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3613 /* TODO: Implement a video mode check_timings function */
3614 int hsa = dsi->vm_timings.hsa;
3615 int hfp = dsi->vm_timings.hfp;
3616 int hbp = dsi->vm_timings.hbp;
3617 int vsa = dsi->vm_timings.vsa;
3618 int vfp = dsi->vm_timings.vfp;
3619 int vbp = dsi->vm_timings.vbp;
3620 int window_sync = dsi->vm_timings.window_sync;
3621 bool hsync_end;
3622 const struct videomode *vm = &dsi->vm;
3623 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3624 int tl, t_he, width_bytes;
3625
3626 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3627 t_he = hsync_end ?
3628 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3629
3630 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3631
3632 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3633 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3634 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3635
3636 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3637 hfp, hsync_end ? hsa : 0, tl);
3638 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3639 vsa, vm->vactive);
3640
3641 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3642 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3643 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3644 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3645 dsi_write_reg(dsi, DSI_VM_TIMING1, r);
3646
3647 r = dsi_read_reg(dsi, DSI_VM_TIMING2);
3648 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3649 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3650 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3651 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3652 dsi_write_reg(dsi, DSI_VM_TIMING2, r);
3653
3654 r = dsi_read_reg(dsi, DSI_VM_TIMING3);
3655 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */
3656 r = FLD_MOD(r, tl, 31, 16); /* TL */
3657 dsi_write_reg(dsi, DSI_VM_TIMING3, r);
3658 }
3659}
3660
3661static int dsi_configure_pins(struct omap_dss_device *dssdev,
3662 const struct omap_dsi_pin_config *pin_cfg)
3663{
3664 struct dsi_data *dsi = to_dsi_data(dssdev);
3665 int num_pins;
3666 const int *pins;
3667 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3668 int num_lanes;
3669 int i;
3670
3671 static const enum dsi_lane_function functions[] = {
3672 DSI_LANE_CLK,
3673 DSI_LANE_DATA1,
3674 DSI_LANE_DATA2,
3675 DSI_LANE_DATA3,
3676 DSI_LANE_DATA4,
3677 };
3678
3679 num_pins = pin_cfg->num_pins;
3680 pins = pin_cfg->pins;
3681
3682 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3683 || num_pins % 2 != 0)
3684 return -EINVAL;
3685
3686 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3687 lanes[i].function = DSI_LANE_UNUSED;
3688
3689 num_lanes = 0;
3690
3691 for (i = 0; i < num_pins; i += 2) {
3692 u8 lane, pol;
3693 int dx, dy;
3694
3695 dx = pins[i];
3696 dy = pins[i + 1];
3697
3698 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3699 return -EINVAL;
3700
3701 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3702 return -EINVAL;
3703
3704 if (dx & 1) {
3705 if (dy != dx - 1)
3706 return -EINVAL;
3707 pol = 1;
3708 } else {
3709 if (dy != dx + 1)
3710 return -EINVAL;
3711 pol = 0;
3712 }
3713
3714 lane = dx / 2;
3715
3716 lanes[lane].function = functions[i / 2];
3717 lanes[lane].polarity = pol;
3718 num_lanes++;
3719 }
3720
3721 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3722 dsi->num_lanes_used = num_lanes;
3723
3724 return 0;
3725}
3726
3727static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3728{
3729 struct dsi_data *dsi = to_dsi_data(dssdev);
3730 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3731 u8 data_type;
3732 u16 word_count;
3733 int r;
3734
3735 r = dsi_display_init_dispc(dsi);
3736 if (r)
3737 return r;
3738
3739 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3740 switch (dsi->pix_fmt) {
3741 case OMAP_DSS_DSI_FMT_RGB888:
3742 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3743 break;
3744 case OMAP_DSS_DSI_FMT_RGB666:
3745 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3746 break;
3747 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3748 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3749 break;
3750 case OMAP_DSS_DSI_FMT_RGB565:
3751 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3752 break;
3753 default:
3754 r = -EINVAL;
3755 goto err_pix_fmt;
3756 }
3757
3758 dsi_if_enable(dsi, false);
3759 dsi_vc_enable(dsi, channel, false);
3760
3761 /* MODE, 1 = video mode */
3762 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4);
3763
3764 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3765
3766 dsi_vc_write_long_header(dsi, channel, data_type,
3767 word_count, 0);
3768
3769 dsi_vc_enable(dsi, channel, true);
3770 dsi_if_enable(dsi, true);
3771 }
3772
3773 r = dss_mgr_enable(&dsi->output);
3774 if (r)
3775 goto err_mgr_enable;
3776
3777 return 0;
3778
3779err_mgr_enable:
3780 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3781 dsi_if_enable(dsi, false);
3782 dsi_vc_enable(dsi, channel, false);
3783 }
3784err_pix_fmt:
3785 dsi_display_uninit_dispc(dsi);
3786 return r;
3787}
3788
3789static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3790{
3791 struct dsi_data *dsi = to_dsi_data(dssdev);
3792
3793 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3794 dsi_if_enable(dsi, false);
3795 dsi_vc_enable(dsi, channel, false);
3796
3797 /* MODE, 0 = command mode */
3798 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4);
3799
3800 dsi_vc_enable(dsi, channel, true);
3801 dsi_if_enable(dsi, true);
3802 }
3803
3804 dss_mgr_disable(&dsi->output);
3805
3806 dsi_display_uninit_dispc(dsi);
3807}
3808
3809static void dsi_update_screen_dispc(struct dsi_data *dsi)
3810{
3811 unsigned int bytespp;
3812 unsigned int bytespl;
3813 unsigned int bytespf;
3814 unsigned int total_len;
3815 unsigned int packet_payload;
3816 unsigned int packet_len;
3817 u32 l;
3818 int r;
3819 const unsigned channel = dsi->update_channel;
3820 const unsigned int line_buf_size = dsi->line_buffer_size;
3821 u16 w = dsi->vm.hactive;
3822 u16 h = dsi->vm.vactive;
3823
3824 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3825
3826 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_VP);
3827
3828 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
3829 bytespl = w * bytespp;
3830 bytespf = bytespl * h;
3831
3832 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3833 * number of lines in a packet. See errata about VP_CLK_RATIO */
3834
3835 if (bytespf < line_buf_size)
3836 packet_payload = bytespf;
3837 else
3838 packet_payload = (line_buf_size) / bytespl * bytespl;
3839
3840 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3841 total_len = (bytespf / packet_payload) * packet_len;
3842
3843 if (bytespf % packet_payload)
3844 total_len += (bytespf % packet_payload) + 1;
3845
3846 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3847 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
3848
3849 dsi_vc_write_long_header(dsi, channel, MIPI_DSI_DCS_LONG_WRITE,
3850 packet_len, 0);
3851
3852 if (dsi->te_enabled)
3853 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3854 else
3855 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3856 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
3857
3858 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3859 * because DSS interrupts are not capable of waking up the CPU and the
3860 * framedone interrupt could be delayed for quite a long time. I think
3861 * the same goes for any DSS interrupts, but for some reason I have not
3862 * seen the problem anywhere else than here.
3863 */
3864 dispc_disable_sidle(dsi->dss->dispc);
3865
3866 dsi_perf_mark_start(dsi);
3867
3868 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3869 msecs_to_jiffies(250));
3870 BUG_ON(r == 0);
3871
3872 dss_mgr_start_update(&dsi->output);
3873
3874 if (dsi->te_enabled) {
3875 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3876 * for TE is longer than the timer allows */
3877 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3878
3879 dsi_vc_send_bta(dsi, channel);
3880
3881#ifdef DSI_CATCH_MISSING_TE
3882 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3883#endif
3884 }
3885}
3886
3887#ifdef DSI_CATCH_MISSING_TE
3888static void dsi_te_timeout(struct timer_list *unused)
3889{
3890 DSSERR("TE not received for 250ms!\n");
3891}
3892#endif
3893
3894static void dsi_handle_framedone(struct dsi_data *dsi, int error)
3895{
3896 /* SIDLEMODE back to smart-idle */
3897 dispc_enable_sidle(dsi->dss->dispc);
3898
3899 if (dsi->te_enabled) {
3900 /* enable LP_RX_TO again after the TE */
3901 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3902 }
3903
3904 dsi->framedone_callback(error, dsi->framedone_data);
3905
3906 if (!error)
3907 dsi_perf_show(dsi, "DISPC");
3908}
3909
3910static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3911{
3912 struct dsi_data *dsi = container_of(work, struct dsi_data,
3913 framedone_timeout_work.work);
3914 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3915 * 250ms which would conflict with this timeout work. What should be
3916 * done is first cancel the transfer on the HW, and then cancel the
3917 * possibly scheduled framedone work. However, cancelling the transfer
3918 * on the HW is buggy, and would probably require resetting the whole
3919 * DSI */
3920
3921 DSSERR("Framedone not received for 250ms!\n");
3922
3923 dsi_handle_framedone(dsi, -ETIMEDOUT);
3924}
3925
3926static void dsi_framedone_irq_callback(void *data)
3927{
3928 struct dsi_data *dsi = data;
3929
3930 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3931 * turns itself off. However, DSI still has the pixels in its buffers,
3932 * and is sending the data.
3933 */
3934
3935 cancel_delayed_work(&dsi->framedone_timeout_work);
3936
3937 dsi_handle_framedone(dsi, 0);
3938}
3939
3940static int dsi_update(struct omap_dss_device *dssdev, int channel,
3941 void (*callback)(int, void *), void *data)
3942{
3943 struct dsi_data *dsi = to_dsi_data(dssdev);
3944 u16 dw, dh;
3945
3946 dsi_perf_mark_setup(dsi);
3947
3948 dsi->update_channel = channel;
3949
3950 dsi->framedone_callback = callback;
3951 dsi->framedone_data = data;
3952
3953 dw = dsi->vm.hactive;
3954 dh = dsi->vm.vactive;
3955
3956#ifdef DSI_PERF_MEASURE
3957 dsi->update_bytes = dw * dh *
3958 dsi_get_pixel_size(dsi->pix_fmt) / 8;
3959#endif
3960 dsi_update_screen_dispc(dsi);
3961
3962 return 0;
3963}
3964
3965/* Display funcs */
3966
3967static int dsi_configure_dispc_clocks(struct dsi_data *dsi)
3968{
3969 struct dispc_clock_info dispc_cinfo;
3970 int r;
3971 unsigned long fck;
3972
3973 fck = dsi_get_pll_hsdiv_dispc_rate(dsi);
3974
3975 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
3976 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
3977
3978 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo);
3979 if (r) {
3980 DSSERR("Failed to calc dispc clocks\n");
3981 return r;
3982 }
3983
3984 dsi->mgr_config.clock_info = dispc_cinfo;
3985
3986 return 0;
3987}
3988
3989static int dsi_display_init_dispc(struct dsi_data *dsi)
3990{
3991 enum omap_channel channel = dsi->output.dispc_channel;
3992 int r;
3993
3994 dss_select_lcd_clk_source(dsi->dss, channel, dsi->module_id == 0 ?
3995 DSS_CLK_SRC_PLL1_1 :
3996 DSS_CLK_SRC_PLL2_1);
3997
3998 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
3999 r = dss_mgr_register_framedone_handler(&dsi->output,
4000 dsi_framedone_irq_callback, dsi);
4001 if (r) {
4002 DSSERR("can't register FRAMEDONE handler\n");
4003 goto err;
4004 }
4005
4006 dsi->mgr_config.stallmode = true;
4007 dsi->mgr_config.fifohandcheck = true;
4008 } else {
4009 dsi->mgr_config.stallmode = false;
4010 dsi->mgr_config.fifohandcheck = false;
4011 }
4012
4013 r = dsi_configure_dispc_clocks(dsi);
4014 if (r)
4015 goto err1;
4016
4017 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4018 dsi->mgr_config.video_port_width =
4019 dsi_get_pixel_size(dsi->pix_fmt);
4020 dsi->mgr_config.lcden_sig_polarity = 0;
4021
4022 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config);
4023
4024 return 0;
4025err1:
4026 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4027 dss_mgr_unregister_framedone_handler(&dsi->output,
4028 dsi_framedone_irq_callback, dsi);
4029err:
4030 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4031 return r;
4032}
4033
4034static void dsi_display_uninit_dispc(struct dsi_data *dsi)
4035{
4036 enum omap_channel channel = dsi->output.dispc_channel;
4037
4038 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4039 dss_mgr_unregister_framedone_handler(&dsi->output,
4040 dsi_framedone_irq_callback, dsi);
4041
4042 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4043}
4044
4045static int dsi_configure_dsi_clocks(struct dsi_data *dsi)
4046{
4047 struct dss_pll_clock_info cinfo;
4048 int r;
4049
4050 cinfo = dsi->user_dsi_cinfo;
4051
4052 r = dss_pll_set_config(&dsi->pll, &cinfo);
4053 if (r) {
4054 DSSERR("Failed to set dsi clocks\n");
4055 return r;
4056 }
4057
4058 return 0;
4059}
4060
4061static int dsi_display_init_dsi(struct dsi_data *dsi)
4062{
4063 int r;
4064
4065 r = dss_pll_enable(&dsi->pll);
4066 if (r)
4067 return r;
4068
4069 r = dsi_configure_dsi_clocks(dsi);
4070 if (r)
4071 goto err0;
4072
4073 dss_select_dsi_clk_source(dsi->dss, dsi->module_id,
4074 dsi->module_id == 0 ?
4075 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2);
4076
4077 DSSDBG("PLL OK\n");
4078
4079 if (!dsi->vdds_dsi_enabled) {
4080 r = regulator_enable(dsi->vdds_dsi_reg);
4081 if (r)
4082 goto err1;
4083
4084 dsi->vdds_dsi_enabled = true;
4085 }
4086
4087 r = dsi_cio_init(dsi);
4088 if (r)
4089 goto err2;
4090
4091 _dsi_print_reset_status(dsi);
4092
4093 dsi_proto_timings(dsi);
4094 dsi_set_lp_clk_divisor(dsi);
4095
4096 if (1)
4097 _dsi_print_reset_status(dsi);
4098
4099 r = dsi_proto_config(dsi);
4100 if (r)
4101 goto err3;
4102
4103 /* enable interface */
4104 dsi_vc_enable(dsi, 0, 1);
4105 dsi_vc_enable(dsi, 1, 1);
4106 dsi_vc_enable(dsi, 2, 1);
4107 dsi_vc_enable(dsi, 3, 1);
4108 dsi_if_enable(dsi, 1);
4109 dsi_force_tx_stop_mode_io(dsi);
4110
4111 return 0;
4112err3:
4113 dsi_cio_uninit(dsi);
4114err2:
4115 regulator_disable(dsi->vdds_dsi_reg);
4116 dsi->vdds_dsi_enabled = false;
4117err1:
4118 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4119err0:
4120 dss_pll_disable(&dsi->pll);
4121
4122 return r;
4123}
4124
4125static void dsi_display_uninit_dsi(struct dsi_data *dsi, bool disconnect_lanes,
4126 bool enter_ulps)
4127{
4128 if (enter_ulps && !dsi->ulps_enabled)
4129 dsi_enter_ulps(dsi);
4130
4131 /* disable interface */
4132 dsi_if_enable(dsi, 0);
4133 dsi_vc_enable(dsi, 0, 0);
4134 dsi_vc_enable(dsi, 1, 0);
4135 dsi_vc_enable(dsi, 2, 0);
4136 dsi_vc_enable(dsi, 3, 0);
4137
4138 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4139 dsi_cio_uninit(dsi);
4140 dss_pll_disable(&dsi->pll);
4141
4142 if (disconnect_lanes) {
4143 regulator_disable(dsi->vdds_dsi_reg);
4144 dsi->vdds_dsi_enabled = false;
4145 }
4146}
4147
4148static void dsi_display_enable(struct omap_dss_device *dssdev)
4149{
4150 struct dsi_data *dsi = to_dsi_data(dssdev);
4151 int r;
4152
4153 DSSDBG("dsi_display_enable\n");
4154
4155 WARN_ON(!dsi_bus_is_locked(dsi));
4156
4157 mutex_lock(&dsi->lock);
4158
4159 r = dsi_runtime_get(dsi);
4160 if (r)
4161 goto err_get_dsi;
4162
4163 _dsi_initialize_irq(dsi);
4164
4165 r = dsi_display_init_dsi(dsi);
4166 if (r)
4167 goto err_init_dsi;
4168
4169 mutex_unlock(&dsi->lock);
4170
4171 return;
4172
4173err_init_dsi:
4174 dsi_runtime_put(dsi);
4175err_get_dsi:
4176 mutex_unlock(&dsi->lock);
4177 DSSDBG("dsi_display_enable FAILED\n");
4178}
4179
4180static void dsi_display_disable(struct omap_dss_device *dssdev,
4181 bool disconnect_lanes, bool enter_ulps)
4182{
4183 struct dsi_data *dsi = to_dsi_data(dssdev);
4184
4185 DSSDBG("dsi_display_disable\n");
4186
4187 WARN_ON(!dsi_bus_is_locked(dsi));
4188
4189 mutex_lock(&dsi->lock);
4190
4191 dsi_sync_vc(dsi, 0);
4192 dsi_sync_vc(dsi, 1);
4193 dsi_sync_vc(dsi, 2);
4194 dsi_sync_vc(dsi, 3);
4195
4196 dsi_display_uninit_dsi(dsi, disconnect_lanes, enter_ulps);
4197
4198 dsi_runtime_put(dsi);
4199
4200 mutex_unlock(&dsi->lock);
4201}
4202
4203static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4204{
4205 struct dsi_data *dsi = to_dsi_data(dssdev);
4206
4207 dsi->te_enabled = enable;
4208 return 0;
4209}
4210
4211#ifdef PRINT_VERBOSE_VM_TIMINGS
4212static void print_dsi_vm(const char *str,
4213 const struct omap_dss_dsi_videomode_timings *t)
4214{
4215 unsigned long byteclk = t->hsclk / 4;
4216 int bl, wc, pps, tot;
4217
4218 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4219 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4220 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4221 tot = bl + pps;
4222
4223#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4224
4225 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4226 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4227 str,
4228 byteclk,
4229 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4230 bl, pps, tot,
4231 TO_DSI_T(t->hss),
4232 TO_DSI_T(t->hsa),
4233 TO_DSI_T(t->hse),
4234 TO_DSI_T(t->hbp),
4235 TO_DSI_T(pps),
4236 TO_DSI_T(t->hfp),
4237
4238 TO_DSI_T(bl),
4239 TO_DSI_T(pps),
4240
4241 TO_DSI_T(tot));
4242#undef TO_DSI_T
4243}
4244
4245static void print_dispc_vm(const char *str, const struct videomode *vm)
4246{
4247 unsigned long pck = vm->pixelclock;
4248 int hact, bl, tot;
4249
4250 hact = vm->hactive;
4251 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch;
4252 tot = hact + bl;
4253
4254#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4255
4256 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4257 "%u/%u/%u/%u = %u + %u = %u\n",
4258 str,
4259 pck,
4260 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch,
4261 bl, hact, tot,
4262 TO_DISPC_T(vm->hsync_len),
4263 TO_DISPC_T(vm->hback_porch),
4264 TO_DISPC_T(hact),
4265 TO_DISPC_T(vm->hfront_porch),
4266 TO_DISPC_T(bl),
4267 TO_DISPC_T(hact),
4268 TO_DISPC_T(tot));
4269#undef TO_DISPC_T
4270}
4271
4272/* note: this is not quite accurate */
4273static void print_dsi_dispc_vm(const char *str,
4274 const struct omap_dss_dsi_videomode_timings *t)
4275{
4276 struct videomode vm = { 0 };
4277 unsigned long byteclk = t->hsclk / 4;
4278 unsigned long pck;
4279 u64 dsi_tput;
4280 int dsi_hact, dsi_htot;
4281
4282 dsi_tput = (u64)byteclk * t->ndl * 8;
4283 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4284 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4285 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4286
4287 vm.pixelclock = pck;
4288 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4289 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk);
4290 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk);
4291 vm.hactive = t->hact;
4292
4293 print_dispc_vm(str, &vm);
4294}
4295#endif /* PRINT_VERBOSE_VM_TIMINGS */
4296
4297static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4298 unsigned long pck, void *data)
4299{
4300 struct dsi_clk_calc_ctx *ctx = data;
4301 struct videomode *vm = &ctx->vm;
4302
4303 ctx->dispc_cinfo.lck_div = lckd;
4304 ctx->dispc_cinfo.pck_div = pckd;
4305 ctx->dispc_cinfo.lck = lck;
4306 ctx->dispc_cinfo.pck = pck;
4307
4308 *vm = *ctx->config->vm;
4309 vm->pixelclock = pck;
4310 vm->hactive = ctx->config->vm->hactive;
4311 vm->vactive = ctx->config->vm->vactive;
4312 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1;
4313 vm->vfront_porch = vm->vback_porch = 0;
4314
4315 return true;
4316}
4317
4318static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4319 void *data)
4320{
4321 struct dsi_clk_calc_ctx *ctx = data;
4322
4323 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4324 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4325
4326 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4327 ctx->req_pck_min, ctx->req_pck_max,
4328 dsi_cm_calc_dispc_cb, ctx);
4329}
4330
4331static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4332 unsigned long clkdco, void *data)
4333{
4334 struct dsi_clk_calc_ctx *ctx = data;
4335 struct dsi_data *dsi = ctx->dsi;
4336
4337 ctx->dsi_cinfo.n = n;
4338 ctx->dsi_cinfo.m = m;
4339 ctx->dsi_cinfo.fint = fint;
4340 ctx->dsi_cinfo.clkdco = clkdco;
4341
4342 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4343 dsi->data->max_fck_freq,
4344 dsi_cm_calc_hsdiv_cb, ctx);
4345}
4346
4347static bool dsi_cm_calc(struct dsi_data *dsi,
4348 const struct omap_dss_dsi_config *cfg,
4349 struct dsi_clk_calc_ctx *ctx)
4350{
4351 unsigned long clkin;
4352 int bitspp, ndl;
4353 unsigned long pll_min, pll_max;
4354 unsigned long pck, txbyteclk;
4355
4356 clkin = clk_get_rate(dsi->pll.clkin);
4357 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4358 ndl = dsi->num_lanes_used - 1;
4359
4360 /*
4361 * Here we should calculate minimum txbyteclk to be able to send the
4362 * frame in time, and also to handle TE. That's not very simple, though,
4363 * especially as we go to LP between each pixel packet due to HW
4364 * "feature". So let's just estimate very roughly and multiply by 1.5.
4365 */
4366 pck = cfg->vm->pixelclock;
4367 pck = pck * 3 / 2;
4368 txbyteclk = pck * bitspp / 8 / ndl;
4369
4370 memset(ctx, 0, sizeof(*ctx));
4371 ctx->dsi = dsi;
4372 ctx->pll = &dsi->pll;
4373 ctx->config = cfg;
4374 ctx->req_pck_min = pck;
4375 ctx->req_pck_nom = pck;
4376 ctx->req_pck_max = pck * 3 / 2;
4377
4378 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4379 pll_max = cfg->hs_clk_max * 4;
4380
4381 return dss_pll_calc_a(ctx->pll, clkin,
4382 pll_min, pll_max,
4383 dsi_cm_calc_pll_cb, ctx);
4384}
4385
4386static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4387{
4388 struct dsi_data *dsi = ctx->dsi;
4389 const struct omap_dss_dsi_config *cfg = ctx->config;
4390 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4391 int ndl = dsi->num_lanes_used - 1;
4392 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4393 unsigned long byteclk = hsclk / 4;
4394
4395 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4396 int xres;
4397 int panel_htot, panel_hbl; /* pixels */
4398 int dispc_htot, dispc_hbl; /* pixels */
4399 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4400 int hfp, hsa, hbp;
4401 const struct videomode *req_vm;
4402 struct videomode *dispc_vm;
4403 struct omap_dss_dsi_videomode_timings *dsi_vm;
4404 u64 dsi_tput, dispc_tput;
4405
4406 dsi_tput = (u64)byteclk * ndl * 8;
4407
4408 req_vm = cfg->vm;
4409 req_pck_min = ctx->req_pck_min;
4410 req_pck_max = ctx->req_pck_max;
4411 req_pck_nom = ctx->req_pck_nom;
4412
4413 dispc_pck = ctx->dispc_cinfo.pck;
4414 dispc_tput = (u64)dispc_pck * bitspp;
4415
4416 xres = req_vm->hactive;
4417
4418 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch +
4419 req_vm->hsync_len;
4420 panel_htot = xres + panel_hbl;
4421
4422 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4423
4424 /*
4425 * When there are no line buffers, DISPC and DSI must have the
4426 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4427 */
4428 if (dsi->line_buffer_size < xres * bitspp / 8) {
4429 if (dispc_tput != dsi_tput)
4430 return false;
4431 } else {
4432 if (dispc_tput < dsi_tput)
4433 return false;
4434 }
4435
4436 /* DSI tput must be over the min requirement */
4437 if (dsi_tput < (u64)bitspp * req_pck_min)
4438 return false;
4439
4440 /* When non-burst mode, DSI tput must be below max requirement. */
4441 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4442 if (dsi_tput > (u64)bitspp * req_pck_max)
4443 return false;
4444 }
4445
4446 hss = DIV_ROUND_UP(4, ndl);
4447
4448 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4449 if (ndl == 3 && req_vm->hsync_len == 0)
4450 hse = 1;
4451 else
4452 hse = DIV_ROUND_UP(4, ndl);
4453 } else {
4454 hse = 0;
4455 }
4456
4457 /* DSI htot to match the panel's nominal pck */
4458 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4459
4460 /* fail if there would be no time for blanking */
4461 if (dsi_htot < hss + hse + dsi_hact)
4462 return false;
4463
4464 /* total DSI blanking needed to achieve panel's TL */
4465 dsi_hbl = dsi_htot - dsi_hact;
4466
4467 /* DISPC htot to match the DSI TL */
4468 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4469
4470 /* verify that the DSI and DISPC TLs are the same */
4471 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4472 return false;
4473
4474 dispc_hbl = dispc_htot - xres;
4475
4476 /* setup DSI videomode */
4477
4478 dsi_vm = &ctx->dsi_vm;
4479 memset(dsi_vm, 0, sizeof(*dsi_vm));
4480
4481 dsi_vm->hsclk = hsclk;
4482
4483 dsi_vm->ndl = ndl;
4484 dsi_vm->bitspp = bitspp;
4485
4486 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4487 hsa = 0;
4488 } else if (ndl == 3 && req_vm->hsync_len == 0) {
4489 hsa = 0;
4490 } else {
4491 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
4492 hsa = max(hsa - hse, 1);
4493 }
4494
4495 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom);
4496 hbp = max(hbp, 1);
4497
4498 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4499 if (hfp < 1) {
4500 int t;
4501 /* we need to take cycles from hbp */
4502
4503 t = 1 - hfp;
4504 hbp = max(hbp - t, 1);
4505 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4506
4507 if (hfp < 1 && hsa > 0) {
4508 /* we need to take cycles from hsa */
4509 t = 1 - hfp;
4510 hsa = max(hsa - t, 1);
4511 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4512 }
4513 }
4514
4515 if (hfp < 1)
4516 return false;
4517
4518 dsi_vm->hss = hss;
4519 dsi_vm->hsa = hsa;
4520 dsi_vm->hse = hse;
4521 dsi_vm->hbp = hbp;
4522 dsi_vm->hact = xres;
4523 dsi_vm->hfp = hfp;
4524
4525 dsi_vm->vsa = req_vm->vsync_len;
4526 dsi_vm->vbp = req_vm->vback_porch;
4527 dsi_vm->vact = req_vm->vactive;
4528 dsi_vm->vfp = req_vm->vfront_porch;
4529
4530 dsi_vm->trans_mode = cfg->trans_mode;
4531
4532 dsi_vm->blanking_mode = 0;
4533 dsi_vm->hsa_blanking_mode = 1;
4534 dsi_vm->hfp_blanking_mode = 1;
4535 dsi_vm->hbp_blanking_mode = 1;
4536
4537 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4538 dsi_vm->window_sync = 4;
4539
4540 /* setup DISPC videomode */
4541
4542 dispc_vm = &ctx->vm;
4543 *dispc_vm = *req_vm;
4544 dispc_vm->pixelclock = dispc_pck;
4545
4546 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4547 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
4548 req_pck_nom);
4549 hsa = max(hsa, 1);
4550 } else {
4551 hsa = 1;
4552 }
4553
4554 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom);
4555 hbp = max(hbp, 1);
4556
4557 hfp = dispc_hbl - hsa - hbp;
4558 if (hfp < 1) {
4559 int t;
4560 /* we need to take cycles from hbp */
4561
4562 t = 1 - hfp;
4563 hbp = max(hbp - t, 1);
4564 hfp = dispc_hbl - hsa - hbp;
4565
4566 if (hfp < 1) {
4567 /* we need to take cycles from hsa */
4568 t = 1 - hfp;
4569 hsa = max(hsa - t, 1);
4570 hfp = dispc_hbl - hsa - hbp;
4571 }
4572 }
4573
4574 if (hfp < 1)
4575 return false;
4576
4577 dispc_vm->hfront_porch = hfp;
4578 dispc_vm->hsync_len = hsa;
4579 dispc_vm->hback_porch = hbp;
4580
4581 return true;
4582}
4583
4584
4585static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4586 unsigned long pck, void *data)
4587{
4588 struct dsi_clk_calc_ctx *ctx = data;
4589
4590 ctx->dispc_cinfo.lck_div = lckd;
4591 ctx->dispc_cinfo.pck_div = pckd;
4592 ctx->dispc_cinfo.lck = lck;
4593 ctx->dispc_cinfo.pck = pck;
4594
4595 if (dsi_vm_calc_blanking(ctx) == false)
4596 return false;
4597
4598#ifdef PRINT_VERBOSE_VM_TIMINGS
4599 print_dispc_vm("dispc", &ctx->vm);
4600 print_dsi_vm("dsi ", &ctx->dsi_vm);
4601 print_dispc_vm("req ", ctx->config->vm);
4602 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4603#endif
4604
4605 return true;
4606}
4607
4608static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4609 void *data)
4610{
4611 struct dsi_clk_calc_ctx *ctx = data;
4612 unsigned long pck_max;
4613
4614 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4615 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4616
4617 /*
4618 * In burst mode we can let the dispc pck be arbitrarily high, but it
4619 * limits our scaling abilities. So for now, don't aim too high.
4620 */
4621
4622 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4623 pck_max = ctx->req_pck_max + 10000000;
4624 else
4625 pck_max = ctx->req_pck_max;
4626
4627 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4628 ctx->req_pck_min, pck_max,
4629 dsi_vm_calc_dispc_cb, ctx);
4630}
4631
4632static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4633 unsigned long clkdco, void *data)
4634{
4635 struct dsi_clk_calc_ctx *ctx = data;
4636 struct dsi_data *dsi = ctx->dsi;
4637
4638 ctx->dsi_cinfo.n = n;
4639 ctx->dsi_cinfo.m = m;
4640 ctx->dsi_cinfo.fint = fint;
4641 ctx->dsi_cinfo.clkdco = clkdco;
4642
4643 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4644 dsi->data->max_fck_freq,
4645 dsi_vm_calc_hsdiv_cb, ctx);
4646}
4647
4648static bool dsi_vm_calc(struct dsi_data *dsi,
4649 const struct omap_dss_dsi_config *cfg,
4650 struct dsi_clk_calc_ctx *ctx)
4651{
4652 const struct videomode *vm = cfg->vm;
4653 unsigned long clkin;
4654 unsigned long pll_min;
4655 unsigned long pll_max;
4656 int ndl = dsi->num_lanes_used - 1;
4657 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4658 unsigned long byteclk_min;
4659
4660 clkin = clk_get_rate(dsi->pll.clkin);
4661
4662 memset(ctx, 0, sizeof(*ctx));
4663 ctx->dsi = dsi;
4664 ctx->pll = &dsi->pll;
4665 ctx->config = cfg;
4666
4667 /* these limits should come from the panel driver */
4668 ctx->req_pck_min = vm->pixelclock - 1000;
4669 ctx->req_pck_nom = vm->pixelclock;
4670 ctx->req_pck_max = vm->pixelclock + 1000;
4671
4672 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4673 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4674
4675 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4676 pll_max = cfg->hs_clk_max * 4;
4677 } else {
4678 unsigned long byteclk_max;
4679 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4680 ndl * 8);
4681
4682 pll_max = byteclk_max * 4 * 4;
4683 }
4684
4685 return dss_pll_calc_a(ctx->pll, clkin,
4686 pll_min, pll_max,
4687 dsi_vm_calc_pll_cb, ctx);
4688}
4689
4690static int dsi_set_config(struct omap_dss_device *dssdev,
4691 const struct omap_dss_dsi_config *config)
4692{
4693 struct dsi_data *dsi = to_dsi_data(dssdev);
4694 struct dsi_clk_calc_ctx ctx;
4695 bool ok;
4696 int r;
4697
4698 mutex_lock(&dsi->lock);
4699
4700 dsi->pix_fmt = config->pixel_format;
4701 dsi->mode = config->mode;
4702
4703 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4704 ok = dsi_vm_calc(dsi, config, &ctx);
4705 else
4706 ok = dsi_cm_calc(dsi, config, &ctx);
4707
4708 if (!ok) {
4709 DSSERR("failed to find suitable DSI clock settings\n");
4710 r = -EINVAL;
4711 goto err;
4712 }
4713
4714 dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo);
4715
4716 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4717 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4718 if (r) {
4719 DSSERR("failed to find suitable DSI LP clock settings\n");
4720 goto err;
4721 }
4722
4723 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4724 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4725
4726 dsi->vm = ctx.vm;
4727
4728 /*
4729 * override interlace, logic level and edge related parameters in
4730 * videomode with default values
4731 */
4732 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4733 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4734 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4735 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4736 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4737 /*
4738 * HACK: These flags should be handled through the omap_dss_device bus
4739 * flags, but this will only be possible when the DSI encoder will be
4740 * converted to the omapdrm-managed encoder model.
4741 */
4742 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4743 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4744 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4745 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4746 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4747 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4748
4749 dss_mgr_set_timings(&dsi->output, &dsi->vm);
4750
4751 dsi->vm_timings = ctx.dsi_vm;
4752
4753 mutex_unlock(&dsi->lock);
4754
4755 return 0;
4756err:
4757 mutex_unlock(&dsi->lock);
4758
4759 return r;
4760}
4761
4762/*
4763 * Return a hardcoded channel for the DSI output. This should work for
4764 * current use cases, but this can be later expanded to either resolve
4765 * the channel in some more dynamic manner, or get the channel as a user
4766 * parameter.
4767 */
4768static enum omap_channel dsi_get_channel(struct dsi_data *dsi)
4769{
4770 switch (dsi->data->model) {
4771 case DSI_MODEL_OMAP3:
4772 return OMAP_DSS_CHANNEL_LCD;
4773
4774 case DSI_MODEL_OMAP4:
4775 switch (dsi->module_id) {
4776 case 0:
4777 return OMAP_DSS_CHANNEL_LCD;
4778 case 1:
4779 return OMAP_DSS_CHANNEL_LCD2;
4780 default:
4781 DSSWARN("unsupported module id\n");
4782 return OMAP_DSS_CHANNEL_LCD;
4783 }
4784
4785 case DSI_MODEL_OMAP5:
4786 switch (dsi->module_id) {
4787 case 0:
4788 return OMAP_DSS_CHANNEL_LCD;
4789 case 1:
4790 return OMAP_DSS_CHANNEL_LCD3;
4791 default:
4792 DSSWARN("unsupported module id\n");
4793 return OMAP_DSS_CHANNEL_LCD;
4794 }
4795
4796 default:
4797 DSSWARN("unsupported DSS version\n");
4798 return OMAP_DSS_CHANNEL_LCD;
4799 }
4800}
4801
4802static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4803{
4804 struct dsi_data *dsi = to_dsi_data(dssdev);
4805 int i;
4806
4807 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4808 if (!dsi->vc[i].dssdev) {
4809 dsi->vc[i].dssdev = dssdev;
4810 *channel = i;
4811 return 0;
4812 }
4813 }
4814
4815 DSSERR("cannot get VC for display %s", dssdev->name);
4816 return -ENOSPC;
4817}
4818
4819static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4820{
4821 struct dsi_data *dsi = to_dsi_data(dssdev);
4822
4823 if (vc_id < 0 || vc_id > 3) {
4824 DSSERR("VC ID out of range\n");
4825 return -EINVAL;
4826 }
4827
4828 if (channel < 0 || channel > 3) {
4829 DSSERR("Virtual Channel out of range\n");
4830 return -EINVAL;
4831 }
4832
4833 if (dsi->vc[channel].dssdev != dssdev) {
4834 DSSERR("Virtual Channel not allocated to display %s\n",
4835 dssdev->name);
4836 return -EINVAL;
4837 }
4838
4839 dsi->vc[channel].vc_id = vc_id;
4840
4841 return 0;
4842}
4843
4844static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4845{
4846 struct dsi_data *dsi = to_dsi_data(dssdev);
4847
4848 if ((channel >= 0 && channel <= 3) &&
4849 dsi->vc[channel].dssdev == dssdev) {
4850 dsi->vc[channel].dssdev = NULL;
4851 dsi->vc[channel].vc_id = 0;
4852 }
4853}
4854
4855
4856static int dsi_get_clocks(struct dsi_data *dsi)
4857{
4858 struct clk *clk;
4859
4860 clk = devm_clk_get(dsi->dev, "fck");
4861 if (IS_ERR(clk)) {
4862 DSSERR("can't get fck\n");
4863 return PTR_ERR(clk);
4864 }
4865
4866 dsi->dss_clk = clk;
4867
4868 return 0;
4869}
4870
4871static int dsi_connect(struct omap_dss_device *src,
4872 struct omap_dss_device *dst)
4873{
4874 return omapdss_device_connect(dst->dss, dst, dst->next);
4875}
4876
4877static void dsi_disconnect(struct omap_dss_device *src,
4878 struct omap_dss_device *dst)
4879{
4880 omapdss_device_disconnect(dst, dst->next);
4881}
4882
4883static const struct omap_dss_device_ops dsi_ops = {
4884 .connect = dsi_connect,
4885 .disconnect = dsi_disconnect,
4886 .enable = dsi_display_enable,
4887
4888 .dsi = {
4889 .bus_lock = dsi_bus_lock,
4890 .bus_unlock = dsi_bus_unlock,
4891
4892 .disable = dsi_display_disable,
4893
4894 .enable_hs = dsi_vc_enable_hs,
4895
4896 .configure_pins = dsi_configure_pins,
4897 .set_config = dsi_set_config,
4898
4899 .enable_video_output = dsi_enable_video_output,
4900 .disable_video_output = dsi_disable_video_output,
4901
4902 .update = dsi_update,
4903
4904 .enable_te = dsi_enable_te,
4905
4906 .request_vc = dsi_request_vc,
4907 .set_vc_id = dsi_set_vc_id,
4908 .release_vc = dsi_release_vc,
4909
4910 .dcs_write = dsi_vc_dcs_write,
4911 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
4912 .dcs_read = dsi_vc_dcs_read,
4913
4914 .gen_write = dsi_vc_generic_write,
4915 .gen_write_nosync = dsi_vc_generic_write_nosync,
4916 .gen_read = dsi_vc_generic_read,
4917
4918 .bta_sync = dsi_vc_send_bta_sync,
4919
4920 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
4921 },
4922};
4923
4924/* -----------------------------------------------------------------------------
4925 * PLL
4926 */
4927
4928static const struct dss_pll_ops dsi_pll_ops = {
4929 .enable = dsi_pll_enable,
4930 .disable = dsi_pll_disable,
4931 .set_config = dss_pll_write_config_type_a,
4932};
4933
4934static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
4935 .type = DSS_PLL_TYPE_A,
4936
4937 .n_max = (1 << 7) - 1,
4938 .m_max = (1 << 11) - 1,
4939 .mX_max = (1 << 4) - 1,
4940 .fint_min = 750000,
4941 .fint_max = 2100000,
4942 .clkdco_low = 1000000000,
4943 .clkdco_max = 1800000000,
4944
4945 .n_msb = 7,
4946 .n_lsb = 1,
4947 .m_msb = 18,
4948 .m_lsb = 8,
4949
4950 .mX_msb[0] = 22,
4951 .mX_lsb[0] = 19,
4952 .mX_msb[1] = 26,
4953 .mX_lsb[1] = 23,
4954
4955 .has_stopmode = true,
4956 .has_freqsel = true,
4957 .has_selfreqdco = false,
4958 .has_refsel = false,
4959};
4960
4961static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
4962 .type = DSS_PLL_TYPE_A,
4963
4964 .n_max = (1 << 8) - 1,
4965 .m_max = (1 << 12) - 1,
4966 .mX_max = (1 << 5) - 1,
4967 .fint_min = 500000,
4968 .fint_max = 2500000,
4969 .clkdco_low = 1000000000,
4970 .clkdco_max = 1800000000,
4971
4972 .n_msb = 8,
4973 .n_lsb = 1,
4974 .m_msb = 20,
4975 .m_lsb = 9,
4976
4977 .mX_msb[0] = 25,
4978 .mX_lsb[0] = 21,
4979 .mX_msb[1] = 30,
4980 .mX_lsb[1] = 26,
4981
4982 .has_stopmode = true,
4983 .has_freqsel = false,
4984 .has_selfreqdco = false,
4985 .has_refsel = false,
4986};
4987
4988static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
4989 .type = DSS_PLL_TYPE_A,
4990
4991 .n_max = (1 << 8) - 1,
4992 .m_max = (1 << 12) - 1,
4993 .mX_max = (1 << 5) - 1,
4994 .fint_min = 150000,
4995 .fint_max = 52000000,
4996 .clkdco_low = 1000000000,
4997 .clkdco_max = 1800000000,
4998
4999 .n_msb = 8,
5000 .n_lsb = 1,
5001 .m_msb = 20,
5002 .m_lsb = 9,
5003
5004 .mX_msb[0] = 25,
5005 .mX_lsb[0] = 21,
5006 .mX_msb[1] = 30,
5007 .mX_lsb[1] = 26,
5008
5009 .has_stopmode = true,
5010 .has_freqsel = false,
5011 .has_selfreqdco = true,
5012 .has_refsel = true,
5013};
5014
5015static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi)
5016{
5017 struct dss_pll *pll = &dsi->pll;
5018 struct clk *clk;
5019 int r;
5020
5021 clk = devm_clk_get(dsi->dev, "sys_clk");
5022 if (IS_ERR(clk)) {
5023 DSSERR("can't get sys_clk\n");
5024 return PTR_ERR(clk);
5025 }
5026
5027 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5028 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5029 pll->clkin = clk;
5030 pll->base = dsi->pll_base;
5031 pll->hw = dsi->data->pll_hw;
5032 pll->ops = &dsi_pll_ops;
5033
5034 r = dss_pll_register(dss, pll);
5035 if (r)
5036 return r;
5037
5038 return 0;
5039}
5040
5041/* -----------------------------------------------------------------------------
5042 * Component Bind & Unbind
5043 */
5044
5045static int dsi_bind(struct device *dev, struct device *master, void *data)
5046{
5047 struct dss_device *dss = dss_get_device(master);
5048 struct dsi_data *dsi = dev_get_drvdata(dev);
5049 char name[10];
5050 u32 rev;
5051 int r;
5052
5053 dsi->dss = dss;
5054
5055 dsi_init_pll_data(dss, dsi);
5056
5057 r = dsi_runtime_get(dsi);
5058 if (r)
5059 return r;
5060
5061 rev = dsi_read_reg(dsi, DSI_REVISION);
5062 dev_dbg(dev, "OMAP DSI rev %d.%d\n",
5063 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5064
5065 dsi->line_buffer_size = dsi_get_line_buf_size(dsi);
5066
5067 dsi_runtime_put(dsi);
5068
5069 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1);
5070 dsi->debugfs.regs = dss_debugfs_create_file(dss, name,
5071 dsi_dump_dsi_regs, dsi);
5072#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5073 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1);
5074 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name,
5075 dsi_dump_dsi_irqs, dsi);
5076#endif
5077 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1);
5078 dsi->debugfs.clks = dss_debugfs_create_file(dss, name,
5079 dsi_dump_dsi_clocks, dsi);
5080
5081 return 0;
5082}
5083
5084static void dsi_unbind(struct device *dev, struct device *master, void *data)
5085{
5086 struct dsi_data *dsi = dev_get_drvdata(dev);
5087
5088 dss_debugfs_remove_file(dsi->debugfs.clks);
5089 dss_debugfs_remove_file(dsi->debugfs.irqs);
5090 dss_debugfs_remove_file(dsi->debugfs.regs);
5091
5092 WARN_ON(dsi->scp_clk_refcount > 0);
5093
5094 dss_pll_unregister(&dsi->pll);
5095}
5096
5097static const struct component_ops dsi_component_ops = {
5098 .bind = dsi_bind,
5099 .unbind = dsi_unbind,
5100};
5101
5102/* -----------------------------------------------------------------------------
5103 * Probe & Remove, Suspend & Resume
5104 */
5105
5106static int dsi_init_output(struct dsi_data *dsi)
5107{
5108 struct omap_dss_device *out = &dsi->output;
5109 int r;
5110
5111 out->dev = dsi->dev;
5112 out->id = dsi->module_id == 0 ?
5113 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5114
5115 out->type = OMAP_DISPLAY_TYPE_DSI;
5116 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5117 out->dispc_channel = dsi_get_channel(dsi);
5118 out->ops = &dsi_ops;
5119 out->owner = THIS_MODULE;
5120 out->of_ports = BIT(0);
5121 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
5122 | DRM_BUS_FLAG_DE_HIGH
5123 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
5124
5125 r = omapdss_device_init_output(out);
5126 if (r < 0)
5127 return r;
5128
5129 omapdss_device_register(out);
5130
5131 return 0;
5132}
5133
5134static void dsi_uninit_output(struct dsi_data *dsi)
5135{
5136 struct omap_dss_device *out = &dsi->output;
5137
5138 omapdss_device_unregister(out);
5139 omapdss_device_cleanup_output(out);
5140}
5141
5142static int dsi_probe_of(struct dsi_data *dsi)
5143{
5144 struct device_node *node = dsi->dev->of_node;
5145 struct property *prop;
5146 u32 lane_arr[10];
5147 int len, num_pins;
5148 int r, i;
5149 struct device_node *ep;
5150 struct omap_dsi_pin_config pin_cfg;
5151
5152 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
5153 if (!ep)
5154 return 0;
5155
5156 prop = of_find_property(ep, "lanes", &len);
5157 if (prop == NULL) {
5158 dev_err(dsi->dev, "failed to find lane data\n");
5159 r = -EINVAL;
5160 goto err;
5161 }
5162
5163 num_pins = len / sizeof(u32);
5164
5165 if (num_pins < 4 || num_pins % 2 != 0 ||
5166 num_pins > dsi->num_lanes_supported * 2) {
5167 dev_err(dsi->dev, "bad number of lanes\n");
5168 r = -EINVAL;
5169 goto err;
5170 }
5171
5172 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5173 if (r) {
5174 dev_err(dsi->dev, "failed to read lane data\n");
5175 goto err;
5176 }
5177
5178 pin_cfg.num_pins = num_pins;
5179 for (i = 0; i < num_pins; ++i)
5180 pin_cfg.pins[i] = (int)lane_arr[i];
5181
5182 r = dsi_configure_pins(&dsi->output, &pin_cfg);
5183 if (r) {
5184 dev_err(dsi->dev, "failed to configure pins");
5185 goto err;
5186 }
5187
5188 of_node_put(ep);
5189
5190 return 0;
5191
5192err:
5193 of_node_put(ep);
5194 return r;
5195}
5196
5197static const struct dsi_of_data dsi_of_data_omap34xx = {
5198 .model = DSI_MODEL_OMAP3,
5199 .pll_hw = &dss_omap3_dsi_pll_hw,
5200 .modules = (const struct dsi_module_id_data[]) {
5201 { .address = 0x4804fc00, .id = 0, },
5202 { },
5203 },
5204 .max_fck_freq = 173000000,
5205 .max_pll_lpdiv = (1 << 13) - 1,
5206 .quirks = DSI_QUIRK_REVERSE_TXCLKESC,
5207};
5208
5209static const struct dsi_of_data dsi_of_data_omap36xx = {
5210 .model = DSI_MODEL_OMAP3,
5211 .pll_hw = &dss_omap3_dsi_pll_hw,
5212 .modules = (const struct dsi_module_id_data[]) {
5213 { .address = 0x4804fc00, .id = 0, },
5214 { },
5215 },
5216 .max_fck_freq = 173000000,
5217 .max_pll_lpdiv = (1 << 13) - 1,
5218 .quirks = DSI_QUIRK_PLL_PWR_BUG,
5219};
5220
5221static const struct dsi_of_data dsi_of_data_omap4 = {
5222 .model = DSI_MODEL_OMAP4,
5223 .pll_hw = &dss_omap4_dsi_pll_hw,
5224 .modules = (const struct dsi_module_id_data[]) {
5225 { .address = 0x58004000, .id = 0, },
5226 { .address = 0x58005000, .id = 1, },
5227 { },
5228 },
5229 .max_fck_freq = 170000000,
5230 .max_pll_lpdiv = (1 << 13) - 1,
5231 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5232 | DSI_QUIRK_GNQ,
5233};
5234
5235static const struct dsi_of_data dsi_of_data_omap5 = {
5236 .model = DSI_MODEL_OMAP5,
5237 .pll_hw = &dss_omap5_dsi_pll_hw,
5238 .modules = (const struct dsi_module_id_data[]) {
5239 { .address = 0x58004000, .id = 0, },
5240 { .address = 0x58009000, .id = 1, },
5241 { },
5242 },
5243 .max_fck_freq = 209250000,
5244 .max_pll_lpdiv = (1 << 13) - 1,
5245 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5246 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC,
5247};
5248
5249static const struct of_device_id dsi_of_match[] = {
5250 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
5251 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
5252 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
5253 {},
5254};
5255
5256static const struct soc_device_attribute dsi_soc_devices[] = {
5257 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx },
5258 { .machine = "AM35*", .data = &dsi_of_data_omap34xx },
5259 { /* sentinel */ }
5260};
5261
5262static int dsi_probe(struct platform_device *pdev)
5263{
5264 const struct soc_device_attribute *soc;
5265 const struct dsi_module_id_data *d;
5266 struct device *dev = &pdev->dev;
5267 struct dsi_data *dsi;
5268 struct resource *dsi_mem;
5269 struct resource *res;
5270 unsigned int i;
5271 int r;
5272
5273 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
5274 if (!dsi)
5275 return -ENOMEM;
5276
5277 dsi->dev = dev;
5278 dev_set_drvdata(dev, dsi);
5279
5280 spin_lock_init(&dsi->irq_lock);
5281 spin_lock_init(&dsi->errors_lock);
5282 dsi->errors = 0;
5283
5284#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5285 spin_lock_init(&dsi->irq_stats_lock);
5286 dsi->irq_stats.last_reset = jiffies;
5287#endif
5288
5289 mutex_init(&dsi->lock);
5290 sema_init(&dsi->bus_lock, 1);
5291
5292 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5293 dsi_framedone_timeout_work_callback);
5294
5295#ifdef DSI_CATCH_MISSING_TE
5296 timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5297#endif
5298
5299 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto");
5300 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem);
5301 if (IS_ERR(dsi->proto_base))
5302 return PTR_ERR(dsi->proto_base);
5303
5304 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
5305 dsi->phy_base = devm_ioremap_resource(dev, res);
5306 if (IS_ERR(dsi->phy_base))
5307 return PTR_ERR(dsi->phy_base);
5308
5309 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
5310 dsi->pll_base = devm_ioremap_resource(dev, res);
5311 if (IS_ERR(dsi->pll_base))
5312 return PTR_ERR(dsi->pll_base);
5313
5314 dsi->irq = platform_get_irq(pdev, 0);
5315 if (dsi->irq < 0) {
5316 DSSERR("platform_get_irq failed\n");
5317 return -ENODEV;
5318 }
5319
5320 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler,
5321 IRQF_SHARED, dev_name(dev), dsi);
5322 if (r < 0) {
5323 DSSERR("request_irq failed\n");
5324 return r;
5325 }
5326
5327 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd");
5328 if (IS_ERR(dsi->vdds_dsi_reg)) {
5329 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER)
5330 DSSERR("can't get DSI VDD regulator\n");
5331 return PTR_ERR(dsi->vdds_dsi_reg);
5332 }
5333
5334 soc = soc_device_match(dsi_soc_devices);
5335 if (soc)
5336 dsi->data = soc->data;
5337 else
5338 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data;
5339
5340 d = dsi->data->modules;
5341 while (d->address != 0 && d->address != dsi_mem->start)
5342 d++;
5343
5344 if (d->address == 0) {
5345 DSSERR("unsupported DSI module\n");
5346 return -ENODEV;
5347 }
5348
5349 dsi->module_id = d->id;
5350
5351 if (dsi->data->model == DSI_MODEL_OMAP4 ||
5352 dsi->data->model == DSI_MODEL_OMAP5) {
5353 struct device_node *np;
5354
5355 /*
5356 * The OMAP4/5 display DT bindings don't reference the padconf
5357 * syscon. Our only option to retrieve it is to find it by name.
5358 */
5359 np = of_find_node_by_name(NULL,
5360 dsi->data->model == DSI_MODEL_OMAP4 ?
5361 "omap4_padconf_global" : "omap5_padconf_global");
5362 if (!np)
5363 return -ENODEV;
5364
5365 dsi->syscon = syscon_node_to_regmap(np);
5366 of_node_put(np);
5367 }
5368
5369 /* DSI VCs initialization */
5370 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5371 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5372 dsi->vc[i].dssdev = NULL;
5373 dsi->vc[i].vc_id = 0;
5374 }
5375
5376 r = dsi_get_clocks(dsi);
5377 if (r)
5378 return r;
5379
5380 pm_runtime_enable(dev);
5381
5382 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5383 * of data to 3 by default */
5384 if (dsi->data->quirks & DSI_QUIRK_GNQ) {
5385 dsi_runtime_get(dsi);
5386 /* NB_DATA_LANES */
5387 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9);
5388 dsi_runtime_put(dsi);
5389 } else {
5390 dsi->num_lanes_supported = 3;
5391 }
5392
5393 r = of_platform_populate(dev->of_node, NULL, NULL, dev);
5394 if (r) {
5395 DSSERR("Failed to populate DSI child devices: %d\n", r);
5396 goto err_pm_disable;
5397 }
5398
5399 r = dsi_init_output(dsi);
5400 if (r)
5401 goto err_of_depopulate;
5402
5403 r = dsi_probe_of(dsi);
5404 if (r) {
5405 DSSERR("Invalid DSI DT data\n");
5406 goto err_uninit_output;
5407 }
5408
5409 r = component_add(&pdev->dev, &dsi_component_ops);
5410 if (r)
5411 goto err_uninit_output;
5412
5413 return 0;
5414
5415err_uninit_output:
5416 dsi_uninit_output(dsi);
5417err_of_depopulate:
5418 of_platform_depopulate(dev);
5419err_pm_disable:
5420 pm_runtime_disable(dev);
5421 return r;
5422}
5423
5424static int dsi_remove(struct platform_device *pdev)
5425{
5426 struct dsi_data *dsi = platform_get_drvdata(pdev);
5427
5428 component_del(&pdev->dev, &dsi_component_ops);
5429
5430 dsi_uninit_output(dsi);
5431
5432 of_platform_depopulate(&pdev->dev);
5433
5434 pm_runtime_disable(&pdev->dev);
5435
5436 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5437 regulator_disable(dsi->vdds_dsi_reg);
5438 dsi->vdds_dsi_enabled = false;
5439 }
5440
5441 return 0;
5442}
5443
5444static int dsi_runtime_suspend(struct device *dev)
5445{
5446 struct dsi_data *dsi = dev_get_drvdata(dev);
5447
5448 dsi->is_enabled = false;
5449 /* ensure the irq handler sees the is_enabled value */
5450 smp_wmb();
5451 /* wait for current handler to finish before turning the DSI off */
5452 synchronize_irq(dsi->irq);
5453
5454 return 0;
5455}
5456
5457static int dsi_runtime_resume(struct device *dev)
5458{
5459 struct dsi_data *dsi = dev_get_drvdata(dev);
5460
5461 dsi->is_enabled = true;
5462 /* ensure the irq handler sees the is_enabled value */
5463 smp_wmb();
5464
5465 return 0;
5466}
5467
5468static const struct dev_pm_ops dsi_pm_ops = {
5469 .runtime_suspend = dsi_runtime_suspend,
5470 .runtime_resume = dsi_runtime_resume,
5471};
5472
5473struct platform_driver omap_dsihw_driver = {
5474 .probe = dsi_probe,
5475 .remove = dsi_remove,
5476 .driver = {
5477 .name = "omapdss_dsi",
5478 .pm = &dsi_pm_ops,
5479 .of_match_table = dsi_of_match,
5480 .suppress_bind_attrs = true,
5481 },
5482};