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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/component.h>
25#include <linux/kernel.h>
26
27#include <drm/drm_edid.h>
28#include <drm/i915_component.h>
29
30#include "i915_drv.h"
31#include "intel_atomic.h"
32#include "intel_audio.h"
33#include "intel_cdclk.h"
34#include "intel_de.h"
35#include "intel_display_types.h"
36#include "intel_lpe_audio.h"
37
38/**
39 * DOC: High Definition Audio over HDMI and Display Port
40 *
41 * The graphics and audio drivers together support High Definition Audio over
42 * HDMI and Display Port. The audio programming sequences are divided into audio
43 * codec and controller enable and disable sequences. The graphics driver
44 * handles the audio codec sequences, while the audio driver handles the audio
45 * controller sequences.
46 *
47 * The disable sequences must be performed before disabling the transcoder or
48 * port. The enable sequences may only be performed after enabling the
49 * transcoder and port, and after completed link training. Therefore the audio
50 * enable/disable sequences are part of the modeset sequence.
51 *
52 * The codec and controller sequences could be done either parallel or serial,
53 * but generally the ELDV/PD change in the codec sequence indicates to the audio
54 * driver that the controller sequence should start. Indeed, most of the
55 * co-operation between the graphics and audio drivers is handled via audio
56 * related registers. (The notable exception is the power management, not
57 * covered here.)
58 *
59 * The struct &i915_audio_component is used to interact between the graphics
60 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
61 * defined in graphics driver and called in audio driver. The
62 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
63 */
64
65/* DP N/M table */
66#define LC_810M 810000
67#define LC_540M 540000
68#define LC_270M 270000
69#define LC_162M 162000
70
71struct dp_aud_n_m {
72 int sample_rate;
73 int clock;
74 u16 m;
75 u16 n;
76};
77
78struct hdmi_aud_ncts {
79 int sample_rate;
80 int clock;
81 int n;
82 int cts;
83};
84
85/* Values according to DP 1.4 Table 2-104 */
86static const struct dp_aud_n_m dp_aud_n_m[] = {
87 { 32000, LC_162M, 1024, 10125 },
88 { 44100, LC_162M, 784, 5625 },
89 { 48000, LC_162M, 512, 3375 },
90 { 64000, LC_162M, 2048, 10125 },
91 { 88200, LC_162M, 1568, 5625 },
92 { 96000, LC_162M, 1024, 3375 },
93 { 128000, LC_162M, 4096, 10125 },
94 { 176400, LC_162M, 3136, 5625 },
95 { 192000, LC_162M, 2048, 3375 },
96 { 32000, LC_270M, 1024, 16875 },
97 { 44100, LC_270M, 784, 9375 },
98 { 48000, LC_270M, 512, 5625 },
99 { 64000, LC_270M, 2048, 16875 },
100 { 88200, LC_270M, 1568, 9375 },
101 { 96000, LC_270M, 1024, 5625 },
102 { 128000, LC_270M, 4096, 16875 },
103 { 176400, LC_270M, 3136, 9375 },
104 { 192000, LC_270M, 2048, 5625 },
105 { 32000, LC_540M, 1024, 33750 },
106 { 44100, LC_540M, 784, 18750 },
107 { 48000, LC_540M, 512, 11250 },
108 { 64000, LC_540M, 2048, 33750 },
109 { 88200, LC_540M, 1568, 18750 },
110 { 96000, LC_540M, 1024, 11250 },
111 { 128000, LC_540M, 4096, 33750 },
112 { 176400, LC_540M, 3136, 18750 },
113 { 192000, LC_540M, 2048, 11250 },
114 { 32000, LC_810M, 1024, 50625 },
115 { 44100, LC_810M, 784, 28125 },
116 { 48000, LC_810M, 512, 16875 },
117 { 64000, LC_810M, 2048, 50625 },
118 { 88200, LC_810M, 1568, 28125 },
119 { 96000, LC_810M, 1024, 16875 },
120 { 128000, LC_810M, 4096, 50625 },
121 { 176400, LC_810M, 3136, 28125 },
122 { 192000, LC_810M, 2048, 16875 },
123};
124
125static const struct dp_aud_n_m *
126audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
127{
128 int i;
129
130 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
131 if (rate == dp_aud_n_m[i].sample_rate &&
132 crtc_state->port_clock == dp_aud_n_m[i].clock)
133 return &dp_aud_n_m[i];
134 }
135
136 return NULL;
137}
138
139static const struct {
140 int clock;
141 u32 config;
142} hdmi_audio_clock[] = {
143 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
144 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
145 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
146 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
147 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
148 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
149 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
150 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
151 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
152 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
153 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
154 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
155 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
156 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
157};
158
159/* HDMI N/CTS table */
160#define TMDS_297M 297000
161#define TMDS_296M 296703
162#define TMDS_594M 594000
163#define TMDS_593M 593407
164
165static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
166 { 32000, TMDS_296M, 5824, 421875 },
167 { 32000, TMDS_297M, 3072, 222750 },
168 { 32000, TMDS_593M, 5824, 843750 },
169 { 32000, TMDS_594M, 3072, 445500 },
170 { 44100, TMDS_296M, 4459, 234375 },
171 { 44100, TMDS_297M, 4704, 247500 },
172 { 44100, TMDS_593M, 8918, 937500 },
173 { 44100, TMDS_594M, 9408, 990000 },
174 { 88200, TMDS_296M, 8918, 234375 },
175 { 88200, TMDS_297M, 9408, 247500 },
176 { 88200, TMDS_593M, 17836, 937500 },
177 { 88200, TMDS_594M, 18816, 990000 },
178 { 176400, TMDS_296M, 17836, 234375 },
179 { 176400, TMDS_297M, 18816, 247500 },
180 { 176400, TMDS_593M, 35672, 937500 },
181 { 176400, TMDS_594M, 37632, 990000 },
182 { 48000, TMDS_296M, 5824, 281250 },
183 { 48000, TMDS_297M, 5120, 247500 },
184 { 48000, TMDS_593M, 5824, 562500 },
185 { 48000, TMDS_594M, 6144, 594000 },
186 { 96000, TMDS_296M, 11648, 281250 },
187 { 96000, TMDS_297M, 10240, 247500 },
188 { 96000, TMDS_593M, 11648, 562500 },
189 { 96000, TMDS_594M, 12288, 594000 },
190 { 192000, TMDS_296M, 23296, 281250 },
191 { 192000, TMDS_297M, 20480, 247500 },
192 { 192000, TMDS_593M, 23296, 562500 },
193 { 192000, TMDS_594M, 24576, 594000 },
194};
195
196/* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
197/* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
198#define TMDS_371M 371250
199#define TMDS_370M 370878
200
201static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
202 { 32000, TMDS_370M, 5824, 527344 },
203 { 32000, TMDS_371M, 6144, 556875 },
204 { 44100, TMDS_370M, 8918, 585938 },
205 { 44100, TMDS_371M, 4704, 309375 },
206 { 88200, TMDS_370M, 17836, 585938 },
207 { 88200, TMDS_371M, 9408, 309375 },
208 { 176400, TMDS_370M, 35672, 585938 },
209 { 176400, TMDS_371M, 18816, 309375 },
210 { 48000, TMDS_370M, 11648, 703125 },
211 { 48000, TMDS_371M, 5120, 309375 },
212 { 96000, TMDS_370M, 23296, 703125 },
213 { 96000, TMDS_371M, 10240, 309375 },
214 { 192000, TMDS_370M, 46592, 703125 },
215 { 192000, TMDS_371M, 20480, 309375 },
216};
217
218/* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
219#define TMDS_445_5M 445500
220#define TMDS_445M 445054
221
222static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
223 { 32000, TMDS_445M, 5824, 632813 },
224 { 32000, TMDS_445_5M, 4096, 445500 },
225 { 44100, TMDS_445M, 8918, 703125 },
226 { 44100, TMDS_445_5M, 4704, 371250 },
227 { 88200, TMDS_445M, 17836, 703125 },
228 { 88200, TMDS_445_5M, 9408, 371250 },
229 { 176400, TMDS_445M, 35672, 703125 },
230 { 176400, TMDS_445_5M, 18816, 371250 },
231 { 48000, TMDS_445M, 5824, 421875 },
232 { 48000, TMDS_445_5M, 5120, 371250 },
233 { 96000, TMDS_445M, 11648, 421875 },
234 { 96000, TMDS_445_5M, 10240, 371250 },
235 { 192000, TMDS_445M, 23296, 421875 },
236 { 192000, TMDS_445_5M, 20480, 371250 },
237};
238
239/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
240static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
241{
242 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
243 const struct drm_display_mode *adjusted_mode =
244 &crtc_state->hw.adjusted_mode;
245 int i;
246
247 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
248 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
249 break;
250 }
251
252 if (DISPLAY_VER(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
253 i = ARRAY_SIZE(hdmi_audio_clock);
254
255 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
256 drm_dbg_kms(&dev_priv->drm,
257 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
258 adjusted_mode->crtc_clock);
259 i = 1;
260 }
261
262 drm_dbg_kms(&dev_priv->drm,
263 "Configuring HDMI audio for pixel clock %d (0x%08x)\n",
264 hdmi_audio_clock[i].clock,
265 hdmi_audio_clock[i].config);
266
267 return hdmi_audio_clock[i].config;
268}
269
270static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
271 int rate)
272{
273 const struct hdmi_aud_ncts *hdmi_ncts_table;
274 int i, size;
275
276 if (crtc_state->pipe_bpp == 36) {
277 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
278 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
279 } else if (crtc_state->pipe_bpp == 30) {
280 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
281 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
282 } else {
283 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
284 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
285 }
286
287 for (i = 0; i < size; i++) {
288 if (rate == hdmi_ncts_table[i].sample_rate &&
289 crtc_state->port_clock == hdmi_ncts_table[i].clock) {
290 return hdmi_ncts_table[i].n;
291 }
292 }
293 return 0;
294}
295
296static bool intel_eld_uptodate(struct drm_connector *connector,
297 i915_reg_t reg_eldv, u32 bits_eldv,
298 i915_reg_t reg_elda, u32 bits_elda,
299 i915_reg_t reg_edid)
300{
301 struct drm_i915_private *dev_priv = to_i915(connector->dev);
302 const u8 *eld = connector->eld;
303 u32 tmp;
304 int i;
305
306 tmp = intel_de_read(dev_priv, reg_eldv);
307 tmp &= bits_eldv;
308
309 if (!tmp)
310 return false;
311
312 tmp = intel_de_read(dev_priv, reg_elda);
313 tmp &= ~bits_elda;
314 intel_de_write(dev_priv, reg_elda, tmp);
315
316 for (i = 0; i < drm_eld_size(eld) / 4; i++)
317 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i))
318 return false;
319
320 return true;
321}
322
323static void g4x_audio_codec_disable(struct intel_encoder *encoder,
324 const struct intel_crtc_state *old_crtc_state,
325 const struct drm_connector_state *old_conn_state)
326{
327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
328 u32 eldv, tmp;
329
330 drm_dbg_kms(&dev_priv->drm, "Disable audio codec\n");
331
332 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
333 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
334 eldv = G4X_ELDV_DEVCL_DEVBLC;
335 else
336 eldv = G4X_ELDV_DEVCTG;
337
338 /* Invalidate ELD */
339 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
340 tmp &= ~eldv;
341 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
342}
343
344static void g4x_audio_codec_enable(struct intel_encoder *encoder,
345 const struct intel_crtc_state *crtc_state,
346 const struct drm_connector_state *conn_state)
347{
348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
349 struct drm_connector *connector = conn_state->connector;
350 const u8 *eld = connector->eld;
351 u32 eldv;
352 u32 tmp;
353 int len, i;
354
355 drm_dbg_kms(&dev_priv->drm, "Enable audio codec, %u bytes ELD\n",
356 drm_eld_size(eld));
357
358 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
359 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
360 eldv = G4X_ELDV_DEVCL_DEVBLC;
361 else
362 eldv = G4X_ELDV_DEVCTG;
363
364 if (intel_eld_uptodate(connector,
365 G4X_AUD_CNTL_ST, eldv,
366 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
367 G4X_HDMIW_HDMIEDID))
368 return;
369
370 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
371 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
372 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
373 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
374
375 len = min(drm_eld_size(eld) / 4, len);
376 drm_dbg(&dev_priv->drm, "ELD size %d\n", len);
377 for (i = 0; i < len; i++)
378 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID,
379 *((const u32 *)eld + i));
380
381 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
382 tmp |= eldv;
383 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
384}
385
386static void
387hsw_dp_audio_config_update(struct intel_encoder *encoder,
388 const struct intel_crtc_state *crtc_state)
389{
390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
391 struct i915_audio_component *acomp = dev_priv->audio_component;
392 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
393 enum port port = encoder->port;
394 const struct dp_aud_n_m *nm;
395 int rate;
396 u32 tmp;
397
398 rate = acomp ? acomp->aud_sample_rate[port] : 0;
399 nm = audio_config_dp_get_n_m(crtc_state, rate);
400 if (nm)
401 drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m,
402 nm->n);
403 else
404 drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n");
405
406 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
407 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
408 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
409 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
410 tmp |= AUD_CONFIG_N_VALUE_INDEX;
411
412 if (nm) {
413 tmp &= ~AUD_CONFIG_N_MASK;
414 tmp |= AUD_CONFIG_N(nm->n);
415 tmp |= AUD_CONFIG_N_PROG_ENABLE;
416 }
417
418 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
419
420 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
421 tmp &= ~AUD_CONFIG_M_MASK;
422 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
423 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
424
425 if (nm) {
426 tmp |= nm->m;
427 tmp |= AUD_M_CTS_M_VALUE_INDEX;
428 tmp |= AUD_M_CTS_M_PROG_ENABLE;
429 }
430
431 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
432}
433
434static void
435hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
436 const struct intel_crtc_state *crtc_state)
437{
438 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
439 struct i915_audio_component *acomp = dev_priv->audio_component;
440 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
441 enum port port = encoder->port;
442 int n, rate;
443 u32 tmp;
444
445 rate = acomp ? acomp->aud_sample_rate[port] : 0;
446
447 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
448 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
449 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
450 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
451 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
452
453 n = audio_config_hdmi_get_n(crtc_state, rate);
454 if (n != 0) {
455 drm_dbg_kms(&dev_priv->drm, "using N %d\n", n);
456
457 tmp &= ~AUD_CONFIG_N_MASK;
458 tmp |= AUD_CONFIG_N(n);
459 tmp |= AUD_CONFIG_N_PROG_ENABLE;
460 } else {
461 drm_dbg_kms(&dev_priv->drm, "using automatic N\n");
462 }
463
464 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
465
466 /*
467 * Let's disable "Enable CTS or M Prog bit"
468 * and let HW calculate the value
469 */
470 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
471 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
472 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
473 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
474}
475
476static void
477hsw_audio_config_update(struct intel_encoder *encoder,
478 const struct intel_crtc_state *crtc_state)
479{
480 if (intel_crtc_has_dp_encoder(crtc_state))
481 hsw_dp_audio_config_update(encoder, crtc_state);
482 else
483 hsw_hdmi_audio_config_update(encoder, crtc_state);
484}
485
486static void hsw_audio_codec_disable(struct intel_encoder *encoder,
487 const struct intel_crtc_state *old_crtc_state,
488 const struct drm_connector_state *old_conn_state)
489{
490 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
491 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
492 u32 tmp;
493
494 drm_dbg_kms(&dev_priv->drm, "Disable audio codec on transcoder %s\n",
495 transcoder_name(cpu_transcoder));
496
497 mutex_lock(&dev_priv->av_mutex);
498
499 /* Disable timestamps */
500 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
501 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
502 tmp |= AUD_CONFIG_N_PROG_ENABLE;
503 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
504 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
505 if (intel_crtc_has_dp_encoder(old_crtc_state))
506 tmp |= AUD_CONFIG_N_VALUE_INDEX;
507 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
508
509 /* Invalidate ELD */
510 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
511 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
512 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
513 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
514
515 mutex_unlock(&dev_priv->av_mutex);
516}
517
518static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
519 const struct intel_crtc_state *crtc_state)
520{
521 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
522 unsigned int link_clks_available, link_clks_required;
523 unsigned int tu_data, tu_line, link_clks_active;
524 unsigned int h_active, h_total, hblank_delta, pixel_clk;
525 unsigned int fec_coeff, cdclk, vdsc_bpp;
526 unsigned int link_clk, lanes;
527 unsigned int hblank_rise;
528
529 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
530 h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
531 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
532 vdsc_bpp = crtc_state->dsc.compressed_bpp;
533 cdclk = i915->cdclk.hw.cdclk;
534 /* fec= 0.972261, using rounding multiplier of 1000000 */
535 fec_coeff = 972261;
536 link_clk = crtc_state->port_clock;
537 lanes = crtc_state->lane_count;
538
539 drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
540 "lanes = %u vdsc_bpp = %u cdclk = %u\n",
541 h_active, link_clk, lanes, vdsc_bpp, cdclk);
542
543 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
544 return 0;
545
546 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
547 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2);
548
549 if (link_clks_available > link_clks_required)
550 hblank_delta = 32;
551 else
552 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
553 mul_u32_u32(link_clk, cdclk));
554
555 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
556 mul_u32_u32(link_clk * lanes, fec_coeff));
557 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
558 mul_u32_u32(64 * pixel_clk, 1000000));
559 link_clks_active = (tu_line - 1) * 64 + tu_data;
560
561 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk;
562
563 return h_active - hblank_rise + hblank_delta;
564}
565
566static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state)
567{
568 unsigned int h_active, h_total, pixel_clk;
569 unsigned int link_clk, lanes;
570
571 h_active = crtc_state->hw.adjusted_mode.hdisplay;
572 h_total = crtc_state->hw.adjusted_mode.htotal;
573 pixel_clk = crtc_state->hw.adjusted_mode.clock;
574 link_clk = crtc_state->port_clock;
575 lanes = crtc_state->lane_count;
576
577 return ((h_total - h_active) * link_clk - 12 * pixel_clk) /
578 (pixel_clk * (48 / lanes + 2));
579}
580
581static void enable_audio_dsc_wa(struct intel_encoder *encoder,
582 const struct intel_crtc_state *crtc_state)
583{
584 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
585 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
586 enum pipe pipe = crtc->pipe;
587 unsigned int hblank_early_prog, samples_room;
588 unsigned int val;
589
590 if (DISPLAY_VER(i915) < 11)
591 return;
592
593 val = intel_de_read(i915, AUD_CONFIG_BE);
594
595 if (DISPLAY_VER(i915) == 11)
596 val |= HBLANK_EARLY_ENABLE_ICL(pipe);
597 else if (DISPLAY_VER(i915) >= 12)
598 val |= HBLANK_EARLY_ENABLE_TGL(pipe);
599
600 if (crtc_state->dsc.compression_enable &&
601 crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
602 crtc_state->hw.adjusted_mode.vdisplay >= 2160) {
603 /* Get hblank early enable value required */
604 val &= ~HBLANK_START_COUNT_MASK(pipe);
605 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state);
606 if (hblank_early_prog < 32)
607 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32);
608 else if (hblank_early_prog < 64)
609 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64);
610 else if (hblank_early_prog < 96)
611 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96);
612 else
613 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128);
614
615 /* Get samples room value required */
616 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
617 samples_room = calc_samples_room(crtc_state);
618 if (samples_room < 3)
619 val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room);
620 else /* Program 0 i.e "All Samples available in buffer" */
621 val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0);
622 }
623
624 intel_de_write(i915, AUD_CONFIG_BE, val);
625}
626
627#undef ROUNDING_FACTOR
628
629static void hsw_audio_codec_enable(struct intel_encoder *encoder,
630 const struct intel_crtc_state *crtc_state,
631 const struct drm_connector_state *conn_state)
632{
633 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
634 struct drm_connector *connector = conn_state->connector;
635 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
636 const u8 *eld = connector->eld;
637 u32 tmp;
638 int len, i;
639
640 drm_dbg_kms(&dev_priv->drm,
641 "Enable audio codec on transcoder %s, %u bytes ELD\n",
642 transcoder_name(cpu_transcoder), drm_eld_size(eld));
643
644 mutex_lock(&dev_priv->av_mutex);
645
646 /* Enable Audio WA for 4k DSC usecases */
647 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
648 enable_audio_dsc_wa(encoder, crtc_state);
649
650 /* Enable audio presence detect, invalidate ELD */
651 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
652 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
653 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
654 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
655
656 /*
657 * FIXME: We're supposed to wait for vblank here, but we have vblanks
658 * disabled during the mode set. The proper fix would be to push the
659 * rest of the setup into a vblank work item, queued here, but the
660 * infrastructure is not there yet.
661 */
662
663 /* Reset ELD write address */
664 tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
665 tmp &= ~IBX_ELD_ADDRESS_MASK;
666 intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
667
668 /* Up to 84 bytes of hw ELD buffer */
669 len = min(drm_eld_size(eld), 84);
670 for (i = 0; i < len / 4; i++)
671 intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder),
672 *((const u32 *)eld + i));
673
674 /* ELD valid */
675 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
676 tmp |= AUDIO_ELD_VALID(cpu_transcoder);
677 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
678
679 /* Enable timestamps */
680 hsw_audio_config_update(encoder, crtc_state);
681
682 mutex_unlock(&dev_priv->av_mutex);
683}
684
685static void ilk_audio_codec_disable(struct intel_encoder *encoder,
686 const struct intel_crtc_state *old_crtc_state,
687 const struct drm_connector_state *old_conn_state)
688{
689 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
690 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
691 enum pipe pipe = crtc->pipe;
692 enum port port = encoder->port;
693 u32 tmp, eldv;
694 i915_reg_t aud_config, aud_cntrl_st2;
695
696 drm_dbg_kms(&dev_priv->drm,
697 "Disable audio codec on [ENCODER:%d:%s], pipe %c\n",
698 encoder->base.base.id, encoder->base.name,
699 pipe_name(pipe));
700
701 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
702 return;
703
704 if (HAS_PCH_IBX(dev_priv)) {
705 aud_config = IBX_AUD_CFG(pipe);
706 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
707 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
708 aud_config = VLV_AUD_CFG(pipe);
709 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
710 } else {
711 aud_config = CPT_AUD_CFG(pipe);
712 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
713 }
714
715 /* Disable timestamps */
716 tmp = intel_de_read(dev_priv, aud_config);
717 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
718 tmp |= AUD_CONFIG_N_PROG_ENABLE;
719 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
720 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
721 if (intel_crtc_has_dp_encoder(old_crtc_state))
722 tmp |= AUD_CONFIG_N_VALUE_INDEX;
723 intel_de_write(dev_priv, aud_config, tmp);
724
725 eldv = IBX_ELD_VALID(port);
726
727 /* Invalidate ELD */
728 tmp = intel_de_read(dev_priv, aud_cntrl_st2);
729 tmp &= ~eldv;
730 intel_de_write(dev_priv, aud_cntrl_st2, tmp);
731}
732
733static void ilk_audio_codec_enable(struct intel_encoder *encoder,
734 const struct intel_crtc_state *crtc_state,
735 const struct drm_connector_state *conn_state)
736{
737 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
738 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
739 struct drm_connector *connector = conn_state->connector;
740 enum pipe pipe = crtc->pipe;
741 enum port port = encoder->port;
742 const u8 *eld = connector->eld;
743 u32 tmp, eldv;
744 int len, i;
745 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
746
747 drm_dbg_kms(&dev_priv->drm,
748 "Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n",
749 encoder->base.base.id, encoder->base.name,
750 pipe_name(pipe), drm_eld_size(eld));
751
752 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
753 return;
754
755 /*
756 * FIXME: We're supposed to wait for vblank here, but we have vblanks
757 * disabled during the mode set. The proper fix would be to push the
758 * rest of the setup into a vblank work item, queued here, but the
759 * infrastructure is not there yet.
760 */
761
762 if (HAS_PCH_IBX(dev_priv)) {
763 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
764 aud_config = IBX_AUD_CFG(pipe);
765 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
766 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
767 } else if (IS_VALLEYVIEW(dev_priv) ||
768 IS_CHERRYVIEW(dev_priv)) {
769 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
770 aud_config = VLV_AUD_CFG(pipe);
771 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
772 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
773 } else {
774 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
775 aud_config = CPT_AUD_CFG(pipe);
776 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
777 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
778 }
779
780 eldv = IBX_ELD_VALID(port);
781
782 /* Invalidate ELD */
783 tmp = intel_de_read(dev_priv, aud_cntrl_st2);
784 tmp &= ~eldv;
785 intel_de_write(dev_priv, aud_cntrl_st2, tmp);
786
787 /* Reset ELD write address */
788 tmp = intel_de_read(dev_priv, aud_cntl_st);
789 tmp &= ~IBX_ELD_ADDRESS_MASK;
790 intel_de_write(dev_priv, aud_cntl_st, tmp);
791
792 /* Up to 84 bytes of hw ELD buffer */
793 len = min(drm_eld_size(eld), 84);
794 for (i = 0; i < len / 4; i++)
795 intel_de_write(dev_priv, hdmiw_hdmiedid,
796 *((const u32 *)eld + i));
797
798 /* ELD valid */
799 tmp = intel_de_read(dev_priv, aud_cntrl_st2);
800 tmp |= eldv;
801 intel_de_write(dev_priv, aud_cntrl_st2, tmp);
802
803 /* Enable timestamps */
804 tmp = intel_de_read(dev_priv, aud_config);
805 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
806 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
807 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
808 if (intel_crtc_has_dp_encoder(crtc_state))
809 tmp |= AUD_CONFIG_N_VALUE_INDEX;
810 else
811 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
812 intel_de_write(dev_priv, aud_config, tmp);
813}
814
815/**
816 * intel_audio_codec_enable - Enable the audio codec for HD audio
817 * @encoder: encoder on which to enable audio
818 * @crtc_state: pointer to the current crtc state.
819 * @conn_state: pointer to the current connector state.
820 *
821 * The enable sequences may only be performed after enabling the transcoder and
822 * port, and after completed link training.
823 */
824void intel_audio_codec_enable(struct intel_encoder *encoder,
825 const struct intel_crtc_state *crtc_state,
826 const struct drm_connector_state *conn_state)
827{
828 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
829 struct i915_audio_component *acomp = dev_priv->audio_component;
830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
831 struct drm_connector *connector = conn_state->connector;
832 const struct drm_display_mode *adjusted_mode =
833 &crtc_state->hw.adjusted_mode;
834 enum port port = encoder->port;
835 enum pipe pipe = crtc->pipe;
836
837 /* FIXME precompute the ELD in .compute_config() */
838 if (!connector->eld[0])
839 drm_dbg_kms(&dev_priv->drm,
840 "Bogus ELD on [CONNECTOR:%d:%s]\n",
841 connector->base.id, connector->name);
842
843 drm_dbg(&dev_priv->drm, "ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
844 connector->base.id,
845 connector->name,
846 encoder->base.base.id,
847 encoder->base.name);
848
849 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
850
851 if (dev_priv->display.audio_codec_enable)
852 dev_priv->display.audio_codec_enable(encoder,
853 crtc_state,
854 conn_state);
855
856 mutex_lock(&dev_priv->av_mutex);
857 encoder->audio_connector = connector;
858
859 /* referred in audio callbacks */
860 dev_priv->av_enc_map[pipe] = encoder;
861 mutex_unlock(&dev_priv->av_mutex);
862
863 if (acomp && acomp->base.audio_ops &&
864 acomp->base.audio_ops->pin_eld_notify) {
865 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
866 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
867 pipe = -1;
868 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
869 (int) port, (int) pipe);
870 }
871
872 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
873 crtc_state->port_clock,
874 intel_crtc_has_dp_encoder(crtc_state));
875}
876
877/**
878 * intel_audio_codec_disable - Disable the audio codec for HD audio
879 * @encoder: encoder on which to disable audio
880 * @old_crtc_state: pointer to the old crtc state.
881 * @old_conn_state: pointer to the old connector state.
882 *
883 * The disable sequences must be performed before disabling the transcoder or
884 * port.
885 */
886void intel_audio_codec_disable(struct intel_encoder *encoder,
887 const struct intel_crtc_state *old_crtc_state,
888 const struct drm_connector_state *old_conn_state)
889{
890 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
891 struct i915_audio_component *acomp = dev_priv->audio_component;
892 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
893 enum port port = encoder->port;
894 enum pipe pipe = crtc->pipe;
895
896 if (dev_priv->display.audio_codec_disable)
897 dev_priv->display.audio_codec_disable(encoder,
898 old_crtc_state,
899 old_conn_state);
900
901 mutex_lock(&dev_priv->av_mutex);
902 encoder->audio_connector = NULL;
903 dev_priv->av_enc_map[pipe] = NULL;
904 mutex_unlock(&dev_priv->av_mutex);
905
906 if (acomp && acomp->base.audio_ops &&
907 acomp->base.audio_ops->pin_eld_notify) {
908 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
909 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
910 pipe = -1;
911 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
912 (int) port, (int) pipe);
913 }
914
915 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
916}
917
918/**
919 * intel_init_audio_hooks - Set up chip specific audio hooks
920 * @dev_priv: device private
921 */
922void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
923{
924 if (IS_G4X(dev_priv)) {
925 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
926 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
927 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
928 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
929 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
930 } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
931 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
932 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
933 } else if (HAS_PCH_SPLIT(dev_priv)) {
934 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
935 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
936 }
937}
938
939static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
940 struct intel_crtc *crtc,
941 bool enable)
942{
943 struct intel_cdclk_state *cdclk_state;
944 int ret;
945
946 /* need to hold at least one crtc lock for the global state */
947 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
948 if (ret)
949 return ret;
950
951 cdclk_state = intel_atomic_get_cdclk_state(state);
952 if (IS_ERR(cdclk_state))
953 return PTR_ERR(cdclk_state);
954
955 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
956
957 return drm_atomic_commit(&state->base);
958}
959
960static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
961 bool enable)
962{
963 struct drm_modeset_acquire_ctx ctx;
964 struct drm_atomic_state *state;
965 struct intel_crtc *crtc;
966 int ret;
967
968 crtc = intel_get_first_crtc(dev_priv);
969 if (!crtc)
970 return;
971
972 drm_modeset_acquire_init(&ctx, 0);
973 state = drm_atomic_state_alloc(&dev_priv->drm);
974 if (drm_WARN_ON(&dev_priv->drm, !state))
975 return;
976
977 state->acquire_ctx = &ctx;
978
979retry:
980 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
981 enable);
982 if (ret == -EDEADLK) {
983 drm_atomic_state_clear(state);
984 drm_modeset_backoff(&ctx);
985 goto retry;
986 }
987
988 drm_WARN_ON(&dev_priv->drm, ret);
989
990 drm_atomic_state_put(state);
991
992 drm_modeset_drop_locks(&ctx);
993 drm_modeset_acquire_fini(&ctx);
994}
995
996static unsigned long i915_audio_component_get_power(struct device *kdev)
997{
998 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
999 intel_wakeref_t ret;
1000
1001 /* Catch potential impedance mismatches before they occur! */
1002 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
1003
1004 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1005
1006 if (dev_priv->audio_power_refcount++ == 0) {
1007 if (DISPLAY_VER(dev_priv) >= 9) {
1008 intel_de_write(dev_priv, AUD_FREQ_CNTRL,
1009 dev_priv->audio_freq_cntrl);
1010 drm_dbg_kms(&dev_priv->drm,
1011 "restored AUD_FREQ_CNTRL to 0x%x\n",
1012 dev_priv->audio_freq_cntrl);
1013 }
1014
1015 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
1016 if (IS_GEMINILAKE(dev_priv))
1017 glk_force_audio_cdclk(dev_priv, true);
1018
1019 if (DISPLAY_VER(dev_priv) >= 10)
1020 intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
1021 (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
1022 }
1023
1024 return ret;
1025}
1026
1027static void i915_audio_component_put_power(struct device *kdev,
1028 unsigned long cookie)
1029{
1030 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1031
1032 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
1033 if (--dev_priv->audio_power_refcount == 0)
1034 if (IS_GEMINILAKE(dev_priv))
1035 glk_force_audio_cdclk(dev_priv, false);
1036
1037 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
1038}
1039
1040static void i915_audio_component_codec_wake_override(struct device *kdev,
1041 bool enable)
1042{
1043 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1044 unsigned long cookie;
1045 u32 tmp;
1046
1047 if (DISPLAY_VER(dev_priv) < 9)
1048 return;
1049
1050 cookie = i915_audio_component_get_power(kdev);
1051
1052 /*
1053 * Enable/disable generating the codec wake signal, overriding the
1054 * internal logic to generate the codec wake to controller.
1055 */
1056 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1057 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
1058 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1059 usleep_range(1000, 1500);
1060
1061 if (enable) {
1062 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1063 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
1064 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1065 usleep_range(1000, 1500);
1066 }
1067
1068 i915_audio_component_put_power(kdev, cookie);
1069}
1070
1071/* Get CDCLK in kHz */
1072static int i915_audio_component_get_cdclk_freq(struct device *kdev)
1073{
1074 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1075
1076 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
1077 return -ENODEV;
1078
1079 return dev_priv->cdclk.hw.cdclk;
1080}
1081
1082/*
1083 * get the intel_encoder according to the parameter port and pipe
1084 * intel_encoder is saved by the index of pipe
1085 * MST & (pipe >= 0): return the av_enc_map[pipe],
1086 * when port is matched
1087 * MST & (pipe < 0): this is invalid
1088 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
1089 * will get the right intel_encoder with port matched
1090 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
1091 */
1092static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
1093 int port, int pipe)
1094{
1095 struct intel_encoder *encoder;
1096
1097 /* MST */
1098 if (pipe >= 0) {
1099 if (drm_WARN_ON(&dev_priv->drm,
1100 pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
1101 return NULL;
1102
1103 encoder = dev_priv->av_enc_map[pipe];
1104 /*
1105 * when bootup, audio driver may not know it is
1106 * MST or not. So it will poll all the port & pipe
1107 * combinations
1108 */
1109 if (encoder != NULL && encoder->port == port &&
1110 encoder->type == INTEL_OUTPUT_DP_MST)
1111 return encoder;
1112 }
1113
1114 /* Non-MST */
1115 if (pipe > 0)
1116 return NULL;
1117
1118 for_each_pipe(dev_priv, pipe) {
1119 encoder = dev_priv->av_enc_map[pipe];
1120 if (encoder == NULL)
1121 continue;
1122
1123 if (encoder->type == INTEL_OUTPUT_DP_MST)
1124 continue;
1125
1126 if (port == encoder->port)
1127 return encoder;
1128 }
1129
1130 return NULL;
1131}
1132
1133static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
1134 int pipe, int rate)
1135{
1136 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1137 struct i915_audio_component *acomp = dev_priv->audio_component;
1138 struct intel_encoder *encoder;
1139 struct intel_crtc *crtc;
1140 unsigned long cookie;
1141 int err = 0;
1142
1143 if (!HAS_DDI(dev_priv))
1144 return 0;
1145
1146 cookie = i915_audio_component_get_power(kdev);
1147 mutex_lock(&dev_priv->av_mutex);
1148
1149 /* 1. get the pipe */
1150 encoder = get_saved_enc(dev_priv, port, pipe);
1151 if (!encoder || !encoder->base.crtc) {
1152 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1153 port_name(port));
1154 err = -ENODEV;
1155 goto unlock;
1156 }
1157
1158 crtc = to_intel_crtc(encoder->base.crtc);
1159
1160 /* port must be valid now, otherwise the pipe will be invalid */
1161 acomp->aud_sample_rate[port] = rate;
1162
1163 hsw_audio_config_update(encoder, crtc->config);
1164
1165 unlock:
1166 mutex_unlock(&dev_priv->av_mutex);
1167 i915_audio_component_put_power(kdev, cookie);
1168 return err;
1169}
1170
1171static int i915_audio_component_get_eld(struct device *kdev, int port,
1172 int pipe, bool *enabled,
1173 unsigned char *buf, int max_bytes)
1174{
1175 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1176 struct intel_encoder *intel_encoder;
1177 const u8 *eld;
1178 int ret = -EINVAL;
1179
1180 mutex_lock(&dev_priv->av_mutex);
1181
1182 intel_encoder = get_saved_enc(dev_priv, port, pipe);
1183 if (!intel_encoder) {
1184 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1185 port_name(port));
1186 mutex_unlock(&dev_priv->av_mutex);
1187 return ret;
1188 }
1189
1190 ret = 0;
1191 *enabled = intel_encoder->audio_connector != NULL;
1192 if (*enabled) {
1193 eld = intel_encoder->audio_connector->eld;
1194 ret = drm_eld_size(eld);
1195 memcpy(buf, eld, min(max_bytes, ret));
1196 }
1197
1198 mutex_unlock(&dev_priv->av_mutex);
1199 return ret;
1200}
1201
1202static const struct drm_audio_component_ops i915_audio_component_ops = {
1203 .owner = THIS_MODULE,
1204 .get_power = i915_audio_component_get_power,
1205 .put_power = i915_audio_component_put_power,
1206 .codec_wake_override = i915_audio_component_codec_wake_override,
1207 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1208 .sync_audio_rate = i915_audio_component_sync_audio_rate,
1209 .get_eld = i915_audio_component_get_eld,
1210};
1211
1212static int i915_audio_component_bind(struct device *i915_kdev,
1213 struct device *hda_kdev, void *data)
1214{
1215 struct i915_audio_component *acomp = data;
1216 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1217 int i;
1218
1219 if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev))
1220 return -EEXIST;
1221
1222 if (drm_WARN_ON(&dev_priv->drm,
1223 !device_link_add(hda_kdev, i915_kdev,
1224 DL_FLAG_STATELESS)))
1225 return -ENOMEM;
1226
1227 drm_modeset_lock_all(&dev_priv->drm);
1228 acomp->base.ops = &i915_audio_component_ops;
1229 acomp->base.dev = i915_kdev;
1230 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1231 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1232 acomp->aud_sample_rate[i] = 0;
1233 dev_priv->audio_component = acomp;
1234 drm_modeset_unlock_all(&dev_priv->drm);
1235
1236 return 0;
1237}
1238
1239static void i915_audio_component_unbind(struct device *i915_kdev,
1240 struct device *hda_kdev, void *data)
1241{
1242 struct i915_audio_component *acomp = data;
1243 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1244
1245 drm_modeset_lock_all(&dev_priv->drm);
1246 acomp->base.ops = NULL;
1247 acomp->base.dev = NULL;
1248 dev_priv->audio_component = NULL;
1249 drm_modeset_unlock_all(&dev_priv->drm);
1250
1251 device_link_remove(hda_kdev, i915_kdev);
1252
1253 if (dev_priv->audio_power_refcount)
1254 drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n",
1255 dev_priv->audio_power_refcount);
1256}
1257
1258static const struct component_ops i915_audio_component_bind_ops = {
1259 .bind = i915_audio_component_bind,
1260 .unbind = i915_audio_component_unbind,
1261};
1262
1263#define AUD_FREQ_TMODE_SHIFT 14
1264#define AUD_FREQ_4T 0
1265#define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT)
1266#define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11)
1267#define AUD_FREQ_BCLK_96M BIT(4)
1268
1269#define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M)
1270#define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M)
1271
1272/**
1273 * i915_audio_component_init - initialize and register the audio component
1274 * @dev_priv: i915 device instance
1275 *
1276 * This will register with the component framework a child component which
1277 * will bind dynamically to the snd_hda_intel driver's corresponding master
1278 * component when the latter is registered. During binding the child
1279 * initializes an instance of struct i915_audio_component which it receives
1280 * from the master. The master can then start to use the interface defined by
1281 * this struct. Each side can break the binding at any point by deregistering
1282 * its own component after which each side's component unbind callback is
1283 * called.
1284 *
1285 * We ignore any error during registration and continue with reduced
1286 * functionality (i.e. without HDMI audio).
1287 */
1288static void i915_audio_component_init(struct drm_i915_private *dev_priv)
1289{
1290 u32 aud_freq, aud_freq_init;
1291 int ret;
1292
1293 ret = component_add_typed(dev_priv->drm.dev,
1294 &i915_audio_component_bind_ops,
1295 I915_COMPONENT_AUDIO);
1296 if (ret < 0) {
1297 drm_err(&dev_priv->drm,
1298 "failed to add audio component (%d)\n", ret);
1299 /* continue with reduced functionality */
1300 return;
1301 }
1302
1303 if (DISPLAY_VER(dev_priv) >= 9) {
1304 aud_freq_init = intel_de_read(dev_priv, AUD_FREQ_CNTRL);
1305
1306 if (DISPLAY_VER(dev_priv) >= 12)
1307 aud_freq = AUD_FREQ_GEN12;
1308 else
1309 aud_freq = aud_freq_init;
1310
1311 /* use BIOS provided value for TGL and RKL unless it is a known bad value */
1312 if ((IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) &&
1313 aud_freq_init != AUD_FREQ_TGL_BROKEN)
1314 aud_freq = aud_freq_init;
1315
1316 drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
1317 aud_freq, aud_freq_init);
1318
1319 dev_priv->audio_freq_cntrl = aud_freq;
1320 }
1321
1322 dev_priv->audio_component_registered = true;
1323}
1324
1325/**
1326 * i915_audio_component_cleanup - deregister the audio component
1327 * @dev_priv: i915 device instance
1328 *
1329 * Deregisters the audio component, breaking any existing binding to the
1330 * corresponding snd_hda_intel driver's master component.
1331 */
1332static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1333{
1334 if (!dev_priv->audio_component_registered)
1335 return;
1336
1337 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1338 dev_priv->audio_component_registered = false;
1339}
1340
1341/**
1342 * intel_audio_init() - Initialize the audio driver either using
1343 * component framework or using lpe audio bridge
1344 * @dev_priv: the i915 drm device private data
1345 *
1346 */
1347void intel_audio_init(struct drm_i915_private *dev_priv)
1348{
1349 if (intel_lpe_audio_init(dev_priv) < 0)
1350 i915_audio_component_init(dev_priv);
1351}
1352
1353/**
1354 * intel_audio_deinit() - deinitialize the audio driver
1355 * @dev_priv: the i915 drm device private data
1356 *
1357 */
1358void intel_audio_deinit(struct drm_i915_private *dev_priv)
1359{
1360 if ((dev_priv)->lpe_audio.platdev != NULL)
1361 intel_lpe_audio_teardown(dev_priv);
1362 else
1363 i915_audio_component_cleanup(dev_priv);
1364}
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/component.h>
25#include <linux/kernel.h>
26
27#include <drm/drm_edid.h>
28#include <drm/i915_component.h>
29
30#include "i915_drv.h"
31#include "intel_audio.h"
32#include "intel_display_types.h"
33#include "intel_lpe_audio.h"
34
35/**
36 * DOC: High Definition Audio over HDMI and Display Port
37 *
38 * The graphics and audio drivers together support High Definition Audio over
39 * HDMI and Display Port. The audio programming sequences are divided into audio
40 * codec and controller enable and disable sequences. The graphics driver
41 * handles the audio codec sequences, while the audio driver handles the audio
42 * controller sequences.
43 *
44 * The disable sequences must be performed before disabling the transcoder or
45 * port. The enable sequences may only be performed after enabling the
46 * transcoder and port, and after completed link training. Therefore the audio
47 * enable/disable sequences are part of the modeset sequence.
48 *
49 * The codec and controller sequences could be done either parallel or serial,
50 * but generally the ELDV/PD change in the codec sequence indicates to the audio
51 * driver that the controller sequence should start. Indeed, most of the
52 * co-operation between the graphics and audio drivers is handled via audio
53 * related registers. (The notable exception is the power management, not
54 * covered here.)
55 *
56 * The struct &i915_audio_component is used to interact between the graphics
57 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
58 * defined in graphics driver and called in audio driver. The
59 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
60 */
61
62/* DP N/M table */
63#define LC_810M 810000
64#define LC_540M 540000
65#define LC_270M 270000
66#define LC_162M 162000
67
68struct dp_aud_n_m {
69 int sample_rate;
70 int clock;
71 u16 m;
72 u16 n;
73};
74
75struct hdmi_aud_ncts {
76 int sample_rate;
77 int clock;
78 int n;
79 int cts;
80};
81
82/* Values according to DP 1.4 Table 2-104 */
83static const struct dp_aud_n_m dp_aud_n_m[] = {
84 { 32000, LC_162M, 1024, 10125 },
85 { 44100, LC_162M, 784, 5625 },
86 { 48000, LC_162M, 512, 3375 },
87 { 64000, LC_162M, 2048, 10125 },
88 { 88200, LC_162M, 1568, 5625 },
89 { 96000, LC_162M, 1024, 3375 },
90 { 128000, LC_162M, 4096, 10125 },
91 { 176400, LC_162M, 3136, 5625 },
92 { 192000, LC_162M, 2048, 3375 },
93 { 32000, LC_270M, 1024, 16875 },
94 { 44100, LC_270M, 784, 9375 },
95 { 48000, LC_270M, 512, 5625 },
96 { 64000, LC_270M, 2048, 16875 },
97 { 88200, LC_270M, 1568, 9375 },
98 { 96000, LC_270M, 1024, 5625 },
99 { 128000, LC_270M, 4096, 16875 },
100 { 176400, LC_270M, 3136, 9375 },
101 { 192000, LC_270M, 2048, 5625 },
102 { 32000, LC_540M, 1024, 33750 },
103 { 44100, LC_540M, 784, 18750 },
104 { 48000, LC_540M, 512, 11250 },
105 { 64000, LC_540M, 2048, 33750 },
106 { 88200, LC_540M, 1568, 18750 },
107 { 96000, LC_540M, 1024, 11250 },
108 { 128000, LC_540M, 4096, 33750 },
109 { 176400, LC_540M, 3136, 18750 },
110 { 192000, LC_540M, 2048, 11250 },
111 { 32000, LC_810M, 1024, 50625 },
112 { 44100, LC_810M, 784, 28125 },
113 { 48000, LC_810M, 512, 16875 },
114 { 64000, LC_810M, 2048, 50625 },
115 { 88200, LC_810M, 1568, 28125 },
116 { 96000, LC_810M, 1024, 16875 },
117 { 128000, LC_810M, 4096, 50625 },
118 { 176400, LC_810M, 3136, 28125 },
119 { 192000, LC_810M, 2048, 16875 },
120};
121
122static const struct dp_aud_n_m *
123audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
124{
125 int i;
126
127 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
128 if (rate == dp_aud_n_m[i].sample_rate &&
129 crtc_state->port_clock == dp_aud_n_m[i].clock)
130 return &dp_aud_n_m[i];
131 }
132
133 return NULL;
134}
135
136static const struct {
137 int clock;
138 u32 config;
139} hdmi_audio_clock[] = {
140 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
141 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
142 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
143 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
144 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
145 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
146 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
147 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
148 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
149 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
150};
151
152/* HDMI N/CTS table */
153#define TMDS_297M 297000
154#define TMDS_296M 296703
155#define TMDS_594M 594000
156#define TMDS_593M 593407
157
158static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
159 { 32000, TMDS_296M, 5824, 421875 },
160 { 32000, TMDS_297M, 3072, 222750 },
161 { 32000, TMDS_593M, 5824, 843750 },
162 { 32000, TMDS_594M, 3072, 445500 },
163 { 44100, TMDS_296M, 4459, 234375 },
164 { 44100, TMDS_297M, 4704, 247500 },
165 { 44100, TMDS_593M, 8918, 937500 },
166 { 44100, TMDS_594M, 9408, 990000 },
167 { 88200, TMDS_296M, 8918, 234375 },
168 { 88200, TMDS_297M, 9408, 247500 },
169 { 88200, TMDS_593M, 17836, 937500 },
170 { 88200, TMDS_594M, 18816, 990000 },
171 { 176400, TMDS_296M, 17836, 234375 },
172 { 176400, TMDS_297M, 18816, 247500 },
173 { 176400, TMDS_593M, 35672, 937500 },
174 { 176400, TMDS_594M, 37632, 990000 },
175 { 48000, TMDS_296M, 5824, 281250 },
176 { 48000, TMDS_297M, 5120, 247500 },
177 { 48000, TMDS_593M, 5824, 562500 },
178 { 48000, TMDS_594M, 6144, 594000 },
179 { 96000, TMDS_296M, 11648, 281250 },
180 { 96000, TMDS_297M, 10240, 247500 },
181 { 96000, TMDS_593M, 11648, 562500 },
182 { 96000, TMDS_594M, 12288, 594000 },
183 { 192000, TMDS_296M, 23296, 281250 },
184 { 192000, TMDS_297M, 20480, 247500 },
185 { 192000, TMDS_593M, 23296, 562500 },
186 { 192000, TMDS_594M, 24576, 594000 },
187};
188
189/* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
190/* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
191#define TMDS_371M 371250
192#define TMDS_370M 370878
193
194static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
195 { 32000, TMDS_370M, 5824, 527344 },
196 { 32000, TMDS_371M, 6144, 556875 },
197 { 44100, TMDS_370M, 8918, 585938 },
198 { 44100, TMDS_371M, 4704, 309375 },
199 { 88200, TMDS_370M, 17836, 585938 },
200 { 88200, TMDS_371M, 9408, 309375 },
201 { 176400, TMDS_370M, 35672, 585938 },
202 { 176400, TMDS_371M, 18816, 309375 },
203 { 48000, TMDS_370M, 11648, 703125 },
204 { 48000, TMDS_371M, 5120, 309375 },
205 { 96000, TMDS_370M, 23296, 703125 },
206 { 96000, TMDS_371M, 10240, 309375 },
207 { 192000, TMDS_370M, 46592, 703125 },
208 { 192000, TMDS_371M, 20480, 309375 },
209};
210
211/* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
212#define TMDS_445_5M 445500
213#define TMDS_445M 445054
214
215static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
216 { 32000, TMDS_445M, 5824, 632813 },
217 { 32000, TMDS_445_5M, 4096, 445500 },
218 { 44100, TMDS_445M, 8918, 703125 },
219 { 44100, TMDS_445_5M, 4704, 371250 },
220 { 88200, TMDS_445M, 17836, 703125 },
221 { 88200, TMDS_445_5M, 9408, 371250 },
222 { 176400, TMDS_445M, 35672, 703125 },
223 { 176400, TMDS_445_5M, 18816, 371250 },
224 { 48000, TMDS_445M, 5824, 421875 },
225 { 48000, TMDS_445_5M, 5120, 371250 },
226 { 96000, TMDS_445M, 11648, 421875 },
227 { 96000, TMDS_445_5M, 10240, 371250 },
228 { 192000, TMDS_445M, 23296, 421875 },
229 { 192000, TMDS_445_5M, 20480, 371250 },
230};
231
232/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
233static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
234{
235 const struct drm_display_mode *adjusted_mode =
236 &crtc_state->base.adjusted_mode;
237 int i;
238
239 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
240 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
241 break;
242 }
243
244 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
245 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
246 adjusted_mode->crtc_clock);
247 i = 1;
248 }
249
250 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
251 hdmi_audio_clock[i].clock,
252 hdmi_audio_clock[i].config);
253
254 return hdmi_audio_clock[i].config;
255}
256
257static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
258 int rate)
259{
260 const struct hdmi_aud_ncts *hdmi_ncts_table;
261 int i, size;
262
263 if (crtc_state->pipe_bpp == 36) {
264 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
265 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
266 } else if (crtc_state->pipe_bpp == 30) {
267 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
268 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
269 } else {
270 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
271 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
272 }
273
274 for (i = 0; i < size; i++) {
275 if (rate == hdmi_ncts_table[i].sample_rate &&
276 crtc_state->port_clock == hdmi_ncts_table[i].clock) {
277 return hdmi_ncts_table[i].n;
278 }
279 }
280 return 0;
281}
282
283static bool intel_eld_uptodate(struct drm_connector *connector,
284 i915_reg_t reg_eldv, u32 bits_eldv,
285 i915_reg_t reg_elda, u32 bits_elda,
286 i915_reg_t reg_edid)
287{
288 struct drm_i915_private *dev_priv = to_i915(connector->dev);
289 const u8 *eld = connector->eld;
290 u32 tmp;
291 int i;
292
293 tmp = I915_READ(reg_eldv);
294 tmp &= bits_eldv;
295
296 if (!tmp)
297 return false;
298
299 tmp = I915_READ(reg_elda);
300 tmp &= ~bits_elda;
301 I915_WRITE(reg_elda, tmp);
302
303 for (i = 0; i < drm_eld_size(eld) / 4; i++)
304 if (I915_READ(reg_edid) != *((const u32 *)eld + i))
305 return false;
306
307 return true;
308}
309
310static void g4x_audio_codec_disable(struct intel_encoder *encoder,
311 const struct intel_crtc_state *old_crtc_state,
312 const struct drm_connector_state *old_conn_state)
313{
314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
315 u32 eldv, tmp;
316
317 DRM_DEBUG_KMS("Disable audio codec\n");
318
319 tmp = I915_READ(G4X_AUD_VID_DID);
320 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
321 eldv = G4X_ELDV_DEVCL_DEVBLC;
322 else
323 eldv = G4X_ELDV_DEVCTG;
324
325 /* Invalidate ELD */
326 tmp = I915_READ(G4X_AUD_CNTL_ST);
327 tmp &= ~eldv;
328 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
329}
330
331static void g4x_audio_codec_enable(struct intel_encoder *encoder,
332 const struct intel_crtc_state *crtc_state,
333 const struct drm_connector_state *conn_state)
334{
335 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
336 struct drm_connector *connector = conn_state->connector;
337 const u8 *eld = connector->eld;
338 u32 eldv;
339 u32 tmp;
340 int len, i;
341
342 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld));
343
344 tmp = I915_READ(G4X_AUD_VID_DID);
345 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
346 eldv = G4X_ELDV_DEVCL_DEVBLC;
347 else
348 eldv = G4X_ELDV_DEVCTG;
349
350 if (intel_eld_uptodate(connector,
351 G4X_AUD_CNTL_ST, eldv,
352 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
353 G4X_HDMIW_HDMIEDID))
354 return;
355
356 tmp = I915_READ(G4X_AUD_CNTL_ST);
357 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
358 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
359 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
360
361 len = min(drm_eld_size(eld) / 4, len);
362 DRM_DEBUG_DRIVER("ELD size %d\n", len);
363 for (i = 0; i < len; i++)
364 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
365
366 tmp = I915_READ(G4X_AUD_CNTL_ST);
367 tmp |= eldv;
368 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
369}
370
371static void
372hsw_dp_audio_config_update(struct intel_encoder *encoder,
373 const struct intel_crtc_state *crtc_state)
374{
375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
376 struct i915_audio_component *acomp = dev_priv->audio_component;
377 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
378 enum port port = encoder->port;
379 const struct dp_aud_n_m *nm;
380 int rate;
381 u32 tmp;
382
383 rate = acomp ? acomp->aud_sample_rate[port] : 0;
384 nm = audio_config_dp_get_n_m(crtc_state, rate);
385 if (nm)
386 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
387 else
388 DRM_DEBUG_KMS("using automatic Maud, Naud\n");
389
390 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
391 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
392 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
393 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
394 tmp |= AUD_CONFIG_N_VALUE_INDEX;
395
396 if (nm) {
397 tmp &= ~AUD_CONFIG_N_MASK;
398 tmp |= AUD_CONFIG_N(nm->n);
399 tmp |= AUD_CONFIG_N_PROG_ENABLE;
400 }
401
402 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
403
404 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
405 tmp &= ~AUD_CONFIG_M_MASK;
406 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
407 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
408
409 if (nm) {
410 tmp |= nm->m;
411 tmp |= AUD_M_CTS_M_VALUE_INDEX;
412 tmp |= AUD_M_CTS_M_PROG_ENABLE;
413 }
414
415 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
416}
417
418static void
419hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
420 const struct intel_crtc_state *crtc_state)
421{
422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
423 struct i915_audio_component *acomp = dev_priv->audio_component;
424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
425 enum port port = encoder->port;
426 int n, rate;
427 u32 tmp;
428
429 rate = acomp ? acomp->aud_sample_rate[port] : 0;
430
431 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
432 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
433 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
434 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
435 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
436
437 n = audio_config_hdmi_get_n(crtc_state, rate);
438 if (n != 0) {
439 DRM_DEBUG_KMS("using N %d\n", n);
440
441 tmp &= ~AUD_CONFIG_N_MASK;
442 tmp |= AUD_CONFIG_N(n);
443 tmp |= AUD_CONFIG_N_PROG_ENABLE;
444 } else {
445 DRM_DEBUG_KMS("using automatic N\n");
446 }
447
448 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
449
450 /*
451 * Let's disable "Enable CTS or M Prog bit"
452 * and let HW calculate the value
453 */
454 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
455 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
456 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
457 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
458}
459
460static void
461hsw_audio_config_update(struct intel_encoder *encoder,
462 const struct intel_crtc_state *crtc_state)
463{
464 if (intel_crtc_has_dp_encoder(crtc_state))
465 hsw_dp_audio_config_update(encoder, crtc_state);
466 else
467 hsw_hdmi_audio_config_update(encoder, crtc_state);
468}
469
470static void hsw_audio_codec_disable(struct intel_encoder *encoder,
471 const struct intel_crtc_state *old_crtc_state,
472 const struct drm_connector_state *old_conn_state)
473{
474 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
475 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
476 u32 tmp;
477
478 DRM_DEBUG_KMS("Disable audio codec on transcoder %s\n",
479 transcoder_name(cpu_transcoder));
480
481 mutex_lock(&dev_priv->av_mutex);
482
483 /* Disable timestamps */
484 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
485 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
486 tmp |= AUD_CONFIG_N_PROG_ENABLE;
487 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
488 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
489 if (intel_crtc_has_dp_encoder(old_crtc_state))
490 tmp |= AUD_CONFIG_N_VALUE_INDEX;
491 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
492
493 /* Invalidate ELD */
494 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
495 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
496 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
497 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
498
499 mutex_unlock(&dev_priv->av_mutex);
500}
501
502static void hsw_audio_codec_enable(struct intel_encoder *encoder,
503 const struct intel_crtc_state *crtc_state,
504 const struct drm_connector_state *conn_state)
505{
506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
507 struct drm_connector *connector = conn_state->connector;
508 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
509 const u8 *eld = connector->eld;
510 u32 tmp;
511 int len, i;
512
513 DRM_DEBUG_KMS("Enable audio codec on transcoder %s, %u bytes ELD\n",
514 transcoder_name(cpu_transcoder), drm_eld_size(eld));
515
516 mutex_lock(&dev_priv->av_mutex);
517
518 /* Enable audio presence detect, invalidate ELD */
519 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
520 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
521 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
522 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
523
524 /*
525 * FIXME: We're supposed to wait for vblank here, but we have vblanks
526 * disabled during the mode set. The proper fix would be to push the
527 * rest of the setup into a vblank work item, queued here, but the
528 * infrastructure is not there yet.
529 */
530
531 /* Reset ELD write address */
532 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
533 tmp &= ~IBX_ELD_ADDRESS_MASK;
534 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
535
536 /* Up to 84 bytes of hw ELD buffer */
537 len = min(drm_eld_size(eld), 84);
538 for (i = 0; i < len / 4; i++)
539 I915_WRITE(HSW_AUD_EDID_DATA(cpu_transcoder), *((const u32 *)eld + i));
540
541 /* ELD valid */
542 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
543 tmp |= AUDIO_ELD_VALID(cpu_transcoder);
544 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
545
546 /* Enable timestamps */
547 hsw_audio_config_update(encoder, crtc_state);
548
549 mutex_unlock(&dev_priv->av_mutex);
550}
551
552static void ilk_audio_codec_disable(struct intel_encoder *encoder,
553 const struct intel_crtc_state *old_crtc_state,
554 const struct drm_connector_state *old_conn_state)
555{
556 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
557 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
558 enum pipe pipe = crtc->pipe;
559 enum port port = encoder->port;
560 u32 tmp, eldv;
561 i915_reg_t aud_config, aud_cntrl_st2;
562
563 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
564 port_name(port), pipe_name(pipe));
565
566 if (WARN_ON(port == PORT_A))
567 return;
568
569 if (HAS_PCH_IBX(dev_priv)) {
570 aud_config = IBX_AUD_CFG(pipe);
571 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
572 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
573 aud_config = VLV_AUD_CFG(pipe);
574 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
575 } else {
576 aud_config = CPT_AUD_CFG(pipe);
577 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
578 }
579
580 /* Disable timestamps */
581 tmp = I915_READ(aud_config);
582 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
583 tmp |= AUD_CONFIG_N_PROG_ENABLE;
584 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
585 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
586 if (intel_crtc_has_dp_encoder(old_crtc_state))
587 tmp |= AUD_CONFIG_N_VALUE_INDEX;
588 I915_WRITE(aud_config, tmp);
589
590 eldv = IBX_ELD_VALID(port);
591
592 /* Invalidate ELD */
593 tmp = I915_READ(aud_cntrl_st2);
594 tmp &= ~eldv;
595 I915_WRITE(aud_cntrl_st2, tmp);
596}
597
598static void ilk_audio_codec_enable(struct intel_encoder *encoder,
599 const struct intel_crtc_state *crtc_state,
600 const struct drm_connector_state *conn_state)
601{
602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
603 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
604 struct drm_connector *connector = conn_state->connector;
605 enum pipe pipe = crtc->pipe;
606 enum port port = encoder->port;
607 const u8 *eld = connector->eld;
608 u32 tmp, eldv;
609 int len, i;
610 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
611
612 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
613 port_name(port), pipe_name(pipe), drm_eld_size(eld));
614
615 if (WARN_ON(port == PORT_A))
616 return;
617
618 /*
619 * FIXME: We're supposed to wait for vblank here, but we have vblanks
620 * disabled during the mode set. The proper fix would be to push the
621 * rest of the setup into a vblank work item, queued here, but the
622 * infrastructure is not there yet.
623 */
624
625 if (HAS_PCH_IBX(dev_priv)) {
626 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
627 aud_config = IBX_AUD_CFG(pipe);
628 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
629 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
630 } else if (IS_VALLEYVIEW(dev_priv) ||
631 IS_CHERRYVIEW(dev_priv)) {
632 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
633 aud_config = VLV_AUD_CFG(pipe);
634 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
635 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
636 } else {
637 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
638 aud_config = CPT_AUD_CFG(pipe);
639 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
640 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
641 }
642
643 eldv = IBX_ELD_VALID(port);
644
645 /* Invalidate ELD */
646 tmp = I915_READ(aud_cntrl_st2);
647 tmp &= ~eldv;
648 I915_WRITE(aud_cntrl_st2, tmp);
649
650 /* Reset ELD write address */
651 tmp = I915_READ(aud_cntl_st);
652 tmp &= ~IBX_ELD_ADDRESS_MASK;
653 I915_WRITE(aud_cntl_st, tmp);
654
655 /* Up to 84 bytes of hw ELD buffer */
656 len = min(drm_eld_size(eld), 84);
657 for (i = 0; i < len / 4; i++)
658 I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i));
659
660 /* ELD valid */
661 tmp = I915_READ(aud_cntrl_st2);
662 tmp |= eldv;
663 I915_WRITE(aud_cntrl_st2, tmp);
664
665 /* Enable timestamps */
666 tmp = I915_READ(aud_config);
667 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
668 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
669 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
670 if (intel_crtc_has_dp_encoder(crtc_state))
671 tmp |= AUD_CONFIG_N_VALUE_INDEX;
672 else
673 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
674 I915_WRITE(aud_config, tmp);
675}
676
677/**
678 * intel_audio_codec_enable - Enable the audio codec for HD audio
679 * @encoder: encoder on which to enable audio
680 * @crtc_state: pointer to the current crtc state.
681 * @conn_state: pointer to the current connector state.
682 *
683 * The enable sequences may only be performed after enabling the transcoder and
684 * port, and after completed link training.
685 */
686void intel_audio_codec_enable(struct intel_encoder *encoder,
687 const struct intel_crtc_state *crtc_state,
688 const struct drm_connector_state *conn_state)
689{
690 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
691 struct i915_audio_component *acomp = dev_priv->audio_component;
692 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
693 struct drm_connector *connector = conn_state->connector;
694 const struct drm_display_mode *adjusted_mode =
695 &crtc_state->base.adjusted_mode;
696 enum port port = encoder->port;
697 enum pipe pipe = crtc->pipe;
698
699 /* FIXME precompute the ELD in .compute_config() */
700 if (!connector->eld[0])
701 DRM_DEBUG_KMS("Bogus ELD on [CONNECTOR:%d:%s]\n",
702 connector->base.id, connector->name);
703
704 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
705 connector->base.id,
706 connector->name,
707 connector->encoder->base.id,
708 connector->encoder->name);
709
710 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
711
712 if (dev_priv->display.audio_codec_enable)
713 dev_priv->display.audio_codec_enable(encoder,
714 crtc_state,
715 conn_state);
716
717 mutex_lock(&dev_priv->av_mutex);
718 encoder->audio_connector = connector;
719
720 /* referred in audio callbacks */
721 dev_priv->av_enc_map[pipe] = encoder;
722 mutex_unlock(&dev_priv->av_mutex);
723
724 if (acomp && acomp->base.audio_ops &&
725 acomp->base.audio_ops->pin_eld_notify) {
726 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
727 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
728 pipe = -1;
729 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
730 (int) port, (int) pipe);
731 }
732
733 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
734 crtc_state->port_clock,
735 intel_crtc_has_dp_encoder(crtc_state));
736}
737
738/**
739 * intel_audio_codec_disable - Disable the audio codec for HD audio
740 * @encoder: encoder on which to disable audio
741 * @old_crtc_state: pointer to the old crtc state.
742 * @old_conn_state: pointer to the old connector state.
743 *
744 * The disable sequences must be performed before disabling the transcoder or
745 * port.
746 */
747void intel_audio_codec_disable(struct intel_encoder *encoder,
748 const struct intel_crtc_state *old_crtc_state,
749 const struct drm_connector_state *old_conn_state)
750{
751 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
752 struct i915_audio_component *acomp = dev_priv->audio_component;
753 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
754 enum port port = encoder->port;
755 enum pipe pipe = crtc->pipe;
756
757 if (dev_priv->display.audio_codec_disable)
758 dev_priv->display.audio_codec_disable(encoder,
759 old_crtc_state,
760 old_conn_state);
761
762 mutex_lock(&dev_priv->av_mutex);
763 encoder->audio_connector = NULL;
764 dev_priv->av_enc_map[pipe] = NULL;
765 mutex_unlock(&dev_priv->av_mutex);
766
767 if (acomp && acomp->base.audio_ops &&
768 acomp->base.audio_ops->pin_eld_notify) {
769 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
770 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
771 pipe = -1;
772 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
773 (int) port, (int) pipe);
774 }
775
776 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
777}
778
779/**
780 * intel_init_audio_hooks - Set up chip specific audio hooks
781 * @dev_priv: device private
782 */
783void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
784{
785 if (IS_G4X(dev_priv)) {
786 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
787 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
788 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
789 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
790 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
791 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
792 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
793 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
794 } else if (HAS_PCH_SPLIT(dev_priv)) {
795 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
796 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
797 }
798}
799
800static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
801 bool enable)
802{
803 struct drm_modeset_acquire_ctx ctx;
804 struct drm_atomic_state *state;
805 int ret;
806
807 drm_modeset_acquire_init(&ctx, 0);
808 state = drm_atomic_state_alloc(&dev_priv->drm);
809 if (WARN_ON(!state))
810 return;
811
812 state->acquire_ctx = &ctx;
813
814retry:
815 to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true;
816 to_intel_atomic_state(state)->cdclk.force_min_cdclk =
817 enable ? 2 * 96000 : 0;
818
819 /*
820 * Protects dev_priv->cdclk.force_min_cdclk
821 * Need to lock this here in case we have no active pipes
822 * and thus wouldn't lock it during the commit otherwise.
823 */
824 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
825 &ctx);
826 if (!ret)
827 ret = drm_atomic_commit(state);
828
829 if (ret == -EDEADLK) {
830 drm_atomic_state_clear(state);
831 drm_modeset_backoff(&ctx);
832 goto retry;
833 }
834
835 WARN_ON(ret);
836
837 drm_atomic_state_put(state);
838
839 drm_modeset_drop_locks(&ctx);
840 drm_modeset_acquire_fini(&ctx);
841}
842
843static unsigned long i915_audio_component_get_power(struct device *kdev)
844{
845 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
846 intel_wakeref_t ret;
847
848 /* Catch potential impedance mismatches before they occur! */
849 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
850
851 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
852
853 /* Force CDCLK to 2*BCLK as long as we need audio to be powered. */
854 if (dev_priv->audio_power_refcount++ == 0)
855 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
856 glk_force_audio_cdclk(dev_priv, true);
857
858 return ret;
859}
860
861static void i915_audio_component_put_power(struct device *kdev,
862 unsigned long cookie)
863{
864 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
865
866 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
867 if (--dev_priv->audio_power_refcount == 0)
868 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
869 glk_force_audio_cdclk(dev_priv, false);
870
871 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
872}
873
874static void i915_audio_component_codec_wake_override(struct device *kdev,
875 bool enable)
876{
877 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
878 unsigned long cookie;
879 u32 tmp;
880
881 if (!IS_GEN(dev_priv, 9))
882 return;
883
884 cookie = i915_audio_component_get_power(kdev);
885
886 /*
887 * Enable/disable generating the codec wake signal, overriding the
888 * internal logic to generate the codec wake to controller.
889 */
890 tmp = I915_READ(HSW_AUD_CHICKENBIT);
891 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
892 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
893 usleep_range(1000, 1500);
894
895 if (enable) {
896 tmp = I915_READ(HSW_AUD_CHICKENBIT);
897 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
898 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
899 usleep_range(1000, 1500);
900 }
901
902 i915_audio_component_put_power(kdev, cookie);
903}
904
905/* Get CDCLK in kHz */
906static int i915_audio_component_get_cdclk_freq(struct device *kdev)
907{
908 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
909
910 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
911 return -ENODEV;
912
913 return dev_priv->cdclk.hw.cdclk;
914}
915
916/*
917 * get the intel_encoder according to the parameter port and pipe
918 * intel_encoder is saved by the index of pipe
919 * MST & (pipe >= 0): return the av_enc_map[pipe],
920 * when port is matched
921 * MST & (pipe < 0): this is invalid
922 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
923 * will get the right intel_encoder with port matched
924 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
925 */
926static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
927 int port, int pipe)
928{
929 struct intel_encoder *encoder;
930
931 /* MST */
932 if (pipe >= 0) {
933 if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
934 return NULL;
935
936 encoder = dev_priv->av_enc_map[pipe];
937 /*
938 * when bootup, audio driver may not know it is
939 * MST or not. So it will poll all the port & pipe
940 * combinations
941 */
942 if (encoder != NULL && encoder->port == port &&
943 encoder->type == INTEL_OUTPUT_DP_MST)
944 return encoder;
945 }
946
947 /* Non-MST */
948 if (pipe > 0)
949 return NULL;
950
951 for_each_pipe(dev_priv, pipe) {
952 encoder = dev_priv->av_enc_map[pipe];
953 if (encoder == NULL)
954 continue;
955
956 if (encoder->type == INTEL_OUTPUT_DP_MST)
957 continue;
958
959 if (port == encoder->port)
960 return encoder;
961 }
962
963 return NULL;
964}
965
966static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
967 int pipe, int rate)
968{
969 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
970 struct i915_audio_component *acomp = dev_priv->audio_component;
971 struct intel_encoder *encoder;
972 struct intel_crtc *crtc;
973 unsigned long cookie;
974 int err = 0;
975
976 if (!HAS_DDI(dev_priv))
977 return 0;
978
979 cookie = i915_audio_component_get_power(kdev);
980 mutex_lock(&dev_priv->av_mutex);
981
982 /* 1. get the pipe */
983 encoder = get_saved_enc(dev_priv, port, pipe);
984 if (!encoder || !encoder->base.crtc) {
985 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
986 err = -ENODEV;
987 goto unlock;
988 }
989
990 crtc = to_intel_crtc(encoder->base.crtc);
991
992 /* port must be valid now, otherwise the pipe will be invalid */
993 acomp->aud_sample_rate[port] = rate;
994
995 hsw_audio_config_update(encoder, crtc->config);
996
997 unlock:
998 mutex_unlock(&dev_priv->av_mutex);
999 i915_audio_component_put_power(kdev, cookie);
1000 return err;
1001}
1002
1003static int i915_audio_component_get_eld(struct device *kdev, int port,
1004 int pipe, bool *enabled,
1005 unsigned char *buf, int max_bytes)
1006{
1007 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1008 struct intel_encoder *intel_encoder;
1009 const u8 *eld;
1010 int ret = -EINVAL;
1011
1012 mutex_lock(&dev_priv->av_mutex);
1013
1014 intel_encoder = get_saved_enc(dev_priv, port, pipe);
1015 if (!intel_encoder) {
1016 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
1017 mutex_unlock(&dev_priv->av_mutex);
1018 return ret;
1019 }
1020
1021 ret = 0;
1022 *enabled = intel_encoder->audio_connector != NULL;
1023 if (*enabled) {
1024 eld = intel_encoder->audio_connector->eld;
1025 ret = drm_eld_size(eld);
1026 memcpy(buf, eld, min(max_bytes, ret));
1027 }
1028
1029 mutex_unlock(&dev_priv->av_mutex);
1030 return ret;
1031}
1032
1033static const struct drm_audio_component_ops i915_audio_component_ops = {
1034 .owner = THIS_MODULE,
1035 .get_power = i915_audio_component_get_power,
1036 .put_power = i915_audio_component_put_power,
1037 .codec_wake_override = i915_audio_component_codec_wake_override,
1038 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1039 .sync_audio_rate = i915_audio_component_sync_audio_rate,
1040 .get_eld = i915_audio_component_get_eld,
1041};
1042
1043static int i915_audio_component_bind(struct device *i915_kdev,
1044 struct device *hda_kdev, void *data)
1045{
1046 struct i915_audio_component *acomp = data;
1047 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1048 int i;
1049
1050 if (WARN_ON(acomp->base.ops || acomp->base.dev))
1051 return -EEXIST;
1052
1053 if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS)))
1054 return -ENOMEM;
1055
1056 drm_modeset_lock_all(&dev_priv->drm);
1057 acomp->base.ops = &i915_audio_component_ops;
1058 acomp->base.dev = i915_kdev;
1059 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1060 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1061 acomp->aud_sample_rate[i] = 0;
1062 dev_priv->audio_component = acomp;
1063 drm_modeset_unlock_all(&dev_priv->drm);
1064
1065 return 0;
1066}
1067
1068static void i915_audio_component_unbind(struct device *i915_kdev,
1069 struct device *hda_kdev, void *data)
1070{
1071 struct i915_audio_component *acomp = data;
1072 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1073
1074 drm_modeset_lock_all(&dev_priv->drm);
1075 acomp->base.ops = NULL;
1076 acomp->base.dev = NULL;
1077 dev_priv->audio_component = NULL;
1078 drm_modeset_unlock_all(&dev_priv->drm);
1079
1080 device_link_remove(hda_kdev, i915_kdev);
1081}
1082
1083static const struct component_ops i915_audio_component_bind_ops = {
1084 .bind = i915_audio_component_bind,
1085 .unbind = i915_audio_component_unbind,
1086};
1087
1088/**
1089 * i915_audio_component_init - initialize and register the audio component
1090 * @dev_priv: i915 device instance
1091 *
1092 * This will register with the component framework a child component which
1093 * will bind dynamically to the snd_hda_intel driver's corresponding master
1094 * component when the latter is registered. During binding the child
1095 * initializes an instance of struct i915_audio_component which it receives
1096 * from the master. The master can then start to use the interface defined by
1097 * this struct. Each side can break the binding at any point by deregistering
1098 * its own component after which each side's component unbind callback is
1099 * called.
1100 *
1101 * We ignore any error during registration and continue with reduced
1102 * functionality (i.e. without HDMI audio).
1103 */
1104static void i915_audio_component_init(struct drm_i915_private *dev_priv)
1105{
1106 int ret;
1107
1108 ret = component_add_typed(dev_priv->drm.dev,
1109 &i915_audio_component_bind_ops,
1110 I915_COMPONENT_AUDIO);
1111 if (ret < 0) {
1112 DRM_ERROR("failed to add audio component (%d)\n", ret);
1113 /* continue with reduced functionality */
1114 return;
1115 }
1116
1117 dev_priv->audio_component_registered = true;
1118}
1119
1120/**
1121 * i915_audio_component_cleanup - deregister the audio component
1122 * @dev_priv: i915 device instance
1123 *
1124 * Deregisters the audio component, breaking any existing binding to the
1125 * corresponding snd_hda_intel driver's master component.
1126 */
1127static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1128{
1129 if (!dev_priv->audio_component_registered)
1130 return;
1131
1132 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1133 dev_priv->audio_component_registered = false;
1134}
1135
1136/**
1137 * intel_audio_init() - Initialize the audio driver either using
1138 * component framework or using lpe audio bridge
1139 * @dev_priv: the i915 drm device private data
1140 *
1141 */
1142void intel_audio_init(struct drm_i915_private *dev_priv)
1143{
1144 if (intel_lpe_audio_init(dev_priv) < 0)
1145 i915_audio_component_init(dev_priv);
1146}
1147
1148/**
1149 * intel_audio_deinit() - deinitialize the audio driver
1150 * @dev_priv: the i915 drm device private data
1151 *
1152 */
1153void intel_audio_deinit(struct drm_i915_private *dev_priv)
1154{
1155 if ((dev_priv)->lpe_audio.platdev != NULL)
1156 intel_lpe_audio_teardown(dev_priv);
1157 else
1158 i915_audio_component_cleanup(dev_priv);
1159}