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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include "amdgpu.h"
26#include "amdgpu_psp.h"
27#include "amdgpu_ucode.h"
28#include "soc15_common.h"
29#include "psp_v12_0.h"
30
31#include "mp/mp_12_0_0_offset.h"
32#include "mp/mp_12_0_0_sh_mask.h"
33#include "gc/gc_9_0_offset.h"
34#include "sdma0/sdma0_4_0_offset.h"
35#include "nbio/nbio_7_4_offset.h"
36
37#include "oss/osssys_4_0_offset.h"
38#include "oss/osssys_4_0_sh_mask.h"
39
40MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
42MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
43MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin");
44
45/* address block */
46#define smnMP1_FIRMWARE_FLAGS 0x3010024
47
48static int psp_v12_0_init_microcode(struct psp_context *psp)
49{
50 struct amdgpu_device *adev = psp->adev;
51 const char *chip_name;
52 char fw_name[30];
53 int err = 0;
54 const struct ta_firmware_header_v1_0 *ta_hdr;
55 DRM_DEBUG("\n");
56
57 switch (adev->asic_type) {
58 case CHIP_RENOIR:
59 if (adev->apu_flags & AMD_APU_IS_RENOIR)
60 chip_name = "renoir";
61 else
62 chip_name = "green_sardine";
63 break;
64 default:
65 BUG();
66 }
67
68 err = psp_init_asd_microcode(psp, chip_name);
69 if (err)
70 return err;
71
72 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
73 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
74 if (err) {
75 release_firmware(adev->psp.ta_fw);
76 adev->psp.ta_fw = NULL;
77 dev_info(adev->dev,
78 "psp v12.0: Failed to load firmware \"%s\"\n",
79 fw_name);
80 } else {
81 err = amdgpu_ucode_validate(adev->psp.ta_fw);
82 if (err)
83 goto out;
84
85 ta_hdr = (const struct ta_firmware_header_v1_0 *)
86 adev->psp.ta_fw->data;
87 adev->psp.ta_hdcp_ucode_version =
88 le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
89 adev->psp.ta_hdcp_ucode_size =
90 le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
91 adev->psp.ta_hdcp_start_addr =
92 (uint8_t *)ta_hdr +
93 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
94
95 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
96
97 adev->psp.ta_dtm_ucode_version =
98 le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
99 adev->psp.ta_dtm_ucode_size =
100 le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
101 adev->psp.ta_dtm_start_addr =
102 (uint8_t *)adev->psp.ta_hdcp_start_addr +
103 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
104 }
105
106 return 0;
107
108out:
109 release_firmware(adev->psp.ta_fw);
110 adev->psp.ta_fw = NULL;
111 if (err) {
112 dev_err(adev->dev,
113 "psp v12.0: Failed to load firmware \"%s\"\n",
114 fw_name);
115 }
116
117 return err;
118}
119
120static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
121{
122 int ret;
123 uint32_t psp_gfxdrv_command_reg = 0;
124 struct amdgpu_device *adev = psp->adev;
125 uint32_t sol_reg;
126
127 /* Check sOS sign of life register to confirm sys driver and sOS
128 * are already been loaded.
129 */
130 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
131 if (sol_reg)
132 return 0;
133
134 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
135 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
136 0x80000000, 0x80000000, false);
137 if (ret)
138 return ret;
139
140 /* Copy PSP System Driver binary to memory */
141 psp_copy_fw(psp, psp->sys_start_addr, psp->sys_bin_size);
142
143 /* Provide the sys driver to bootloader */
144 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
145 (uint32_t)(psp->fw_pri_mc_addr >> 20));
146 psp_gfxdrv_command_reg = 1 << 16;
147 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
148 psp_gfxdrv_command_reg);
149
150 /* there might be handshake issue with hardware which needs delay */
151 mdelay(20);
152
153 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
154 0x80000000, 0x80000000, false);
155
156 return ret;
157}
158
159static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
160{
161 int ret;
162 unsigned int psp_gfxdrv_command_reg = 0;
163 struct amdgpu_device *adev = psp->adev;
164 uint32_t sol_reg;
165
166 /* Check sOS sign of life register to confirm sys driver and sOS
167 * are already been loaded.
168 */
169 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
170 if (sol_reg)
171 return 0;
172
173 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
174 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
175 0x80000000, 0x80000000, false);
176 if (ret)
177 return ret;
178
179 /* Copy Secure OS binary to PSP memory */
180 psp_copy_fw(psp, psp->sos_start_addr, psp->sos_bin_size);
181
182 /* Provide the PSP secure OS to bootloader */
183 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
184 (uint32_t)(psp->fw_pri_mc_addr >> 20));
185 psp_gfxdrv_command_reg = 2 << 16;
186 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
187 psp_gfxdrv_command_reg);
188
189 /* there might be handshake issue with hardware which needs delay */
190 mdelay(20);
191 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
192 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
193 0, true);
194
195 return ret;
196}
197
198static void psp_v12_0_reroute_ih(struct psp_context *psp)
199{
200 struct amdgpu_device *adev = psp->adev;
201 uint32_t tmp;
202
203 /* Change IH ring for VMC */
204 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
205 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
206 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
207
208 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
209 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
210 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
211
212 mdelay(20);
213 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
214 0x80000000, 0x8000FFFF, false);
215
216 /* Change IH ring for UMC */
217 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
218 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
219
220 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
221 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
222 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
223
224 mdelay(20);
225 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
226 0x80000000, 0x8000FFFF, false);
227}
228
229static int psp_v12_0_ring_init(struct psp_context *psp,
230 enum psp_ring_type ring_type)
231{
232 int ret = 0;
233 struct psp_ring *ring;
234 struct amdgpu_device *adev = psp->adev;
235
236 psp_v12_0_reroute_ih(psp);
237
238 ring = &psp->km_ring;
239
240 ring->ring_type = ring_type;
241
242 /* allocate 4k Page of Local Frame Buffer memory for ring */
243 ring->ring_size = 0x1000;
244 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
245 AMDGPU_GEM_DOMAIN_VRAM,
246 &adev->firmware.rbuf,
247 &ring->ring_mem_mc_addr,
248 (void **)&ring->ring_mem);
249 if (ret) {
250 ring->ring_size = 0;
251 return ret;
252 }
253
254 return 0;
255}
256
257static int psp_v12_0_ring_create(struct psp_context *psp,
258 enum psp_ring_type ring_type)
259{
260 int ret = 0;
261 unsigned int psp_ring_reg = 0;
262 struct psp_ring *ring = &psp->km_ring;
263 struct amdgpu_device *adev = psp->adev;
264
265 if (amdgpu_sriov_vf(psp->adev)) {
266 /* Write low address of the ring to C2PMSG_102 */
267 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
269 /* Write high address of the ring to C2PMSG_103 */
270 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
271 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
272
273 /* Write the ring initialization command to C2PMSG_101 */
274 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
275 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
276
277 /* there might be handshake issue with hardware which needs delay */
278 mdelay(20);
279
280 /* Wait for response flag (bit 31) in C2PMSG_101 */
281 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
282 0x80000000, 0x8000FFFF, false);
283
284 } else {
285 /* Write low address of the ring to C2PMSG_69 */
286 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
287 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
288 /* Write high address of the ring to C2PMSG_70 */
289 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
290 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
291 /* Write size of ring to C2PMSG_71 */
292 psp_ring_reg = ring->ring_size;
293 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
294 /* Write the ring initialization command to C2PMSG_64 */
295 psp_ring_reg = ring_type;
296 psp_ring_reg = psp_ring_reg << 16;
297 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
298
299 /* there might be handshake issue with hardware which needs delay */
300 mdelay(20);
301
302 /* Wait for response flag (bit 31) in C2PMSG_64 */
303 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
304 0x80000000, 0x8000FFFF, false);
305 }
306
307 return ret;
308}
309
310static int psp_v12_0_ring_stop(struct psp_context *psp,
311 enum psp_ring_type ring_type)
312{
313 int ret = 0;
314 struct amdgpu_device *adev = psp->adev;
315
316 /* Write the ring destroy command*/
317 if (amdgpu_sriov_vf(adev))
318 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
319 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
320 else
321 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
322 GFX_CTRL_CMD_ID_DESTROY_RINGS);
323
324 /* there might be handshake issue with hardware which needs delay */
325 mdelay(20);
326
327 /* Wait for response flag (bit 31) */
328 if (amdgpu_sriov_vf(adev))
329 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
330 0x80000000, 0x80000000, false);
331 else
332 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
333 0x80000000, 0x80000000, false);
334
335 return ret;
336}
337
338static int psp_v12_0_ring_destroy(struct psp_context *psp,
339 enum psp_ring_type ring_type)
340{
341 int ret = 0;
342 struct psp_ring *ring = &psp->km_ring;
343 struct amdgpu_device *adev = psp->adev;
344
345 ret = psp_v12_0_ring_stop(psp, ring_type);
346 if (ret)
347 DRM_ERROR("Fail to stop psp ring\n");
348
349 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
350 &ring->ring_mem_mc_addr,
351 (void **)&ring->ring_mem);
352
353 return ret;
354}
355
356static int psp_v12_0_mode1_reset(struct psp_context *psp)
357{
358 int ret;
359 uint32_t offset;
360 struct amdgpu_device *adev = psp->adev;
361
362 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
363
364 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
365
366 if (ret) {
367 DRM_INFO("psp is not working correctly before mode1 reset!\n");
368 return -EINVAL;
369 }
370
371 /*send the mode 1 reset command*/
372 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
373
374 msleep(500);
375
376 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
377
378 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
379
380 if (ret) {
381 DRM_INFO("psp mode 1 reset failed!\n");
382 return -EINVAL;
383 }
384
385 DRM_INFO("psp mode1 reset succeed \n");
386
387 return 0;
388}
389
390static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
391{
392 uint32_t data;
393 struct amdgpu_device *adev = psp->adev;
394
395 if (amdgpu_sriov_vf(adev))
396 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
397 else
398 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
399
400 return data;
401}
402
403static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
404{
405 struct amdgpu_device *adev = psp->adev;
406
407 if (amdgpu_sriov_vf(adev)) {
408 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
409 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
410 } else
411 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
412}
413
414static const struct psp_funcs psp_v12_0_funcs = {
415 .init_microcode = psp_v12_0_init_microcode,
416 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
417 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
418 .ring_init = psp_v12_0_ring_init,
419 .ring_create = psp_v12_0_ring_create,
420 .ring_stop = psp_v12_0_ring_stop,
421 .ring_destroy = psp_v12_0_ring_destroy,
422 .mode1_reset = psp_v12_0_mode1_reset,
423 .ring_get_wptr = psp_v12_0_ring_get_wptr,
424 .ring_set_wptr = psp_v12_0_ring_set_wptr,
425};
426
427void psp_v12_0_set_psp_funcs(struct psp_context *psp)
428{
429 psp->funcs = &psp_v12_0_funcs;
430}
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include "amdgpu.h"
26#include "amdgpu_psp.h"
27#include "amdgpu_ucode.h"
28#include "soc15_common.h"
29#include "psp_v12_0.h"
30
31#include "mp/mp_12_0_0_offset.h"
32#include "mp/mp_12_0_0_sh_mask.h"
33#include "gc/gc_9_0_offset.h"
34#include "sdma0/sdma0_4_0_offset.h"
35#include "nbio/nbio_7_4_offset.h"
36
37#include "oss/osssys_4_0_offset.h"
38#include "oss/osssys_4_0_sh_mask.h"
39
40MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41/* address block */
42#define smnMP1_FIRMWARE_FLAGS 0x3010024
43
44static int psp_v12_0_init_microcode(struct psp_context *psp)
45{
46 struct amdgpu_device *adev = psp->adev;
47 const char *chip_name;
48 char fw_name[30];
49 int err = 0;
50 const struct psp_firmware_header_v1_0 *asd_hdr;
51
52 DRM_DEBUG("\n");
53
54 switch (adev->asic_type) {
55 case CHIP_RENOIR:
56 chip_name = "renoir";
57 break;
58 default:
59 BUG();
60 }
61
62 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
63 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
64 if (err)
65 goto out1;
66
67 err = amdgpu_ucode_validate(adev->psp.asd_fw);
68 if (err)
69 goto out1;
70
71 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
72 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
73 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
74 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
75 adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
76 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
77
78 return 0;
79
80out1:
81 release_firmware(adev->psp.asd_fw);
82 adev->psp.asd_fw = NULL;
83
84 return err;
85}
86
87static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
88{
89 int ret;
90 uint32_t psp_gfxdrv_command_reg = 0;
91 struct amdgpu_device *adev = psp->adev;
92 uint32_t sol_reg;
93
94 /* Check sOS sign of life register to confirm sys driver and sOS
95 * are already been loaded.
96 */
97 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
98 if (sol_reg) {
99 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
100 printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
101 return 0;
102 }
103
104 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
105 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
106 0x80000000, 0x80000000, false);
107 if (ret)
108 return ret;
109
110 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
111
112 /* Copy PSP System Driver binary to memory */
113 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
114
115 /* Provide the sys driver to bootloader */
116 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
117 (uint32_t)(psp->fw_pri_mc_addr >> 20));
118 psp_gfxdrv_command_reg = 1 << 16;
119 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
120 psp_gfxdrv_command_reg);
121
122 /* there might be handshake issue with hardware which needs delay */
123 mdelay(20);
124
125 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
126 0x80000000, 0x80000000, false);
127
128 return ret;
129}
130
131static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
132{
133 int ret;
134 unsigned int psp_gfxdrv_command_reg = 0;
135 struct amdgpu_device *adev = psp->adev;
136 uint32_t sol_reg;
137
138 /* Check sOS sign of life register to confirm sys driver and sOS
139 * are already been loaded.
140 */
141 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
142 if (sol_reg)
143 return 0;
144
145 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
146 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
147 0x80000000, 0x80000000, false);
148 if (ret)
149 return ret;
150
151 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
152
153 /* Copy Secure OS binary to PSP memory */
154 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
155
156 /* Provide the PSP secure OS to bootloader */
157 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
158 (uint32_t)(psp->fw_pri_mc_addr >> 20));
159 psp_gfxdrv_command_reg = 2 << 16;
160 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
161 psp_gfxdrv_command_reg);
162
163 /* there might be handshake issue with hardware which needs delay */
164 mdelay(20);
165 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
166 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
167 0, true);
168
169 return ret;
170}
171
172static void psp_v12_0_reroute_ih(struct psp_context *psp)
173{
174 struct amdgpu_device *adev = psp->adev;
175 uint32_t tmp;
176
177 /* Change IH ring for VMC */
178 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
179 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
180 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
181
182 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
183 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
184 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
185
186 mdelay(20);
187 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
188 0x80000000, 0x8000FFFF, false);
189
190 /* Change IH ring for UMC */
191 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
192 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
193
194 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
195 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
196 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
197
198 mdelay(20);
199 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
200 0x80000000, 0x8000FFFF, false);
201}
202
203static int psp_v12_0_ring_init(struct psp_context *psp,
204 enum psp_ring_type ring_type)
205{
206 int ret = 0;
207 struct psp_ring *ring;
208 struct amdgpu_device *adev = psp->adev;
209
210 psp_v12_0_reroute_ih(psp);
211
212 ring = &psp->km_ring;
213
214 ring->ring_type = ring_type;
215
216 /* allocate 4k Page of Local Frame Buffer memory for ring */
217 ring->ring_size = 0x1000;
218 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
219 AMDGPU_GEM_DOMAIN_VRAM,
220 &adev->firmware.rbuf,
221 &ring->ring_mem_mc_addr,
222 (void **)&ring->ring_mem);
223 if (ret) {
224 ring->ring_size = 0;
225 return ret;
226 }
227
228 return 0;
229}
230
231static bool psp_v12_0_support_vmr_ring(struct psp_context *psp)
232{
233 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
234 return true;
235 return false;
236}
237
238static int psp_v12_0_ring_create(struct psp_context *psp,
239 enum psp_ring_type ring_type)
240{
241 int ret = 0;
242 unsigned int psp_ring_reg = 0;
243 struct psp_ring *ring = &psp->km_ring;
244 struct amdgpu_device *adev = psp->adev;
245
246 if (psp_v12_0_support_vmr_ring(psp)) {
247 /* Write low address of the ring to C2PMSG_102 */
248 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
249 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
250 /* Write high address of the ring to C2PMSG_103 */
251 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
252 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
253
254 /* Write the ring initialization command to C2PMSG_101 */
255 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
256 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
257
258 /* there might be handshake issue with hardware which needs delay */
259 mdelay(20);
260
261 /* Wait for response flag (bit 31) in C2PMSG_101 */
262 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
263 0x80000000, 0x8000FFFF, false);
264
265 } else {
266 /* Write low address of the ring to C2PMSG_69 */
267 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
269 /* Write high address of the ring to C2PMSG_70 */
270 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
271 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
272 /* Write size of ring to C2PMSG_71 */
273 psp_ring_reg = ring->ring_size;
274 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
275 /* Write the ring initialization command to C2PMSG_64 */
276 psp_ring_reg = ring_type;
277 psp_ring_reg = psp_ring_reg << 16;
278 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
279
280 /* there might be handshake issue with hardware which needs delay */
281 mdelay(20);
282
283 /* Wait for response flag (bit 31) in C2PMSG_64 */
284 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
285 0x80000000, 0x8000FFFF, false);
286 }
287
288 return ret;
289}
290
291static int psp_v12_0_ring_stop(struct psp_context *psp,
292 enum psp_ring_type ring_type)
293{
294 int ret = 0;
295 struct amdgpu_device *adev = psp->adev;
296
297 /* Write the ring destroy command*/
298 if (psp_v12_0_support_vmr_ring(psp))
299 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
300 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
301 else
302 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
303 GFX_CTRL_CMD_ID_DESTROY_RINGS);
304
305 /* there might be handshake issue with hardware which needs delay */
306 mdelay(20);
307
308 /* Wait for response flag (bit 31) */
309 if (psp_v12_0_support_vmr_ring(psp))
310 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
311 0x80000000, 0x80000000, false);
312 else
313 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
314 0x80000000, 0x80000000, false);
315
316 return ret;
317}
318
319static int psp_v12_0_ring_destroy(struct psp_context *psp,
320 enum psp_ring_type ring_type)
321{
322 int ret = 0;
323 struct psp_ring *ring = &psp->km_ring;
324 struct amdgpu_device *adev = psp->adev;
325
326 ret = psp_v12_0_ring_stop(psp, ring_type);
327 if (ret)
328 DRM_ERROR("Fail to stop psp ring\n");
329
330 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
331 &ring->ring_mem_mc_addr,
332 (void **)&ring->ring_mem);
333
334 return ret;
335}
336
337static int psp_v12_0_cmd_submit(struct psp_context *psp,
338 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
339 int index)
340{
341 unsigned int psp_write_ptr_reg = 0;
342 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
343 struct psp_ring *ring = &psp->km_ring;
344 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
345 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
346 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
347 struct amdgpu_device *adev = psp->adev;
348 uint32_t ring_size_dw = ring->ring_size / 4;
349 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
350
351 /* KM (GPCOM) prepare write pointer */
352 if (psp_v12_0_support_vmr_ring(psp))
353 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
354 else
355 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
356
357 /* Update KM RB frame pointer to new frame */
358 /* write_frame ptr increments by size of rb_frame in bytes */
359 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
360 if ((psp_write_ptr_reg % ring_size_dw) == 0)
361 write_frame = ring_buffer_start;
362 else
363 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
364 /* Check invalid write_frame ptr address */
365 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
366 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
367 ring_buffer_start, ring_buffer_end, write_frame);
368 DRM_ERROR("write_frame is pointing to address out of bounds\n");
369 return -EINVAL;
370 }
371
372 /* Initialize KM RB frame */
373 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
374
375 /* Update KM RB frame */
376 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
377 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
378 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
379 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
380 write_frame->fence_value = index;
381
382 /* Update the write Pointer in DWORDs */
383 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
384 if (psp_v12_0_support_vmr_ring(psp)) {
385 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
386 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
387 } else
388 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
389
390 return 0;
391}
392
393static int
394psp_v12_0_sram_map(struct amdgpu_device *adev,
395 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
396 unsigned int *sram_data_reg_offset,
397 enum AMDGPU_UCODE_ID ucode_id)
398{
399 int ret = 0;
400
401 switch (ucode_id) {
402/* TODO: needs to confirm */
403#if 0
404 case AMDGPU_UCODE_ID_SMC:
405 *sram_offset = 0;
406 *sram_addr_reg_offset = 0;
407 *sram_data_reg_offset = 0;
408 break;
409#endif
410
411 case AMDGPU_UCODE_ID_CP_CE:
412 *sram_offset = 0x0;
413 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
414 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
415 break;
416
417 case AMDGPU_UCODE_ID_CP_PFP:
418 *sram_offset = 0x0;
419 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
420 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
421 break;
422
423 case AMDGPU_UCODE_ID_CP_ME:
424 *sram_offset = 0x0;
425 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
426 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
427 break;
428
429 case AMDGPU_UCODE_ID_CP_MEC1:
430 *sram_offset = 0x10000;
431 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
432 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
433 break;
434
435 case AMDGPU_UCODE_ID_CP_MEC2:
436 *sram_offset = 0x10000;
437 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
438 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
439 break;
440
441 case AMDGPU_UCODE_ID_RLC_G:
442 *sram_offset = 0x2000;
443 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
444 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
445 break;
446
447 case AMDGPU_UCODE_ID_SDMA0:
448 *sram_offset = 0x0;
449 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
450 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
451 break;
452
453/* TODO: needs to confirm */
454#if 0
455 case AMDGPU_UCODE_ID_SDMA1:
456 *sram_offset = ;
457 *sram_addr_reg_offset = ;
458 break;
459
460 case AMDGPU_UCODE_ID_UVD:
461 *sram_offset = ;
462 *sram_addr_reg_offset = ;
463 break;
464
465 case AMDGPU_UCODE_ID_VCE:
466 *sram_offset = ;
467 *sram_addr_reg_offset = ;
468 break;
469#endif
470
471 case AMDGPU_UCODE_ID_MAXIMUM:
472 default:
473 ret = -EINVAL;
474 break;
475 }
476
477 return ret;
478}
479
480static bool psp_v12_0_compare_sram_data(struct psp_context *psp,
481 struct amdgpu_firmware_info *ucode,
482 enum AMDGPU_UCODE_ID ucode_type)
483{
484 int err = 0;
485 unsigned int fw_sram_reg_val = 0;
486 unsigned int fw_sram_addr_reg_offset = 0;
487 unsigned int fw_sram_data_reg_offset = 0;
488 unsigned int ucode_size;
489 uint32_t *ucode_mem = NULL;
490 struct amdgpu_device *adev = psp->adev;
491
492 err = psp_v12_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
493 &fw_sram_data_reg_offset, ucode_type);
494 if (err)
495 return false;
496
497 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
498
499 ucode_size = ucode->ucode_size;
500 ucode_mem = (uint32_t *)ucode->kaddr;
501 while (ucode_size) {
502 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
503
504 if (*ucode_mem != fw_sram_reg_val)
505 return false;
506
507 ucode_mem++;
508 /* 4 bytes */
509 ucode_size -= 4;
510 }
511
512 return true;
513}
514
515static int psp_v12_0_mode1_reset(struct psp_context *psp)
516{
517 int ret;
518 uint32_t offset;
519 struct amdgpu_device *adev = psp->adev;
520
521 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
522
523 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
524
525 if (ret) {
526 DRM_INFO("psp is not working correctly before mode1 reset!\n");
527 return -EINVAL;
528 }
529
530 /*send the mode 1 reset command*/
531 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
532
533 msleep(500);
534
535 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
536
537 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
538
539 if (ret) {
540 DRM_INFO("psp mode 1 reset failed!\n");
541 return -EINVAL;
542 }
543
544 DRM_INFO("psp mode1 reset succeed \n");
545
546 return 0;
547}
548
549static const struct psp_funcs psp_v12_0_funcs = {
550 .init_microcode = psp_v12_0_init_microcode,
551 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
552 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
553 .ring_init = psp_v12_0_ring_init,
554 .ring_create = psp_v12_0_ring_create,
555 .ring_stop = psp_v12_0_ring_stop,
556 .ring_destroy = psp_v12_0_ring_destroy,
557 .cmd_submit = psp_v12_0_cmd_submit,
558 .compare_sram_data = psp_v12_0_compare_sram_data,
559 .mode1_reset = psp_v12_0_mode1_reset,
560};
561
562void psp_v12_0_set_psp_funcs(struct psp_context *psp)
563{
564 psp->funcs = &psp_v12_0_funcs;
565}