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1/* SPDX-License-Identifier: GPL-2.0 */
2//
3// Spreadtrum divider clock driver
4//
5// Copyright (C) 2017 Spreadtrum, Inc.
6// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
7
8#ifndef _SPRD_DIV_H_
9#define _SPRD_DIV_H_
10
11#include "common.h"
12
13/**
14 * struct sprd_div_internal - Internal divider description
15 * @shift: Bit offset of the divider in its register
16 * @width: Width of the divider field in its register
17 *
18 * That structure represents a single divider, and is meant to be
19 * embedded in other structures representing the various clock
20 * classes.
21 */
22struct sprd_div_internal {
23 u8 shift;
24 u8 width;
25};
26
27#define _SPRD_DIV_CLK(_shift, _width) \
28 { \
29 .shift = _shift, \
30 .width = _width, \
31 }
32
33struct sprd_div {
34 struct sprd_div_internal div;
35 struct sprd_clk_common common;
36};
37
38#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
39 _shift, _width, _flags, _fn) \
40 struct sprd_div _struct = { \
41 .div = _SPRD_DIV_CLK(_shift, _width), \
42 .common = { \
43 .regmap = NULL, \
44 .reg = _reg, \
45 .hw.init = _fn(_name, _parent, \
46 &sprd_div_ops, _flags), \
47 } \
48 }
49
50#define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
51 _shift, _width, _flags) \
52 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
53 _shift, _width, _flags, CLK_HW_INIT)
54
55#define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \
56 _shift, _width, _flags) \
57 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
58 _shift, _width, _flags, CLK_HW_INIT_HW)
59
60static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)
61{
62 struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
63
64 return container_of(common, struct sprd_div, common);
65}
66
67long sprd_div_helper_round_rate(struct sprd_clk_common *common,
68 const struct sprd_div_internal *div,
69 unsigned long rate,
70 unsigned long *parent_rate);
71
72unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
73 const struct sprd_div_internal *div,
74 unsigned long parent_rate);
75
76int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
77 const struct sprd_div_internal *div,
78 unsigned long rate,
79 unsigned long parent_rate);
80
81extern const struct clk_ops sprd_div_ops;
82
83#endif /* _SPRD_DIV_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2//
3// Spreadtrum divider clock driver
4//
5// Copyright (C) 2017 Spreadtrum, Inc.
6// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
7
8#ifndef _SPRD_DIV_H_
9#define _SPRD_DIV_H_
10
11#include "common.h"
12
13/**
14 * struct sprd_div_internal - Internal divider description
15 * @shift: Bit offset of the divider in its register
16 * @width: Width of the divider field in its register
17 *
18 * That structure represents a single divider, and is meant to be
19 * embedded in other structures representing the various clock
20 * classes.
21 */
22struct sprd_div_internal {
23 u8 shift;
24 u8 width;
25};
26
27#define _SPRD_DIV_CLK(_shift, _width) \
28 { \
29 .shift = _shift, \
30 .width = _width, \
31 }
32
33struct sprd_div {
34 struct sprd_div_internal div;
35 struct sprd_clk_common common;
36};
37
38#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
39 _shift, _width, _flags, _fn) \
40 struct sprd_div _struct = { \
41 .div = _SPRD_DIV_CLK(_shift, _width), \
42 .common = { \
43 .regmap = NULL, \
44 .reg = _reg, \
45 .hw.init = _fn(_name, _parent, \
46 &sprd_div_ops, _flags), \
47 } \
48 }
49
50#define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
51 _shift, _width, _flags) \
52 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
53 _shift, _width, _flags, CLK_HW_INIT)
54
55#define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \
56 _shift, _width, _flags) \
57 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
58 _shift, _width, _flags, CLK_HW_INIT_HW)
59
60static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)
61{
62 struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
63
64 return container_of(common, struct sprd_div, common);
65}
66
67long sprd_div_helper_round_rate(struct sprd_clk_common *common,
68 const struct sprd_div_internal *div,
69 unsigned long rate,
70 unsigned long *parent_rate);
71
72unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
73 const struct sprd_div_internal *div,
74 unsigned long parent_rate);
75
76int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
77 const struct sprd_div_internal *div,
78 unsigned long rate,
79 unsigned long parent_rate);
80
81extern const struct clk_ops sprd_div_ops;
82
83#endif /* _SPRD_DIV_H_ */