1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2020 MediaTek Inc.
 4 * Author: Yong Liang <yong.liang@mediatek.com>
 5 */
 6
 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
 8#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
 9
10#define MT8192_TOPRGU_MM_SW_RST					1
11#define MT8192_TOPRGU_MFG_SW_RST				2
12#define MT8192_TOPRGU_VENC_SW_RST				3
13#define MT8192_TOPRGU_VDEC_SW_RST				4
14#define MT8192_TOPRGU_IMG_SW_RST				5
15#define MT8192_TOPRGU_MD_SW_RST					7
16#define MT8192_TOPRGU_CONN_SW_RST				9
17#define MT8192_TOPRGU_CONN_MCU_SW_RST			12
18#define MT8192_TOPRGU_IPU0_SW_RST				14
19#define MT8192_TOPRGU_IPU1_SW_RST				15
20#define MT8192_TOPRGU_AUDIO_SW_RST				17
21#define MT8192_TOPRGU_CAMSYS_SW_RST				18
22#define MT8192_TOPRGU_MJC_SW_RST				19
23#define MT8192_TOPRGU_C2K_S2_SW_RST				20
24#define MT8192_TOPRGU_C2K_SW_RST				21
25#define MT8192_TOPRGU_PERI_SW_RST				22
26#define MT8192_TOPRGU_PERI_AO_SW_RST			23
27
28#define MT8192_TOPRGU_SW_RST_NUM				23
29
30#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */