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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#include <linux/pm_runtime.h>
7
8#include "i915_drv.h"
9#include "i915_vgpu.h"
10#include "intel_gt.h"
11#include "intel_gt_pm.h"
12#include "intel_rc6.h"
13#include "intel_sideband.h"
14
15/**
16 * DOC: RC6
17 *
18 * RC6 is a special power stage which allows the GPU to enter an very
19 * low-voltage mode when idle, using down to 0V while at this stage. This
20 * stage is entered automatically when the GPU is idle when RC6 support is
21 * enabled, and as soon as new workload arises GPU wakes up automatically as
22 * well.
23 *
24 * There are different RC6 modes available in Intel GPU, which differentiate
25 * among each other with the latency required to enter and leave RC6 and
26 * voltage consumed by the GPU in different states.
27 *
28 * The combination of the following flags define which states GPU is allowed
29 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
30 * RC6pp is deepest RC6. Their support by hardware varies according to the
31 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
32 * which brings the most power savings; deeper states save more power, but
33 * require higher latency to switch to and wake up.
34 */
35
36static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6)
37{
38 return container_of(rc6, struct intel_gt, rc6);
39}
40
41static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc)
42{
43 return rc6_to_gt(rc)->uncore;
44}
45
46static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
47{
48 return rc6_to_gt(rc)->i915;
49}
50
51static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
52{
53 intel_uncore_write_fw(uncore, reg, val);
54}
55
56static void gen11_rc6_enable(struct intel_rc6 *rc6)
57{
58 struct intel_gt *gt = rc6_to_gt(rc6);
59 struct intel_uncore *uncore = gt->uncore;
60 struct intel_engine_cs *engine;
61 enum intel_engine_id id;
62 u32 pg_enable;
63 int i;
64
65 /* 2b: Program RC6 thresholds.*/
66 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
67 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
68
69 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
70 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
71 for_each_engine(engine, rc6_to_gt(rc6), id)
72 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
73
74 set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
75
76 set(uncore, GEN6_RC_SLEEP, 0);
77
78 set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
79
80 /*
81 * 2c: Program Coarse Power Gating Policies.
82 *
83 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
84 * use instead is a more conservative estimate for the maximum time
85 * it takes us to service a CS interrupt and submit a new ELSP - that
86 * is the time which the GPU is idle waiting for the CPU to select the
87 * next request to execute. If the idle hysteresis is less than that
88 * interrupt service latency, the hardware will automatically gate
89 * the power well and we will then incur the wake up cost on top of
90 * the service latency. A similar guide from plane_state is that we
91 * do not want the enable hysteresis to less than the wakeup latency.
92 *
93 * igt/gem_exec_nop/sequential provides a rough estimate for the
94 * service latency, and puts it under 10us for Icelake, similar to
95 * Broadwell+, To be conservative, we want to factor in a context
96 * switch on top (due to ksoftirqd).
97 */
98 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
99 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
100
101 /* 3a: Enable RC6 */
102 rc6->ctl_enable =
103 GEN6_RC_CTL_HW_ENABLE |
104 GEN6_RC_CTL_RC6_ENABLE |
105 GEN6_RC_CTL_EI_MODE(1);
106
107 pg_enable =
108 GEN9_RENDER_PG_ENABLE |
109 GEN9_MEDIA_PG_ENABLE |
110 GEN11_MEDIA_SAMPLER_PG_ENABLE;
111
112 if (GRAPHICS_VER(gt->i915) >= 12) {
113 for (i = 0; i < I915_MAX_VCS; i++)
114 if (HAS_ENGINE(gt, _VCS(i)))
115 pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
116 VDN_MFX_POWERGATE_ENABLE(i));
117 }
118
119 set(uncore, GEN9_PG_ENABLE, pg_enable);
120}
121
122static void gen9_rc6_enable(struct intel_rc6 *rc6)
123{
124 struct intel_uncore *uncore = rc6_to_uncore(rc6);
125 struct intel_engine_cs *engine;
126 enum intel_engine_id id;
127
128 /* 2b: Program RC6 thresholds.*/
129 if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
130 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
131 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
132 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
133 /*
134 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
135 * when CPG is enabled
136 */
137 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
138 } else {
139 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
140 }
141
142 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
143 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
144 for_each_engine(engine, rc6_to_gt(rc6), id)
145 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
146
147 set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
148
149 set(uncore, GEN6_RC_SLEEP, 0);
150
151 /*
152 * 2c: Program Coarse Power Gating Policies.
153 *
154 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
155 * use instead is a more conservative estimate for the maximum time
156 * it takes us to service a CS interrupt and submit a new ELSP - that
157 * is the time which the GPU is idle waiting for the CPU to select the
158 * next request to execute. If the idle hysteresis is less than that
159 * interrupt service latency, the hardware will automatically gate
160 * the power well and we will then incur the wake up cost on top of
161 * the service latency. A similar guide from plane_state is that we
162 * do not want the enable hysteresis to less than the wakeup latency.
163 *
164 * igt/gem_exec_nop/sequential provides a rough estimate for the
165 * service latency, and puts it around 10us for Broadwell (and other
166 * big core) and around 40us for Broxton (and other low power cores).
167 * [Note that for legacy ringbuffer submission, this is less than 1us!]
168 * However, the wakeup latency on Broxton is closer to 100us. To be
169 * conservative, we have to factor in a context switch on top (due
170 * to ksoftirqd).
171 */
172 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
173 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
174
175 /* 3a: Enable RC6 */
176 set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
177
178 rc6->ctl_enable =
179 GEN6_RC_CTL_HW_ENABLE |
180 GEN6_RC_CTL_RC6_ENABLE |
181 GEN6_RC_CTL_EI_MODE(1);
182
183 /*
184 * WaRsDisableCoarsePowerGating:skl,cnl
185 * - Render/Media PG need to be disabled with RC6.
186 */
187 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
188 set(uncore, GEN9_PG_ENABLE,
189 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
190}
191
192static void gen8_rc6_enable(struct intel_rc6 *rc6)
193{
194 struct intel_uncore *uncore = rc6_to_uncore(rc6);
195 struct intel_engine_cs *engine;
196 enum intel_engine_id id;
197
198 /* 2b: Program RC6 thresholds.*/
199 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
200 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
201 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
202 for_each_engine(engine, rc6_to_gt(rc6), id)
203 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
204 set(uncore, GEN6_RC_SLEEP, 0);
205 set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
206
207 /* 3: Enable RC6 */
208 rc6->ctl_enable =
209 GEN6_RC_CTL_HW_ENABLE |
210 GEN7_RC_CTL_TO_MODE |
211 GEN6_RC_CTL_RC6_ENABLE;
212}
213
214static void gen6_rc6_enable(struct intel_rc6 *rc6)
215{
216 struct intel_uncore *uncore = rc6_to_uncore(rc6);
217 struct drm_i915_private *i915 = rc6_to_i915(rc6);
218 struct intel_engine_cs *engine;
219 enum intel_engine_id id;
220 u32 rc6vids, rc6_mask;
221 int ret;
222
223 set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
224 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
225 set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
226 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
227 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
228
229 for_each_engine(engine, rc6_to_gt(rc6), id)
230 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
231
232 set(uncore, GEN6_RC_SLEEP, 0);
233 set(uncore, GEN6_RC1e_THRESHOLD, 1000);
234 set(uncore, GEN6_RC6_THRESHOLD, 50000);
235 set(uncore, GEN6_RC6p_THRESHOLD, 150000);
236 set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
237
238 /* We don't use those on Haswell */
239 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
240 if (HAS_RC6p(i915))
241 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
242 if (HAS_RC6pp(i915))
243 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
244 rc6->ctl_enable =
245 rc6_mask |
246 GEN6_RC_CTL_EI_MODE(1) |
247 GEN6_RC_CTL_HW_ENABLE;
248
249 rc6vids = 0;
250 ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
251 &rc6vids, NULL);
252 if (GRAPHICS_VER(i915) == 6 && ret) {
253 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
254 } else if (GRAPHICS_VER(i915) == 6 &&
255 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
256 drm_dbg(&i915->drm,
257 "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
258 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
259 rc6vids &= 0xffff00;
260 rc6vids |= GEN6_ENCODE_RC6_VID(450);
261 ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
262 if (ret)
263 drm_err(&i915->drm,
264 "Couldn't fix incorrect rc6 voltage\n");
265 }
266}
267
268/* Check that the pcbr address is not empty. */
269static int chv_rc6_init(struct intel_rc6 *rc6)
270{
271 struct intel_uncore *uncore = rc6_to_uncore(rc6);
272 struct drm_i915_private *i915 = rc6_to_i915(rc6);
273 resource_size_t pctx_paddr, paddr;
274 resource_size_t pctx_size = 32 * SZ_1K;
275 u32 pcbr;
276
277 pcbr = intel_uncore_read(uncore, VLV_PCBR);
278 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
279 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");
280 paddr = i915->dsm.end + 1 - pctx_size;
281 GEM_BUG_ON(paddr > U32_MAX);
282
283 pctx_paddr = (paddr & ~4095);
284 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
285 }
286
287 return 0;
288}
289
290static int vlv_rc6_init(struct intel_rc6 *rc6)
291{
292 struct drm_i915_private *i915 = rc6_to_i915(rc6);
293 struct intel_uncore *uncore = rc6_to_uncore(rc6);
294 struct drm_i915_gem_object *pctx;
295 resource_size_t pctx_paddr;
296 resource_size_t pctx_size = 24 * SZ_1K;
297 u32 pcbr;
298
299 pcbr = intel_uncore_read(uncore, VLV_PCBR);
300 if (pcbr) {
301 /* BIOS set it up already, grab the pre-alloc'd space */
302 resource_size_t pcbr_offset;
303
304 pcbr_offset = (pcbr & ~4095) - i915->dsm.start;
305 pctx = i915_gem_object_create_stolen_for_preallocated(i915,
306 pcbr_offset,
307 pctx_size);
308 if (IS_ERR(pctx))
309 return PTR_ERR(pctx);
310
311 goto out;
312 }
313
314 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");
315
316 /*
317 * From the Gunit register HAS:
318 * The Gfx driver is expected to program this register and ensure
319 * proper allocation within Gfx stolen memory. For example, this
320 * register should be programmed such than the PCBR range does not
321 * overlap with other ranges, such as the frame buffer, protected
322 * memory, or any other relevant ranges.
323 */
324 pctx = i915_gem_object_create_stolen(i915, pctx_size);
325 if (IS_ERR(pctx)) {
326 drm_dbg(&i915->drm,
327 "not enough stolen space for PCTX, disabling\n");
328 return PTR_ERR(pctx);
329 }
330
331 GEM_BUG_ON(range_overflows_end_t(u64,
332 i915->dsm.start,
333 pctx->stolen->start,
334 U32_MAX));
335 pctx_paddr = i915->dsm.start + pctx->stolen->start;
336 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
337
338out:
339 rc6->pctx = pctx;
340 return 0;
341}
342
343static void chv_rc6_enable(struct intel_rc6 *rc6)
344{
345 struct intel_uncore *uncore = rc6_to_uncore(rc6);
346 struct intel_engine_cs *engine;
347 enum intel_engine_id id;
348
349 /* 2a: Program RC6 thresholds.*/
350 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
351 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
352 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
353
354 for_each_engine(engine, rc6_to_gt(rc6), id)
355 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
356 set(uncore, GEN6_RC_SLEEP, 0);
357
358 /* TO threshold set to 500 us (0x186 * 1.28 us) */
359 set(uncore, GEN6_RC6_THRESHOLD, 0x186);
360
361 /* Allows RC6 residency counter to work */
362 set(uncore, VLV_COUNTER_CONTROL,
363 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
364 VLV_MEDIA_RC6_COUNT_EN |
365 VLV_RENDER_RC6_COUNT_EN));
366
367 /* 3: Enable RC6 */
368 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
369}
370
371static void vlv_rc6_enable(struct intel_rc6 *rc6)
372{
373 struct intel_uncore *uncore = rc6_to_uncore(rc6);
374 struct intel_engine_cs *engine;
375 enum intel_engine_id id;
376
377 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
378 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
379 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
380
381 for_each_engine(engine, rc6_to_gt(rc6), id)
382 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
383
384 set(uncore, GEN6_RC6_THRESHOLD, 0x557);
385
386 /* Allows RC6 residency counter to work */
387 set(uncore, VLV_COUNTER_CONTROL,
388 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
389 VLV_MEDIA_RC0_COUNT_EN |
390 VLV_RENDER_RC0_COUNT_EN |
391 VLV_MEDIA_RC6_COUNT_EN |
392 VLV_RENDER_RC6_COUNT_EN));
393
394 rc6->ctl_enable =
395 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
396}
397
398static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
399{
400 struct intel_uncore *uncore = rc6_to_uncore(rc6);
401 struct drm_i915_private *i915 = rc6_to_i915(rc6);
402 u32 rc6_ctx_base, rc_ctl, rc_sw_target;
403 bool enable_rc6 = true;
404
405 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL);
406 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE);
407 rc_sw_target &= RC_SW_TARGET_STATE_MASK;
408 rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT;
409 drm_dbg(&i915->drm, "BIOS enabled RC states: "
410 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
411 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
412 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
413 rc_sw_target);
414
415 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
416 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n");
417 enable_rc6 = false;
418 }
419
420 /*
421 * The exact context size is not known for BXT, so assume a page size
422 * for this check.
423 */
424 rc6_ctx_base =
425 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
426 if (!(rc6_ctx_base >= i915->dsm_reserved.start &&
427 rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) {
428 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n");
429 enable_rc6 = false;
430 }
431
432 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
433 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
434 (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
435 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
436 drm_dbg(&i915->drm,
437 "Engine Idle wait time not set properly.\n");
438 enable_rc6 = false;
439 }
440
441 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) ||
442 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) ||
443 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) {
444 drm_dbg(&i915->drm, "Pushbus not setup properly.\n");
445 enable_rc6 = false;
446 }
447
448 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) {
449 drm_dbg(&i915->drm, "GFX pause not setup properly.\n");
450 enable_rc6 = false;
451 }
452
453 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) {
454 drm_dbg(&i915->drm, "GPM control not setup properly.\n");
455 enable_rc6 = false;
456 }
457
458 return enable_rc6;
459}
460
461static bool rc6_supported(struct intel_rc6 *rc6)
462{
463 struct drm_i915_private *i915 = rc6_to_i915(rc6);
464
465 if (!HAS_RC6(i915))
466 return false;
467
468 if (intel_vgpu_active(i915))
469 return false;
470
471 if (is_mock_gt(rc6_to_gt(rc6)))
472 return false;
473
474 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) {
475 drm_notice(&i915->drm,
476 "RC6 and powersaving disabled by BIOS\n");
477 return false;
478 }
479
480 return true;
481}
482
483static void rpm_get(struct intel_rc6 *rc6)
484{
485 GEM_BUG_ON(rc6->wakeref);
486 pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev);
487 rc6->wakeref = true;
488}
489
490static void rpm_put(struct intel_rc6 *rc6)
491{
492 GEM_BUG_ON(!rc6->wakeref);
493 pm_runtime_put(rc6_to_i915(rc6)->drm.dev);
494 rc6->wakeref = false;
495}
496
497static bool pctx_corrupted(struct intel_rc6 *rc6)
498{
499 struct drm_i915_private *i915 = rc6_to_i915(rc6);
500
501 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915))
502 return false;
503
504 if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO))
505 return false;
506
507 drm_notice(&i915->drm,
508 "RC6 context corruption, disabling runtime power management\n");
509 return true;
510}
511
512static void __intel_rc6_disable(struct intel_rc6 *rc6)
513{
514 struct drm_i915_private *i915 = rc6_to_i915(rc6);
515 struct intel_uncore *uncore = rc6_to_uncore(rc6);
516
517 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
518 if (GRAPHICS_VER(i915) >= 9)
519 set(uncore, GEN9_PG_ENABLE, 0);
520 set(uncore, GEN6_RC_CONTROL, 0);
521 set(uncore, GEN6_RC_STATE, 0);
522 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
523}
524
525void intel_rc6_init(struct intel_rc6 *rc6)
526{
527 struct drm_i915_private *i915 = rc6_to_i915(rc6);
528 int err;
529
530 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */
531 rpm_get(rc6);
532
533 if (!rc6_supported(rc6))
534 return;
535
536 if (IS_CHERRYVIEW(i915))
537 err = chv_rc6_init(rc6);
538 else if (IS_VALLEYVIEW(i915))
539 err = vlv_rc6_init(rc6);
540 else
541 err = 0;
542
543 /* Sanitize rc6, ensure it is disabled before we are ready. */
544 __intel_rc6_disable(rc6);
545
546 rc6->supported = err == 0;
547}
548
549void intel_rc6_sanitize(struct intel_rc6 *rc6)
550{
551 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency));
552
553 if (rc6->enabled) { /* unbalanced suspend/resume */
554 rpm_get(rc6);
555 rc6->enabled = false;
556 }
557
558 if (rc6->supported)
559 __intel_rc6_disable(rc6);
560}
561
562void intel_rc6_enable(struct intel_rc6 *rc6)
563{
564 struct drm_i915_private *i915 = rc6_to_i915(rc6);
565 struct intel_uncore *uncore = rc6_to_uncore(rc6);
566
567 if (!rc6->supported)
568 return;
569
570 GEM_BUG_ON(rc6->enabled);
571
572 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
573
574 if (IS_CHERRYVIEW(i915))
575 chv_rc6_enable(rc6);
576 else if (IS_VALLEYVIEW(i915))
577 vlv_rc6_enable(rc6);
578 else if (GRAPHICS_VER(i915) >= 11)
579 gen11_rc6_enable(rc6);
580 else if (GRAPHICS_VER(i915) >= 9)
581 gen9_rc6_enable(rc6);
582 else if (IS_BROADWELL(i915))
583 gen8_rc6_enable(rc6);
584 else if (GRAPHICS_VER(i915) >= 6)
585 gen6_rc6_enable(rc6);
586
587 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
588 if (NEEDS_RC6_CTX_CORRUPTION_WA(i915))
589 rc6->ctl_enable = 0;
590
591 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
592
593 if (unlikely(pctx_corrupted(rc6)))
594 return;
595
596 /* rc6 is ready, runtime-pm is go! */
597 rpm_put(rc6);
598 rc6->enabled = true;
599}
600
601void intel_rc6_unpark(struct intel_rc6 *rc6)
602{
603 struct intel_uncore *uncore = rc6_to_uncore(rc6);
604
605 if (!rc6->enabled)
606 return;
607
608 /* Restore HW timers for automatic RC6 entry while busy */
609 set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
610}
611
612void intel_rc6_park(struct intel_rc6 *rc6)
613{
614 struct intel_uncore *uncore = rc6_to_uncore(rc6);
615 unsigned int target;
616
617 if (!rc6->enabled)
618 return;
619
620 if (unlikely(pctx_corrupted(rc6))) {
621 intel_rc6_disable(rc6);
622 return;
623 }
624
625 if (!rc6->manual)
626 return;
627
628 /* Turn off the HW timers and go directly to rc6 */
629 set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
630
631 if (HAS_RC6pp(rc6_to_i915(rc6)))
632 target = 0x6; /* deepest rc6 */
633 else if (HAS_RC6p(rc6_to_i915(rc6)))
634 target = 0x5; /* deep rc6 */
635 else
636 target = 0x4; /* normal rc6 */
637 set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
638}
639
640void intel_rc6_disable(struct intel_rc6 *rc6)
641{
642 if (!rc6->enabled)
643 return;
644
645 rpm_get(rc6);
646 rc6->enabled = false;
647
648 __intel_rc6_disable(rc6);
649}
650
651void intel_rc6_fini(struct intel_rc6 *rc6)
652{
653 struct drm_i915_gem_object *pctx;
654
655 intel_rc6_disable(rc6);
656
657 pctx = fetch_and_zero(&rc6->pctx);
658 if (pctx)
659 i915_gem_object_put(pctx);
660
661 if (rc6->wakeref)
662 rpm_put(rc6);
663}
664
665static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
666{
667 u32 lower, upper, tmp;
668 int loop = 2;
669
670 /*
671 * The register accessed do not need forcewake. We borrow
672 * uncore lock to prevent concurrent access to range reg.
673 */
674 lockdep_assert_held(&uncore->lock);
675
676 /*
677 * vlv and chv residency counters are 40 bits in width.
678 * With a control bit, we can choose between upper or lower
679 * 32bit window into this counter.
680 *
681 * Although we always use the counter in high-range mode elsewhere,
682 * userspace may attempt to read the value before rc6 is initialised,
683 * before we have set the default VLV_COUNTER_CONTROL value. So always
684 * set the high bit to be safe.
685 */
686 set(uncore, VLV_COUNTER_CONTROL,
687 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
688 upper = intel_uncore_read_fw(uncore, reg);
689 do {
690 tmp = upper;
691
692 set(uncore, VLV_COUNTER_CONTROL,
693 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
694 lower = intel_uncore_read_fw(uncore, reg);
695
696 set(uncore, VLV_COUNTER_CONTROL,
697 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
698 upper = intel_uncore_read_fw(uncore, reg);
699 } while (upper != tmp && --loop);
700
701 /*
702 * Everywhere else we always use VLV_COUNTER_CONTROL with the
703 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
704 * now.
705 */
706
707 return lower | (u64)upper << 8;
708}
709
710u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
711{
712 struct drm_i915_private *i915 = rc6_to_i915(rc6);
713 struct intel_uncore *uncore = rc6_to_uncore(rc6);
714 u64 time_hw, prev_hw, overflow_hw;
715 unsigned int fw_domains;
716 unsigned long flags;
717 unsigned int i;
718 u32 mul, div;
719
720 if (!rc6->supported)
721 return 0;
722
723 /*
724 * Store previous hw counter values for counter wrap-around handling.
725 *
726 * There are only four interesting registers and they live next to each
727 * other so we can use the relative address, compared to the smallest
728 * one as the index into driver storage.
729 */
730 i = (i915_mmio_reg_offset(reg) -
731 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
732 if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))
733 return 0;
734
735 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
736
737 spin_lock_irqsave(&uncore->lock, flags);
738 intel_uncore_forcewake_get__locked(uncore, fw_domains);
739
740 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
741 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
742 mul = 1000000;
743 div = i915->czclk_freq;
744 overflow_hw = BIT_ULL(40);
745 time_hw = vlv_residency_raw(uncore, reg);
746 } else {
747 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
748 if (IS_GEN9_LP(i915)) {
749 mul = 10000;
750 div = 12;
751 } else {
752 mul = 1280;
753 div = 1;
754 }
755
756 overflow_hw = BIT_ULL(32);
757 time_hw = intel_uncore_read_fw(uncore, reg);
758 }
759
760 /*
761 * Counter wrap handling.
762 *
763 * But relying on a sufficient frequency of queries otherwise counters
764 * can still wrap.
765 */
766 prev_hw = rc6->prev_hw_residency[i];
767 rc6->prev_hw_residency[i] = time_hw;
768
769 /* RC6 delta from last sample. */
770 if (time_hw >= prev_hw)
771 time_hw -= prev_hw;
772 else
773 time_hw += overflow_hw - prev_hw;
774
775 /* Add delta to RC6 extended raw driver copy. */
776 time_hw += rc6->cur_residency[i];
777 rc6->cur_residency[i] = time_hw;
778
779 intel_uncore_forcewake_put__locked(uncore, fw_domains);
780 spin_unlock_irqrestore(&uncore->lock, flags);
781
782 return mul_u64_u32_div(time_hw, mul, div);
783}
784
785u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
786{
787 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
788}
789
790#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
791#include "selftest_rc6.c"
792#endif