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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 *
5 */
6
7#include "i915_drv.h"
8#include "intel_de.h"
9#include "intel_display_types.h"
10#include "intel_vrr.h"
11
12bool intel_vrr_is_capable(struct drm_connector *connector)
13{
14 struct intel_dp *intel_dp;
15 const struct drm_display_info *info = &connector->display_info;
16 struct drm_i915_private *i915 = to_i915(connector->dev);
17
18 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
19 connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
20 return false;
21
22 intel_dp = intel_attached_dp(to_intel_connector(connector));
23 /*
24 * DP Sink is capable of VRR video timings if
25 * Ignore MSA bit is set in DPCD.
26 * EDID monitor range also should be atleast 10 for reasonable
27 * Adaptive Sync or Variable Refresh Rate end user experience.
28 */
29 return HAS_VRR(i915) &&
30 drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
31 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
32}
33
34void
35intel_vrr_check_modeset(struct intel_atomic_state *state)
36{
37 int i;
38 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
39 struct intel_crtc *crtc;
40
41 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
42 new_crtc_state, i) {
43 if (new_crtc_state->uapi.vrr_enabled !=
44 old_crtc_state->uapi.vrr_enabled)
45 new_crtc_state->uapi.mode_changed = true;
46 }
47}
48
49/*
50 * Without VRR registers get latched at:
51 * vblank_start
52 *
53 * With VRR the earliest registers can get latched is:
54 * intel_vrr_vmin_vblank_start(), which if we want to maintain
55 * the correct min vtotal is >=vblank_start+1
56 *
57 * The latest point registers can get latched is the vmax decision boundary:
58 * intel_vrr_vmax_vblank_start()
59 *
60 * Between those two points the vblank exit starts (and hence registers get
61 * latched) ASAP after a push is sent.
62 *
63 * framestart_delay is programmable 0-3.
64 */
65static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
66{
67 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
68 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
69
70 /* The hw imposes the extra scanline before frame start */
71 if (DISPLAY_VER(i915) >= 13)
72 return crtc_state->vrr.guardband + i915->framestart_delay + 1;
73 else
74 return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
75}
76
77int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
78{
79 /* Min vblank actually determined by flipline that is always >=vmin+1 */
80 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
81}
82
83int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
84{
85 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
86}
87
88void
89intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
90 struct drm_connector_state *conn_state)
91{
92 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
93 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
94 struct intel_connector *connector =
95 to_intel_connector(conn_state->connector);
96 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
97 const struct drm_display_info *info = &connector->base.display_info;
98 int vmin, vmax;
99
100 if (!intel_vrr_is_capable(&connector->base))
101 return;
102
103 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
104 return;
105
106 if (!crtc_state->uapi.vrr_enabled)
107 return;
108
109 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
110 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
111 vmax = adjusted_mode->crtc_clock * 1000 /
112 (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
113
114 vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal);
115 vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
116
117 if (vmin >= vmax)
118 return;
119
120 /*
121 * flipline determines the min vblank length the hardware will
122 * generate, and flipline>=vmin+1, hence we reduce vmin by one
123 * to make sure we can get the actual min vblank length.
124 */
125 crtc_state->vrr.vmin = vmin - 1;
126 crtc_state->vrr.vmax = vmax;
127 crtc_state->vrr.enable = true;
128
129 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
130
131 /*
132 * For XE_LPD+, we use guardband and pipeline override
133 * is deprecated.
134 */
135 if (DISPLAY_VER(i915) >= 13)
136 crtc_state->vrr.guardband =
137 crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
138 i915->window2_delay;
139 else
140 /*
141 * FIXME: s/4/framestart_delay+1/ to get consistent
142 * earliest/latest points for register latching regardless
143 * of the framestart_delay used?
144 *
145 * FIXME: this really needs the extra scanline to provide consistent
146 * behaviour for all framestart_delay values. Otherwise with
147 * framestart_delay==3 we will end up extending the min vblank by
148 * one extra line.
149 */
150 crtc_state->vrr.pipeline_full =
151 min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
152
153 crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
154}
155
156void intel_vrr_enable(struct intel_encoder *encoder,
157 const struct intel_crtc_state *crtc_state)
158{
159 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
160 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
161 u32 trans_vrr_ctl;
162
163 if (!crtc_state->vrr.enable)
164 return;
165
166 if (DISPLAY_VER(dev_priv) >= 13)
167 trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
168 VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
169 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
170 else
171 trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
172 VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
173 VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
174 VRR_CTL_PIPELINE_FULL_OVERRIDE;
175
176 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
177 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
178 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl);
179 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
180 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
181}
182
183void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
184{
185 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
187 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
188
189 if (!crtc_state->vrr.enable)
190 return;
191
192 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
193 TRANS_PUSH_EN | TRANS_PUSH_SEND);
194}
195
196void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
197{
198 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
199 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
200 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
201
202 if (!old_crtc_state->vrr.enable)
203 return;
204
205 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
206 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
207}
208
209void intel_vrr_get_config(struct intel_crtc *crtc,
210 struct intel_crtc_state *crtc_state)
211{
212 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
213 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
214 u32 trans_vrr_ctl;
215
216 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
217 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
218 if (!crtc_state->vrr.enable)
219 return;
220
221 if (DISPLAY_VER(dev_priv) >= 13)
222 crtc_state->vrr.guardband =
223 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
224 else
225 if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
226 crtc_state->vrr.pipeline_full =
227 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
228 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
229 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
230 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
231 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
232
233 crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
234}