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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5#include "intel_atomic.h"
6#include "intel_ddi.h"
7#include "intel_ddi_buf_trans.h"
8#include "intel_de.h"
9#include "intel_display_types.h"
10#include "intel_fdi.h"
11
12/* units of 100MHz */
13static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
14{
15 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
16 return crtc_state->fdi_lanes;
17
18 return 0;
19}
20
21static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
22 struct intel_crtc_state *pipe_config)
23{
24 struct drm_i915_private *dev_priv = to_i915(dev);
25 struct drm_atomic_state *state = pipe_config->uapi.state;
26 struct intel_crtc *other_crtc;
27 struct intel_crtc_state *other_crtc_state;
28
29 drm_dbg_kms(&dev_priv->drm,
30 "checking fdi config on pipe %c, lanes %i\n",
31 pipe_name(pipe), pipe_config->fdi_lanes);
32 if (pipe_config->fdi_lanes > 4) {
33 drm_dbg_kms(&dev_priv->drm,
34 "invalid fdi lane config on pipe %c: %i lanes\n",
35 pipe_name(pipe), pipe_config->fdi_lanes);
36 return -EINVAL;
37 }
38
39 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
40 if (pipe_config->fdi_lanes > 2) {
41 drm_dbg_kms(&dev_priv->drm,
42 "only 2 lanes on haswell, required: %i lanes\n",
43 pipe_config->fdi_lanes);
44 return -EINVAL;
45 } else {
46 return 0;
47 }
48 }
49
50 if (INTEL_NUM_PIPES(dev_priv) == 2)
51 return 0;
52
53 /* Ivybridge 3 pipe is really complicated */
54 switch (pipe) {
55 case PIPE_A:
56 return 0;
57 case PIPE_B:
58 if (pipe_config->fdi_lanes <= 2)
59 return 0;
60
61 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
62 other_crtc_state =
63 intel_atomic_get_crtc_state(state, other_crtc);
64 if (IS_ERR(other_crtc_state))
65 return PTR_ERR(other_crtc_state);
66
67 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
68 drm_dbg_kms(&dev_priv->drm,
69 "invalid shared fdi lane config on pipe %c: %i lanes\n",
70 pipe_name(pipe), pipe_config->fdi_lanes);
71 return -EINVAL;
72 }
73 return 0;
74 case PIPE_C:
75 if (pipe_config->fdi_lanes > 2) {
76 drm_dbg_kms(&dev_priv->drm,
77 "only 2 lanes on pipe %c: required %i lanes\n",
78 pipe_name(pipe), pipe_config->fdi_lanes);
79 return -EINVAL;
80 }
81
82 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
83 other_crtc_state =
84 intel_atomic_get_crtc_state(state, other_crtc);
85 if (IS_ERR(other_crtc_state))
86 return PTR_ERR(other_crtc_state);
87
88 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
89 drm_dbg_kms(&dev_priv->drm,
90 "fdi link B uses too many lanes to enable link C\n");
91 return -EINVAL;
92 }
93 return 0;
94 default:
95 BUG();
96 }
97}
98
99int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
100 struct intel_crtc_state *pipe_config)
101{
102 struct drm_device *dev = intel_crtc->base.dev;
103 struct drm_i915_private *i915 = to_i915(dev);
104 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
105 int lane, link_bw, fdi_dotclock, ret;
106 bool needs_recompute = false;
107
108retry:
109 /* FDI is a binary signal running at ~2.7GHz, encoding
110 * each output octet as 10 bits. The actual frequency
111 * is stored as a divider into a 100MHz clock, and the
112 * mode pixel clock is stored in units of 1KHz.
113 * Hence the bw of each lane in terms of the mode signal
114 * is:
115 */
116 link_bw = intel_fdi_link_freq(i915, pipe_config);
117
118 fdi_dotclock = adjusted_mode->crtc_clock;
119
120 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
121 pipe_config->pipe_bpp);
122
123 pipe_config->fdi_lanes = lane;
124
125 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
126 link_bw, &pipe_config->fdi_m_n, false, false);
127
128 ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
129 if (ret == -EDEADLK)
130 return ret;
131
132 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
133 pipe_config->pipe_bpp -= 2*3;
134 drm_dbg_kms(&i915->drm,
135 "fdi link bw constraint, reducing pipe bpp to %i\n",
136 pipe_config->pipe_bpp);
137 needs_recompute = true;
138 pipe_config->bw_constrained = true;
139
140 goto retry;
141 }
142
143 if (needs_recompute)
144 return I915_DISPLAY_CONFIG_RETRY;
145
146 return ret;
147}
148
149void intel_fdi_normal_train(struct intel_crtc *crtc)
150{
151 struct drm_device *dev = crtc->base.dev;
152 struct drm_i915_private *dev_priv = to_i915(dev);
153 enum pipe pipe = crtc->pipe;
154 i915_reg_t reg;
155 u32 temp;
156
157 /* enable normal train */
158 reg = FDI_TX_CTL(pipe);
159 temp = intel_de_read(dev_priv, reg);
160 if (IS_IVYBRIDGE(dev_priv)) {
161 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
162 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
163 } else {
164 temp &= ~FDI_LINK_TRAIN_NONE;
165 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
166 }
167 intel_de_write(dev_priv, reg, temp);
168
169 reg = FDI_RX_CTL(pipe);
170 temp = intel_de_read(dev_priv, reg);
171 if (HAS_PCH_CPT(dev_priv)) {
172 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
173 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
174 } else {
175 temp &= ~FDI_LINK_TRAIN_NONE;
176 temp |= FDI_LINK_TRAIN_NONE;
177 }
178 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
179
180 /* wait one idle pattern time */
181 intel_de_posting_read(dev_priv, reg);
182 udelay(1000);
183
184 /* IVB wants error correction enabled */
185 if (IS_IVYBRIDGE(dev_priv))
186 intel_de_write(dev_priv, reg,
187 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
188}
189
190/* The FDI link training functions for ILK/Ibexpeak. */
191static void ilk_fdi_link_train(struct intel_crtc *crtc,
192 const struct intel_crtc_state *crtc_state)
193{
194 struct drm_device *dev = crtc->base.dev;
195 struct drm_i915_private *dev_priv = to_i915(dev);
196 enum pipe pipe = crtc->pipe;
197 i915_reg_t reg;
198 u32 temp, tries;
199
200 /* FDI needs bits from pipe first */
201 assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
202
203 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
204 for train result */
205 reg = FDI_RX_IMR(pipe);
206 temp = intel_de_read(dev_priv, reg);
207 temp &= ~FDI_RX_SYMBOL_LOCK;
208 temp &= ~FDI_RX_BIT_LOCK;
209 intel_de_write(dev_priv, reg, temp);
210 intel_de_read(dev_priv, reg);
211 udelay(150);
212
213 /* enable CPU FDI TX and PCH FDI RX */
214 reg = FDI_TX_CTL(pipe);
215 temp = intel_de_read(dev_priv, reg);
216 temp &= ~FDI_DP_PORT_WIDTH_MASK;
217 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
218 temp &= ~FDI_LINK_TRAIN_NONE;
219 temp |= FDI_LINK_TRAIN_PATTERN_1;
220 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
221
222 reg = FDI_RX_CTL(pipe);
223 temp = intel_de_read(dev_priv, reg);
224 temp &= ~FDI_LINK_TRAIN_NONE;
225 temp |= FDI_LINK_TRAIN_PATTERN_1;
226 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
227
228 intel_de_posting_read(dev_priv, reg);
229 udelay(150);
230
231 /* Ironlake workaround, enable clock pointer after FDI enable*/
232 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
233 FDI_RX_PHASE_SYNC_POINTER_OVR);
234 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
235 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
236
237 reg = FDI_RX_IIR(pipe);
238 for (tries = 0; tries < 5; tries++) {
239 temp = intel_de_read(dev_priv, reg);
240 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
241
242 if ((temp & FDI_RX_BIT_LOCK)) {
243 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
244 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
245 break;
246 }
247 }
248 if (tries == 5)
249 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
250
251 /* Train 2 */
252 reg = FDI_TX_CTL(pipe);
253 temp = intel_de_read(dev_priv, reg);
254 temp &= ~FDI_LINK_TRAIN_NONE;
255 temp |= FDI_LINK_TRAIN_PATTERN_2;
256 intel_de_write(dev_priv, reg, temp);
257
258 reg = FDI_RX_CTL(pipe);
259 temp = intel_de_read(dev_priv, reg);
260 temp &= ~FDI_LINK_TRAIN_NONE;
261 temp |= FDI_LINK_TRAIN_PATTERN_2;
262 intel_de_write(dev_priv, reg, temp);
263
264 intel_de_posting_read(dev_priv, reg);
265 udelay(150);
266
267 reg = FDI_RX_IIR(pipe);
268 for (tries = 0; tries < 5; tries++) {
269 temp = intel_de_read(dev_priv, reg);
270 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
271
272 if (temp & FDI_RX_SYMBOL_LOCK) {
273 intel_de_write(dev_priv, reg,
274 temp | FDI_RX_SYMBOL_LOCK);
275 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
276 break;
277 }
278 }
279 if (tries == 5)
280 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
281
282 drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
283
284}
285
286static const int snb_b_fdi_train_param[] = {
287 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
288 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
289 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
290 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
291};
292
293/* The FDI link training functions for SNB/Cougarpoint. */
294static void gen6_fdi_link_train(struct intel_crtc *crtc,
295 const struct intel_crtc_state *crtc_state)
296{
297 struct drm_device *dev = crtc->base.dev;
298 struct drm_i915_private *dev_priv = to_i915(dev);
299 enum pipe pipe = crtc->pipe;
300 i915_reg_t reg;
301 u32 temp, i, retry;
302
303 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
304 for train result */
305 reg = FDI_RX_IMR(pipe);
306 temp = intel_de_read(dev_priv, reg);
307 temp &= ~FDI_RX_SYMBOL_LOCK;
308 temp &= ~FDI_RX_BIT_LOCK;
309 intel_de_write(dev_priv, reg, temp);
310
311 intel_de_posting_read(dev_priv, reg);
312 udelay(150);
313
314 /* enable CPU FDI TX and PCH FDI RX */
315 reg = FDI_TX_CTL(pipe);
316 temp = intel_de_read(dev_priv, reg);
317 temp &= ~FDI_DP_PORT_WIDTH_MASK;
318 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
319 temp &= ~FDI_LINK_TRAIN_NONE;
320 temp |= FDI_LINK_TRAIN_PATTERN_1;
321 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
322 /* SNB-B */
323 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
324 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
325
326 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
327 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
328
329 reg = FDI_RX_CTL(pipe);
330 temp = intel_de_read(dev_priv, reg);
331 if (HAS_PCH_CPT(dev_priv)) {
332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
333 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
334 } else {
335 temp &= ~FDI_LINK_TRAIN_NONE;
336 temp |= FDI_LINK_TRAIN_PATTERN_1;
337 }
338 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
339
340 intel_de_posting_read(dev_priv, reg);
341 udelay(150);
342
343 for (i = 0; i < 4; i++) {
344 reg = FDI_TX_CTL(pipe);
345 temp = intel_de_read(dev_priv, reg);
346 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
347 temp |= snb_b_fdi_train_param[i];
348 intel_de_write(dev_priv, reg, temp);
349
350 intel_de_posting_read(dev_priv, reg);
351 udelay(500);
352
353 for (retry = 0; retry < 5; retry++) {
354 reg = FDI_RX_IIR(pipe);
355 temp = intel_de_read(dev_priv, reg);
356 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
357 if (temp & FDI_RX_BIT_LOCK) {
358 intel_de_write(dev_priv, reg,
359 temp | FDI_RX_BIT_LOCK);
360 drm_dbg_kms(&dev_priv->drm,
361 "FDI train 1 done.\n");
362 break;
363 }
364 udelay(50);
365 }
366 if (retry < 5)
367 break;
368 }
369 if (i == 4)
370 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
371
372 /* Train 2 */
373 reg = FDI_TX_CTL(pipe);
374 temp = intel_de_read(dev_priv, reg);
375 temp &= ~FDI_LINK_TRAIN_NONE;
376 temp |= FDI_LINK_TRAIN_PATTERN_2;
377 if (IS_SANDYBRIDGE(dev_priv)) {
378 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
379 /* SNB-B */
380 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
381 }
382 intel_de_write(dev_priv, reg, temp);
383
384 reg = FDI_RX_CTL(pipe);
385 temp = intel_de_read(dev_priv, reg);
386 if (HAS_PCH_CPT(dev_priv)) {
387 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
388 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
389 } else {
390 temp &= ~FDI_LINK_TRAIN_NONE;
391 temp |= FDI_LINK_TRAIN_PATTERN_2;
392 }
393 intel_de_write(dev_priv, reg, temp);
394
395 intel_de_posting_read(dev_priv, reg);
396 udelay(150);
397
398 for (i = 0; i < 4; i++) {
399 reg = FDI_TX_CTL(pipe);
400 temp = intel_de_read(dev_priv, reg);
401 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
402 temp |= snb_b_fdi_train_param[i];
403 intel_de_write(dev_priv, reg, temp);
404
405 intel_de_posting_read(dev_priv, reg);
406 udelay(500);
407
408 for (retry = 0; retry < 5; retry++) {
409 reg = FDI_RX_IIR(pipe);
410 temp = intel_de_read(dev_priv, reg);
411 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
412 if (temp & FDI_RX_SYMBOL_LOCK) {
413 intel_de_write(dev_priv, reg,
414 temp | FDI_RX_SYMBOL_LOCK);
415 drm_dbg_kms(&dev_priv->drm,
416 "FDI train 2 done.\n");
417 break;
418 }
419 udelay(50);
420 }
421 if (retry < 5)
422 break;
423 }
424 if (i == 4)
425 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
426
427 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
428}
429
430/* Manual link training for Ivy Bridge A0 parts */
431static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
432 const struct intel_crtc_state *crtc_state)
433{
434 struct drm_device *dev = crtc->base.dev;
435 struct drm_i915_private *dev_priv = to_i915(dev);
436 enum pipe pipe = crtc->pipe;
437 i915_reg_t reg;
438 u32 temp, i, j;
439
440 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
441 for train result */
442 reg = FDI_RX_IMR(pipe);
443 temp = intel_de_read(dev_priv, reg);
444 temp &= ~FDI_RX_SYMBOL_LOCK;
445 temp &= ~FDI_RX_BIT_LOCK;
446 intel_de_write(dev_priv, reg, temp);
447
448 intel_de_posting_read(dev_priv, reg);
449 udelay(150);
450
451 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
452 intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
453
454 /* Try each vswing and preemphasis setting twice before moving on */
455 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
456 /* disable first in case we need to retry */
457 reg = FDI_TX_CTL(pipe);
458 temp = intel_de_read(dev_priv, reg);
459 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
460 temp &= ~FDI_TX_ENABLE;
461 intel_de_write(dev_priv, reg, temp);
462
463 reg = FDI_RX_CTL(pipe);
464 temp = intel_de_read(dev_priv, reg);
465 temp &= ~FDI_LINK_TRAIN_AUTO;
466 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
467 temp &= ~FDI_RX_ENABLE;
468 intel_de_write(dev_priv, reg, temp);
469
470 /* enable CPU FDI TX and PCH FDI RX */
471 reg = FDI_TX_CTL(pipe);
472 temp = intel_de_read(dev_priv, reg);
473 temp &= ~FDI_DP_PORT_WIDTH_MASK;
474 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
475 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
476 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
477 temp |= snb_b_fdi_train_param[j/2];
478 temp |= FDI_COMPOSITE_SYNC;
479 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
480
481 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
482 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
483
484 reg = FDI_RX_CTL(pipe);
485 temp = intel_de_read(dev_priv, reg);
486 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
487 temp |= FDI_COMPOSITE_SYNC;
488 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
489
490 intel_de_posting_read(dev_priv, reg);
491 udelay(1); /* should be 0.5us */
492
493 for (i = 0; i < 4; i++) {
494 reg = FDI_RX_IIR(pipe);
495 temp = intel_de_read(dev_priv, reg);
496 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
497
498 if (temp & FDI_RX_BIT_LOCK ||
499 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
500 intel_de_write(dev_priv, reg,
501 temp | FDI_RX_BIT_LOCK);
502 drm_dbg_kms(&dev_priv->drm,
503 "FDI train 1 done, level %i.\n",
504 i);
505 break;
506 }
507 udelay(1); /* should be 0.5us */
508 }
509 if (i == 4) {
510 drm_dbg_kms(&dev_priv->drm,
511 "FDI train 1 fail on vswing %d\n", j / 2);
512 continue;
513 }
514
515 /* Train 2 */
516 reg = FDI_TX_CTL(pipe);
517 temp = intel_de_read(dev_priv, reg);
518 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
519 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
520 intel_de_write(dev_priv, reg, temp);
521
522 reg = FDI_RX_CTL(pipe);
523 temp = intel_de_read(dev_priv, reg);
524 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
525 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
526 intel_de_write(dev_priv, reg, temp);
527
528 intel_de_posting_read(dev_priv, reg);
529 udelay(2); /* should be 1.5us */
530
531 for (i = 0; i < 4; i++) {
532 reg = FDI_RX_IIR(pipe);
533 temp = intel_de_read(dev_priv, reg);
534 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
535
536 if (temp & FDI_RX_SYMBOL_LOCK ||
537 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
538 intel_de_write(dev_priv, reg,
539 temp | FDI_RX_SYMBOL_LOCK);
540 drm_dbg_kms(&dev_priv->drm,
541 "FDI train 2 done, level %i.\n",
542 i);
543 goto train_done;
544 }
545 udelay(2); /* should be 1.5us */
546 }
547 if (i == 4)
548 drm_dbg_kms(&dev_priv->drm,
549 "FDI train 2 fail on vswing %d\n", j / 2);
550 }
551
552train_done:
553 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
554}
555
556/* Starting with Haswell, different DDI ports can work in FDI mode for
557 * connection to the PCH-located connectors. For this, it is necessary to train
558 * both the DDI port and PCH receiver for the desired DDI buffer settings.
559 *
560 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
561 * please note that when FDI mode is active on DDI E, it shares 2 lines with
562 * DDI A (which is used for eDP)
563 */
564void hsw_fdi_link_train(struct intel_encoder *encoder,
565 const struct intel_crtc_state *crtc_state)
566{
567 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
568 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
569 u32 temp, i, rx_ctl_val;
570 int n_entries;
571
572 intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries);
573
574 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
575
576 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
577 * mode set "sequence for CRT port" document:
578 * - TP1 to TP2 time with the default value
579 * - FDI delay to 90h
580 *
581 * WaFDIAutoLinkSetTimingOverrride:hsw
582 */
583 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
584 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
585
586 /* Enable the PCH Receiver FDI PLL */
587 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
588 FDI_RX_PLL_ENABLE |
589 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
590 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
591 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
592 udelay(220);
593
594 /* Switch from Rawclk to PCDclk */
595 rx_ctl_val |= FDI_PCDCLK;
596 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
597
598 /* Configure Port Clock Select */
599 drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
600 intel_ddi_enable_clock(encoder, crtc_state);
601
602 /* Start the training iterating through available voltages and emphasis,
603 * testing each value twice. */
604 for (i = 0; i < n_entries * 2; i++) {
605 /* Configure DP_TP_CTL with auto-training */
606 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
607 DP_TP_CTL_FDI_AUTOTRAIN |
608 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
609 DP_TP_CTL_LINK_TRAIN_PAT1 |
610 DP_TP_CTL_ENABLE);
611
612 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
613 * DDI E does not support port reversal, the functionality is
614 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
615 * port reversal bit */
616 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
617 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
618 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
619
620 udelay(600);
621
622 /* Program PCH FDI Receiver TU */
623 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
624
625 /* Enable PCH FDI Receiver with auto-training */
626 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
627 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
628 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
629
630 /* Wait for FDI receiver lane calibration */
631 udelay(30);
632
633 /* Unset FDI_RX_MISC pwrdn lanes */
634 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
635 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
636 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
637 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
638
639 /* Wait for FDI auto training time */
640 udelay(5);
641
642 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
643 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
644 drm_dbg_kms(&dev_priv->drm,
645 "FDI link training done on step %d\n", i);
646 break;
647 }
648
649 /*
650 * Leave things enabled even if we failed to train FDI.
651 * Results in less fireworks from the state checker.
652 */
653 if (i == n_entries * 2 - 1) {
654 drm_err(&dev_priv->drm, "FDI link training failed!\n");
655 break;
656 }
657
658 rx_ctl_val &= ~FDI_RX_ENABLE;
659 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
660 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
661
662 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
663 temp &= ~DDI_BUF_CTL_ENABLE;
664 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
665 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
666
667 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
668 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
669 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
670 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
671 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
672 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
673
674 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
675
676 /* Reset FDI_RX_MISC pwrdn lanes */
677 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
678 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
679 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
680 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
681 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
682 }
683
684 /* Enable normal pixel sending for FDI */
685 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
686 DP_TP_CTL_FDI_AUTOTRAIN |
687 DP_TP_CTL_LINK_TRAIN_NORMAL |
688 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
689 DP_TP_CTL_ENABLE);
690}
691
692void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
693{
694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
695 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
696 enum pipe pipe = intel_crtc->pipe;
697 i915_reg_t reg;
698 u32 temp;
699
700 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
701 reg = FDI_RX_CTL(pipe);
702 temp = intel_de_read(dev_priv, reg);
703 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
704 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
705 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
706 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
707
708 intel_de_posting_read(dev_priv, reg);
709 udelay(200);
710
711 /* Switch from Rawclk to PCDclk */
712 temp = intel_de_read(dev_priv, reg);
713 intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
714
715 intel_de_posting_read(dev_priv, reg);
716 udelay(200);
717
718 /* Enable CPU FDI TX PLL, always on for Ironlake */
719 reg = FDI_TX_CTL(pipe);
720 temp = intel_de_read(dev_priv, reg);
721 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
722 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
723
724 intel_de_posting_read(dev_priv, reg);
725 udelay(100);
726 }
727}
728
729void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
730{
731 struct drm_device *dev = intel_crtc->base.dev;
732 struct drm_i915_private *dev_priv = to_i915(dev);
733 enum pipe pipe = intel_crtc->pipe;
734 i915_reg_t reg;
735 u32 temp;
736
737 /* Switch from PCDclk to Rawclk */
738 reg = FDI_RX_CTL(pipe);
739 temp = intel_de_read(dev_priv, reg);
740 intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
741
742 /* Disable CPU FDI TX PLL */
743 reg = FDI_TX_CTL(pipe);
744 temp = intel_de_read(dev_priv, reg);
745 intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
746
747 intel_de_posting_read(dev_priv, reg);
748 udelay(100);
749
750 reg = FDI_RX_CTL(pipe);
751 temp = intel_de_read(dev_priv, reg);
752 intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
753
754 /* Wait for the clocks to turn off. */
755 intel_de_posting_read(dev_priv, reg);
756 udelay(100);
757}
758
759void ilk_fdi_disable(struct intel_crtc *crtc)
760{
761 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
762 enum pipe pipe = crtc->pipe;
763 i915_reg_t reg;
764 u32 temp;
765
766 /* disable CPU FDI tx and PCH FDI rx */
767 reg = FDI_TX_CTL(pipe);
768 temp = intel_de_read(dev_priv, reg);
769 intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
770 intel_de_posting_read(dev_priv, reg);
771
772 reg = FDI_RX_CTL(pipe);
773 temp = intel_de_read(dev_priv, reg);
774 temp &= ~(0x7 << 16);
775 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
776 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
777
778 intel_de_posting_read(dev_priv, reg);
779 udelay(100);
780
781 /* Ironlake workaround, disable clock pointer after downing FDI */
782 if (HAS_PCH_IBX(dev_priv))
783 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
784 FDI_RX_PHASE_SYNC_POINTER_OVR);
785
786 /* still set train pattern 1 */
787 reg = FDI_TX_CTL(pipe);
788 temp = intel_de_read(dev_priv, reg);
789 temp &= ~FDI_LINK_TRAIN_NONE;
790 temp |= FDI_LINK_TRAIN_PATTERN_1;
791 intel_de_write(dev_priv, reg, temp);
792
793 reg = FDI_RX_CTL(pipe);
794 temp = intel_de_read(dev_priv, reg);
795 if (HAS_PCH_CPT(dev_priv)) {
796 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
797 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
798 } else {
799 temp &= ~FDI_LINK_TRAIN_NONE;
800 temp |= FDI_LINK_TRAIN_PATTERN_1;
801 }
802 /* BPC in FDI rx is consistent with that in PIPECONF */
803 temp &= ~(0x07 << 16);
804 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
805 intel_de_write(dev_priv, reg, temp);
806
807 intel_de_posting_read(dev_priv, reg);
808 udelay(100);
809}
810
811void
812intel_fdi_init_hook(struct drm_i915_private *dev_priv)
813{
814 if (IS_IRONLAKE(dev_priv)) {
815 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
816 } else if (IS_SANDYBRIDGE(dev_priv)) {
817 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
818 } else if (IS_IVYBRIDGE(dev_priv)) {
819 /* FIXME: detect B0+ stepping and use auto training */
820 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
821 }
822}