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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29
30#include "amdgpu.h"
31#include "amdgpu_gfx.h"
32#include "amdgpu_ring.h"
33#include "vi.h"
34#include "vi_structs.h"
35#include "vid.h"
36#include "amdgpu_ucode.h"
37#include "amdgpu_atombios.h"
38#include "atombios_i2c.h"
39#include "clearstate_vi.h"
40
41#include "gmc/gmc_8_2_d.h"
42#include "gmc/gmc_8_2_sh_mask.h"
43
44#include "oss/oss_3_0_d.h"
45#include "oss/oss_3_0_sh_mask.h"
46
47#include "bif/bif_5_0_d.h"
48#include "bif/bif_5_0_sh_mask.h"
49#include "gca/gfx_8_0_d.h"
50#include "gca/gfx_8_0_enum.h"
51#include "gca/gfx_8_0_sh_mask.h"
52
53#include "dce/dce_10_0_d.h"
54#include "dce/dce_10_0_sh_mask.h"
55
56#include "smu/smu_7_1_3_d.h"
57
58#include "ivsrcid/ivsrcid_vislands30.h"
59
60#define GFX8_NUM_GFX_RINGS 1
61#define GFX8_MEC_HPD_SIZE 4096
62
63#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
67
68#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
69#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
70#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
71#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
72#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
73#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
74#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
75#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
76#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
77
78#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
79#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
80#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
81#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
82#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
83#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
84
85/* BPM SERDES CMD */
86#define SET_BPM_SERDES_CMD 1
87#define CLE_BPM_SERDES_CMD 0
88
89/* BPM Register Address*/
90enum {
91 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
92 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
93 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
94 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
95 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
96 BPM_REG_FGCG_MAX
97};
98
99#define RLC_FormatDirectRegListLength 14
100
101MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
102MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
103MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
104MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
105MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
106MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
107
108MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
109MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
110MODULE_FIRMWARE("amdgpu/stoney_me.bin");
111MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
112MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
113
114MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
115MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
116MODULE_FIRMWARE("amdgpu/tonga_me.bin");
117MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
118MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
119MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
120
121MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
122MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
123MODULE_FIRMWARE("amdgpu/topaz_me.bin");
124MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
125MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
126
127MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
128MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
129MODULE_FIRMWARE("amdgpu/fiji_me.bin");
130MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
131MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
132MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
133
134MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
135MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
136MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
137MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
138MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
139MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
140MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
141MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
142MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
143MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
144MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
145
146MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
147MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
148MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
149MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
150MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
151MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
152MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
153MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
154MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
155MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
156MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
157
158MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
159MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
160MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
161MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
162MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
163MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
164MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
165MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
166MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
167MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
168MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
169
170MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
171MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
172MODULE_FIRMWARE("amdgpu/vegam_me.bin");
173MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
174MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
175MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
176
177static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
178{
179 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
180 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
181 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
182 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
183 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
184 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
185 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
186 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
187 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
188 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
189 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
190 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
191 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
192 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
193 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
194 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
195};
196
197static const u32 golden_settings_tonga_a11[] =
198{
199 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
200 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
201 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
202 mmGB_GPU_ID, 0x0000000f, 0x00000000,
203 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
204 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
205 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
206 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
207 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
208 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
209 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
210 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
211 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
212 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
213 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
214 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
215};
216
217static const u32 tonga_golden_common_all[] =
218{
219 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
220 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
221 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
222 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
223 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
224 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
225 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
226 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
227};
228
229static const u32 tonga_mgcg_cgcg_init[] =
230{
231 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
232 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
233 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
234 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
235 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
236 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
237 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
238 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
239 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
240 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
241 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
242 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
243 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
244 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
245 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
246 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
247 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
248 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
249 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
250 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
251 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
252 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
253 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
254 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
255 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
256 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
257 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
258 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
260 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
261 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
262 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
263 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
264 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
265 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
266 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
267 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
268 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
269 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
270 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
271 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
272 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
273 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
274 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
275 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
276 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
277 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
278 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
279 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
280 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
281 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
282 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
283 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
284 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
285 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
286 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
287 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
288 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
289 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
290 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
291 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
292 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
293 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
294 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
295 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
296 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
297 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
298 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
299 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
300 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
301 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
302 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
303 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
304 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
305 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
306};
307
308static const u32 golden_settings_vegam_a11[] =
309{
310 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
311 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
312 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
313 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
314 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
315 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
316 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
317 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
318 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
319 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
320 mmSQ_CONFIG, 0x07f80000, 0x01180000,
321 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
322 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
323 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
324 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
325 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
326 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
327};
328
329static const u32 vegam_golden_common_all[] =
330{
331 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
332 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
333 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
334 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
335 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
336 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
337};
338
339static const u32 golden_settings_polaris11_a11[] =
340{
341 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
342 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
343 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
344 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
345 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
346 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
347 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
348 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
349 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
350 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
351 mmSQ_CONFIG, 0x07f80000, 0x01180000,
352 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
353 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
354 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
355 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
356 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
357 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
358};
359
360static const u32 polaris11_golden_common_all[] =
361{
362 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
363 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
364 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
365 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
366 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
367 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
368};
369
370static const u32 golden_settings_polaris10_a11[] =
371{
372 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
373 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
374 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
375 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
376 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
377 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
378 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
379 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
380 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
381 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
382 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
383 mmSQ_CONFIG, 0x07f80000, 0x07180000,
384 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
385 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
386 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
387 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
388 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
389};
390
391static const u32 polaris10_golden_common_all[] =
392{
393 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
394 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
395 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
396 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
397 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
398 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
399 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
400 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
401};
402
403static const u32 fiji_golden_common_all[] =
404{
405 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
406 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
407 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
408 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
409 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
410 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
411 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
412 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
413 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
414 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
415};
416
417static const u32 golden_settings_fiji_a10[] =
418{
419 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
420 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
422 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
423 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
424 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
426 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
427 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
428 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
429 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
430};
431
432static const u32 fiji_mgcg_cgcg_init[] =
433{
434 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
435 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
436 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
437 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
438 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
439 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
440 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
441 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
443 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
444 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
445 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
446 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
447 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
452 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
453 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
454 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
455 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
456 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
458 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
459 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
460 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
461 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
463 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
464 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
465 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
466 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
467 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
468 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
469};
470
471static const u32 golden_settings_iceland_a11[] =
472{
473 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
474 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
475 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
476 mmGB_GPU_ID, 0x0000000f, 0x00000000,
477 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
478 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
479 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
480 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
481 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
482 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
483 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
484 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
485 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
486 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
487 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
488 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
489};
490
491static const u32 iceland_golden_common_all[] =
492{
493 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
494 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
495 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
496 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
497 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
498 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
499 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
500 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
501};
502
503static const u32 iceland_mgcg_cgcg_init[] =
504{
505 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
506 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
507 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
508 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
509 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
510 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
511 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
512 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
513 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
514 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
515 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
516 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
517 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
518 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
519 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
520 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
521 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
522 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
523 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
524 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
525 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
526 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
527 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
528 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
529 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
530 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
531 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
532 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
534 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
535 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
536 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
537 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
538 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
539 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
540 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
541 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
542 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
543 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
544 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
545 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
546 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
547 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
548 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
549 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
550 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
551 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
552 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
553 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
554 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
555 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
556 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
557 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
558 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
559 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
560 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
561 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
562 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
563 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
564 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
565 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
566 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
567 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
568 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
569};
570
571static const u32 cz_golden_settings_a11[] =
572{
573 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
574 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
575 mmGB_GPU_ID, 0x0000000f, 0x00000000,
576 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
577 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
578 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
579 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
580 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
581 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
582 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
583 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
584 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
585};
586
587static const u32 cz_golden_common_all[] =
588{
589 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
590 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
591 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
592 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
593 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
594 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
595 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
596 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
597};
598
599static const u32 cz_mgcg_cgcg_init[] =
600{
601 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
602 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
603 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
604 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
605 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
606 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
607 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
608 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
609 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
610 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
611 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
612 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
613 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
614 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
615 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
616 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
617 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
618 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
619 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
620 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
621 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
622 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
623 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
624 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
625 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
626 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
627 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
628 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
630 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
631 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
632 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
633 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
634 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
635 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
636 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
637 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
638 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
639 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
640 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
641 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
642 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
643 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
644 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
645 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
646 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
647 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
648 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
649 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
650 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
651 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
652 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
653 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
654 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
655 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
656 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
657 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
658 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
659 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
660 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
661 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
662 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
663 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
664 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
665 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
666 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
667 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
668 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
669 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
670 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
671 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
672 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
673 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
674 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
675 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
676};
677
678static const u32 stoney_golden_settings_a11[] =
679{
680 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
681 mmGB_GPU_ID, 0x0000000f, 0x00000000,
682 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
683 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
684 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
685 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
686 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
687 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
688 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
689 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
690};
691
692static const u32 stoney_golden_common_all[] =
693{
694 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
695 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
696 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
697 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
698 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
699 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
700 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
701 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
702};
703
704static const u32 stoney_mgcg_cgcg_init[] =
705{
706 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
707 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
708 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
710 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
711};
712
713
714static const char * const sq_edc_source_names[] = {
715 "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
716 "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
717 "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
718 "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
719 "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
720 "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
721 "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
722};
723
724static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
725static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
726static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
727static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
728static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
729static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
730static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
731static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
732
733#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x0000007fL
734#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x00000000L
735
736static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
737{
738 uint32_t data;
739
740 switch (adev->asic_type) {
741 case CHIP_TOPAZ:
742 amdgpu_device_program_register_sequence(adev,
743 iceland_mgcg_cgcg_init,
744 ARRAY_SIZE(iceland_mgcg_cgcg_init));
745 amdgpu_device_program_register_sequence(adev,
746 golden_settings_iceland_a11,
747 ARRAY_SIZE(golden_settings_iceland_a11));
748 amdgpu_device_program_register_sequence(adev,
749 iceland_golden_common_all,
750 ARRAY_SIZE(iceland_golden_common_all));
751 break;
752 case CHIP_FIJI:
753 amdgpu_device_program_register_sequence(adev,
754 fiji_mgcg_cgcg_init,
755 ARRAY_SIZE(fiji_mgcg_cgcg_init));
756 amdgpu_device_program_register_sequence(adev,
757 golden_settings_fiji_a10,
758 ARRAY_SIZE(golden_settings_fiji_a10));
759 amdgpu_device_program_register_sequence(adev,
760 fiji_golden_common_all,
761 ARRAY_SIZE(fiji_golden_common_all));
762 break;
763
764 case CHIP_TONGA:
765 amdgpu_device_program_register_sequence(adev,
766 tonga_mgcg_cgcg_init,
767 ARRAY_SIZE(tonga_mgcg_cgcg_init));
768 amdgpu_device_program_register_sequence(adev,
769 golden_settings_tonga_a11,
770 ARRAY_SIZE(golden_settings_tonga_a11));
771 amdgpu_device_program_register_sequence(adev,
772 tonga_golden_common_all,
773 ARRAY_SIZE(tonga_golden_common_all));
774 break;
775 case CHIP_VEGAM:
776 amdgpu_device_program_register_sequence(adev,
777 golden_settings_vegam_a11,
778 ARRAY_SIZE(golden_settings_vegam_a11));
779 amdgpu_device_program_register_sequence(adev,
780 vegam_golden_common_all,
781 ARRAY_SIZE(vegam_golden_common_all));
782 break;
783 case CHIP_POLARIS11:
784 case CHIP_POLARIS12:
785 amdgpu_device_program_register_sequence(adev,
786 golden_settings_polaris11_a11,
787 ARRAY_SIZE(golden_settings_polaris11_a11));
788 amdgpu_device_program_register_sequence(adev,
789 polaris11_golden_common_all,
790 ARRAY_SIZE(polaris11_golden_common_all));
791 break;
792 case CHIP_POLARIS10:
793 amdgpu_device_program_register_sequence(adev,
794 golden_settings_polaris10_a11,
795 ARRAY_SIZE(golden_settings_polaris10_a11));
796 amdgpu_device_program_register_sequence(adev,
797 polaris10_golden_common_all,
798 ARRAY_SIZE(polaris10_golden_common_all));
799 data = RREG32_SMC(ixCG_ACLK_CNTL);
800 data &= ~CG_ACLK_CNTL__ACLK_DIVIDER_MASK;
801 data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT;
802 WREG32_SMC(ixCG_ACLK_CNTL, data);
803 if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) &&
804 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
805 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
806 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) {
807 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
808 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
809 }
810 break;
811 case CHIP_CARRIZO:
812 amdgpu_device_program_register_sequence(adev,
813 cz_mgcg_cgcg_init,
814 ARRAY_SIZE(cz_mgcg_cgcg_init));
815 amdgpu_device_program_register_sequence(adev,
816 cz_golden_settings_a11,
817 ARRAY_SIZE(cz_golden_settings_a11));
818 amdgpu_device_program_register_sequence(adev,
819 cz_golden_common_all,
820 ARRAY_SIZE(cz_golden_common_all));
821 break;
822 case CHIP_STONEY:
823 amdgpu_device_program_register_sequence(adev,
824 stoney_mgcg_cgcg_init,
825 ARRAY_SIZE(stoney_mgcg_cgcg_init));
826 amdgpu_device_program_register_sequence(adev,
827 stoney_golden_settings_a11,
828 ARRAY_SIZE(stoney_golden_settings_a11));
829 amdgpu_device_program_register_sequence(adev,
830 stoney_golden_common_all,
831 ARRAY_SIZE(stoney_golden_common_all));
832 break;
833 default:
834 break;
835 }
836}
837
838static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
839{
840 adev->gfx.scratch.num_reg = 8;
841 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
842 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
843}
844
845static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
846{
847 struct amdgpu_device *adev = ring->adev;
848 uint32_t scratch;
849 uint32_t tmp = 0;
850 unsigned i;
851 int r;
852
853 r = amdgpu_gfx_scratch_get(adev, &scratch);
854 if (r)
855 return r;
856
857 WREG32(scratch, 0xCAFEDEAD);
858 r = amdgpu_ring_alloc(ring, 3);
859 if (r)
860 goto error_free_scratch;
861
862 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
863 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
864 amdgpu_ring_write(ring, 0xDEADBEEF);
865 amdgpu_ring_commit(ring);
866
867 for (i = 0; i < adev->usec_timeout; i++) {
868 tmp = RREG32(scratch);
869 if (tmp == 0xDEADBEEF)
870 break;
871 udelay(1);
872 }
873
874 if (i >= adev->usec_timeout)
875 r = -ETIMEDOUT;
876
877error_free_scratch:
878 amdgpu_gfx_scratch_free(adev, scratch);
879 return r;
880}
881
882static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
883{
884 struct amdgpu_device *adev = ring->adev;
885 struct amdgpu_ib ib;
886 struct dma_fence *f = NULL;
887
888 unsigned int index;
889 uint64_t gpu_addr;
890 uint32_t tmp;
891 long r;
892
893 r = amdgpu_device_wb_get(adev, &index);
894 if (r)
895 return r;
896
897 gpu_addr = adev->wb.gpu_addr + (index * 4);
898 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
899 memset(&ib, 0, sizeof(ib));
900 r = amdgpu_ib_get(adev, NULL, 16,
901 AMDGPU_IB_POOL_DIRECT, &ib);
902 if (r)
903 goto err1;
904
905 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
906 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
907 ib.ptr[2] = lower_32_bits(gpu_addr);
908 ib.ptr[3] = upper_32_bits(gpu_addr);
909 ib.ptr[4] = 0xDEADBEEF;
910 ib.length_dw = 5;
911
912 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
913 if (r)
914 goto err2;
915
916 r = dma_fence_wait_timeout(f, false, timeout);
917 if (r == 0) {
918 r = -ETIMEDOUT;
919 goto err2;
920 } else if (r < 0) {
921 goto err2;
922 }
923
924 tmp = adev->wb.wb[index];
925 if (tmp == 0xDEADBEEF)
926 r = 0;
927 else
928 r = -EINVAL;
929
930err2:
931 amdgpu_ib_free(adev, &ib, NULL);
932 dma_fence_put(f);
933err1:
934 amdgpu_device_wb_free(adev, index);
935 return r;
936}
937
938
939static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
940{
941 release_firmware(adev->gfx.pfp_fw);
942 adev->gfx.pfp_fw = NULL;
943 release_firmware(adev->gfx.me_fw);
944 adev->gfx.me_fw = NULL;
945 release_firmware(adev->gfx.ce_fw);
946 adev->gfx.ce_fw = NULL;
947 release_firmware(adev->gfx.rlc_fw);
948 adev->gfx.rlc_fw = NULL;
949 release_firmware(adev->gfx.mec_fw);
950 adev->gfx.mec_fw = NULL;
951 if ((adev->asic_type != CHIP_STONEY) &&
952 (adev->asic_type != CHIP_TOPAZ))
953 release_firmware(adev->gfx.mec2_fw);
954 adev->gfx.mec2_fw = NULL;
955
956 kfree(adev->gfx.rlc.register_list_format);
957}
958
959static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
960{
961 const char *chip_name;
962 char fw_name[30];
963 int err;
964 struct amdgpu_firmware_info *info = NULL;
965 const struct common_firmware_header *header = NULL;
966 const struct gfx_firmware_header_v1_0 *cp_hdr;
967 const struct rlc_firmware_header_v2_0 *rlc_hdr;
968 unsigned int *tmp = NULL, i;
969
970 DRM_DEBUG("\n");
971
972 switch (adev->asic_type) {
973 case CHIP_TOPAZ:
974 chip_name = "topaz";
975 break;
976 case CHIP_TONGA:
977 chip_name = "tonga";
978 break;
979 case CHIP_CARRIZO:
980 chip_name = "carrizo";
981 break;
982 case CHIP_FIJI:
983 chip_name = "fiji";
984 break;
985 case CHIP_STONEY:
986 chip_name = "stoney";
987 break;
988 case CHIP_POLARIS10:
989 chip_name = "polaris10";
990 break;
991 case CHIP_POLARIS11:
992 chip_name = "polaris11";
993 break;
994 case CHIP_POLARIS12:
995 chip_name = "polaris12";
996 break;
997 case CHIP_VEGAM:
998 chip_name = "vegam";
999 break;
1000 default:
1001 BUG();
1002 }
1003
1004 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1005 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
1006 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1007 if (err == -ENOENT) {
1008 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1009 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1010 }
1011 } else {
1012 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1013 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1014 }
1015 if (err)
1016 goto out;
1017 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1018 if (err)
1019 goto out;
1020 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1021 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1022 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1023
1024 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1025 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
1026 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1027 if (err == -ENOENT) {
1028 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1029 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1030 }
1031 } else {
1032 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1033 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1034 }
1035 if (err)
1036 goto out;
1037 err = amdgpu_ucode_validate(adev->gfx.me_fw);
1038 if (err)
1039 goto out;
1040 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1041 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1042
1043 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1044
1045 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1046 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
1047 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1048 if (err == -ENOENT) {
1049 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1050 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1051 }
1052 } else {
1053 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1054 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1055 }
1056 if (err)
1057 goto out;
1058 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1059 if (err)
1060 goto out;
1061 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1062 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1063 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1064
1065 /*
1066 * Support for MCBP/Virtualization in combination with chained IBs is
1067 * formal released on feature version #46
1068 */
1069 if (adev->gfx.ce_feature_version >= 46 &&
1070 adev->gfx.pfp_feature_version >= 46) {
1071 adev->virt.chained_ib_support = true;
1072 DRM_INFO("Chained IB support enabled!\n");
1073 } else
1074 adev->virt.chained_ib_support = false;
1075
1076 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1077 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1078 if (err)
1079 goto out;
1080 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1081 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1082 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1083 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1084
1085 adev->gfx.rlc.save_and_restore_offset =
1086 le32_to_cpu(rlc_hdr->save_and_restore_offset);
1087 adev->gfx.rlc.clear_state_descriptor_offset =
1088 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1089 adev->gfx.rlc.avail_scratch_ram_locations =
1090 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1091 adev->gfx.rlc.reg_restore_list_size =
1092 le32_to_cpu(rlc_hdr->reg_restore_list_size);
1093 adev->gfx.rlc.reg_list_format_start =
1094 le32_to_cpu(rlc_hdr->reg_list_format_start);
1095 adev->gfx.rlc.reg_list_format_separate_start =
1096 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1097 adev->gfx.rlc.starting_offsets_start =
1098 le32_to_cpu(rlc_hdr->starting_offsets_start);
1099 adev->gfx.rlc.reg_list_format_size_bytes =
1100 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1101 adev->gfx.rlc.reg_list_size_bytes =
1102 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1103
1104 adev->gfx.rlc.register_list_format =
1105 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1106 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1107
1108 if (!adev->gfx.rlc.register_list_format) {
1109 err = -ENOMEM;
1110 goto out;
1111 }
1112
1113 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1114 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1115 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1116 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1117
1118 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1119
1120 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1121 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1122 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1123 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1124
1125 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1126 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1127 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1128 if (err == -ENOENT) {
1129 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1130 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1131 }
1132 } else {
1133 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1134 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1135 }
1136 if (err)
1137 goto out;
1138 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1139 if (err)
1140 goto out;
1141 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1142 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1143 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1144
1145 if ((adev->asic_type != CHIP_STONEY) &&
1146 (adev->asic_type != CHIP_TOPAZ)) {
1147 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1148 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1149 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1150 if (err == -ENOENT) {
1151 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1152 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1153 }
1154 } else {
1155 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1156 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1157 }
1158 if (!err) {
1159 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1160 if (err)
1161 goto out;
1162 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1163 adev->gfx.mec2_fw->data;
1164 adev->gfx.mec2_fw_version =
1165 le32_to_cpu(cp_hdr->header.ucode_version);
1166 adev->gfx.mec2_feature_version =
1167 le32_to_cpu(cp_hdr->ucode_feature_version);
1168 } else {
1169 err = 0;
1170 adev->gfx.mec2_fw = NULL;
1171 }
1172 }
1173
1174 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1175 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1176 info->fw = adev->gfx.pfp_fw;
1177 header = (const struct common_firmware_header *)info->fw->data;
1178 adev->firmware.fw_size +=
1179 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1180
1181 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1182 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1183 info->fw = adev->gfx.me_fw;
1184 header = (const struct common_firmware_header *)info->fw->data;
1185 adev->firmware.fw_size +=
1186 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1187
1188 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1189 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1190 info->fw = adev->gfx.ce_fw;
1191 header = (const struct common_firmware_header *)info->fw->data;
1192 adev->firmware.fw_size +=
1193 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1194
1195 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1196 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1197 info->fw = adev->gfx.rlc_fw;
1198 header = (const struct common_firmware_header *)info->fw->data;
1199 adev->firmware.fw_size +=
1200 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1201
1202 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1203 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1204 info->fw = adev->gfx.mec_fw;
1205 header = (const struct common_firmware_header *)info->fw->data;
1206 adev->firmware.fw_size +=
1207 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1208
1209 /* we need account JT in */
1210 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1211 adev->firmware.fw_size +=
1212 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1213
1214 if (amdgpu_sriov_vf(adev)) {
1215 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1216 info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1217 info->fw = adev->gfx.mec_fw;
1218 adev->firmware.fw_size +=
1219 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1220 }
1221
1222 if (adev->gfx.mec2_fw) {
1223 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1224 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1225 info->fw = adev->gfx.mec2_fw;
1226 header = (const struct common_firmware_header *)info->fw->data;
1227 adev->firmware.fw_size +=
1228 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1229 }
1230
1231out:
1232 if (err) {
1233 dev_err(adev->dev,
1234 "gfx8: Failed to load firmware \"%s\"\n",
1235 fw_name);
1236 release_firmware(adev->gfx.pfp_fw);
1237 adev->gfx.pfp_fw = NULL;
1238 release_firmware(adev->gfx.me_fw);
1239 adev->gfx.me_fw = NULL;
1240 release_firmware(adev->gfx.ce_fw);
1241 adev->gfx.ce_fw = NULL;
1242 release_firmware(adev->gfx.rlc_fw);
1243 adev->gfx.rlc_fw = NULL;
1244 release_firmware(adev->gfx.mec_fw);
1245 adev->gfx.mec_fw = NULL;
1246 release_firmware(adev->gfx.mec2_fw);
1247 adev->gfx.mec2_fw = NULL;
1248 }
1249 return err;
1250}
1251
1252static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1253 volatile u32 *buffer)
1254{
1255 u32 count = 0, i;
1256 const struct cs_section_def *sect = NULL;
1257 const struct cs_extent_def *ext = NULL;
1258
1259 if (adev->gfx.rlc.cs_data == NULL)
1260 return;
1261 if (buffer == NULL)
1262 return;
1263
1264 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1265 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1266
1267 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1268 buffer[count++] = cpu_to_le32(0x80000000);
1269 buffer[count++] = cpu_to_le32(0x80000000);
1270
1271 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1272 for (ext = sect->section; ext->extent != NULL; ++ext) {
1273 if (sect->id == SECT_CONTEXT) {
1274 buffer[count++] =
1275 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1276 buffer[count++] = cpu_to_le32(ext->reg_index -
1277 PACKET3_SET_CONTEXT_REG_START);
1278 for (i = 0; i < ext->reg_count; i++)
1279 buffer[count++] = cpu_to_le32(ext->extent[i]);
1280 } else {
1281 return;
1282 }
1283 }
1284 }
1285
1286 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1287 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1288 PACKET3_SET_CONTEXT_REG_START);
1289 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1290 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1291
1292 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1293 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1294
1295 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1296 buffer[count++] = cpu_to_le32(0);
1297}
1298
1299static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
1300{
1301 if (adev->asic_type == CHIP_CARRIZO)
1302 return 5;
1303 else
1304 return 4;
1305}
1306
1307static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1308{
1309 const struct cs_section_def *cs_data;
1310 int r;
1311
1312 adev->gfx.rlc.cs_data = vi_cs_data;
1313
1314 cs_data = adev->gfx.rlc.cs_data;
1315
1316 if (cs_data) {
1317 /* init clear state block */
1318 r = amdgpu_gfx_rlc_init_csb(adev);
1319 if (r)
1320 return r;
1321 }
1322
1323 if ((adev->asic_type == CHIP_CARRIZO) ||
1324 (adev->asic_type == CHIP_STONEY)) {
1325 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1326 r = amdgpu_gfx_rlc_init_cpt(adev);
1327 if (r)
1328 return r;
1329 }
1330
1331 /* init spm vmid with 0xf */
1332 if (adev->gfx.rlc.funcs->update_spm_vmid)
1333 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1334
1335 return 0;
1336}
1337
1338static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1339{
1340 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1341}
1342
1343static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1344{
1345 int r;
1346 u32 *hpd;
1347 size_t mec_hpd_size;
1348
1349 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1350
1351 /* take ownership of the relevant compute queues */
1352 amdgpu_gfx_compute_queue_acquire(adev);
1353
1354 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1355 if (mec_hpd_size) {
1356 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1357 AMDGPU_GEM_DOMAIN_VRAM,
1358 &adev->gfx.mec.hpd_eop_obj,
1359 &adev->gfx.mec.hpd_eop_gpu_addr,
1360 (void **)&hpd);
1361 if (r) {
1362 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1363 return r;
1364 }
1365
1366 memset(hpd, 0, mec_hpd_size);
1367
1368 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1369 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1370 }
1371
1372 return 0;
1373}
1374
1375static const u32 vgpr_init_compute_shader[] =
1376{
1377 0x7e000209, 0x7e020208,
1378 0x7e040207, 0x7e060206,
1379 0x7e080205, 0x7e0a0204,
1380 0x7e0c0203, 0x7e0e0202,
1381 0x7e100201, 0x7e120200,
1382 0x7e140209, 0x7e160208,
1383 0x7e180207, 0x7e1a0206,
1384 0x7e1c0205, 0x7e1e0204,
1385 0x7e200203, 0x7e220202,
1386 0x7e240201, 0x7e260200,
1387 0x7e280209, 0x7e2a0208,
1388 0x7e2c0207, 0x7e2e0206,
1389 0x7e300205, 0x7e320204,
1390 0x7e340203, 0x7e360202,
1391 0x7e380201, 0x7e3a0200,
1392 0x7e3c0209, 0x7e3e0208,
1393 0x7e400207, 0x7e420206,
1394 0x7e440205, 0x7e460204,
1395 0x7e480203, 0x7e4a0202,
1396 0x7e4c0201, 0x7e4e0200,
1397 0x7e500209, 0x7e520208,
1398 0x7e540207, 0x7e560206,
1399 0x7e580205, 0x7e5a0204,
1400 0x7e5c0203, 0x7e5e0202,
1401 0x7e600201, 0x7e620200,
1402 0x7e640209, 0x7e660208,
1403 0x7e680207, 0x7e6a0206,
1404 0x7e6c0205, 0x7e6e0204,
1405 0x7e700203, 0x7e720202,
1406 0x7e740201, 0x7e760200,
1407 0x7e780209, 0x7e7a0208,
1408 0x7e7c0207, 0x7e7e0206,
1409 0xbf8a0000, 0xbf810000,
1410};
1411
1412static const u32 sgpr_init_compute_shader[] =
1413{
1414 0xbe8a0100, 0xbe8c0102,
1415 0xbe8e0104, 0xbe900106,
1416 0xbe920108, 0xbe940100,
1417 0xbe960102, 0xbe980104,
1418 0xbe9a0106, 0xbe9c0108,
1419 0xbe9e0100, 0xbea00102,
1420 0xbea20104, 0xbea40106,
1421 0xbea60108, 0xbea80100,
1422 0xbeaa0102, 0xbeac0104,
1423 0xbeae0106, 0xbeb00108,
1424 0xbeb20100, 0xbeb40102,
1425 0xbeb60104, 0xbeb80106,
1426 0xbeba0108, 0xbebc0100,
1427 0xbebe0102, 0xbec00104,
1428 0xbec20106, 0xbec40108,
1429 0xbec60100, 0xbec80102,
1430 0xbee60004, 0xbee70005,
1431 0xbeea0006, 0xbeeb0007,
1432 0xbee80008, 0xbee90009,
1433 0xbefc0000, 0xbf8a0000,
1434 0xbf810000, 0x00000000,
1435};
1436
1437static const u32 vgpr_init_regs[] =
1438{
1439 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1440 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1441 mmCOMPUTE_NUM_THREAD_X, 256*4,
1442 mmCOMPUTE_NUM_THREAD_Y, 1,
1443 mmCOMPUTE_NUM_THREAD_Z, 1,
1444 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1445 mmCOMPUTE_PGM_RSRC2, 20,
1446 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1447 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1448 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1449 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1450 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1451 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1452 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1453 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1454 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1455 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1456};
1457
1458static const u32 sgpr1_init_regs[] =
1459{
1460 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1461 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1462 mmCOMPUTE_NUM_THREAD_X, 256*5,
1463 mmCOMPUTE_NUM_THREAD_Y, 1,
1464 mmCOMPUTE_NUM_THREAD_Z, 1,
1465 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1466 mmCOMPUTE_PGM_RSRC2, 20,
1467 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1468 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1469 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1470 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1471 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1472 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1473 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1474 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1475 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1476 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1477};
1478
1479static const u32 sgpr2_init_regs[] =
1480{
1481 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1482 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1483 mmCOMPUTE_NUM_THREAD_X, 256*5,
1484 mmCOMPUTE_NUM_THREAD_Y, 1,
1485 mmCOMPUTE_NUM_THREAD_Z, 1,
1486 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1487 mmCOMPUTE_PGM_RSRC2, 20,
1488 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1489 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1490 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1491 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1492 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1493 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1494 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1495 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1496 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1497 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1498};
1499
1500static const u32 sec_ded_counter_registers[] =
1501{
1502 mmCPC_EDC_ATC_CNT,
1503 mmCPC_EDC_SCRATCH_CNT,
1504 mmCPC_EDC_UCODE_CNT,
1505 mmCPF_EDC_ATC_CNT,
1506 mmCPF_EDC_ROQ_CNT,
1507 mmCPF_EDC_TAG_CNT,
1508 mmCPG_EDC_ATC_CNT,
1509 mmCPG_EDC_DMA_CNT,
1510 mmCPG_EDC_TAG_CNT,
1511 mmDC_EDC_CSINVOC_CNT,
1512 mmDC_EDC_RESTORE_CNT,
1513 mmDC_EDC_STATE_CNT,
1514 mmGDS_EDC_CNT,
1515 mmGDS_EDC_GRBM_CNT,
1516 mmGDS_EDC_OA_DED,
1517 mmSPI_EDC_CNT,
1518 mmSQC_ATC_EDC_GATCL1_CNT,
1519 mmSQC_EDC_CNT,
1520 mmSQ_EDC_DED_CNT,
1521 mmSQ_EDC_INFO,
1522 mmSQ_EDC_SEC_CNT,
1523 mmTCC_EDC_CNT,
1524 mmTCP_ATC_EDC_GATCL1_CNT,
1525 mmTCP_EDC_CNT,
1526 mmTD_EDC_CNT
1527};
1528
1529static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1530{
1531 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1532 struct amdgpu_ib ib;
1533 struct dma_fence *f = NULL;
1534 int r, i;
1535 u32 tmp;
1536 unsigned total_size, vgpr_offset, sgpr_offset;
1537 u64 gpu_addr;
1538
1539 /* only supported on CZ */
1540 if (adev->asic_type != CHIP_CARRIZO)
1541 return 0;
1542
1543 /* bail if the compute ring is not ready */
1544 if (!ring->sched.ready)
1545 return 0;
1546
1547 tmp = RREG32(mmGB_EDC_MODE);
1548 WREG32(mmGB_EDC_MODE, 0);
1549
1550 total_size =
1551 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1552 total_size +=
1553 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1554 total_size +=
1555 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1556 total_size = ALIGN(total_size, 256);
1557 vgpr_offset = total_size;
1558 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1559 sgpr_offset = total_size;
1560 total_size += sizeof(sgpr_init_compute_shader);
1561
1562 /* allocate an indirect buffer to put the commands in */
1563 memset(&ib, 0, sizeof(ib));
1564 r = amdgpu_ib_get(adev, NULL, total_size,
1565 AMDGPU_IB_POOL_DIRECT, &ib);
1566 if (r) {
1567 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1568 return r;
1569 }
1570
1571 /* load the compute shaders */
1572 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1573 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1574
1575 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1576 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1577
1578 /* init the ib length to 0 */
1579 ib.length_dw = 0;
1580
1581 /* VGPR */
1582 /* write the register state for the compute dispatch */
1583 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1584 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1585 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1586 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1587 }
1588 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1589 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1590 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1591 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1592 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1593 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1594
1595 /* write dispatch packet */
1596 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1597 ib.ptr[ib.length_dw++] = 8; /* x */
1598 ib.ptr[ib.length_dw++] = 1; /* y */
1599 ib.ptr[ib.length_dw++] = 1; /* z */
1600 ib.ptr[ib.length_dw++] =
1601 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1602
1603 /* write CS partial flush packet */
1604 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1605 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1606
1607 /* SGPR1 */
1608 /* write the register state for the compute dispatch */
1609 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1610 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1611 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1612 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1613 }
1614 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1615 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1616 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1617 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1618 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1619 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1620
1621 /* write dispatch packet */
1622 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1623 ib.ptr[ib.length_dw++] = 8; /* x */
1624 ib.ptr[ib.length_dw++] = 1; /* y */
1625 ib.ptr[ib.length_dw++] = 1; /* z */
1626 ib.ptr[ib.length_dw++] =
1627 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1628
1629 /* write CS partial flush packet */
1630 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1631 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1632
1633 /* SGPR2 */
1634 /* write the register state for the compute dispatch */
1635 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1636 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1637 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1638 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1639 }
1640 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1641 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1642 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1643 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1644 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1645 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1646
1647 /* write dispatch packet */
1648 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1649 ib.ptr[ib.length_dw++] = 8; /* x */
1650 ib.ptr[ib.length_dw++] = 1; /* y */
1651 ib.ptr[ib.length_dw++] = 1; /* z */
1652 ib.ptr[ib.length_dw++] =
1653 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1654
1655 /* write CS partial flush packet */
1656 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1657 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1658
1659 /* shedule the ib on the ring */
1660 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1661 if (r) {
1662 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1663 goto fail;
1664 }
1665
1666 /* wait for the GPU to finish processing the IB */
1667 r = dma_fence_wait(f, false);
1668 if (r) {
1669 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1670 goto fail;
1671 }
1672
1673 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1674 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1675 WREG32(mmGB_EDC_MODE, tmp);
1676
1677 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1678 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1679 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1680
1681
1682 /* read back registers to clear the counters */
1683 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1684 RREG32(sec_ded_counter_registers[i]);
1685
1686fail:
1687 amdgpu_ib_free(adev, &ib, NULL);
1688 dma_fence_put(f);
1689
1690 return r;
1691}
1692
1693static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1694{
1695 u32 gb_addr_config;
1696 u32 mc_arb_ramcfg;
1697 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1698 u32 tmp;
1699 int ret;
1700
1701 switch (adev->asic_type) {
1702 case CHIP_TOPAZ:
1703 adev->gfx.config.max_shader_engines = 1;
1704 adev->gfx.config.max_tile_pipes = 2;
1705 adev->gfx.config.max_cu_per_sh = 6;
1706 adev->gfx.config.max_sh_per_se = 1;
1707 adev->gfx.config.max_backends_per_se = 2;
1708 adev->gfx.config.max_texture_channel_caches = 2;
1709 adev->gfx.config.max_gprs = 256;
1710 adev->gfx.config.max_gs_threads = 32;
1711 adev->gfx.config.max_hw_contexts = 8;
1712
1713 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1714 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1715 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1716 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1717 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1718 break;
1719 case CHIP_FIJI:
1720 adev->gfx.config.max_shader_engines = 4;
1721 adev->gfx.config.max_tile_pipes = 16;
1722 adev->gfx.config.max_cu_per_sh = 16;
1723 adev->gfx.config.max_sh_per_se = 1;
1724 adev->gfx.config.max_backends_per_se = 4;
1725 adev->gfx.config.max_texture_channel_caches = 16;
1726 adev->gfx.config.max_gprs = 256;
1727 adev->gfx.config.max_gs_threads = 32;
1728 adev->gfx.config.max_hw_contexts = 8;
1729
1730 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1731 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1732 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1733 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1734 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1735 break;
1736 case CHIP_POLARIS11:
1737 case CHIP_POLARIS12:
1738 ret = amdgpu_atombios_get_gfx_info(adev);
1739 if (ret)
1740 return ret;
1741 adev->gfx.config.max_gprs = 256;
1742 adev->gfx.config.max_gs_threads = 32;
1743 adev->gfx.config.max_hw_contexts = 8;
1744
1745 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1746 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1747 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1748 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1749 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1750 break;
1751 case CHIP_POLARIS10:
1752 case CHIP_VEGAM:
1753 ret = amdgpu_atombios_get_gfx_info(adev);
1754 if (ret)
1755 return ret;
1756 adev->gfx.config.max_gprs = 256;
1757 adev->gfx.config.max_gs_threads = 32;
1758 adev->gfx.config.max_hw_contexts = 8;
1759
1760 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1761 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1762 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1763 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1764 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1765 break;
1766 case CHIP_TONGA:
1767 adev->gfx.config.max_shader_engines = 4;
1768 adev->gfx.config.max_tile_pipes = 8;
1769 adev->gfx.config.max_cu_per_sh = 8;
1770 adev->gfx.config.max_sh_per_se = 1;
1771 adev->gfx.config.max_backends_per_se = 2;
1772 adev->gfx.config.max_texture_channel_caches = 8;
1773 adev->gfx.config.max_gprs = 256;
1774 adev->gfx.config.max_gs_threads = 32;
1775 adev->gfx.config.max_hw_contexts = 8;
1776
1777 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1778 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1779 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1780 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1781 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1782 break;
1783 case CHIP_CARRIZO:
1784 adev->gfx.config.max_shader_engines = 1;
1785 adev->gfx.config.max_tile_pipes = 2;
1786 adev->gfx.config.max_sh_per_se = 1;
1787 adev->gfx.config.max_backends_per_se = 2;
1788 adev->gfx.config.max_cu_per_sh = 8;
1789 adev->gfx.config.max_texture_channel_caches = 2;
1790 adev->gfx.config.max_gprs = 256;
1791 adev->gfx.config.max_gs_threads = 32;
1792 adev->gfx.config.max_hw_contexts = 8;
1793
1794 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1795 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1796 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1797 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1798 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1799 break;
1800 case CHIP_STONEY:
1801 adev->gfx.config.max_shader_engines = 1;
1802 adev->gfx.config.max_tile_pipes = 2;
1803 adev->gfx.config.max_sh_per_se = 1;
1804 adev->gfx.config.max_backends_per_se = 1;
1805 adev->gfx.config.max_cu_per_sh = 3;
1806 adev->gfx.config.max_texture_channel_caches = 2;
1807 adev->gfx.config.max_gprs = 256;
1808 adev->gfx.config.max_gs_threads = 16;
1809 adev->gfx.config.max_hw_contexts = 8;
1810
1811 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1812 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1813 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1814 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1815 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1816 break;
1817 default:
1818 adev->gfx.config.max_shader_engines = 2;
1819 adev->gfx.config.max_tile_pipes = 4;
1820 adev->gfx.config.max_cu_per_sh = 2;
1821 adev->gfx.config.max_sh_per_se = 1;
1822 adev->gfx.config.max_backends_per_se = 2;
1823 adev->gfx.config.max_texture_channel_caches = 4;
1824 adev->gfx.config.max_gprs = 256;
1825 adev->gfx.config.max_gs_threads = 32;
1826 adev->gfx.config.max_hw_contexts = 8;
1827
1828 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1829 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1830 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1831 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1832 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1833 break;
1834 }
1835
1836 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1837 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1838
1839 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
1840 MC_ARB_RAMCFG, NOOFBANK);
1841 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
1842 MC_ARB_RAMCFG, NOOFRANKS);
1843
1844 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1845 adev->gfx.config.mem_max_burst_length_bytes = 256;
1846 if (adev->flags & AMD_IS_APU) {
1847 /* Get memory bank mapping mode. */
1848 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1849 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1850 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1851
1852 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1853 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1854 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1855
1856 /* Validate settings in case only one DIMM installed. */
1857 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1858 dimm00_addr_map = 0;
1859 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1860 dimm01_addr_map = 0;
1861 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1862 dimm10_addr_map = 0;
1863 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1864 dimm11_addr_map = 0;
1865
1866 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1867 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1868 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1869 adev->gfx.config.mem_row_size_in_kb = 2;
1870 else
1871 adev->gfx.config.mem_row_size_in_kb = 1;
1872 } else {
1873 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1874 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1875 if (adev->gfx.config.mem_row_size_in_kb > 4)
1876 adev->gfx.config.mem_row_size_in_kb = 4;
1877 }
1878
1879 adev->gfx.config.shader_engine_tile_size = 32;
1880 adev->gfx.config.num_gpus = 1;
1881 adev->gfx.config.multi_gpu_tile_size = 64;
1882
1883 /* fix up row size */
1884 switch (adev->gfx.config.mem_row_size_in_kb) {
1885 case 1:
1886 default:
1887 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1888 break;
1889 case 2:
1890 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1891 break;
1892 case 4:
1893 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1894 break;
1895 }
1896 adev->gfx.config.gb_addr_config = gb_addr_config;
1897
1898 return 0;
1899}
1900
1901static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1902 int mec, int pipe, int queue)
1903{
1904 int r;
1905 unsigned irq_type;
1906 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1907 unsigned int hw_prio;
1908
1909 ring = &adev->gfx.compute_ring[ring_id];
1910
1911 /* mec0 is me1 */
1912 ring->me = mec + 1;
1913 ring->pipe = pipe;
1914 ring->queue = queue;
1915
1916 ring->ring_obj = NULL;
1917 ring->use_doorbell = true;
1918 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
1919 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1920 + (ring_id * GFX8_MEC_HPD_SIZE);
1921 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1922
1923 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1924 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1925 + ring->pipe;
1926
1927 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1928 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
1929 /* type-2 packets are deprecated on MEC, use type-3 instead */
1930 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1931 hw_prio, NULL);
1932 if (r)
1933 return r;
1934
1935
1936 return 0;
1937}
1938
1939static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
1940
1941static int gfx_v8_0_sw_init(void *handle)
1942{
1943 int i, j, k, r, ring_id;
1944 struct amdgpu_ring *ring;
1945 struct amdgpu_kiq *kiq;
1946 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1947
1948 switch (adev->asic_type) {
1949 case CHIP_TONGA:
1950 case CHIP_CARRIZO:
1951 case CHIP_FIJI:
1952 case CHIP_POLARIS10:
1953 case CHIP_POLARIS11:
1954 case CHIP_POLARIS12:
1955 case CHIP_VEGAM:
1956 adev->gfx.mec.num_mec = 2;
1957 break;
1958 case CHIP_TOPAZ:
1959 case CHIP_STONEY:
1960 default:
1961 adev->gfx.mec.num_mec = 1;
1962 break;
1963 }
1964
1965 adev->gfx.mec.num_pipe_per_mec = 4;
1966 adev->gfx.mec.num_queue_per_pipe = 8;
1967
1968 /* EOP Event */
1969 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
1970 if (r)
1971 return r;
1972
1973 /* Privileged reg */
1974 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
1975 &adev->gfx.priv_reg_irq);
1976 if (r)
1977 return r;
1978
1979 /* Privileged inst */
1980 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
1981 &adev->gfx.priv_inst_irq);
1982 if (r)
1983 return r;
1984
1985 /* Add CP EDC/ECC irq */
1986 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
1987 &adev->gfx.cp_ecc_error_irq);
1988 if (r)
1989 return r;
1990
1991 /* SQ interrupts. */
1992 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
1993 &adev->gfx.sq_irq);
1994 if (r) {
1995 DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
1996 return r;
1997 }
1998
1999 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
2000
2001 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2002
2003 gfx_v8_0_scratch_init(adev);
2004
2005 r = gfx_v8_0_init_microcode(adev);
2006 if (r) {
2007 DRM_ERROR("Failed to load gfx firmware!\n");
2008 return r;
2009 }
2010
2011 r = adev->gfx.rlc.funcs->init(adev);
2012 if (r) {
2013 DRM_ERROR("Failed to init rlc BOs!\n");
2014 return r;
2015 }
2016
2017 r = gfx_v8_0_mec_init(adev);
2018 if (r) {
2019 DRM_ERROR("Failed to init MEC BOs!\n");
2020 return r;
2021 }
2022
2023 /* set up the gfx ring */
2024 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2025 ring = &adev->gfx.gfx_ring[i];
2026 ring->ring_obj = NULL;
2027 sprintf(ring->name, "gfx");
2028 /* no gfx doorbells on iceland */
2029 if (adev->asic_type != CHIP_TOPAZ) {
2030 ring->use_doorbell = true;
2031 ring->doorbell_index = adev->doorbell_index.gfx_ring0;
2032 }
2033
2034 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2035 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
2036 AMDGPU_RING_PRIO_DEFAULT, NULL);
2037 if (r)
2038 return r;
2039 }
2040
2041
2042 /* set up the compute queues - allocate horizontally across pipes */
2043 ring_id = 0;
2044 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2045 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2046 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2047 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2048 continue;
2049
2050 r = gfx_v8_0_compute_ring_init(adev,
2051 ring_id,
2052 i, k, j);
2053 if (r)
2054 return r;
2055
2056 ring_id++;
2057 }
2058 }
2059 }
2060
2061 r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
2062 if (r) {
2063 DRM_ERROR("Failed to init KIQ BOs!\n");
2064 return r;
2065 }
2066
2067 kiq = &adev->gfx.kiq;
2068 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2069 if (r)
2070 return r;
2071
2072 /* create MQD for all compute queues as well as KIQ for SRIOV case */
2073 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
2074 if (r)
2075 return r;
2076
2077 adev->gfx.ce_ram_size = 0x8000;
2078
2079 r = gfx_v8_0_gpu_early_init(adev);
2080 if (r)
2081 return r;
2082
2083 return 0;
2084}
2085
2086static int gfx_v8_0_sw_fini(void *handle)
2087{
2088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2089 int i;
2090
2091 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2092 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2093 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2094 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2095
2096 amdgpu_gfx_mqd_sw_fini(adev);
2097 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
2098 amdgpu_gfx_kiq_fini(adev);
2099
2100 gfx_v8_0_mec_fini(adev);
2101 amdgpu_gfx_rlc_fini(adev);
2102 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2103 &adev->gfx.rlc.clear_state_gpu_addr,
2104 (void **)&adev->gfx.rlc.cs_ptr);
2105 if ((adev->asic_type == CHIP_CARRIZO) ||
2106 (adev->asic_type == CHIP_STONEY)) {
2107 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2108 &adev->gfx.rlc.cp_table_gpu_addr,
2109 (void **)&adev->gfx.rlc.cp_table_ptr);
2110 }
2111 gfx_v8_0_free_microcode(adev);
2112
2113 return 0;
2114}
2115
2116static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2117{
2118 uint32_t *modearray, *mod2array;
2119 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2120 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2121 u32 reg_offset;
2122
2123 modearray = adev->gfx.config.tile_mode_array;
2124 mod2array = adev->gfx.config.macrotile_mode_array;
2125
2126 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2127 modearray[reg_offset] = 0;
2128
2129 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2130 mod2array[reg_offset] = 0;
2131
2132 switch (adev->asic_type) {
2133 case CHIP_TOPAZ:
2134 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2135 PIPE_CONFIG(ADDR_SURF_P2) |
2136 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2137 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2138 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2139 PIPE_CONFIG(ADDR_SURF_P2) |
2140 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2141 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2142 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2143 PIPE_CONFIG(ADDR_SURF_P2) |
2144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2145 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2146 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2147 PIPE_CONFIG(ADDR_SURF_P2) |
2148 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2149 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2150 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2151 PIPE_CONFIG(ADDR_SURF_P2) |
2152 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2153 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2154 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2155 PIPE_CONFIG(ADDR_SURF_P2) |
2156 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2157 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2158 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2159 PIPE_CONFIG(ADDR_SURF_P2) |
2160 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2161 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2162 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2163 PIPE_CONFIG(ADDR_SURF_P2));
2164 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2165 PIPE_CONFIG(ADDR_SURF_P2) |
2166 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2167 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2168 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2169 PIPE_CONFIG(ADDR_SURF_P2) |
2170 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2171 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2172 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2173 PIPE_CONFIG(ADDR_SURF_P2) |
2174 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2175 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2176 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2177 PIPE_CONFIG(ADDR_SURF_P2) |
2178 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2179 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2180 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2181 PIPE_CONFIG(ADDR_SURF_P2) |
2182 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2183 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2184 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2185 PIPE_CONFIG(ADDR_SURF_P2) |
2186 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2187 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2188 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2189 PIPE_CONFIG(ADDR_SURF_P2) |
2190 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2191 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2192 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2193 PIPE_CONFIG(ADDR_SURF_P2) |
2194 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2195 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2196 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2197 PIPE_CONFIG(ADDR_SURF_P2) |
2198 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2199 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2200 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2201 PIPE_CONFIG(ADDR_SURF_P2) |
2202 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2203 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2204 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2205 PIPE_CONFIG(ADDR_SURF_P2) |
2206 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2207 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2208 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2209 PIPE_CONFIG(ADDR_SURF_P2) |
2210 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2211 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2212 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2213 PIPE_CONFIG(ADDR_SURF_P2) |
2214 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2215 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2216 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2217 PIPE_CONFIG(ADDR_SURF_P2) |
2218 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2219 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2220 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2221 PIPE_CONFIG(ADDR_SURF_P2) |
2222 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2223 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2224 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2225 PIPE_CONFIG(ADDR_SURF_P2) |
2226 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2227 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2228 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2229 PIPE_CONFIG(ADDR_SURF_P2) |
2230 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2231 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2232 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2233 PIPE_CONFIG(ADDR_SURF_P2) |
2234 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2235 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2236
2237 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2240 NUM_BANKS(ADDR_SURF_8_BANK));
2241 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2242 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2243 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2244 NUM_BANKS(ADDR_SURF_8_BANK));
2245 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2248 NUM_BANKS(ADDR_SURF_8_BANK));
2249 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2252 NUM_BANKS(ADDR_SURF_8_BANK));
2253 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2256 NUM_BANKS(ADDR_SURF_8_BANK));
2257 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2258 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2259 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2260 NUM_BANKS(ADDR_SURF_8_BANK));
2261 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2264 NUM_BANKS(ADDR_SURF_8_BANK));
2265 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2266 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2267 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2268 NUM_BANKS(ADDR_SURF_16_BANK));
2269 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2272 NUM_BANKS(ADDR_SURF_16_BANK));
2273 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2274 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2275 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2276 NUM_BANKS(ADDR_SURF_16_BANK));
2277 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2278 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2279 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2280 NUM_BANKS(ADDR_SURF_16_BANK));
2281 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2282 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2283 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2284 NUM_BANKS(ADDR_SURF_16_BANK));
2285 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2286 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2287 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2288 NUM_BANKS(ADDR_SURF_16_BANK));
2289 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2290 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2291 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2292 NUM_BANKS(ADDR_SURF_8_BANK));
2293
2294 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2295 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2296 reg_offset != 23)
2297 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2298
2299 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2300 if (reg_offset != 7)
2301 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2302
2303 break;
2304 case CHIP_FIJI:
2305 case CHIP_VEGAM:
2306 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2307 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2308 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2309 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2310 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2312 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2313 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2314 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2316 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2317 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2318 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2320 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2321 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2322 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2324 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2325 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2326 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2328 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2329 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2330 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2332 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2333 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2334 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2335 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2336 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2337 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2338 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2339 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2340 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2341 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2342 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2343 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2344 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2345 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2346 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2347 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2348 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2349 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2350 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2351 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2352 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2353 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2354 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2355 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2356 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2357 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2358 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2359 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2360 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2361 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2362 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2363 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2364 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2365 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2366 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2368 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2369 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2370 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2371 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2372 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2373 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2374 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2375 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2376 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2377 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2378 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2379 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2380 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2381 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2382 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2383 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2384 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2385 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2386 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2387 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2388 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2389 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2390 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2391 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2392 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2393 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2395 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2396 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2397 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2398 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2399 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2400 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2401 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2404 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2405 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2407 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2408 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2409 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2410 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2411 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2412 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2413 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2414 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2416 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2417 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2418 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2420 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2421 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2423 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2424 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2425 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2426 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2428
2429 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2432 NUM_BANKS(ADDR_SURF_8_BANK));
2433 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2436 NUM_BANKS(ADDR_SURF_8_BANK));
2437 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2440 NUM_BANKS(ADDR_SURF_8_BANK));
2441 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2442 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2443 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2444 NUM_BANKS(ADDR_SURF_8_BANK));
2445 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2448 NUM_BANKS(ADDR_SURF_8_BANK));
2449 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2452 NUM_BANKS(ADDR_SURF_8_BANK));
2453 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2456 NUM_BANKS(ADDR_SURF_8_BANK));
2457 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2459 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2460 NUM_BANKS(ADDR_SURF_8_BANK));
2461 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2464 NUM_BANKS(ADDR_SURF_8_BANK));
2465 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2468 NUM_BANKS(ADDR_SURF_8_BANK));
2469 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2471 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2472 NUM_BANKS(ADDR_SURF_8_BANK));
2473 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2476 NUM_BANKS(ADDR_SURF_8_BANK));
2477 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2480 NUM_BANKS(ADDR_SURF_8_BANK));
2481 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2484 NUM_BANKS(ADDR_SURF_4_BANK));
2485
2486 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2487 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2488
2489 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2490 if (reg_offset != 7)
2491 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2492
2493 break;
2494 case CHIP_TONGA:
2495 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2496 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2498 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2499 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2500 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2502 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2503 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2504 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2506 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2507 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2508 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2510 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2511 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2512 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2514 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2515 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2516 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2518 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2519 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2520 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2523 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2524 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2526 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2527 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2528 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2529 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2530 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2531 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2532 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2533 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2534 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2535 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2536 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2537 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2538 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2539 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2540 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2541 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2542 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2543 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2544 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2545 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2546 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2547 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2548 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2549 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2550 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2551 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2552 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2553 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2554 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2555 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2556 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2557 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2558 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2560 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2561 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2562 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2563 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2564 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2565 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2566 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2567 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2569 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2570 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2571 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2572 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2573 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2574 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2576 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2577 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2578 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2579 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2581 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2582 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2583 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2584 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2585 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2586 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2587 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2588 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2589 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2590 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2591 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2593 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2594 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2595 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2597 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2598 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2599 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2600 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2601 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2602 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2603 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2605 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2606 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2607 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2608 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2609 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2610 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2611 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2612 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2613 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2614 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2615 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2617
2618 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2621 NUM_BANKS(ADDR_SURF_16_BANK));
2622 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2623 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2624 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2625 NUM_BANKS(ADDR_SURF_16_BANK));
2626 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2629 NUM_BANKS(ADDR_SURF_16_BANK));
2630 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2632 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2633 NUM_BANKS(ADDR_SURF_16_BANK));
2634 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2637 NUM_BANKS(ADDR_SURF_16_BANK));
2638 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2640 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2641 NUM_BANKS(ADDR_SURF_16_BANK));
2642 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2643 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2644 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2645 NUM_BANKS(ADDR_SURF_16_BANK));
2646 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2649 NUM_BANKS(ADDR_SURF_16_BANK));
2650 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2653 NUM_BANKS(ADDR_SURF_16_BANK));
2654 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2657 NUM_BANKS(ADDR_SURF_16_BANK));
2658 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2659 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2660 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2661 NUM_BANKS(ADDR_SURF_16_BANK));
2662 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2665 NUM_BANKS(ADDR_SURF_8_BANK));
2666 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2669 NUM_BANKS(ADDR_SURF_4_BANK));
2670 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2673 NUM_BANKS(ADDR_SURF_4_BANK));
2674
2675 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2676 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2677
2678 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2679 if (reg_offset != 7)
2680 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2681
2682 break;
2683 case CHIP_POLARIS11:
2684 case CHIP_POLARIS12:
2685 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2686 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2687 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2688 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2689 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2690 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2691 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2692 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2693 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2694 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2695 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2696 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2697 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2698 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2699 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2700 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2701 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2702 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2703 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2704 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2705 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2706 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2707 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2708 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2709 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2710 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2711 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2712 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2713 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2714 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2715 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2716 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2717 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2718 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2719 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2720 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2721 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2722 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2723 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2724 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2725 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2726 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2727 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2728 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2729 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2730 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2731 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2732 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2733 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2734 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2735 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2736 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2737 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2738 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2739 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2740 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2741 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2742 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2743 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2744 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2745 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2746 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2747 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2748 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2749 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2750 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2751 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2752 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2753 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2754 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2755 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2756 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2757 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2758 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2759 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2760 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2761 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2762 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2763 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2764 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2765 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2766 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2767 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2768 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2769 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2770 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2771 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2772 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2773 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2774 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2775 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2776 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2777 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2778 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2779 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2780 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2781 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2782 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2783 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2784 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2785 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2786 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2787 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2788 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2789 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2790 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2791 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2792 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2793 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2794 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2795 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2796 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2797 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2798 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2799 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2800 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2801 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2802 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2803 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2804 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2805 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2806 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2807
2808 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2810 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2811 NUM_BANKS(ADDR_SURF_16_BANK));
2812
2813 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2816 NUM_BANKS(ADDR_SURF_16_BANK));
2817
2818 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2819 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2820 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2821 NUM_BANKS(ADDR_SURF_16_BANK));
2822
2823 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2824 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2825 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2826 NUM_BANKS(ADDR_SURF_16_BANK));
2827
2828 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2829 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2830 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2831 NUM_BANKS(ADDR_SURF_16_BANK));
2832
2833 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2836 NUM_BANKS(ADDR_SURF_16_BANK));
2837
2838 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2839 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2840 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2841 NUM_BANKS(ADDR_SURF_16_BANK));
2842
2843 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2846 NUM_BANKS(ADDR_SURF_16_BANK));
2847
2848 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2851 NUM_BANKS(ADDR_SURF_16_BANK));
2852
2853 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2856 NUM_BANKS(ADDR_SURF_16_BANK));
2857
2858 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2859 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2860 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2861 NUM_BANKS(ADDR_SURF_16_BANK));
2862
2863 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2864 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2865 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2866 NUM_BANKS(ADDR_SURF_16_BANK));
2867
2868 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2869 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2870 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2871 NUM_BANKS(ADDR_SURF_8_BANK));
2872
2873 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2876 NUM_BANKS(ADDR_SURF_4_BANK));
2877
2878 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2879 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2880
2881 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2882 if (reg_offset != 7)
2883 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2884
2885 break;
2886 case CHIP_POLARIS10:
2887 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2888 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2889 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2890 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2891 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2892 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2893 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2894 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2895 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2896 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2897 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2898 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2899 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2900 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2901 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2902 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2903 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2904 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2905 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2906 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2907 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2908 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2909 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2910 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2911 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2912 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2913 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2914 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2915 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2916 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2918 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2919 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2920 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2921 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2922 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2923 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2924 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2925 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2926 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2927 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2928 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2929 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2930 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2931 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2932 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2933 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2934 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2935 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2936 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2937 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2938 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2939 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2940 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2941 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2942 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2943 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2944 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2945 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2946 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2947 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2948 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2949 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2950 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2951 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2952 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2953 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2954 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2955 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2956 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2957 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2958 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2959 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2960 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2961 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2962 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2963 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2964 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2965 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2966 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2967 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2968 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2969 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2970 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2971 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2972 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2973 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2974 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2975 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2976 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2977 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2978 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2979 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2980 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2981 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2982 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2983 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2984 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2985 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2986 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2987 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2988 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2989 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2990 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2991 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2992 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2993 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2994 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2995 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2996 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2997 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2998 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2999 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3000 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3001 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3002 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3003 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3004 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3005 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3006 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
3007 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3008 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3009
3010 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3011 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3012 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3013 NUM_BANKS(ADDR_SURF_16_BANK));
3014
3015 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3016 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3017 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3018 NUM_BANKS(ADDR_SURF_16_BANK));
3019
3020 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3023 NUM_BANKS(ADDR_SURF_16_BANK));
3024
3025 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3026 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3027 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3028 NUM_BANKS(ADDR_SURF_16_BANK));
3029
3030 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3033 NUM_BANKS(ADDR_SURF_16_BANK));
3034
3035 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3036 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3037 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3038 NUM_BANKS(ADDR_SURF_16_BANK));
3039
3040 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3041 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3042 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3043 NUM_BANKS(ADDR_SURF_16_BANK));
3044
3045 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3048 NUM_BANKS(ADDR_SURF_16_BANK));
3049
3050 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3053 NUM_BANKS(ADDR_SURF_16_BANK));
3054
3055 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3056 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3057 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3058 NUM_BANKS(ADDR_SURF_16_BANK));
3059
3060 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3061 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3062 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3063 NUM_BANKS(ADDR_SURF_16_BANK));
3064
3065 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3066 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3067 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3068 NUM_BANKS(ADDR_SURF_8_BANK));
3069
3070 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3073 NUM_BANKS(ADDR_SURF_4_BANK));
3074
3075 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3076 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3077 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3078 NUM_BANKS(ADDR_SURF_4_BANK));
3079
3080 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3081 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3082
3083 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3084 if (reg_offset != 7)
3085 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3086
3087 break;
3088 case CHIP_STONEY:
3089 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3090 PIPE_CONFIG(ADDR_SURF_P2) |
3091 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3092 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3093 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3094 PIPE_CONFIG(ADDR_SURF_P2) |
3095 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3096 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3097 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3098 PIPE_CONFIG(ADDR_SURF_P2) |
3099 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3100 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3101 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3102 PIPE_CONFIG(ADDR_SURF_P2) |
3103 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3104 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3105 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3106 PIPE_CONFIG(ADDR_SURF_P2) |
3107 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3108 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3109 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3110 PIPE_CONFIG(ADDR_SURF_P2) |
3111 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3112 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3113 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3114 PIPE_CONFIG(ADDR_SURF_P2) |
3115 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3116 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3117 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3118 PIPE_CONFIG(ADDR_SURF_P2));
3119 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3120 PIPE_CONFIG(ADDR_SURF_P2) |
3121 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3123 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3124 PIPE_CONFIG(ADDR_SURF_P2) |
3125 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3127 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3128 PIPE_CONFIG(ADDR_SURF_P2) |
3129 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3130 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3131 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3132 PIPE_CONFIG(ADDR_SURF_P2) |
3133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3135 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3136 PIPE_CONFIG(ADDR_SURF_P2) |
3137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3139 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3140 PIPE_CONFIG(ADDR_SURF_P2) |
3141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3143 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3144 PIPE_CONFIG(ADDR_SURF_P2) |
3145 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3146 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3147 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3148 PIPE_CONFIG(ADDR_SURF_P2) |
3149 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3150 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3151 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3152 PIPE_CONFIG(ADDR_SURF_P2) |
3153 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3154 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3155 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3156 PIPE_CONFIG(ADDR_SURF_P2) |
3157 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3158 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3159 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3160 PIPE_CONFIG(ADDR_SURF_P2) |
3161 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3162 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3163 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3164 PIPE_CONFIG(ADDR_SURF_P2) |
3165 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3166 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3167 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3168 PIPE_CONFIG(ADDR_SURF_P2) |
3169 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3170 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3171 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3172 PIPE_CONFIG(ADDR_SURF_P2) |
3173 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3174 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3175 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3176 PIPE_CONFIG(ADDR_SURF_P2) |
3177 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3178 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3179 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3180 PIPE_CONFIG(ADDR_SURF_P2) |
3181 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3182 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3183 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3184 PIPE_CONFIG(ADDR_SURF_P2) |
3185 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3186 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3187 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3188 PIPE_CONFIG(ADDR_SURF_P2) |
3189 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3190 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3191
3192 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3195 NUM_BANKS(ADDR_SURF_8_BANK));
3196 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3199 NUM_BANKS(ADDR_SURF_8_BANK));
3200 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3203 NUM_BANKS(ADDR_SURF_8_BANK));
3204 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3207 NUM_BANKS(ADDR_SURF_8_BANK));
3208 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3211 NUM_BANKS(ADDR_SURF_8_BANK));
3212 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3215 NUM_BANKS(ADDR_SURF_8_BANK));
3216 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3217 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3218 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3219 NUM_BANKS(ADDR_SURF_8_BANK));
3220 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3223 NUM_BANKS(ADDR_SURF_16_BANK));
3224 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3225 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3226 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3227 NUM_BANKS(ADDR_SURF_16_BANK));
3228 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3231 NUM_BANKS(ADDR_SURF_16_BANK));
3232 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3233 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3234 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3235 NUM_BANKS(ADDR_SURF_16_BANK));
3236 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3239 NUM_BANKS(ADDR_SURF_16_BANK));
3240 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3241 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3242 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3243 NUM_BANKS(ADDR_SURF_16_BANK));
3244 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3247 NUM_BANKS(ADDR_SURF_8_BANK));
3248
3249 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3250 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3251 reg_offset != 23)
3252 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3253
3254 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3255 if (reg_offset != 7)
3256 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3257
3258 break;
3259 default:
3260 dev_warn(adev->dev,
3261 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3262 adev->asic_type);
3263 fallthrough;
3264
3265 case CHIP_CARRIZO:
3266 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3267 PIPE_CONFIG(ADDR_SURF_P2) |
3268 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3269 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3270 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3271 PIPE_CONFIG(ADDR_SURF_P2) |
3272 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3273 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3274 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3275 PIPE_CONFIG(ADDR_SURF_P2) |
3276 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3277 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3278 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3279 PIPE_CONFIG(ADDR_SURF_P2) |
3280 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3281 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3282 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3283 PIPE_CONFIG(ADDR_SURF_P2) |
3284 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3285 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3286 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3287 PIPE_CONFIG(ADDR_SURF_P2) |
3288 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3289 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3290 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3291 PIPE_CONFIG(ADDR_SURF_P2) |
3292 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3293 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3294 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3295 PIPE_CONFIG(ADDR_SURF_P2));
3296 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3297 PIPE_CONFIG(ADDR_SURF_P2) |
3298 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3299 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3300 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3301 PIPE_CONFIG(ADDR_SURF_P2) |
3302 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3303 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3304 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3305 PIPE_CONFIG(ADDR_SURF_P2) |
3306 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3307 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3308 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3309 PIPE_CONFIG(ADDR_SURF_P2) |
3310 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3311 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3312 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3313 PIPE_CONFIG(ADDR_SURF_P2) |
3314 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3315 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3316 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3317 PIPE_CONFIG(ADDR_SURF_P2) |
3318 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3319 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3320 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3321 PIPE_CONFIG(ADDR_SURF_P2) |
3322 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3323 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3324 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3325 PIPE_CONFIG(ADDR_SURF_P2) |
3326 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3327 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3328 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3329 PIPE_CONFIG(ADDR_SURF_P2) |
3330 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3331 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3332 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3333 PIPE_CONFIG(ADDR_SURF_P2) |
3334 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3335 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3336 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3337 PIPE_CONFIG(ADDR_SURF_P2) |
3338 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3339 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3340 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3341 PIPE_CONFIG(ADDR_SURF_P2) |
3342 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3343 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3344 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3345 PIPE_CONFIG(ADDR_SURF_P2) |
3346 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3347 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3348 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3349 PIPE_CONFIG(ADDR_SURF_P2) |
3350 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3351 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3352 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3353 PIPE_CONFIG(ADDR_SURF_P2) |
3354 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3355 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3356 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3357 PIPE_CONFIG(ADDR_SURF_P2) |
3358 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3359 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3360 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3361 PIPE_CONFIG(ADDR_SURF_P2) |
3362 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3363 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3364 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3365 PIPE_CONFIG(ADDR_SURF_P2) |
3366 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3368
3369 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3370 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3371 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3372 NUM_BANKS(ADDR_SURF_8_BANK));
3373 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3374 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3375 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3376 NUM_BANKS(ADDR_SURF_8_BANK));
3377 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3378 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3379 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3380 NUM_BANKS(ADDR_SURF_8_BANK));
3381 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3382 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3383 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3384 NUM_BANKS(ADDR_SURF_8_BANK));
3385 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3386 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3387 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3388 NUM_BANKS(ADDR_SURF_8_BANK));
3389 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3390 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3391 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3392 NUM_BANKS(ADDR_SURF_8_BANK));
3393 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3394 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3395 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3396 NUM_BANKS(ADDR_SURF_8_BANK));
3397 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3398 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3399 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3400 NUM_BANKS(ADDR_SURF_16_BANK));
3401 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3402 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3403 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3404 NUM_BANKS(ADDR_SURF_16_BANK));
3405 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3406 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3407 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3408 NUM_BANKS(ADDR_SURF_16_BANK));
3409 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3410 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3411 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3412 NUM_BANKS(ADDR_SURF_16_BANK));
3413 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3415 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3416 NUM_BANKS(ADDR_SURF_16_BANK));
3417 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3418 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3419 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3420 NUM_BANKS(ADDR_SURF_16_BANK));
3421 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3424 NUM_BANKS(ADDR_SURF_8_BANK));
3425
3426 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3427 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3428 reg_offset != 23)
3429 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3430
3431 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3432 if (reg_offset != 7)
3433 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3434
3435 break;
3436 }
3437}
3438
3439static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3440 u32 se_num, u32 sh_num, u32 instance)
3441{
3442 u32 data;
3443
3444 if (instance == 0xffffffff)
3445 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3446 else
3447 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3448
3449 if (se_num == 0xffffffff)
3450 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3451 else
3452 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3453
3454 if (sh_num == 0xffffffff)
3455 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3456 else
3457 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3458
3459 WREG32(mmGRBM_GFX_INDEX, data);
3460}
3461
3462static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3463 u32 me, u32 pipe, u32 q, u32 vm)
3464{
3465 vi_srbm_select(adev, me, pipe, q, vm);
3466}
3467
3468static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
3469{
3470 u32 data, mask;
3471
3472 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
3473 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3474
3475 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
3476
3477 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3478 adev->gfx.config.max_sh_per_se);
3479
3480 return (~data) & mask;
3481}
3482
3483static void
3484gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3485{
3486 switch (adev->asic_type) {
3487 case CHIP_FIJI:
3488 case CHIP_VEGAM:
3489 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3490 RB_XSEL2(1) | PKR_MAP(2) |
3491 PKR_XSEL(1) | PKR_YSEL(1) |
3492 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3493 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3494 SE_PAIR_YSEL(2);
3495 break;
3496 case CHIP_TONGA:
3497 case CHIP_POLARIS10:
3498 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3499 SE_XSEL(1) | SE_YSEL(1);
3500 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3501 SE_PAIR_YSEL(2);
3502 break;
3503 case CHIP_TOPAZ:
3504 case CHIP_CARRIZO:
3505 *rconf |= RB_MAP_PKR0(2);
3506 *rconf1 |= 0x0;
3507 break;
3508 case CHIP_POLARIS11:
3509 case CHIP_POLARIS12:
3510 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3511 SE_XSEL(1) | SE_YSEL(1);
3512 *rconf1 |= 0x0;
3513 break;
3514 case CHIP_STONEY:
3515 *rconf |= 0x0;
3516 *rconf1 |= 0x0;
3517 break;
3518 default:
3519 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3520 break;
3521 }
3522}
3523
3524static void
3525gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3526 u32 raster_config, u32 raster_config_1,
3527 unsigned rb_mask, unsigned num_rb)
3528{
3529 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3530 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3531 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3532 unsigned rb_per_se = num_rb / num_se;
3533 unsigned se_mask[4];
3534 unsigned se;
3535
3536 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3537 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3538 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3539 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3540
3541 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3542 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3543 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3544
3545 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3546 (!se_mask[2] && !se_mask[3]))) {
3547 raster_config_1 &= ~SE_PAIR_MAP_MASK;
3548
3549 if (!se_mask[0] && !se_mask[1]) {
3550 raster_config_1 |=
3551 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3552 } else {
3553 raster_config_1 |=
3554 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3555 }
3556 }
3557
3558 for (se = 0; se < num_se; se++) {
3559 unsigned raster_config_se = raster_config;
3560 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3561 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3562 int idx = (se / 2) * 2;
3563
3564 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3565 raster_config_se &= ~SE_MAP_MASK;
3566
3567 if (!se_mask[idx]) {
3568 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3569 } else {
3570 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3571 }
3572 }
3573
3574 pkr0_mask &= rb_mask;
3575 pkr1_mask &= rb_mask;
3576 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3577 raster_config_se &= ~PKR_MAP_MASK;
3578
3579 if (!pkr0_mask) {
3580 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3581 } else {
3582 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3583 }
3584 }
3585
3586 if (rb_per_se >= 2) {
3587 unsigned rb0_mask = 1 << (se * rb_per_se);
3588 unsigned rb1_mask = rb0_mask << 1;
3589
3590 rb0_mask &= rb_mask;
3591 rb1_mask &= rb_mask;
3592 if (!rb0_mask || !rb1_mask) {
3593 raster_config_se &= ~RB_MAP_PKR0_MASK;
3594
3595 if (!rb0_mask) {
3596 raster_config_se |=
3597 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3598 } else {
3599 raster_config_se |=
3600 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3601 }
3602 }
3603
3604 if (rb_per_se > 2) {
3605 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3606 rb1_mask = rb0_mask << 1;
3607 rb0_mask &= rb_mask;
3608 rb1_mask &= rb_mask;
3609 if (!rb0_mask || !rb1_mask) {
3610 raster_config_se &= ~RB_MAP_PKR1_MASK;
3611
3612 if (!rb0_mask) {
3613 raster_config_se |=
3614 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3615 } else {
3616 raster_config_se |=
3617 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3618 }
3619 }
3620 }
3621 }
3622
3623 /* GRBM_GFX_INDEX has a different offset on VI */
3624 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
3625 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3626 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3627 }
3628
3629 /* GRBM_GFX_INDEX has a different offset on VI */
3630 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3631}
3632
3633static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
3634{
3635 int i, j;
3636 u32 data;
3637 u32 raster_config = 0, raster_config_1 = 0;
3638 u32 active_rbs = 0;
3639 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3640 adev->gfx.config.max_sh_per_se;
3641 unsigned num_rb_pipes;
3642
3643 mutex_lock(&adev->grbm_idx_mutex);
3644 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3646 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3647 data = gfx_v8_0_get_rb_active_bitmap(adev);
3648 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
3649 rb_bitmap_width_per_sh);
3650 }
3651 }
3652 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3653
3654 adev->gfx.config.backend_enable_mask = active_rbs;
3655 adev->gfx.config.num_rbs = hweight32(active_rbs);
3656
3657 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3658 adev->gfx.config.max_shader_engines, 16);
3659
3660 gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3661
3662 if (!adev->gfx.config.backend_enable_mask ||
3663 adev->gfx.config.num_rbs >= num_rb_pipes) {
3664 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3665 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3666 } else {
3667 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3668 adev->gfx.config.backend_enable_mask,
3669 num_rb_pipes);
3670 }
3671
3672 /* cache the values for userspace */
3673 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3674 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3675 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3676 adev->gfx.config.rb_config[i][j].rb_backend_disable =
3677 RREG32(mmCC_RB_BACKEND_DISABLE);
3678 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3679 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3680 adev->gfx.config.rb_config[i][j].raster_config =
3681 RREG32(mmPA_SC_RASTER_CONFIG);
3682 adev->gfx.config.rb_config[i][j].raster_config_1 =
3683 RREG32(mmPA_SC_RASTER_CONFIG_1);
3684 }
3685 }
3686 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3687 mutex_unlock(&adev->grbm_idx_mutex);
3688}
3689
3690#define DEFAULT_SH_MEM_BASES (0x6000)
3691/**
3692 * gfx_v8_0_init_compute_vmid - gart enable
3693 *
3694 * @adev: amdgpu_device pointer
3695 *
3696 * Initialize compute vmid sh_mem registers
3697 *
3698 */
3699static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
3700{
3701 int i;
3702 uint32_t sh_mem_config;
3703 uint32_t sh_mem_bases;
3704
3705 /*
3706 * Configure apertures:
3707 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3708 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3709 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3710 */
3711 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3712
3713 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3714 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3715 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3716 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3717 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3718 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3719
3720 mutex_lock(&adev->srbm_mutex);
3721 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3722 vi_srbm_select(adev, 0, 0, 0, i);
3723 /* CP and shaders */
3724 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3725 WREG32(mmSH_MEM_APE1_BASE, 1);
3726 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3727 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3728 }
3729 vi_srbm_select(adev, 0, 0, 0, 0);
3730 mutex_unlock(&adev->srbm_mutex);
3731
3732 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
3733 acccess. These should be enabled by FW for target VMIDs. */
3734 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3735 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
3736 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
3737 WREG32(amdgpu_gds_reg_offset[i].gws, 0);
3738 WREG32(amdgpu_gds_reg_offset[i].oa, 0);
3739 }
3740}
3741
3742static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
3743{
3744 int vmid;
3745
3746 /*
3747 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
3748 * access. Compute VMIDs should be enabled by FW for target VMIDs,
3749 * the driver can enable them for graphics. VMID0 should maintain
3750 * access so that HWS firmware can save/restore entries.
3751 */
3752 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
3753 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
3754 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
3755 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
3756 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
3757 }
3758}
3759
3760static void gfx_v8_0_config_init(struct amdgpu_device *adev)
3761{
3762 switch (adev->asic_type) {
3763 default:
3764 adev->gfx.config.double_offchip_lds_buf = 1;
3765 break;
3766 case CHIP_CARRIZO:
3767 case CHIP_STONEY:
3768 adev->gfx.config.double_offchip_lds_buf = 0;
3769 break;
3770 }
3771}
3772
3773static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
3774{
3775 u32 tmp, sh_static_mem_cfg;
3776 int i;
3777
3778 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3779 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3780 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3781 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
3782
3783 gfx_v8_0_tiling_mode_table_init(adev);
3784 gfx_v8_0_setup_rb(adev);
3785 gfx_v8_0_get_cu_info(adev);
3786 gfx_v8_0_config_init(adev);
3787
3788 /* XXX SH_MEM regs */
3789 /* where to put LDS, scratch, GPUVM in FSA64 space */
3790 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
3791 SWIZZLE_ENABLE, 1);
3792 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3793 ELEMENT_SIZE, 1);
3794 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3795 INDEX_STRIDE, 3);
3796 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
3797
3798 mutex_lock(&adev->srbm_mutex);
3799 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
3800 vi_srbm_select(adev, 0, 0, 0, i);
3801 /* CP and shaders */
3802 if (i == 0) {
3803 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3804 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3805 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3806 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3807 WREG32(mmSH_MEM_CONFIG, tmp);
3808 WREG32(mmSH_MEM_BASES, 0);
3809 } else {
3810 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3811 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3812 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3813 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3814 WREG32(mmSH_MEM_CONFIG, tmp);
3815 tmp = adev->gmc.shared_aperture_start >> 48;
3816 WREG32(mmSH_MEM_BASES, tmp);
3817 }
3818
3819 WREG32(mmSH_MEM_APE1_BASE, 1);
3820 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3821 }
3822 vi_srbm_select(adev, 0, 0, 0, 0);
3823 mutex_unlock(&adev->srbm_mutex);
3824
3825 gfx_v8_0_init_compute_vmid(adev);
3826 gfx_v8_0_init_gds_vmid(adev);
3827
3828 mutex_lock(&adev->grbm_idx_mutex);
3829 /*
3830 * making sure that the following register writes will be broadcasted
3831 * to all the shaders
3832 */
3833 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3834
3835 WREG32(mmPA_SC_FIFO_SIZE,
3836 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3837 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3838 (adev->gfx.config.sc_prim_fifo_size_backend <<
3839 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3840 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3841 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3842 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3843 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3844
3845 tmp = RREG32(mmSPI_ARB_PRIORITY);
3846 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3847 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3848 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3849 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3850 WREG32(mmSPI_ARB_PRIORITY, tmp);
3851
3852 mutex_unlock(&adev->grbm_idx_mutex);
3853
3854}
3855
3856static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3857{
3858 u32 i, j, k;
3859 u32 mask;
3860
3861 mutex_lock(&adev->grbm_idx_mutex);
3862 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3863 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3864 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3865 for (k = 0; k < adev->usec_timeout; k++) {
3866 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3867 break;
3868 udelay(1);
3869 }
3870 if (k == adev->usec_timeout) {
3871 gfx_v8_0_select_se_sh(adev, 0xffffffff,
3872 0xffffffff, 0xffffffff);
3873 mutex_unlock(&adev->grbm_idx_mutex);
3874 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
3875 i, j);
3876 return;
3877 }
3878 }
3879 }
3880 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3881 mutex_unlock(&adev->grbm_idx_mutex);
3882
3883 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3884 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3885 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3886 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3887 for (k = 0; k < adev->usec_timeout; k++) {
3888 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3889 break;
3890 udelay(1);
3891 }
3892}
3893
3894static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3895 bool enable)
3896{
3897 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3898
3899 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3900 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3901 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3902 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3903
3904 WREG32(mmCP_INT_CNTL_RING0, tmp);
3905}
3906
3907static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3908{
3909 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
3910 /* csib */
3911 WREG32(mmRLC_CSIB_ADDR_HI,
3912 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3913 WREG32(mmRLC_CSIB_ADDR_LO,
3914 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3915 WREG32(mmRLC_CSIB_LENGTH,
3916 adev->gfx.rlc.clear_state_size);
3917}
3918
3919static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3920 int ind_offset,
3921 int list_size,
3922 int *unique_indices,
3923 int *indices_count,
3924 int max_indices,
3925 int *ind_start_offsets,
3926 int *offset_count,
3927 int max_offset)
3928{
3929 int indices;
3930 bool new_entry = true;
3931
3932 for (; ind_offset < list_size; ind_offset++) {
3933
3934 if (new_entry) {
3935 new_entry = false;
3936 ind_start_offsets[*offset_count] = ind_offset;
3937 *offset_count = *offset_count + 1;
3938 BUG_ON(*offset_count >= max_offset);
3939 }
3940
3941 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3942 new_entry = true;
3943 continue;
3944 }
3945
3946 ind_offset += 2;
3947
3948 /* look for the matching indice */
3949 for (indices = 0;
3950 indices < *indices_count;
3951 indices++) {
3952 if (unique_indices[indices] ==
3953 register_list_format[ind_offset])
3954 break;
3955 }
3956
3957 if (indices >= *indices_count) {
3958 unique_indices[*indices_count] =
3959 register_list_format[ind_offset];
3960 indices = *indices_count;
3961 *indices_count = *indices_count + 1;
3962 BUG_ON(*indices_count >= max_indices);
3963 }
3964
3965 register_list_format[ind_offset] = indices;
3966 }
3967}
3968
3969static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3970{
3971 int i, temp, data;
3972 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3973 int indices_count = 0;
3974 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3975 int offset_count = 0;
3976
3977 int list_size;
3978 unsigned int *register_list_format =
3979 kmemdup(adev->gfx.rlc.register_list_format,
3980 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3981 if (!register_list_format)
3982 return -ENOMEM;
3983
3984 gfx_v8_0_parse_ind_reg_list(register_list_format,
3985 RLC_FormatDirectRegListLength,
3986 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3987 unique_indices,
3988 &indices_count,
3989 ARRAY_SIZE(unique_indices),
3990 indirect_start_offsets,
3991 &offset_count,
3992 ARRAY_SIZE(indirect_start_offsets));
3993
3994 /* save and restore list */
3995 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
3996
3997 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3998 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3999 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
4000
4001 /* indirect list */
4002 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
4003 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
4004 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
4005
4006 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
4007 list_size = list_size >> 1;
4008 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
4009 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
4010
4011 /* starting offsets starts */
4012 WREG32(mmRLC_GPM_SCRATCH_ADDR,
4013 adev->gfx.rlc.starting_offsets_start);
4014 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
4015 WREG32(mmRLC_GPM_SCRATCH_DATA,
4016 indirect_start_offsets[i]);
4017
4018 /* unique indices */
4019 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
4020 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
4021 for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
4022 if (unique_indices[i] != 0) {
4023 WREG32(temp + i, unique_indices[i] & 0x3FFFF);
4024 WREG32(data + i, unique_indices[i] >> 20);
4025 }
4026 }
4027 kfree(register_list_format);
4028
4029 return 0;
4030}
4031
4032static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
4033{
4034 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
4035}
4036
4037static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
4038{
4039 uint32_t data;
4040
4041 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
4042
4043 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
4044 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
4045 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
4046 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
4047 WREG32(mmRLC_PG_DELAY, data);
4048
4049 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
4050 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
4051
4052}
4053
4054static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
4055 bool enable)
4056{
4057 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4058}
4059
4060static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
4061 bool enable)
4062{
4063 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4064}
4065
4066static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
4067{
4068 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4069}
4070
4071static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4072{
4073 if ((adev->asic_type == CHIP_CARRIZO) ||
4074 (adev->asic_type == CHIP_STONEY)) {
4075 gfx_v8_0_init_csb(adev);
4076 gfx_v8_0_init_save_restore_list(adev);
4077 gfx_v8_0_enable_save_restore_machine(adev);
4078 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4079 gfx_v8_0_init_power_gating(adev);
4080 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4081 } else if ((adev->asic_type == CHIP_POLARIS11) ||
4082 (adev->asic_type == CHIP_POLARIS12) ||
4083 (adev->asic_type == CHIP_VEGAM)) {
4084 gfx_v8_0_init_csb(adev);
4085 gfx_v8_0_init_save_restore_list(adev);
4086 gfx_v8_0_enable_save_restore_machine(adev);
4087 gfx_v8_0_init_power_gating(adev);
4088 }
4089
4090}
4091
4092static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
4093{
4094 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
4095
4096 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4097 gfx_v8_0_wait_for_rlc_serdes(adev);
4098}
4099
4100static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
4101{
4102 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4103 udelay(50);
4104
4105 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4106 udelay(50);
4107}
4108
4109static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
4110{
4111 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
4112
4113 /* carrizo do enable cp interrupt after cp inited */
4114 if (!(adev->flags & AMD_IS_APU))
4115 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4116
4117 udelay(50);
4118}
4119
4120static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4121{
4122 if (amdgpu_sriov_vf(adev)) {
4123 gfx_v8_0_init_csb(adev);
4124 return 0;
4125 }
4126
4127 adev->gfx.rlc.funcs->stop(adev);
4128 adev->gfx.rlc.funcs->reset(adev);
4129 gfx_v8_0_init_pg(adev);
4130 adev->gfx.rlc.funcs->start(adev);
4131
4132 return 0;
4133}
4134
4135static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4136{
4137 u32 tmp = RREG32(mmCP_ME_CNTL);
4138
4139 if (enable) {
4140 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4141 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4142 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4143 } else {
4144 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4145 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4146 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4147 }
4148 WREG32(mmCP_ME_CNTL, tmp);
4149 udelay(50);
4150}
4151
4152static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4153{
4154 u32 count = 0;
4155 const struct cs_section_def *sect = NULL;
4156 const struct cs_extent_def *ext = NULL;
4157
4158 /* begin clear state */
4159 count += 2;
4160 /* context control state */
4161 count += 3;
4162
4163 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4164 for (ext = sect->section; ext->extent != NULL; ++ext) {
4165 if (sect->id == SECT_CONTEXT)
4166 count += 2 + ext->reg_count;
4167 else
4168 return 0;
4169 }
4170 }
4171 /* pa_sc_raster_config/pa_sc_raster_config1 */
4172 count += 4;
4173 /* end clear state */
4174 count += 2;
4175 /* clear state */
4176 count += 2;
4177
4178 return count;
4179}
4180
4181static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4182{
4183 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4184 const struct cs_section_def *sect = NULL;
4185 const struct cs_extent_def *ext = NULL;
4186 int r, i;
4187
4188 /* init the CP */
4189 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4190 WREG32(mmCP_ENDIAN_SWAP, 0);
4191 WREG32(mmCP_DEVICE_ID, 1);
4192
4193 gfx_v8_0_cp_gfx_enable(adev, true);
4194
4195 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
4196 if (r) {
4197 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4198 return r;
4199 }
4200
4201 /* clear state buffer */
4202 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4203 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4204
4205 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4206 amdgpu_ring_write(ring, 0x80000000);
4207 amdgpu_ring_write(ring, 0x80000000);
4208
4209 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4210 for (ext = sect->section; ext->extent != NULL; ++ext) {
4211 if (sect->id == SECT_CONTEXT) {
4212 amdgpu_ring_write(ring,
4213 PACKET3(PACKET3_SET_CONTEXT_REG,
4214 ext->reg_count));
4215 amdgpu_ring_write(ring,
4216 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4217 for (i = 0; i < ext->reg_count; i++)
4218 amdgpu_ring_write(ring, ext->extent[i]);
4219 }
4220 }
4221 }
4222
4223 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4224 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4225 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
4226 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
4227
4228 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4229 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4230
4231 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4232 amdgpu_ring_write(ring, 0);
4233
4234 /* init the CE partitions */
4235 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4236 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4237 amdgpu_ring_write(ring, 0x8000);
4238 amdgpu_ring_write(ring, 0x8000);
4239
4240 amdgpu_ring_commit(ring);
4241
4242 return 0;
4243}
4244static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring)
4245{
4246 u32 tmp;
4247 /* no gfx doorbells on iceland */
4248 if (adev->asic_type == CHIP_TOPAZ)
4249 return;
4250
4251 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4252
4253 if (ring->use_doorbell) {
4254 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4255 DOORBELL_OFFSET, ring->doorbell_index);
4256 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4257 DOORBELL_HIT, 0);
4258 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4259 DOORBELL_EN, 1);
4260 } else {
4261 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
4262 }
4263
4264 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4265
4266 if (adev->flags & AMD_IS_APU)
4267 return;
4268
4269 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4270 DOORBELL_RANGE_LOWER,
4271 adev->doorbell_index.gfx_ring0);
4272 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4273
4274 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4275 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4276}
4277
4278static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4279{
4280 struct amdgpu_ring *ring;
4281 u32 tmp;
4282 u32 rb_bufsz;
4283 u64 rb_addr, rptr_addr, wptr_gpu_addr;
4284
4285 /* Set the write pointer delay */
4286 WREG32(mmCP_RB_WPTR_DELAY, 0);
4287
4288 /* set the RB to use vmid 0 */
4289 WREG32(mmCP_RB_VMID, 0);
4290
4291 /* Set ring buffer size */
4292 ring = &adev->gfx.gfx_ring[0];
4293 rb_bufsz = order_base_2(ring->ring_size / 8);
4294 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4295 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4296 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4297 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4298#ifdef __BIG_ENDIAN
4299 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4300#endif
4301 WREG32(mmCP_RB0_CNTL, tmp);
4302
4303 /* Initialize the ring buffer's read and write pointers */
4304 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4305 ring->wptr = 0;
4306 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4307
4308 /* set the wb address wether it's enabled or not */
4309 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4310 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4311 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4312
4313 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4314 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4315 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
4316 mdelay(1);
4317 WREG32(mmCP_RB0_CNTL, tmp);
4318
4319 rb_addr = ring->gpu_addr >> 8;
4320 WREG32(mmCP_RB0_BASE, rb_addr);
4321 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4322
4323 gfx_v8_0_set_cpg_door_bell(adev, ring);
4324 /* start the ring */
4325 amdgpu_ring_clear_ring(ring);
4326 gfx_v8_0_cp_gfx_start(adev);
4327 ring->sched.ready = true;
4328
4329 return 0;
4330}
4331
4332static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4333{
4334 if (enable) {
4335 WREG32(mmCP_MEC_CNTL, 0);
4336 } else {
4337 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4338 adev->gfx.kiq.ring.sched.ready = false;
4339 }
4340 udelay(50);
4341}
4342
4343/* KIQ functions */
4344static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
4345{
4346 uint32_t tmp;
4347 struct amdgpu_device *adev = ring->adev;
4348
4349 /* tell RLC which is KIQ queue */
4350 tmp = RREG32(mmRLC_CP_SCHEDULERS);
4351 tmp &= 0xffffff00;
4352 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
4353 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4354 tmp |= 0x80;
4355 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4356}
4357
4358static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
4359{
4360 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4361 uint64_t queue_mask = 0;
4362 int r, i;
4363
4364 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
4365 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
4366 continue;
4367
4368 /* This situation may be hit in the future if a new HW
4369 * generation exposes more than 64 queues. If so, the
4370 * definition of queue_mask needs updating */
4371 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
4372 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
4373 break;
4374 }
4375
4376 queue_mask |= (1ull << i);
4377 }
4378
4379 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
4380 if (r) {
4381 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4382 return r;
4383 }
4384 /* set resources */
4385 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
4386 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
4387 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
4388 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
4389 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
4390 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
4391 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
4392 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
4393 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4394 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4395 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
4396 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4397
4398 /* map queues */
4399 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
4400 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
4401 amdgpu_ring_write(kiq_ring,
4402 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
4403 amdgpu_ring_write(kiq_ring,
4404 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) |
4405 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
4406 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
4407 PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */
4408 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
4409 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
4410 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
4411 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
4412 }
4413
4414 amdgpu_ring_commit(kiq_ring);
4415
4416 return 0;
4417}
4418
4419static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
4420{
4421 int i, r = 0;
4422
4423 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4424 WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);
4425 for (i = 0; i < adev->usec_timeout; i++) {
4426 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4427 break;
4428 udelay(1);
4429 }
4430 if (i == adev->usec_timeout)
4431 r = -ETIMEDOUT;
4432 }
4433 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
4434 WREG32(mmCP_HQD_PQ_RPTR, 0);
4435 WREG32(mmCP_HQD_PQ_WPTR, 0);
4436
4437 return r;
4438}
4439
4440static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *mqd)
4441{
4442 struct amdgpu_device *adev = ring->adev;
4443
4444 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4445 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
4446 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
4447 mqd->cp_hqd_queue_priority =
4448 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
4449 }
4450 }
4451}
4452
4453static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
4454{
4455 struct amdgpu_device *adev = ring->adev;
4456 struct vi_mqd *mqd = ring->mqd_ptr;
4457 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4458 uint32_t tmp;
4459
4460 mqd->header = 0xC0310800;
4461 mqd->compute_pipelinestat_enable = 0x00000001;
4462 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4463 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4464 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4465 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4466 mqd->compute_misc_reserved = 0x00000003;
4467 mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
4468 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4469 mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
4470 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4471 eop_base_addr = ring->eop_gpu_addr >> 8;
4472 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
4473 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
4474
4475 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4476 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4477 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4478 (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1));
4479
4480 mqd->cp_hqd_eop_control = tmp;
4481
4482 /* enable doorbell? */
4483 tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
4484 CP_HQD_PQ_DOORBELL_CONTROL,
4485 DOORBELL_EN,
4486 ring->use_doorbell ? 1 : 0);
4487
4488 mqd->cp_hqd_pq_doorbell_control = tmp;
4489
4490 /* set the pointer to the MQD */
4491 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
4492 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
4493
4494 /* set MQD vmid to 0 */
4495 tmp = RREG32(mmCP_MQD_CONTROL);
4496 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4497 mqd->cp_mqd_control = tmp;
4498
4499 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4500 hqd_gpu_addr = ring->gpu_addr >> 8;
4501 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4502 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4503
4504 /* set up the HQD, this is similar to CP_RB0_CNTL */
4505 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4507 (order_base_2(ring->ring_size / 4) - 1));
4508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4509 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4510#ifdef __BIG_ENDIAN
4511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4512#endif
4513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4514 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4515 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4516 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4517 mqd->cp_hqd_pq_control = tmp;
4518
4519 /* set the wb address whether it's enabled or not */
4520 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4521 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4522 mqd->cp_hqd_pq_rptr_report_addr_hi =
4523 upper_32_bits(wb_gpu_addr) & 0xffff;
4524
4525 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4526 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4527 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4528 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4529
4530 tmp = 0;
4531 /* enable the doorbell if requested */
4532 if (ring->use_doorbell) {
4533 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4535 DOORBELL_OFFSET, ring->doorbell_index);
4536
4537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4538 DOORBELL_EN, 1);
4539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4540 DOORBELL_SOURCE, 0);
4541 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4542 DOORBELL_HIT, 0);
4543 }
4544
4545 mqd->cp_hqd_pq_doorbell_control = tmp;
4546
4547 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4548 ring->wptr = 0;
4549 mqd->cp_hqd_pq_wptr = ring->wptr;
4550 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4551
4552 /* set the vmid for the queue */
4553 mqd->cp_hqd_vmid = 0;
4554
4555 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4556 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4557 mqd->cp_hqd_persistent_state = tmp;
4558
4559 /* set MTYPE */
4560 tmp = RREG32(mmCP_HQD_IB_CONTROL);
4561 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
4562 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
4563 mqd->cp_hqd_ib_control = tmp;
4564
4565 tmp = RREG32(mmCP_HQD_IQ_TIMER);
4566 tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
4567 mqd->cp_hqd_iq_timer = tmp;
4568
4569 tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
4570 tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
4571 mqd->cp_hqd_ctx_save_control = tmp;
4572
4573 /* defaults */
4574 mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
4575 mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
4576 mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
4577 mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
4578 mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
4579 mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
4580 mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
4581 mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
4582 mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
4583 mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
4584 mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
4585 mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
4586
4587 /* set static priority for a queue/ring */
4588 gfx_v8_0_mqd_set_priority(ring, mqd);
4589 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
4590
4591 /* map_queues packet doesn't need activate the queue,
4592 * so only kiq need set this field.
4593 */
4594 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
4595 mqd->cp_hqd_active = 1;
4596
4597 return 0;
4598}
4599
4600static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
4601 struct vi_mqd *mqd)
4602{
4603 uint32_t mqd_reg;
4604 uint32_t *mqd_data;
4605
4606 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */
4607 mqd_data = &mqd->cp_mqd_base_addr_lo;
4608
4609 /* disable wptr polling */
4610 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
4611
4612 /* program all HQD registers */
4613 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
4614 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4615
4616 /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
4617 * This is safe since EOP RPTR==WPTR for any inactive HQD
4618 * on ASICs that do not support context-save.
4619 * EOP writes/reads can start anywhere in the ring.
4620 */
4621 if (adev->asic_type != CHIP_TONGA) {
4622 WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
4623 WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
4624 WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
4625 }
4626
4627 for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
4628 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4629
4630 /* activate the HQD */
4631 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
4632 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4633
4634 return 0;
4635}
4636
4637static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
4638{
4639 struct amdgpu_device *adev = ring->adev;
4640 struct vi_mqd *mqd = ring->mqd_ptr;
4641 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
4642
4643 gfx_v8_0_kiq_setting(ring);
4644
4645 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4646 /* reset MQD to a clean status */
4647 if (adev->gfx.mec.mqd_backup[mqd_idx])
4648 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4649
4650 /* reset ring buffer */
4651 ring->wptr = 0;
4652 amdgpu_ring_clear_ring(ring);
4653 mutex_lock(&adev->srbm_mutex);
4654 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4655 gfx_v8_0_mqd_commit(adev, mqd);
4656 vi_srbm_select(adev, 0, 0, 0, 0);
4657 mutex_unlock(&adev->srbm_mutex);
4658 } else {
4659 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4660 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4661 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4662 mutex_lock(&adev->srbm_mutex);
4663 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4664 gfx_v8_0_mqd_init(ring);
4665 gfx_v8_0_mqd_commit(adev, mqd);
4666 vi_srbm_select(adev, 0, 0, 0, 0);
4667 mutex_unlock(&adev->srbm_mutex);
4668
4669 if (adev->gfx.mec.mqd_backup[mqd_idx])
4670 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4671 }
4672
4673 return 0;
4674}
4675
4676static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
4677{
4678 struct amdgpu_device *adev = ring->adev;
4679 struct vi_mqd *mqd = ring->mqd_ptr;
4680 int mqd_idx = ring - &adev->gfx.compute_ring[0];
4681
4682 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4683 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4684 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4685 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4686 mutex_lock(&adev->srbm_mutex);
4687 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4688 gfx_v8_0_mqd_init(ring);
4689 vi_srbm_select(adev, 0, 0, 0, 0);
4690 mutex_unlock(&adev->srbm_mutex);
4691
4692 if (adev->gfx.mec.mqd_backup[mqd_idx])
4693 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4694 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4695 /* reset MQD to a clean status */
4696 if (adev->gfx.mec.mqd_backup[mqd_idx])
4697 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4698 /* reset ring buffer */
4699 ring->wptr = 0;
4700 amdgpu_ring_clear_ring(ring);
4701 } else {
4702 amdgpu_ring_clear_ring(ring);
4703 }
4704 return 0;
4705}
4706
4707static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
4708{
4709 if (adev->asic_type > CHIP_TONGA) {
4710 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
4711 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
4712 }
4713 /* enable doorbells */
4714 WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4715}
4716
4717static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4718{
4719 struct amdgpu_ring *ring;
4720 int r;
4721
4722 ring = &adev->gfx.kiq.ring;
4723
4724 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4725 if (unlikely(r != 0))
4726 return r;
4727
4728 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4729 if (unlikely(r != 0))
4730 return r;
4731
4732 gfx_v8_0_kiq_init_queue(ring);
4733 amdgpu_bo_kunmap(ring->mqd_obj);
4734 ring->mqd_ptr = NULL;
4735 amdgpu_bo_unreserve(ring->mqd_obj);
4736 ring->sched.ready = true;
4737 return 0;
4738}
4739
4740static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
4741{
4742 struct amdgpu_ring *ring = NULL;
4743 int r = 0, i;
4744
4745 gfx_v8_0_cp_compute_enable(adev, true);
4746
4747 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4748 ring = &adev->gfx.compute_ring[i];
4749
4750 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4751 if (unlikely(r != 0))
4752 goto done;
4753 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4754 if (!r) {
4755 r = gfx_v8_0_kcq_init_queue(ring);
4756 amdgpu_bo_kunmap(ring->mqd_obj);
4757 ring->mqd_ptr = NULL;
4758 }
4759 amdgpu_bo_unreserve(ring->mqd_obj);
4760 if (r)
4761 goto done;
4762 }
4763
4764 gfx_v8_0_set_mec_doorbell_range(adev);
4765
4766 r = gfx_v8_0_kiq_kcq_enable(adev);
4767 if (r)
4768 goto done;
4769
4770done:
4771 return r;
4772}
4773
4774static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
4775{
4776 int r, i;
4777 struct amdgpu_ring *ring;
4778
4779 /* collect all the ring_tests here, gfx, kiq, compute */
4780 ring = &adev->gfx.gfx_ring[0];
4781 r = amdgpu_ring_test_helper(ring);
4782 if (r)
4783 return r;
4784
4785 ring = &adev->gfx.kiq.ring;
4786 r = amdgpu_ring_test_helper(ring);
4787 if (r)
4788 return r;
4789
4790 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4791 ring = &adev->gfx.compute_ring[i];
4792 amdgpu_ring_test_helper(ring);
4793 }
4794
4795 return 0;
4796}
4797
4798static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4799{
4800 int r;
4801
4802 if (!(adev->flags & AMD_IS_APU))
4803 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4804
4805 r = gfx_v8_0_kiq_resume(adev);
4806 if (r)
4807 return r;
4808
4809 r = gfx_v8_0_cp_gfx_resume(adev);
4810 if (r)
4811 return r;
4812
4813 r = gfx_v8_0_kcq_resume(adev);
4814 if (r)
4815 return r;
4816
4817 r = gfx_v8_0_cp_test_all_rings(adev);
4818 if (r)
4819 return r;
4820
4821 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4822
4823 return 0;
4824}
4825
4826static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4827{
4828 gfx_v8_0_cp_gfx_enable(adev, enable);
4829 gfx_v8_0_cp_compute_enable(adev, enable);
4830}
4831
4832static int gfx_v8_0_hw_init(void *handle)
4833{
4834 int r;
4835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4836
4837 gfx_v8_0_init_golden_registers(adev);
4838 gfx_v8_0_constants_init(adev);
4839
4840 r = adev->gfx.rlc.funcs->resume(adev);
4841 if (r)
4842 return r;
4843
4844 r = gfx_v8_0_cp_resume(adev);
4845
4846 return r;
4847}
4848
4849static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
4850{
4851 int r, i;
4852 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4853
4854 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
4855 if (r)
4856 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4857
4858 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4859 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4860
4861 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
4862 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
4863 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
4864 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
4865 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
4866 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
4867 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
4868 amdgpu_ring_write(kiq_ring, 0);
4869 amdgpu_ring_write(kiq_ring, 0);
4870 amdgpu_ring_write(kiq_ring, 0);
4871 }
4872 r = amdgpu_ring_test_helper(kiq_ring);
4873 if (r)
4874 DRM_ERROR("KCQ disable failed\n");
4875
4876 return r;
4877}
4878
4879static bool gfx_v8_0_is_idle(void *handle)
4880{
4881 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4882
4883 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
4884 || RREG32(mmGRBM_STATUS2) != 0x8)
4885 return false;
4886 else
4887 return true;
4888}
4889
4890static bool gfx_v8_0_rlc_is_idle(void *handle)
4891{
4892 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4893
4894 if (RREG32(mmGRBM_STATUS2) != 0x8)
4895 return false;
4896 else
4897 return true;
4898}
4899
4900static int gfx_v8_0_wait_for_rlc_idle(void *handle)
4901{
4902 unsigned int i;
4903 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4904
4905 for (i = 0; i < adev->usec_timeout; i++) {
4906 if (gfx_v8_0_rlc_is_idle(handle))
4907 return 0;
4908
4909 udelay(1);
4910 }
4911 return -ETIMEDOUT;
4912}
4913
4914static int gfx_v8_0_wait_for_idle(void *handle)
4915{
4916 unsigned int i;
4917 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4918
4919 for (i = 0; i < adev->usec_timeout; i++) {
4920 if (gfx_v8_0_is_idle(handle))
4921 return 0;
4922
4923 udelay(1);
4924 }
4925 return -ETIMEDOUT;
4926}
4927
4928static int gfx_v8_0_hw_fini(void *handle)
4929{
4930 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4931
4932 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4933 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4934
4935 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
4936
4937 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0);
4938
4939 /* disable KCQ to avoid CPC touch memory not valid anymore */
4940 gfx_v8_0_kcq_disable(adev);
4941
4942 if (amdgpu_sriov_vf(adev)) {
4943 pr_debug("For SRIOV client, shouldn't do anything.\n");
4944 return 0;
4945 }
4946 amdgpu_gfx_rlc_enter_safe_mode(adev);
4947 if (!gfx_v8_0_wait_for_idle(adev))
4948 gfx_v8_0_cp_enable(adev, false);
4949 else
4950 pr_err("cp is busy, skip halt cp\n");
4951 if (!gfx_v8_0_wait_for_rlc_idle(adev))
4952 adev->gfx.rlc.funcs->stop(adev);
4953 else
4954 pr_err("rlc is busy, skip halt rlc\n");
4955 amdgpu_gfx_rlc_exit_safe_mode(adev);
4956
4957 return 0;
4958}
4959
4960static int gfx_v8_0_suspend(void *handle)
4961{
4962 return gfx_v8_0_hw_fini(handle);
4963}
4964
4965static int gfx_v8_0_resume(void *handle)
4966{
4967 return gfx_v8_0_hw_init(handle);
4968}
4969
4970static bool gfx_v8_0_check_soft_reset(void *handle)
4971{
4972 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4973 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4974 u32 tmp;
4975
4976 /* GRBM_STATUS */
4977 tmp = RREG32(mmGRBM_STATUS);
4978 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4979 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4980 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4981 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4982 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4983 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK |
4984 GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4985 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4986 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4987 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4988 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4989 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4990 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4991 }
4992
4993 /* GRBM_STATUS2 */
4994 tmp = RREG32(mmGRBM_STATUS2);
4995 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4996 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4997 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4998
4999 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
5000 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
5001 REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
5002 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5003 SOFT_RESET_CPF, 1);
5004 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5005 SOFT_RESET_CPC, 1);
5006 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5007 SOFT_RESET_CPG, 1);
5008 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
5009 SOFT_RESET_GRBM, 1);
5010 }
5011
5012 /* SRBM_STATUS */
5013 tmp = RREG32(mmSRBM_STATUS);
5014 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
5015 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5016 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5017 if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
5018 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5019 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
5020
5021 if (grbm_soft_reset || srbm_soft_reset) {
5022 adev->gfx.grbm_soft_reset = grbm_soft_reset;
5023 adev->gfx.srbm_soft_reset = srbm_soft_reset;
5024 return true;
5025 } else {
5026 adev->gfx.grbm_soft_reset = 0;
5027 adev->gfx.srbm_soft_reset = 0;
5028 return false;
5029 }
5030}
5031
5032static int gfx_v8_0_pre_soft_reset(void *handle)
5033{
5034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5035 u32 grbm_soft_reset = 0;
5036
5037 if ((!adev->gfx.grbm_soft_reset) &&
5038 (!adev->gfx.srbm_soft_reset))
5039 return 0;
5040
5041 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5042
5043 /* stop the rlc */
5044 adev->gfx.rlc.funcs->stop(adev);
5045
5046 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5047 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5048 /* Disable GFX parsing/prefetching */
5049 gfx_v8_0_cp_gfx_enable(adev, false);
5050
5051 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5052 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5053 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5054 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5055 int i;
5056
5057 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5058 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5059
5060 mutex_lock(&adev->srbm_mutex);
5061 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5062 gfx_v8_0_deactivate_hqd(adev, 2);
5063 vi_srbm_select(adev, 0, 0, 0, 0);
5064 mutex_unlock(&adev->srbm_mutex);
5065 }
5066 /* Disable MEC parsing/prefetching */
5067 gfx_v8_0_cp_compute_enable(adev, false);
5068 }
5069
5070 return 0;
5071}
5072
5073static int gfx_v8_0_soft_reset(void *handle)
5074{
5075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5076 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5077 u32 tmp;
5078
5079 if ((!adev->gfx.grbm_soft_reset) &&
5080 (!adev->gfx.srbm_soft_reset))
5081 return 0;
5082
5083 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5084 srbm_soft_reset = adev->gfx.srbm_soft_reset;
5085
5086 if (grbm_soft_reset || srbm_soft_reset) {
5087 tmp = RREG32(mmGMCON_DEBUG);
5088 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
5089 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
5090 WREG32(mmGMCON_DEBUG, tmp);
5091 udelay(50);
5092 }
5093
5094 if (grbm_soft_reset) {
5095 tmp = RREG32(mmGRBM_SOFT_RESET);
5096 tmp |= grbm_soft_reset;
5097 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5098 WREG32(mmGRBM_SOFT_RESET, tmp);
5099 tmp = RREG32(mmGRBM_SOFT_RESET);
5100
5101 udelay(50);
5102
5103 tmp &= ~grbm_soft_reset;
5104 WREG32(mmGRBM_SOFT_RESET, tmp);
5105 tmp = RREG32(mmGRBM_SOFT_RESET);
5106 }
5107
5108 if (srbm_soft_reset) {
5109 tmp = RREG32(mmSRBM_SOFT_RESET);
5110 tmp |= srbm_soft_reset;
5111 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5112 WREG32(mmSRBM_SOFT_RESET, tmp);
5113 tmp = RREG32(mmSRBM_SOFT_RESET);
5114
5115 udelay(50);
5116
5117 tmp &= ~srbm_soft_reset;
5118 WREG32(mmSRBM_SOFT_RESET, tmp);
5119 tmp = RREG32(mmSRBM_SOFT_RESET);
5120 }
5121
5122 if (grbm_soft_reset || srbm_soft_reset) {
5123 tmp = RREG32(mmGMCON_DEBUG);
5124 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
5125 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
5126 WREG32(mmGMCON_DEBUG, tmp);
5127 }
5128
5129 /* Wait a little for things to settle down */
5130 udelay(50);
5131
5132 return 0;
5133}
5134
5135static int gfx_v8_0_post_soft_reset(void *handle)
5136{
5137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5138 u32 grbm_soft_reset = 0;
5139
5140 if ((!adev->gfx.grbm_soft_reset) &&
5141 (!adev->gfx.srbm_soft_reset))
5142 return 0;
5143
5144 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5145
5146 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5147 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5148 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5149 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5150 int i;
5151
5152 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5153 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5154
5155 mutex_lock(&adev->srbm_mutex);
5156 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5157 gfx_v8_0_deactivate_hqd(adev, 2);
5158 vi_srbm_select(adev, 0, 0, 0, 0);
5159 mutex_unlock(&adev->srbm_mutex);
5160 }
5161 gfx_v8_0_kiq_resume(adev);
5162 gfx_v8_0_kcq_resume(adev);
5163 }
5164
5165 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5166 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5167 gfx_v8_0_cp_gfx_resume(adev);
5168
5169 gfx_v8_0_cp_test_all_rings(adev);
5170
5171 adev->gfx.rlc.funcs->start(adev);
5172
5173 return 0;
5174}
5175
5176/**
5177 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5178 *
5179 * @adev: amdgpu_device pointer
5180 *
5181 * Fetches a GPU clock counter snapshot.
5182 * Returns the 64 bit clock counter snapshot.
5183 */
5184static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5185{
5186 uint64_t clock;
5187
5188 mutex_lock(&adev->gfx.gpu_clock_mutex);
5189 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5190 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5191 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5192 mutex_unlock(&adev->gfx.gpu_clock_mutex);
5193 return clock;
5194}
5195
5196static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5197 uint32_t vmid,
5198 uint32_t gds_base, uint32_t gds_size,
5199 uint32_t gws_base, uint32_t gws_size,
5200 uint32_t oa_base, uint32_t oa_size)
5201{
5202 /* GDS Base */
5203 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5204 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5205 WRITE_DATA_DST_SEL(0)));
5206 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5207 amdgpu_ring_write(ring, 0);
5208 amdgpu_ring_write(ring, gds_base);
5209
5210 /* GDS Size */
5211 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5212 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5213 WRITE_DATA_DST_SEL(0)));
5214 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5215 amdgpu_ring_write(ring, 0);
5216 amdgpu_ring_write(ring, gds_size);
5217
5218 /* GWS */
5219 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5220 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5221 WRITE_DATA_DST_SEL(0)));
5222 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5223 amdgpu_ring_write(ring, 0);
5224 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5225
5226 /* OA */
5227 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5228 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5229 WRITE_DATA_DST_SEL(0)));
5230 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5231 amdgpu_ring_write(ring, 0);
5232 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5233}
5234
5235static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5236{
5237 WREG32(mmSQ_IND_INDEX,
5238 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5239 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5240 (address << SQ_IND_INDEX__INDEX__SHIFT) |
5241 (SQ_IND_INDEX__FORCE_READ_MASK));
5242 return RREG32(mmSQ_IND_DATA);
5243}
5244
5245static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
5246 uint32_t wave, uint32_t thread,
5247 uint32_t regno, uint32_t num, uint32_t *out)
5248{
5249 WREG32(mmSQ_IND_INDEX,
5250 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5251 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5252 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
5253 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
5254 (SQ_IND_INDEX__FORCE_READ_MASK) |
5255 (SQ_IND_INDEX__AUTO_INCR_MASK));
5256 while (num--)
5257 *(out++) = RREG32(mmSQ_IND_DATA);
5258}
5259
5260static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5261{
5262 /* type 0 wave data */
5263 dst[(*no_fields)++] = 0;
5264 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5265 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5266 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5267 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
5268 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
5269 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
5270 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
5271 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
5272 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
5273 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
5274 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
5275 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
5276 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
5277 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
5278 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
5279 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
5280 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
5281 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
5282}
5283
5284static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
5285 uint32_t wave, uint32_t start,
5286 uint32_t size, uint32_t *dst)
5287{
5288 wave_read_regs(
5289 adev, simd, wave, 0,
5290 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
5291}
5292
5293
5294static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5295 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
5296 .select_se_sh = &gfx_v8_0_select_se_sh,
5297 .read_wave_data = &gfx_v8_0_read_wave_data,
5298 .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5299 .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
5300};
5301
5302static int gfx_v8_0_early_init(void *handle)
5303{
5304 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5305
5306 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5307 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
5308 AMDGPU_MAX_COMPUTE_RINGS);
5309 adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
5310 gfx_v8_0_set_ring_funcs(adev);
5311 gfx_v8_0_set_irq_funcs(adev);
5312 gfx_v8_0_set_gds_init(adev);
5313 gfx_v8_0_set_rlc_funcs(adev);
5314
5315 return 0;
5316}
5317
5318static int gfx_v8_0_late_init(void *handle)
5319{
5320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5321 int r;
5322
5323 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5324 if (r)
5325 return r;
5326
5327 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5328 if (r)
5329 return r;
5330
5331 /* requires IBs so do in late init after IB pool is initialized */
5332 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5333 if (r)
5334 return r;
5335
5336 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
5337 if (r) {
5338 DRM_ERROR("amdgpu_irq_get() failed to get IRQ for EDC, r: %d.\n", r);
5339 return r;
5340 }
5341
5342 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0);
5343 if (r) {
5344 DRM_ERROR(
5345 "amdgpu_irq_get() failed to get IRQ for SQ, r: %d.\n",
5346 r);
5347 return r;
5348 }
5349
5350 return 0;
5351}
5352
5353static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5354 bool enable)
5355{
5356 if ((adev->asic_type == CHIP_POLARIS11) ||
5357 (adev->asic_type == CHIP_POLARIS12) ||
5358 (adev->asic_type == CHIP_VEGAM))
5359 /* Send msg to SMU via Powerplay */
5360 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
5361
5362 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5363}
5364
5365static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5366 bool enable)
5367{
5368 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
5369}
5370
5371static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
5372 bool enable)
5373{
5374 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
5375}
5376
5377static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5378 bool enable)
5379{
5380 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
5381}
5382
5383static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5384 bool enable)
5385{
5386 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
5387
5388 /* Read any GFX register to wake up GFX. */
5389 if (!enable)
5390 RREG32(mmDB_RENDER_CONTROL);
5391}
5392
5393static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5394 bool enable)
5395{
5396 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5397 cz_enable_gfx_cg_power_gating(adev, true);
5398 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5399 cz_enable_gfx_pipeline_power_gating(adev, true);
5400 } else {
5401 cz_enable_gfx_cg_power_gating(adev, false);
5402 cz_enable_gfx_pipeline_power_gating(adev, false);
5403 }
5404}
5405
5406static int gfx_v8_0_set_powergating_state(void *handle,
5407 enum amd_powergating_state state)
5408{
5409 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5410 bool enable = (state == AMD_PG_STATE_GATE);
5411
5412 if (amdgpu_sriov_vf(adev))
5413 return 0;
5414
5415 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5416 AMD_PG_SUPPORT_RLC_SMU_HS |
5417 AMD_PG_SUPPORT_CP |
5418 AMD_PG_SUPPORT_GFX_DMG))
5419 amdgpu_gfx_rlc_enter_safe_mode(adev);
5420 switch (adev->asic_type) {
5421 case CHIP_CARRIZO:
5422 case CHIP_STONEY:
5423
5424 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
5425 cz_enable_sck_slow_down_on_power_up(adev, true);
5426 cz_enable_sck_slow_down_on_power_down(adev, true);
5427 } else {
5428 cz_enable_sck_slow_down_on_power_up(adev, false);
5429 cz_enable_sck_slow_down_on_power_down(adev, false);
5430 }
5431 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
5432 cz_enable_cp_power_gating(adev, true);
5433 else
5434 cz_enable_cp_power_gating(adev, false);
5435
5436 cz_update_gfx_cg_power_gating(adev, enable);
5437
5438 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5439 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5440 else
5441 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5442
5443 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5444 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5445 else
5446 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5447 break;
5448 case CHIP_POLARIS11:
5449 case CHIP_POLARIS12:
5450 case CHIP_VEGAM:
5451 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5452 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5453 else
5454 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5455
5456 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5457 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5458 else
5459 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5460
5461 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5462 polaris11_enable_gfx_quick_mg_power_gating(adev, true);
5463 else
5464 polaris11_enable_gfx_quick_mg_power_gating(adev, false);
5465 break;
5466 default:
5467 break;
5468 }
5469 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5470 AMD_PG_SUPPORT_RLC_SMU_HS |
5471 AMD_PG_SUPPORT_CP |
5472 AMD_PG_SUPPORT_GFX_DMG))
5473 amdgpu_gfx_rlc_exit_safe_mode(adev);
5474 return 0;
5475}
5476
5477static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags)
5478{
5479 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5480 int data;
5481
5482 if (amdgpu_sriov_vf(adev))
5483 *flags = 0;
5484
5485 /* AMD_CG_SUPPORT_GFX_MGCG */
5486 data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5487 if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
5488 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5489
5490 /* AMD_CG_SUPPORT_GFX_CGLG */
5491 data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5492 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5493 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5494
5495 /* AMD_CG_SUPPORT_GFX_CGLS */
5496 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5497 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5498
5499 /* AMD_CG_SUPPORT_GFX_CGTS */
5500 data = RREG32(mmCGTS_SM_CTRL_REG);
5501 if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK))
5502 *flags |= AMD_CG_SUPPORT_GFX_CGTS;
5503
5504 /* AMD_CG_SUPPORT_GFX_CGTS_LS */
5505 if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK))
5506 *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS;
5507
5508 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5509 data = RREG32(mmRLC_MEM_SLP_CNTL);
5510 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5511 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5512
5513 /* AMD_CG_SUPPORT_GFX_CP_LS */
5514 data = RREG32(mmCP_MEM_SLP_CNTL);
5515 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5516 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5517}
5518
5519static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
5520 uint32_t reg_addr, uint32_t cmd)
5521{
5522 uint32_t data;
5523
5524 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5525
5526 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5527 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5528
5529 data = RREG32(mmRLC_SERDES_WR_CTRL);
5530 if (adev->asic_type == CHIP_STONEY)
5531 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5532 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5533 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5534 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5535 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5536 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5537 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5538 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5539 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5540 else
5541 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5542 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5543 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5544 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5545 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5546 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5547 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5548 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5549 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5550 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5551 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5552 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
5553 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5554 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5555 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
5556
5557 WREG32(mmRLC_SERDES_WR_CTRL, data);
5558}
5559
5560#define MSG_ENTER_RLC_SAFE_MODE 1
5561#define MSG_EXIT_RLC_SAFE_MODE 0
5562#define RLC_GPR_REG2__REQ_MASK 0x00000001
5563#define RLC_GPR_REG2__REQ__SHIFT 0
5564#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5565#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5566
5567static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev)
5568{
5569 uint32_t rlc_setting;
5570
5571 rlc_setting = RREG32(mmRLC_CNTL);
5572 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
5573 return false;
5574
5575 return true;
5576}
5577
5578static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev)
5579{
5580 uint32_t data;
5581 unsigned i;
5582 data = RREG32(mmRLC_CNTL);
5583 data |= RLC_SAFE_MODE__CMD_MASK;
5584 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5585 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5586 WREG32(mmRLC_SAFE_MODE, data);
5587
5588 /* wait for RLC_SAFE_MODE */
5589 for (i = 0; i < adev->usec_timeout; i++) {
5590 if ((RREG32(mmRLC_GPM_STAT) &
5591 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5592 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5593 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5594 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5595 break;
5596 udelay(1);
5597 }
5598 for (i = 0; i < adev->usec_timeout; i++) {
5599 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5600 break;
5601 udelay(1);
5602 }
5603}
5604
5605static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev)
5606{
5607 uint32_t data;
5608 unsigned i;
5609
5610 data = RREG32(mmRLC_CNTL);
5611 data |= RLC_SAFE_MODE__CMD_MASK;
5612 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5613 WREG32(mmRLC_SAFE_MODE, data);
5614
5615 for (i = 0; i < adev->usec_timeout; i++) {
5616 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5617 break;
5618 udelay(1);
5619 }
5620}
5621
5622static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
5623{
5624 u32 data;
5625
5626 if (amdgpu_sriov_is_pp_one_vf(adev))
5627 data = RREG32_NO_KIQ(mmRLC_SPM_VMID);
5628 else
5629 data = RREG32(mmRLC_SPM_VMID);
5630
5631 data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
5632 data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
5633
5634 if (amdgpu_sriov_is_pp_one_vf(adev))
5635 WREG32_NO_KIQ(mmRLC_SPM_VMID, data);
5636 else
5637 WREG32(mmRLC_SPM_VMID, data);
5638}
5639
5640static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5641 .is_rlc_enabled = gfx_v8_0_is_rlc_enabled,
5642 .set_safe_mode = gfx_v8_0_set_safe_mode,
5643 .unset_safe_mode = gfx_v8_0_unset_safe_mode,
5644 .init = gfx_v8_0_rlc_init,
5645 .get_csb_size = gfx_v8_0_get_csb_size,
5646 .get_csb_buffer = gfx_v8_0_get_csb_buffer,
5647 .get_cp_table_num = gfx_v8_0_cp_jump_table_num,
5648 .resume = gfx_v8_0_rlc_resume,
5649 .stop = gfx_v8_0_rlc_stop,
5650 .reset = gfx_v8_0_rlc_reset,
5651 .start = gfx_v8_0_rlc_start,
5652 .update_spm_vmid = gfx_v8_0_update_spm_vmid
5653};
5654
5655static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5656 bool enable)
5657{
5658 uint32_t temp, data;
5659
5660 amdgpu_gfx_rlc_enter_safe_mode(adev);
5661
5662 /* It is disabled by HW by default */
5663 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5664 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5665 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)
5666 /* 1 - RLC memory Light sleep */
5667 WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
5668
5669 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)
5670 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
5671 }
5672
5673 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5674 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5675 if (adev->flags & AMD_IS_APU)
5676 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5677 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5678 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5679 else
5680 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5681 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5682 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5683 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5684
5685 if (temp != data)
5686 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5687
5688 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5689 gfx_v8_0_wait_for_rlc_serdes(adev);
5690
5691 /* 5 - clear mgcg override */
5692 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5693
5694 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5695 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5696 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5697 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5698 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5699 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5700 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5701 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5702 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5703 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5704 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5705 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5706 if (temp != data)
5707 WREG32(mmCGTS_SM_CTRL_REG, data);
5708 }
5709 udelay(50);
5710
5711 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5712 gfx_v8_0_wait_for_rlc_serdes(adev);
5713 } else {
5714 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5715 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5716 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5717 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5718 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5719 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5720 if (temp != data)
5721 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5722
5723 /* 2 - disable MGLS in RLC */
5724 data = RREG32(mmRLC_MEM_SLP_CNTL);
5725 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5726 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5727 WREG32(mmRLC_MEM_SLP_CNTL, data);
5728 }
5729
5730 /* 3 - disable MGLS in CP */
5731 data = RREG32(mmCP_MEM_SLP_CNTL);
5732 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5733 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5734 WREG32(mmCP_MEM_SLP_CNTL, data);
5735 }
5736
5737 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5738 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5739 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5740 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5741 if (temp != data)
5742 WREG32(mmCGTS_SM_CTRL_REG, data);
5743
5744 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5745 gfx_v8_0_wait_for_rlc_serdes(adev);
5746
5747 /* 6 - set mgcg override */
5748 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5749
5750 udelay(50);
5751
5752 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5753 gfx_v8_0_wait_for_rlc_serdes(adev);
5754 }
5755
5756 amdgpu_gfx_rlc_exit_safe_mode(adev);
5757}
5758
5759static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5760 bool enable)
5761{
5762 uint32_t temp, temp1, data, data1;
5763
5764 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5765
5766 amdgpu_gfx_rlc_enter_safe_mode(adev);
5767
5768 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5769 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5770 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5771 if (temp1 != data1)
5772 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5773
5774 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5775 gfx_v8_0_wait_for_rlc_serdes(adev);
5776
5777 /* 2 - clear cgcg override */
5778 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5779
5780 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5781 gfx_v8_0_wait_for_rlc_serdes(adev);
5782
5783 /* 3 - write cmd to set CGLS */
5784 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
5785
5786 /* 4 - enable cgcg */
5787 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5788
5789 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5790 /* enable cgls*/
5791 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5792
5793 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5794 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
5795
5796 if (temp1 != data1)
5797 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5798 } else {
5799 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5800 }
5801
5802 if (temp != data)
5803 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5804
5805 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5806 * Cmp_busy/GFX_Idle interrupts
5807 */
5808 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5809 } else {
5810 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5811 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5812
5813 /* TEST CGCG */
5814 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5815 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5816 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5817 if (temp1 != data1)
5818 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5819
5820 /* read gfx register to wake up cgcg */
5821 RREG32(mmCB_CGTT_SCLK_CTRL);
5822 RREG32(mmCB_CGTT_SCLK_CTRL);
5823 RREG32(mmCB_CGTT_SCLK_CTRL);
5824 RREG32(mmCB_CGTT_SCLK_CTRL);
5825
5826 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5827 gfx_v8_0_wait_for_rlc_serdes(adev);
5828
5829 /* write cmd to Set CGCG Overrride */
5830 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5831
5832 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5833 gfx_v8_0_wait_for_rlc_serdes(adev);
5834
5835 /* write cmd to Clear CGLS */
5836 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
5837
5838 /* disable cgcg, cgls should be disabled too. */
5839 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
5840 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
5841 if (temp != data)
5842 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5843 /* enable interrupts again for PG */
5844 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5845 }
5846
5847 gfx_v8_0_wait_for_rlc_serdes(adev);
5848
5849 amdgpu_gfx_rlc_exit_safe_mode(adev);
5850}
5851static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5852 bool enable)
5853{
5854 if (enable) {
5855 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5856 * === MGCG + MGLS + TS(CG/LS) ===
5857 */
5858 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5859 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5860 } else {
5861 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5862 * === CGCG + CGLS ===
5863 */
5864 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5865 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5866 }
5867 return 0;
5868}
5869
5870static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5871 enum amd_clockgating_state state)
5872{
5873 uint32_t msg_id, pp_state = 0;
5874 uint32_t pp_support_state = 0;
5875
5876 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5877 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5878 pp_support_state = PP_STATE_SUPPORT_LS;
5879 pp_state = PP_STATE_LS;
5880 }
5881 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5882 pp_support_state |= PP_STATE_SUPPORT_CG;
5883 pp_state |= PP_STATE_CG;
5884 }
5885 if (state == AMD_CG_STATE_UNGATE)
5886 pp_state = 0;
5887
5888 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5889 PP_BLOCK_GFX_CG,
5890 pp_support_state,
5891 pp_state);
5892 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5893 }
5894
5895 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5896 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5897 pp_support_state = PP_STATE_SUPPORT_LS;
5898 pp_state = PP_STATE_LS;
5899 }
5900
5901 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5902 pp_support_state |= PP_STATE_SUPPORT_CG;
5903 pp_state |= PP_STATE_CG;
5904 }
5905
5906 if (state == AMD_CG_STATE_UNGATE)
5907 pp_state = 0;
5908
5909 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5910 PP_BLOCK_GFX_MG,
5911 pp_support_state,
5912 pp_state);
5913 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5914 }
5915
5916 return 0;
5917}
5918
5919static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
5920 enum amd_clockgating_state state)
5921{
5922
5923 uint32_t msg_id, pp_state = 0;
5924 uint32_t pp_support_state = 0;
5925
5926 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5927 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5928 pp_support_state = PP_STATE_SUPPORT_LS;
5929 pp_state = PP_STATE_LS;
5930 }
5931 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5932 pp_support_state |= PP_STATE_SUPPORT_CG;
5933 pp_state |= PP_STATE_CG;
5934 }
5935 if (state == AMD_CG_STATE_UNGATE)
5936 pp_state = 0;
5937
5938 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5939 PP_BLOCK_GFX_CG,
5940 pp_support_state,
5941 pp_state);
5942 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5943 }
5944
5945 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
5946 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5947 pp_support_state = PP_STATE_SUPPORT_LS;
5948 pp_state = PP_STATE_LS;
5949 }
5950 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5951 pp_support_state |= PP_STATE_SUPPORT_CG;
5952 pp_state |= PP_STATE_CG;
5953 }
5954 if (state == AMD_CG_STATE_UNGATE)
5955 pp_state = 0;
5956
5957 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5958 PP_BLOCK_GFX_3D,
5959 pp_support_state,
5960 pp_state);
5961 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5962 }
5963
5964 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5965 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5966 pp_support_state = PP_STATE_SUPPORT_LS;
5967 pp_state = PP_STATE_LS;
5968 }
5969
5970 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5971 pp_support_state |= PP_STATE_SUPPORT_CG;
5972 pp_state |= PP_STATE_CG;
5973 }
5974
5975 if (state == AMD_CG_STATE_UNGATE)
5976 pp_state = 0;
5977
5978 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5979 PP_BLOCK_GFX_MG,
5980 pp_support_state,
5981 pp_state);
5982 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5983 }
5984
5985 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5986 pp_support_state = PP_STATE_SUPPORT_LS;
5987
5988 if (state == AMD_CG_STATE_UNGATE)
5989 pp_state = 0;
5990 else
5991 pp_state = PP_STATE_LS;
5992
5993 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5994 PP_BLOCK_GFX_RLC,
5995 pp_support_state,
5996 pp_state);
5997 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5998 }
5999
6000 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
6001 pp_support_state = PP_STATE_SUPPORT_LS;
6002
6003 if (state == AMD_CG_STATE_UNGATE)
6004 pp_state = 0;
6005 else
6006 pp_state = PP_STATE_LS;
6007 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
6008 PP_BLOCK_GFX_CP,
6009 pp_support_state,
6010 pp_state);
6011 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6012 }
6013
6014 return 0;
6015}
6016
6017static int gfx_v8_0_set_clockgating_state(void *handle,
6018 enum amd_clockgating_state state)
6019{
6020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6021
6022 if (amdgpu_sriov_vf(adev))
6023 return 0;
6024
6025 switch (adev->asic_type) {
6026 case CHIP_FIJI:
6027 case CHIP_CARRIZO:
6028 case CHIP_STONEY:
6029 gfx_v8_0_update_gfx_clock_gating(adev,
6030 state == AMD_CG_STATE_GATE);
6031 break;
6032 case CHIP_TONGA:
6033 gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
6034 break;
6035 case CHIP_POLARIS10:
6036 case CHIP_POLARIS11:
6037 case CHIP_POLARIS12:
6038 case CHIP_VEGAM:
6039 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
6040 break;
6041 default:
6042 break;
6043 }
6044 return 0;
6045}
6046
6047static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
6048{
6049 return ring->adev->wb.wb[ring->rptr_offs];
6050}
6051
6052static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
6053{
6054 struct amdgpu_device *adev = ring->adev;
6055
6056 if (ring->use_doorbell)
6057 /* XXX check if swapping is necessary on BE */
6058 return ring->adev->wb.wb[ring->wptr_offs];
6059 else
6060 return RREG32(mmCP_RB0_WPTR);
6061}
6062
6063static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
6064{
6065 struct amdgpu_device *adev = ring->adev;
6066
6067 if (ring->use_doorbell) {
6068 /* XXX check if swapping is necessary on BE */
6069 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6070 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6071 } else {
6072 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6073 (void)RREG32(mmCP_RB0_WPTR);
6074 }
6075}
6076
6077static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6078{
6079 u32 ref_and_mask, reg_mem_engine;
6080
6081 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ||
6082 (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) {
6083 switch (ring->me) {
6084 case 1:
6085 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6086 break;
6087 case 2:
6088 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6089 break;
6090 default:
6091 return;
6092 }
6093 reg_mem_engine = 0;
6094 } else {
6095 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6096 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
6097 }
6098
6099 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6100 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
6101 WAIT_REG_MEM_FUNCTION(3) | /* == */
6102 reg_mem_engine));
6103 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
6104 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
6105 amdgpu_ring_write(ring, ref_and_mask);
6106 amdgpu_ring_write(ring, ref_and_mask);
6107 amdgpu_ring_write(ring, 0x20); /* poll interval */
6108}
6109
6110static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6111{
6112 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6113 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6114 EVENT_INDEX(4));
6115
6116 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6117 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6118 EVENT_INDEX(0));
6119}
6120
6121static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6122 struct amdgpu_job *job,
6123 struct amdgpu_ib *ib,
6124 uint32_t flags)
6125{
6126 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6127 u32 header, control = 0;
6128
6129 if (ib->flags & AMDGPU_IB_FLAG_CE)
6130 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
6131 else
6132 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
6133
6134 control |= ib->length_dw | (vmid << 24);
6135
6136 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
6137 control |= INDIRECT_BUFFER_PRE_ENB(1);
6138
6139 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
6140 gfx_v8_0_ring_emit_de_meta(ring);
6141 }
6142
6143 amdgpu_ring_write(ring, header);
6144 amdgpu_ring_write(ring,
6145#ifdef __BIG_ENDIAN
6146 (2 << 0) |
6147#endif
6148 (ib->gpu_addr & 0xFFFFFFFC));
6149 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6150 amdgpu_ring_write(ring, control);
6151}
6152
6153static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
6154 struct amdgpu_job *job,
6155 struct amdgpu_ib *ib,
6156 uint32_t flags)
6157{
6158 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6159 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
6160
6161 /* Currently, there is a high possibility to get wave ID mismatch
6162 * between ME and GDS, leading to a hw deadlock, because ME generates
6163 * different wave IDs than the GDS expects. This situation happens
6164 * randomly when at least 5 compute pipes use GDS ordered append.
6165 * The wave IDs generated by ME are also wrong after suspend/resume.
6166 * Those are probably bugs somewhere else in the kernel driver.
6167 *
6168 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
6169 * GDS to 0 for this ring (me/pipe).
6170 */
6171 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
6172 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
6173 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
6174 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
6175 }
6176
6177 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
6178 amdgpu_ring_write(ring,
6179#ifdef __BIG_ENDIAN
6180 (2 << 0) |
6181#endif
6182 (ib->gpu_addr & 0xFFFFFFFC));
6183 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6184 amdgpu_ring_write(ring, control);
6185}
6186
6187static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
6188 u64 seq, unsigned flags)
6189{
6190 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6191 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6192
6193 /* Workaround for cache flush problems. First send a dummy EOP
6194 * event down the pipe with seq one below.
6195 */
6196 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6197 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6198 EOP_TC_ACTION_EN |
6199 EOP_TC_WB_ACTION_EN |
6200 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6201 EVENT_INDEX(5)));
6202 amdgpu_ring_write(ring, addr & 0xfffffffc);
6203 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6204 DATA_SEL(1) | INT_SEL(0));
6205 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
6206 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
6207
6208 /* Then send the real EOP event down the pipe:
6209 * EVENT_WRITE_EOP - flush caches, send int */
6210 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6211 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6212 EOP_TC_ACTION_EN |
6213 EOP_TC_WB_ACTION_EN |
6214 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6215 EVENT_INDEX(5)));
6216 amdgpu_ring_write(ring, addr & 0xfffffffc);
6217 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6218 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6219 amdgpu_ring_write(ring, lower_32_bits(seq));
6220 amdgpu_ring_write(ring, upper_32_bits(seq));
6221
6222}
6223
6224static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
6225{
6226 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6227 uint32_t seq = ring->fence_drv.sync_seq;
6228 uint64_t addr = ring->fence_drv.gpu_addr;
6229
6230 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6231 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
6232 WAIT_REG_MEM_FUNCTION(3) | /* equal */
6233 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
6234 amdgpu_ring_write(ring, addr & 0xfffffffc);
6235 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6236 amdgpu_ring_write(ring, seq);
6237 amdgpu_ring_write(ring, 0xffffffff);
6238 amdgpu_ring_write(ring, 4); /* poll interval */
6239}
6240
6241static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6242 unsigned vmid, uint64_t pd_addr)
6243{
6244 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6245
6246 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
6247
6248 /* wait for the invalidate to complete */
6249 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6250 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6251 WAIT_REG_MEM_FUNCTION(0) | /* always */
6252 WAIT_REG_MEM_ENGINE(0))); /* me */
6253 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6254 amdgpu_ring_write(ring, 0);
6255 amdgpu_ring_write(ring, 0); /* ref */
6256 amdgpu_ring_write(ring, 0); /* mask */
6257 amdgpu_ring_write(ring, 0x20); /* poll interval */
6258
6259 /* compute doesn't have PFP */
6260 if (usepfp) {
6261 /* sync PFP to ME, otherwise we might get invalid PFP reads */
6262 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6263 amdgpu_ring_write(ring, 0x0);
6264 }
6265}
6266
6267static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6268{
6269 return ring->adev->wb.wb[ring->wptr_offs];
6270}
6271
6272static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6273{
6274 struct amdgpu_device *adev = ring->adev;
6275
6276 /* XXX check if swapping is necessary on BE */
6277 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6278 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6279}
6280
6281static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6282 u64 addr, u64 seq,
6283 unsigned flags)
6284{
6285 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6286 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6287
6288 /* RELEASE_MEM - flush caches, send int */
6289 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6290 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6291 EOP_TC_ACTION_EN |
6292 EOP_TC_WB_ACTION_EN |
6293 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6294 EVENT_INDEX(5)));
6295 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6296 amdgpu_ring_write(ring, addr & 0xfffffffc);
6297 amdgpu_ring_write(ring, upper_32_bits(addr));
6298 amdgpu_ring_write(ring, lower_32_bits(seq));
6299 amdgpu_ring_write(ring, upper_32_bits(seq));
6300}
6301
6302static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
6303 u64 seq, unsigned int flags)
6304{
6305 /* we only allocate 32bit for each seq wb address */
6306 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
6307
6308 /* write fence seq to the "addr" */
6309 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6310 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6311 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
6312 amdgpu_ring_write(ring, lower_32_bits(addr));
6313 amdgpu_ring_write(ring, upper_32_bits(addr));
6314 amdgpu_ring_write(ring, lower_32_bits(seq));
6315
6316 if (flags & AMDGPU_FENCE_FLAG_INT) {
6317 /* set register to trigger INT */
6318 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6319 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6320 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
6321 amdgpu_ring_write(ring, mmCPC_INT_STATUS);
6322 amdgpu_ring_write(ring, 0);
6323 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
6324 }
6325}
6326
6327static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
6328{
6329 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6330 amdgpu_ring_write(ring, 0);
6331}
6332
6333static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6334{
6335 uint32_t dw2 = 0;
6336
6337 if (amdgpu_sriov_vf(ring->adev))
6338 gfx_v8_0_ring_emit_ce_meta(ring);
6339
6340 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6341 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6342 gfx_v8_0_ring_emit_vgt_flush(ring);
6343 /* set load_global_config & load_global_uconfig */
6344 dw2 |= 0x8001;
6345 /* set load_cs_sh_regs */
6346 dw2 |= 0x01000000;
6347 /* set load_per_context_state & load_gfx_sh_regs for GFX */
6348 dw2 |= 0x10002;
6349
6350 /* set load_ce_ram if preamble presented */
6351 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
6352 dw2 |= 0x10000000;
6353 } else {
6354 /* still load_ce_ram if this is the first time preamble presented
6355 * although there is no context switch happens.
6356 */
6357 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
6358 dw2 |= 0x10000000;
6359 }
6360
6361 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6362 amdgpu_ring_write(ring, dw2);
6363 amdgpu_ring_write(ring, 0);
6364}
6365
6366static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
6367{
6368 unsigned ret;
6369
6370 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
6371 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
6372 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
6373 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
6374 ret = ring->wptr & ring->buf_mask;
6375 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
6376 return ret;
6377}
6378
6379static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
6380{
6381 unsigned cur;
6382
6383 BUG_ON(offset > ring->buf_mask);
6384 BUG_ON(ring->ring[offset] != 0x55aa55aa);
6385
6386 cur = (ring->wptr & ring->buf_mask) - 1;
6387 if (likely(cur > offset))
6388 ring->ring[offset] = cur - offset;
6389 else
6390 ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
6391}
6392
6393static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
6394 uint32_t reg_val_offs)
6395{
6396 struct amdgpu_device *adev = ring->adev;
6397
6398 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
6399 amdgpu_ring_write(ring, 0 | /* src: register*/
6400 (5 << 8) | /* dst: memory */
6401 (1 << 20)); /* write confirm */
6402 amdgpu_ring_write(ring, reg);
6403 amdgpu_ring_write(ring, 0);
6404 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
6405 reg_val_offs * 4));
6406 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
6407 reg_val_offs * 4));
6408}
6409
6410static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6411 uint32_t val)
6412{
6413 uint32_t cmd;
6414
6415 switch (ring->funcs->type) {
6416 case AMDGPU_RING_TYPE_GFX:
6417 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
6418 break;
6419 case AMDGPU_RING_TYPE_KIQ:
6420 cmd = 1 << 16; /* no inc addr */
6421 break;
6422 default:
6423 cmd = WR_CONFIRM;
6424 break;
6425 }
6426
6427 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6428 amdgpu_ring_write(ring, cmd);
6429 amdgpu_ring_write(ring, reg);
6430 amdgpu_ring_write(ring, 0);
6431 amdgpu_ring_write(ring, val);
6432}
6433
6434static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
6435{
6436 struct amdgpu_device *adev = ring->adev;
6437 uint32_t value = 0;
6438
6439 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
6440 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
6441 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
6442 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
6443 WREG32(mmSQ_CMD, value);
6444}
6445
6446static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6447 enum amdgpu_interrupt_state state)
6448{
6449 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6450 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6451}
6452
6453static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6454 int me, int pipe,
6455 enum amdgpu_interrupt_state state)
6456{
6457 u32 mec_int_cntl, mec_int_cntl_reg;
6458
6459 /*
6460 * amdgpu controls only the first MEC. That's why this function only
6461 * handles the setting of interrupts for this specific MEC. All other
6462 * pipes' interrupts are set by amdkfd.
6463 */
6464
6465 if (me == 1) {
6466 switch (pipe) {
6467 case 0:
6468 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6469 break;
6470 case 1:
6471 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
6472 break;
6473 case 2:
6474 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
6475 break;
6476 case 3:
6477 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
6478 break;
6479 default:
6480 DRM_DEBUG("invalid pipe %d\n", pipe);
6481 return;
6482 }
6483 } else {
6484 DRM_DEBUG("invalid me %d\n", me);
6485 return;
6486 }
6487
6488 switch (state) {
6489 case AMDGPU_IRQ_STATE_DISABLE:
6490 mec_int_cntl = RREG32(mec_int_cntl_reg);
6491 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6492 WREG32(mec_int_cntl_reg, mec_int_cntl);
6493 break;
6494 case AMDGPU_IRQ_STATE_ENABLE:
6495 mec_int_cntl = RREG32(mec_int_cntl_reg);
6496 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6497 WREG32(mec_int_cntl_reg, mec_int_cntl);
6498 break;
6499 default:
6500 break;
6501 }
6502}
6503
6504static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6505 struct amdgpu_irq_src *source,
6506 unsigned type,
6507 enum amdgpu_interrupt_state state)
6508{
6509 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6510 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6511
6512 return 0;
6513}
6514
6515static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6516 struct amdgpu_irq_src *source,
6517 unsigned type,
6518 enum amdgpu_interrupt_state state)
6519{
6520 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6521 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6522
6523 return 0;
6524}
6525
6526static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6527 struct amdgpu_irq_src *src,
6528 unsigned type,
6529 enum amdgpu_interrupt_state state)
6530{
6531 switch (type) {
6532 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
6533 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6534 break;
6535 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6536 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6537 break;
6538 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6539 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6540 break;
6541 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6542 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6543 break;
6544 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6545 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6546 break;
6547 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6548 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6549 break;
6550 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6551 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6552 break;
6553 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6554 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6555 break;
6556 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6557 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6558 break;
6559 default:
6560 break;
6561 }
6562 return 0;
6563}
6564
6565static int gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device *adev,
6566 struct amdgpu_irq_src *source,
6567 unsigned int type,
6568 enum amdgpu_interrupt_state state)
6569{
6570 int enable_flag;
6571
6572 switch (state) {
6573 case AMDGPU_IRQ_STATE_DISABLE:
6574 enable_flag = 0;
6575 break;
6576
6577 case AMDGPU_IRQ_STATE_ENABLE:
6578 enable_flag = 1;
6579 break;
6580
6581 default:
6582 return -EINVAL;
6583 }
6584
6585 WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6586 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6587 WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6588 WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6589 WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6590 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6591 enable_flag);
6592 WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6593 enable_flag);
6594 WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6595 enable_flag);
6596 WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6597 enable_flag);
6598 WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6599 enable_flag);
6600 WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6601 enable_flag);
6602 WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6603 enable_flag);
6604 WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6605 enable_flag);
6606
6607 return 0;
6608}
6609
6610static int gfx_v8_0_set_sq_int_state(struct amdgpu_device *adev,
6611 struct amdgpu_irq_src *source,
6612 unsigned int type,
6613 enum amdgpu_interrupt_state state)
6614{
6615 int enable_flag;
6616
6617 switch (state) {
6618 case AMDGPU_IRQ_STATE_DISABLE:
6619 enable_flag = 1;
6620 break;
6621
6622 case AMDGPU_IRQ_STATE_ENABLE:
6623 enable_flag = 0;
6624 break;
6625
6626 default:
6627 return -EINVAL;
6628 }
6629
6630 WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,
6631 enable_flag);
6632
6633 return 0;
6634}
6635
6636static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6637 struct amdgpu_irq_src *source,
6638 struct amdgpu_iv_entry *entry)
6639{
6640 int i;
6641 u8 me_id, pipe_id, queue_id;
6642 struct amdgpu_ring *ring;
6643
6644 DRM_DEBUG("IH: CP EOP\n");
6645 me_id = (entry->ring_id & 0x0c) >> 2;
6646 pipe_id = (entry->ring_id & 0x03) >> 0;
6647 queue_id = (entry->ring_id & 0x70) >> 4;
6648
6649 switch (me_id) {
6650 case 0:
6651 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6652 break;
6653 case 1:
6654 case 2:
6655 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6656 ring = &adev->gfx.compute_ring[i];
6657 /* Per-queue interrupt is supported for MEC starting from VI.
6658 * The interrupt can only be enabled/disabled per pipe instead of per queue.
6659 */
6660 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6661 amdgpu_fence_process(ring);
6662 }
6663 break;
6664 }
6665 return 0;
6666}
6667
6668static void gfx_v8_0_fault(struct amdgpu_device *adev,
6669 struct amdgpu_iv_entry *entry)
6670{
6671 u8 me_id, pipe_id, queue_id;
6672 struct amdgpu_ring *ring;
6673 int i;
6674
6675 me_id = (entry->ring_id & 0x0c) >> 2;
6676 pipe_id = (entry->ring_id & 0x03) >> 0;
6677 queue_id = (entry->ring_id & 0x70) >> 4;
6678
6679 switch (me_id) {
6680 case 0:
6681 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
6682 break;
6683 case 1:
6684 case 2:
6685 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6686 ring = &adev->gfx.compute_ring[i];
6687 if (ring->me == me_id && ring->pipe == pipe_id &&
6688 ring->queue == queue_id)
6689 drm_sched_fault(&ring->sched);
6690 }
6691 break;
6692 }
6693}
6694
6695static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6696 struct amdgpu_irq_src *source,
6697 struct amdgpu_iv_entry *entry)
6698{
6699 DRM_ERROR("Illegal register access in command stream\n");
6700 gfx_v8_0_fault(adev, entry);
6701 return 0;
6702}
6703
6704static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6705 struct amdgpu_irq_src *source,
6706 struct amdgpu_iv_entry *entry)
6707{
6708 DRM_ERROR("Illegal instruction in command stream\n");
6709 gfx_v8_0_fault(adev, entry);
6710 return 0;
6711}
6712
6713static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev,
6714 struct amdgpu_irq_src *source,
6715 struct amdgpu_iv_entry *entry)
6716{
6717 DRM_ERROR("CP EDC/ECC error detected.");
6718 return 0;
6719}
6720
6721static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data,
6722 bool from_wq)
6723{
6724 u32 enc, se_id, sh_id, cu_id;
6725 char type[20];
6726 int sq_edc_source = -1;
6727
6728 enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
6729 se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
6730
6731 switch (enc) {
6732 case 0:
6733 DRM_INFO("SQ general purpose intr detected:"
6734 "se_id %d, immed_overflow %d, host_reg_overflow %d,"
6735 "host_cmd_overflow %d, cmd_timestamp %d,"
6736 "reg_timestamp %d, thread_trace_buff_full %d,"
6737 "wlt %d, thread_trace %d.\n",
6738 se_id,
6739 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
6740 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
6741 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
6742 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
6743 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
6744 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
6745 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
6746 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
6747 );
6748 break;
6749 case 1:
6750 case 2:
6751
6752 cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
6753 sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
6754
6755 /*
6756 * This function can be called either directly from ISR
6757 * or from BH in which case we can access SQ_EDC_INFO
6758 * instance
6759 */
6760 if (from_wq) {
6761 mutex_lock(&adev->grbm_idx_mutex);
6762 gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id);
6763
6764 sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
6765
6766 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6767 mutex_unlock(&adev->grbm_idx_mutex);
6768 }
6769
6770 if (enc == 1)
6771 sprintf(type, "instruction intr");
6772 else
6773 sprintf(type, "EDC/ECC error");
6774
6775 DRM_INFO(
6776 "SQ %s detected: "
6777 "se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d "
6778 "trap %s, sq_ed_info.source %s.\n",
6779 type, se_id, sh_id, cu_id,
6780 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
6781 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
6782 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
6783 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
6784 (sq_edc_source != -1) ? sq_edc_source_names[sq_edc_source] : "unavailable"
6785 );
6786 break;
6787 default:
6788 DRM_ERROR("SQ invalid encoding type\n.");
6789 }
6790}
6791
6792static void gfx_v8_0_sq_irq_work_func(struct work_struct *work)
6793{
6794
6795 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work);
6796 struct sq_work *sq_work = container_of(work, struct sq_work, work);
6797
6798 gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data, true);
6799}
6800
6801static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
6802 struct amdgpu_irq_src *source,
6803 struct amdgpu_iv_entry *entry)
6804{
6805 unsigned ih_data = entry->src_data[0];
6806
6807 /*
6808 * Try to submit work so SQ_EDC_INFO can be accessed from
6809 * BH. If previous work submission hasn't finished yet
6810 * just print whatever info is possible directly from the ISR.
6811 */
6812 if (work_pending(&adev->gfx.sq_work.work)) {
6813 gfx_v8_0_parse_sq_irq(adev, ih_data, false);
6814 } else {
6815 adev->gfx.sq_work.ih_data = ih_data;
6816 schedule_work(&adev->gfx.sq_work.work);
6817 }
6818
6819 return 0;
6820}
6821
6822static void gfx_v8_0_emit_mem_sync(struct amdgpu_ring *ring)
6823{
6824 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
6825 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6826 PACKET3_TC_ACTION_ENA |
6827 PACKET3_SH_KCACHE_ACTION_ENA |
6828 PACKET3_SH_ICACHE_ACTION_ENA |
6829 PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6830 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6831 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6832 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6833}
6834
6835static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
6836{
6837 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
6838 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6839 PACKET3_TC_ACTION_ENA |
6840 PACKET3_SH_KCACHE_ACTION_ENA |
6841 PACKET3_SH_ICACHE_ACTION_ENA |
6842 PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6843 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6844 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */
6845 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6846 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
6847 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6848}
6849
6850
6851/* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
6852#define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f
6853static void gfx_v8_0_emit_wave_limit_cs(struct amdgpu_ring *ring,
6854 uint32_t pipe, bool enable)
6855{
6856 uint32_t val;
6857 uint32_t wcl_cs_reg;
6858
6859 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT;
6860
6861 switch (pipe) {
6862 case 0:
6863 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0;
6864 break;
6865 case 1:
6866 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1;
6867 break;
6868 case 2:
6869 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2;
6870 break;
6871 case 3:
6872 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3;
6873 break;
6874 default:
6875 DRM_DEBUG("invalid pipe %d\n", pipe);
6876 return;
6877 }
6878
6879 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
6880
6881}
6882
6883#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
6884static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
6885{
6886 struct amdgpu_device *adev = ring->adev;
6887 uint32_t val;
6888 int i;
6889
6890 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
6891 * number of gfx waves. Setting 5 bit will make sure gfx only gets
6892 * around 25% of gpu resources.
6893 */
6894 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
6895 amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
6896
6897 /* Restrict waves for normal/low priority compute queues as well
6898 * to get best QoS for high priority compute jobs.
6899 *
6900 * amdgpu controls only 1st ME(0-3 CS pipes).
6901 */
6902 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
6903 if (i != ring->pipe)
6904 gfx_v8_0_emit_wave_limit_cs(ring, i, enable);
6905
6906 }
6907
6908}
6909
6910static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6911 .name = "gfx_v8_0",
6912 .early_init = gfx_v8_0_early_init,
6913 .late_init = gfx_v8_0_late_init,
6914 .sw_init = gfx_v8_0_sw_init,
6915 .sw_fini = gfx_v8_0_sw_fini,
6916 .hw_init = gfx_v8_0_hw_init,
6917 .hw_fini = gfx_v8_0_hw_fini,
6918 .suspend = gfx_v8_0_suspend,
6919 .resume = gfx_v8_0_resume,
6920 .is_idle = gfx_v8_0_is_idle,
6921 .wait_for_idle = gfx_v8_0_wait_for_idle,
6922 .check_soft_reset = gfx_v8_0_check_soft_reset,
6923 .pre_soft_reset = gfx_v8_0_pre_soft_reset,
6924 .soft_reset = gfx_v8_0_soft_reset,
6925 .post_soft_reset = gfx_v8_0_post_soft_reset,
6926 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6927 .set_powergating_state = gfx_v8_0_set_powergating_state,
6928 .get_clockgating_state = gfx_v8_0_get_clockgating_state,
6929};
6930
6931static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6932 .type = AMDGPU_RING_TYPE_GFX,
6933 .align_mask = 0xff,
6934 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6935 .support_64bit_ptrs = false,
6936 .get_rptr = gfx_v8_0_ring_get_rptr,
6937 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6938 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6939 .emit_frame_size = /* maximum 215dw if count 16 IBs in */
6940 5 + /* COND_EXEC */
6941 7 + /* PIPELINE_SYNC */
6942 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
6943 12 + /* FENCE for VM_FLUSH */
6944 20 + /* GDS switch */
6945 4 + /* double SWITCH_BUFFER,
6946 the first COND_EXEC jump to the place just
6947 prior to this double SWITCH_BUFFER */
6948 5 + /* COND_EXEC */
6949 7 + /* HDP_flush */
6950 4 + /* VGT_flush */
6951 14 + /* CE_META */
6952 31 + /* DE_META */
6953 3 + /* CNTX_CTRL */
6954 5 + /* HDP_INVL */
6955 12 + 12 + /* FENCE x2 */
6956 2 + /* SWITCH_BUFFER */
6957 5, /* SURFACE_SYNC */
6958 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6959 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6960 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
6961 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6962 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6963 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6964 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6965 .test_ring = gfx_v8_0_ring_test_ring,
6966 .test_ib = gfx_v8_0_ring_test_ib,
6967 .insert_nop = amdgpu_ring_insert_nop,
6968 .pad_ib = amdgpu_ring_generic_pad_ib,
6969 .emit_switch_buffer = gfx_v8_ring_emit_sb,
6970 .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
6971 .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
6972 .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
6973 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6974 .soft_recovery = gfx_v8_0_ring_soft_recovery,
6975 .emit_mem_sync = gfx_v8_0_emit_mem_sync,
6976};
6977
6978static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6979 .type = AMDGPU_RING_TYPE_COMPUTE,
6980 .align_mask = 0xff,
6981 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6982 .support_64bit_ptrs = false,
6983 .get_rptr = gfx_v8_0_ring_get_rptr,
6984 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6985 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6986 .emit_frame_size =
6987 20 + /* gfx_v8_0_ring_emit_gds_switch */
6988 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6989 5 + /* hdp_invalidate */
6990 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6991 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
6992 7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6993 7 + /* gfx_v8_0_emit_mem_sync_compute */
6994 5 + /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
6995 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */
6996 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6997 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
6998 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
6999 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
7000 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
7001 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
7002 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
7003 .test_ring = gfx_v8_0_ring_test_ring,
7004 .test_ib = gfx_v8_0_ring_test_ib,
7005 .insert_nop = amdgpu_ring_insert_nop,
7006 .pad_ib = amdgpu_ring_generic_pad_ib,
7007 .emit_wreg = gfx_v8_0_ring_emit_wreg,
7008 .emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
7009 .emit_wave_limit = gfx_v8_0_emit_wave_limit,
7010};
7011
7012static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
7013 .type = AMDGPU_RING_TYPE_KIQ,
7014 .align_mask = 0xff,
7015 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7016 .support_64bit_ptrs = false,
7017 .get_rptr = gfx_v8_0_ring_get_rptr,
7018 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
7019 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
7020 .emit_frame_size =
7021 20 + /* gfx_v8_0_ring_emit_gds_switch */
7022 7 + /* gfx_v8_0_ring_emit_hdp_flush */
7023 5 + /* hdp_invalidate */
7024 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
7025 17 + /* gfx_v8_0_ring_emit_vm_flush */
7026 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
7027 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
7028 .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
7029 .test_ring = gfx_v8_0_ring_test_ring,
7030 .insert_nop = amdgpu_ring_insert_nop,
7031 .pad_ib = amdgpu_ring_generic_pad_ib,
7032 .emit_rreg = gfx_v8_0_ring_emit_rreg,
7033 .emit_wreg = gfx_v8_0_ring_emit_wreg,
7034};
7035
7036static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
7037{
7038 int i;
7039
7040 adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq;
7041
7042 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7043 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
7044
7045 for (i = 0; i < adev->gfx.num_compute_rings; i++)
7046 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
7047}
7048
7049static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
7050 .set = gfx_v8_0_set_eop_interrupt_state,
7051 .process = gfx_v8_0_eop_irq,
7052};
7053
7054static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
7055 .set = gfx_v8_0_set_priv_reg_fault_state,
7056 .process = gfx_v8_0_priv_reg_irq,
7057};
7058
7059static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
7060 .set = gfx_v8_0_set_priv_inst_fault_state,
7061 .process = gfx_v8_0_priv_inst_irq,
7062};
7063
7064static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = {
7065 .set = gfx_v8_0_set_cp_ecc_int_state,
7066 .process = gfx_v8_0_cp_ecc_error_irq,
7067};
7068
7069static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = {
7070 .set = gfx_v8_0_set_sq_int_state,
7071 .process = gfx_v8_0_sq_irq,
7072};
7073
7074static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
7075{
7076 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
7077 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
7078
7079 adev->gfx.priv_reg_irq.num_types = 1;
7080 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
7081
7082 adev->gfx.priv_inst_irq.num_types = 1;
7083 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
7084
7085 adev->gfx.cp_ecc_error_irq.num_types = 1;
7086 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs;
7087
7088 adev->gfx.sq_irq.num_types = 1;
7089 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs;
7090}
7091
7092static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
7093{
7094 adev->gfx.rlc.funcs = &iceland_rlc_funcs;
7095}
7096
7097static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
7098{
7099 /* init asci gds info */
7100 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
7101 adev->gds.gws_size = 64;
7102 adev->gds.oa_size = 16;
7103 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
7104}
7105
7106static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
7107 u32 bitmap)
7108{
7109 u32 data;
7110
7111 if (!bitmap)
7112 return;
7113
7114 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7115 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7116
7117 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
7118}
7119
7120static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
7121{
7122 u32 data, mask;
7123
7124 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
7125 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
7126
7127 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7128
7129 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
7130}
7131
7132static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
7133{
7134 int i, j, k, counter, active_cu_number = 0;
7135 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7136 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
7137 unsigned disable_masks[4 * 2];
7138 u32 ao_cu_num;
7139
7140 memset(cu_info, 0, sizeof(*cu_info));
7141
7142 if (adev->flags & AMD_IS_APU)
7143 ao_cu_num = 2;
7144 else
7145 ao_cu_num = adev->gfx.config.max_cu_per_sh;
7146
7147 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
7148
7149 mutex_lock(&adev->grbm_idx_mutex);
7150 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7151 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7152 mask = 1;
7153 ao_bitmap = 0;
7154 counter = 0;
7155 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
7156 if (i < 4 && j < 2)
7157 gfx_v8_0_set_user_cu_inactive_bitmap(
7158 adev, disable_masks[i * 2 + j]);
7159 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
7160 cu_info->bitmap[i][j] = bitmap;
7161
7162 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7163 if (bitmap & mask) {
7164 if (counter < ao_cu_num)
7165 ao_bitmap |= mask;
7166 counter ++;
7167 }
7168 mask <<= 1;
7169 }
7170 active_cu_number += counter;
7171 if (i < 2 && j < 2)
7172 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7173 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
7174 }
7175 }
7176 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
7177 mutex_unlock(&adev->grbm_idx_mutex);
7178
7179 cu_info->number = active_cu_number;
7180 cu_info->ao_cu_mask = ao_cu_mask;
7181 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7182 cu_info->max_waves_per_simd = 10;
7183 cu_info->max_scratch_slots_per_cu = 32;
7184 cu_info->wave_front_size = 64;
7185 cu_info->lds_size = 64;
7186}
7187
7188const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
7189{
7190 .type = AMD_IP_BLOCK_TYPE_GFX,
7191 .major = 8,
7192 .minor = 0,
7193 .rev = 0,
7194 .funcs = &gfx_v8_0_ip_funcs,
7195};
7196
7197const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
7198{
7199 .type = AMD_IP_BLOCK_TYPE_GFX,
7200 .major = 8,
7201 .minor = 1,
7202 .rev = 0,
7203 .funcs = &gfx_v8_0_ip_funcs,
7204};
7205
7206static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
7207{
7208 uint64_t ce_payload_addr;
7209 int cnt_ce;
7210 union {
7211 struct vi_ce_ib_state regular;
7212 struct vi_ce_ib_state_chained_ib chained;
7213 } ce_payload = {};
7214
7215 if (ring->adev->virt.chained_ib_support) {
7216 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7217 offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
7218 cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
7219 } else {
7220 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7221 offsetof(struct vi_gfx_meta_data, ce_payload);
7222 cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
7223 }
7224
7225 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));
7226 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7227 WRITE_DATA_DST_SEL(8) |
7228 WR_CONFIRM) |
7229 WRITE_DATA_CACHE_POLICY(0));
7230 amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));
7231 amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));
7232 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
7233}
7234
7235static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
7236{
7237 uint64_t de_payload_addr, gds_addr, csa_addr;
7238 int cnt_de;
7239 union {
7240 struct vi_de_ib_state regular;
7241 struct vi_de_ib_state_chained_ib chained;
7242 } de_payload = {};
7243
7244 csa_addr = amdgpu_csa_vaddr(ring->adev);
7245 gds_addr = csa_addr + 4096;
7246 if (ring->adev->virt.chained_ib_support) {
7247 de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
7248 de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);
7249 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload);
7250 cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2;
7251 } else {
7252 de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);
7253 de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);
7254 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload);
7255 cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2;
7256 }
7257
7258 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));
7259 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7260 WRITE_DATA_DST_SEL(8) |
7261 WR_CONFIRM) |
7262 WRITE_DATA_CACHE_POLICY(0));
7263 amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));
7264 amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));
7265 amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2);
7266}
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "vi.h"
28#include "vid.h"
29#include "amdgpu_ucode.h"
30#include "clearstate_vi.h"
31
32#include "gmc/gmc_8_2_d.h"
33#include "gmc/gmc_8_2_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "bif/bif_5_0_d.h"
39#include "bif/bif_5_0_sh_mask.h"
40
41#include "gca/gfx_8_0_d.h"
42#include "gca/gfx_8_0_enum.h"
43#include "gca/gfx_8_0_sh_mask.h"
44#include "gca/gfx_8_0_enum.h"
45
46#include "dce/dce_10_0_d.h"
47#include "dce/dce_10_0_sh_mask.h"
48
49#define GFX8_NUM_GFX_RINGS 1
50#define GFX8_NUM_COMPUTE_RINGS 8
51
52#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
53#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
54#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
55
56#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
57#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
58#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
59#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
60#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
61#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
62#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
63#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
64#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
65
66#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
67#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
68#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
69#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
70#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
71#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
72
73/* BPM SERDES CMD */
74#define SET_BPM_SERDES_CMD 1
75#define CLE_BPM_SERDES_CMD 0
76
77/* BPM Register Address*/
78enum {
79 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
80 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
81 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
82 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
83 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
84 BPM_REG_FGCG_MAX
85};
86
87MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
88MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
89MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
90MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
91MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
92MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
93
94MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
95MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
96MODULE_FIRMWARE("amdgpu/stoney_me.bin");
97MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
98MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
99
100MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
101MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
102MODULE_FIRMWARE("amdgpu/tonga_me.bin");
103MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
104MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
105MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
106
107MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
108MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
109MODULE_FIRMWARE("amdgpu/topaz_me.bin");
110MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
111MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
112
113MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
114MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
115MODULE_FIRMWARE("amdgpu/fiji_me.bin");
116MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
117MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
118MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
119
120static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
121{
122 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
123 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
124 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
125 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
126 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
127 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
128 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
129 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
130 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
131 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
132 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
133 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
134 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
135 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
136 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
137 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
138};
139
140static const u32 golden_settings_tonga_a11[] =
141{
142 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
143 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
144 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
145 mmGB_GPU_ID, 0x0000000f, 0x00000000,
146 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
147 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
148 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
149 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
150 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
151 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
152 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
153 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
154 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
155 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
156 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
157};
158
159static const u32 tonga_golden_common_all[] =
160{
161 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
162 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
163 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
164 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
165 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
166 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
167 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
168 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
169};
170
171static const u32 tonga_mgcg_cgcg_init[] =
172{
173 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
174 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
175 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
176 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
177 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
178 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
179 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
180 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
181 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
182 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
183 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
184 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
185 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
186 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
187 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
188 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
189 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
190 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
191 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
192 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
193 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
194 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
195 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
196 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
197 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
198 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
199 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
200 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
201 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
202 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
203 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
204 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
205 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
206 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
207 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
208 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
209 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
210 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
211 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
212 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
213 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
214 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
215 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
216 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
217 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
218 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
219 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
220 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
221 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
222 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
223 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
224 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
225 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
226 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
227 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
228 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
229 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
230 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
231 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
232 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
233 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
234 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
235 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
236 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
237 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
238 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
239 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
240 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
241 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
242 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
243 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
244 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
245 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
246 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
247 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
248};
249
250static const u32 fiji_golden_common_all[] =
251{
252 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
253 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
254 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
255 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
256 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
257 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
258 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
259 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
260 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
261 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
262};
263
264static const u32 golden_settings_fiji_a10[] =
265{
266 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
267 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
268 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
269 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
270 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
271 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
272 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
273 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
274 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
275 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
276 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
277};
278
279static const u32 fiji_mgcg_cgcg_init[] =
280{
281 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
282 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
283 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
284 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
285 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
286 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
287 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
288 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
289 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
290 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
291 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
292 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
293 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
294 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
295 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
296 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
297 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
298 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
299 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
300 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
301 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
302 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
303 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
304 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
305 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
306 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
307 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
308 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
309 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
310 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
311 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
312 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
313 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
314 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
315 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
316};
317
318static const u32 golden_settings_iceland_a11[] =
319{
320 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
321 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
322 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
323 mmGB_GPU_ID, 0x0000000f, 0x00000000,
324 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
325 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
326 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
327 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
328 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
329 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
330 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
331 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
332 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
333 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
334 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
335};
336
337static const u32 iceland_golden_common_all[] =
338{
339 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
340 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
341 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
342 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
343 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
344 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
345 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
346 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
347};
348
349static const u32 iceland_mgcg_cgcg_init[] =
350{
351 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
352 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
353 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
354 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
355 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
356 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
357 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
358 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
359 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
360 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
361 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
362 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
363 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
364 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
365 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
366 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
367 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
368 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
369 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
370 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
371 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
372 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
373 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
374 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
375 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
376 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
377 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
378 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
379 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
380 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
381 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
382 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
383 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
384 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
385 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
386 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
387 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
388 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
389 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
390 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
391 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
392 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
393 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
394 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
395 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
396 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
397 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
398 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
399 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
400 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
401 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
402 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
403 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
404 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
405 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
406 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
407 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
408 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
409 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
410 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
411 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
412 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
413 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
414 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
415};
416
417static const u32 cz_golden_settings_a11[] =
418{
419 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
420 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421 mmGB_GPU_ID, 0x0000000f, 0x00000000,
422 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
423 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
424 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
426 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
427 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
428 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
429};
430
431static const u32 cz_golden_common_all[] =
432{
433 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
434 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
435 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
436 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
437 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
438 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
439 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
440 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
441};
442
443static const u32 cz_mgcg_cgcg_init[] =
444{
445 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
446 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
447 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
452 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
453 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
454 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
455 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
456 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
458 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
459 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
460 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
461 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
462 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
463 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
464 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
465 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
466 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
467 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
468 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
469 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
470 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
471 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
472 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
473 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
474 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
475 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
476 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
477 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
478 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
479 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
480 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
481 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
482 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
483 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
484 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
485 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
486 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
487 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
488 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
489 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
490 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
491 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
492 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
493 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
494 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
495 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
496 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
497 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
498 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
499 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
500 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
501 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
502 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
503 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
504 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
505 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
506 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
507 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
508 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
509 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
510 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
511 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
512 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
513 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
514 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
515 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
516 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
517 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
518 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
519 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
520};
521
522static const u32 stoney_golden_settings_a11[] =
523{
524 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
525 mmGB_GPU_ID, 0x0000000f, 0x00000000,
526 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
527 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
528 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
529 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
530 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
531 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
532 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
533 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
534};
535
536static const u32 stoney_golden_common_all[] =
537{
538 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
539 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
540 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
541 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
542 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
543 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
544 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
545 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
546};
547
548static const u32 stoney_mgcg_cgcg_init[] =
549{
550 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
551 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
552 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
553 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
554 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
555 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
556};
557
558static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
559static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
560static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
561
562static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
563{
564 switch (adev->asic_type) {
565 case CHIP_TOPAZ:
566 amdgpu_program_register_sequence(adev,
567 iceland_mgcg_cgcg_init,
568 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
569 amdgpu_program_register_sequence(adev,
570 golden_settings_iceland_a11,
571 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
572 amdgpu_program_register_sequence(adev,
573 iceland_golden_common_all,
574 (const u32)ARRAY_SIZE(iceland_golden_common_all));
575 break;
576 case CHIP_FIJI:
577 amdgpu_program_register_sequence(adev,
578 fiji_mgcg_cgcg_init,
579 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
580 amdgpu_program_register_sequence(adev,
581 golden_settings_fiji_a10,
582 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
583 amdgpu_program_register_sequence(adev,
584 fiji_golden_common_all,
585 (const u32)ARRAY_SIZE(fiji_golden_common_all));
586 break;
587
588 case CHIP_TONGA:
589 amdgpu_program_register_sequence(adev,
590 tonga_mgcg_cgcg_init,
591 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
592 amdgpu_program_register_sequence(adev,
593 golden_settings_tonga_a11,
594 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
595 amdgpu_program_register_sequence(adev,
596 tonga_golden_common_all,
597 (const u32)ARRAY_SIZE(tonga_golden_common_all));
598 break;
599 case CHIP_CARRIZO:
600 amdgpu_program_register_sequence(adev,
601 cz_mgcg_cgcg_init,
602 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
603 amdgpu_program_register_sequence(adev,
604 cz_golden_settings_a11,
605 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
606 amdgpu_program_register_sequence(adev,
607 cz_golden_common_all,
608 (const u32)ARRAY_SIZE(cz_golden_common_all));
609 break;
610 case CHIP_STONEY:
611 amdgpu_program_register_sequence(adev,
612 stoney_mgcg_cgcg_init,
613 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
614 amdgpu_program_register_sequence(adev,
615 stoney_golden_settings_a11,
616 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
617 amdgpu_program_register_sequence(adev,
618 stoney_golden_common_all,
619 (const u32)ARRAY_SIZE(stoney_golden_common_all));
620 break;
621 default:
622 break;
623 }
624}
625
626static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
627{
628 int i;
629
630 adev->gfx.scratch.num_reg = 7;
631 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
632 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
633 adev->gfx.scratch.free[i] = true;
634 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
635 }
636}
637
638static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
639{
640 struct amdgpu_device *adev = ring->adev;
641 uint32_t scratch;
642 uint32_t tmp = 0;
643 unsigned i;
644 int r;
645
646 r = amdgpu_gfx_scratch_get(adev, &scratch);
647 if (r) {
648 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
649 return r;
650 }
651 WREG32(scratch, 0xCAFEDEAD);
652 r = amdgpu_ring_alloc(ring, 3);
653 if (r) {
654 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
655 ring->idx, r);
656 amdgpu_gfx_scratch_free(adev, scratch);
657 return r;
658 }
659 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
660 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
661 amdgpu_ring_write(ring, 0xDEADBEEF);
662 amdgpu_ring_commit(ring);
663
664 for (i = 0; i < adev->usec_timeout; i++) {
665 tmp = RREG32(scratch);
666 if (tmp == 0xDEADBEEF)
667 break;
668 DRM_UDELAY(1);
669 }
670 if (i < adev->usec_timeout) {
671 DRM_INFO("ring test on %d succeeded in %d usecs\n",
672 ring->idx, i);
673 } else {
674 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
675 ring->idx, scratch, tmp);
676 r = -EINVAL;
677 }
678 amdgpu_gfx_scratch_free(adev, scratch);
679 return r;
680}
681
682static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
683{
684 struct amdgpu_device *adev = ring->adev;
685 struct amdgpu_ib ib;
686 struct fence *f = NULL;
687 uint32_t scratch;
688 uint32_t tmp = 0;
689 unsigned i;
690 int r;
691
692 r = amdgpu_gfx_scratch_get(adev, &scratch);
693 if (r) {
694 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
695 return r;
696 }
697 WREG32(scratch, 0xCAFEDEAD);
698 memset(&ib, 0, sizeof(ib));
699 r = amdgpu_ib_get(adev, NULL, 256, &ib);
700 if (r) {
701 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
702 goto err1;
703 }
704 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
705 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
706 ib.ptr[2] = 0xDEADBEEF;
707 ib.length_dw = 3;
708
709 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
710 if (r)
711 goto err2;
712
713 r = fence_wait(f, false);
714 if (r) {
715 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
716 goto err2;
717 }
718 for (i = 0; i < adev->usec_timeout; i++) {
719 tmp = RREG32(scratch);
720 if (tmp == 0xDEADBEEF)
721 break;
722 DRM_UDELAY(1);
723 }
724 if (i < adev->usec_timeout) {
725 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
726 ring->idx, i);
727 goto err2;
728 } else {
729 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
730 scratch, tmp);
731 r = -EINVAL;
732 }
733err2:
734 fence_put(f);
735 amdgpu_ib_free(adev, &ib, NULL);
736 fence_put(f);
737err1:
738 amdgpu_gfx_scratch_free(adev, scratch);
739 return r;
740}
741
742static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
743{
744 const char *chip_name;
745 char fw_name[30];
746 int err;
747 struct amdgpu_firmware_info *info = NULL;
748 const struct common_firmware_header *header = NULL;
749 const struct gfx_firmware_header_v1_0 *cp_hdr;
750
751 DRM_DEBUG("\n");
752
753 switch (adev->asic_type) {
754 case CHIP_TOPAZ:
755 chip_name = "topaz";
756 break;
757 case CHIP_TONGA:
758 chip_name = "tonga";
759 break;
760 case CHIP_CARRIZO:
761 chip_name = "carrizo";
762 break;
763 case CHIP_FIJI:
764 chip_name = "fiji";
765 break;
766 case CHIP_STONEY:
767 chip_name = "stoney";
768 break;
769 default:
770 BUG();
771 }
772
773 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
774 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
775 if (err)
776 goto out;
777 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
778 if (err)
779 goto out;
780 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
781 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
782 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
783
784 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
785 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
786 if (err)
787 goto out;
788 err = amdgpu_ucode_validate(adev->gfx.me_fw);
789 if (err)
790 goto out;
791 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
792 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
793 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
794
795 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
796 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
797 if (err)
798 goto out;
799 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
800 if (err)
801 goto out;
802 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
803 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
804 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
805
806 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
807 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
808 if (err)
809 goto out;
810 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
811 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
812 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
813 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
814
815 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
816 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
817 if (err)
818 goto out;
819 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
820 if (err)
821 goto out;
822 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
823 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
824 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
825
826 if ((adev->asic_type != CHIP_STONEY) &&
827 (adev->asic_type != CHIP_TOPAZ)) {
828 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
829 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
830 if (!err) {
831 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
832 if (err)
833 goto out;
834 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
835 adev->gfx.mec2_fw->data;
836 adev->gfx.mec2_fw_version =
837 le32_to_cpu(cp_hdr->header.ucode_version);
838 adev->gfx.mec2_feature_version =
839 le32_to_cpu(cp_hdr->ucode_feature_version);
840 } else {
841 err = 0;
842 adev->gfx.mec2_fw = NULL;
843 }
844 }
845
846 if (adev->firmware.smu_load) {
847 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
848 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
849 info->fw = adev->gfx.pfp_fw;
850 header = (const struct common_firmware_header *)info->fw->data;
851 adev->firmware.fw_size +=
852 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
853
854 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
855 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
856 info->fw = adev->gfx.me_fw;
857 header = (const struct common_firmware_header *)info->fw->data;
858 adev->firmware.fw_size +=
859 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
860
861 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
862 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
863 info->fw = adev->gfx.ce_fw;
864 header = (const struct common_firmware_header *)info->fw->data;
865 adev->firmware.fw_size +=
866 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
867
868 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
869 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
870 info->fw = adev->gfx.rlc_fw;
871 header = (const struct common_firmware_header *)info->fw->data;
872 adev->firmware.fw_size +=
873 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
874
875 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
876 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
877 info->fw = adev->gfx.mec_fw;
878 header = (const struct common_firmware_header *)info->fw->data;
879 adev->firmware.fw_size +=
880 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
881
882 if (adev->gfx.mec2_fw) {
883 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
884 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
885 info->fw = adev->gfx.mec2_fw;
886 header = (const struct common_firmware_header *)info->fw->data;
887 adev->firmware.fw_size +=
888 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
889 }
890
891 }
892
893out:
894 if (err) {
895 dev_err(adev->dev,
896 "gfx8: Failed to load firmware \"%s\"\n",
897 fw_name);
898 release_firmware(adev->gfx.pfp_fw);
899 adev->gfx.pfp_fw = NULL;
900 release_firmware(adev->gfx.me_fw);
901 adev->gfx.me_fw = NULL;
902 release_firmware(adev->gfx.ce_fw);
903 adev->gfx.ce_fw = NULL;
904 release_firmware(adev->gfx.rlc_fw);
905 adev->gfx.rlc_fw = NULL;
906 release_firmware(adev->gfx.mec_fw);
907 adev->gfx.mec_fw = NULL;
908 release_firmware(adev->gfx.mec2_fw);
909 adev->gfx.mec2_fw = NULL;
910 }
911 return err;
912}
913
914static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
915{
916 int r;
917
918 if (adev->gfx.mec.hpd_eop_obj) {
919 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
920 if (unlikely(r != 0))
921 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
922 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
923 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
924
925 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
926 adev->gfx.mec.hpd_eop_obj = NULL;
927 }
928}
929
930#define MEC_HPD_SIZE 2048
931
932static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
933{
934 int r;
935 u32 *hpd;
936
937 /*
938 * we assign only 1 pipe because all other pipes will
939 * be handled by KFD
940 */
941 adev->gfx.mec.num_mec = 1;
942 adev->gfx.mec.num_pipe = 1;
943 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
944
945 if (adev->gfx.mec.hpd_eop_obj == NULL) {
946 r = amdgpu_bo_create(adev,
947 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
948 PAGE_SIZE, true,
949 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
950 &adev->gfx.mec.hpd_eop_obj);
951 if (r) {
952 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
953 return r;
954 }
955 }
956
957 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
958 if (unlikely(r != 0)) {
959 gfx_v8_0_mec_fini(adev);
960 return r;
961 }
962 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
963 &adev->gfx.mec.hpd_eop_gpu_addr);
964 if (r) {
965 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
966 gfx_v8_0_mec_fini(adev);
967 return r;
968 }
969 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
970 if (r) {
971 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
972 gfx_v8_0_mec_fini(adev);
973 return r;
974 }
975
976 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
977
978 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
979 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
980
981 return 0;
982}
983
984static const u32 vgpr_init_compute_shader[] =
985{
986 0x7e000209, 0x7e020208,
987 0x7e040207, 0x7e060206,
988 0x7e080205, 0x7e0a0204,
989 0x7e0c0203, 0x7e0e0202,
990 0x7e100201, 0x7e120200,
991 0x7e140209, 0x7e160208,
992 0x7e180207, 0x7e1a0206,
993 0x7e1c0205, 0x7e1e0204,
994 0x7e200203, 0x7e220202,
995 0x7e240201, 0x7e260200,
996 0x7e280209, 0x7e2a0208,
997 0x7e2c0207, 0x7e2e0206,
998 0x7e300205, 0x7e320204,
999 0x7e340203, 0x7e360202,
1000 0x7e380201, 0x7e3a0200,
1001 0x7e3c0209, 0x7e3e0208,
1002 0x7e400207, 0x7e420206,
1003 0x7e440205, 0x7e460204,
1004 0x7e480203, 0x7e4a0202,
1005 0x7e4c0201, 0x7e4e0200,
1006 0x7e500209, 0x7e520208,
1007 0x7e540207, 0x7e560206,
1008 0x7e580205, 0x7e5a0204,
1009 0x7e5c0203, 0x7e5e0202,
1010 0x7e600201, 0x7e620200,
1011 0x7e640209, 0x7e660208,
1012 0x7e680207, 0x7e6a0206,
1013 0x7e6c0205, 0x7e6e0204,
1014 0x7e700203, 0x7e720202,
1015 0x7e740201, 0x7e760200,
1016 0x7e780209, 0x7e7a0208,
1017 0x7e7c0207, 0x7e7e0206,
1018 0xbf8a0000, 0xbf810000,
1019};
1020
1021static const u32 sgpr_init_compute_shader[] =
1022{
1023 0xbe8a0100, 0xbe8c0102,
1024 0xbe8e0104, 0xbe900106,
1025 0xbe920108, 0xbe940100,
1026 0xbe960102, 0xbe980104,
1027 0xbe9a0106, 0xbe9c0108,
1028 0xbe9e0100, 0xbea00102,
1029 0xbea20104, 0xbea40106,
1030 0xbea60108, 0xbea80100,
1031 0xbeaa0102, 0xbeac0104,
1032 0xbeae0106, 0xbeb00108,
1033 0xbeb20100, 0xbeb40102,
1034 0xbeb60104, 0xbeb80106,
1035 0xbeba0108, 0xbebc0100,
1036 0xbebe0102, 0xbec00104,
1037 0xbec20106, 0xbec40108,
1038 0xbec60100, 0xbec80102,
1039 0xbee60004, 0xbee70005,
1040 0xbeea0006, 0xbeeb0007,
1041 0xbee80008, 0xbee90009,
1042 0xbefc0000, 0xbf8a0000,
1043 0xbf810000, 0x00000000,
1044};
1045
1046static const u32 vgpr_init_regs[] =
1047{
1048 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1049 mmCOMPUTE_RESOURCE_LIMITS, 0,
1050 mmCOMPUTE_NUM_THREAD_X, 256*4,
1051 mmCOMPUTE_NUM_THREAD_Y, 1,
1052 mmCOMPUTE_NUM_THREAD_Z, 1,
1053 mmCOMPUTE_PGM_RSRC2, 20,
1054 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1055 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1056 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1057 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1058 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1059 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1060 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1061 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1062 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1063 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1064};
1065
1066static const u32 sgpr1_init_regs[] =
1067{
1068 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1069 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1070 mmCOMPUTE_NUM_THREAD_X, 256*5,
1071 mmCOMPUTE_NUM_THREAD_Y, 1,
1072 mmCOMPUTE_NUM_THREAD_Z, 1,
1073 mmCOMPUTE_PGM_RSRC2, 20,
1074 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1075 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1076 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1077 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1078 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1079 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1080 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1081 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1082 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1083 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1084};
1085
1086static const u32 sgpr2_init_regs[] =
1087{
1088 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1089 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1090 mmCOMPUTE_NUM_THREAD_X, 256*5,
1091 mmCOMPUTE_NUM_THREAD_Y, 1,
1092 mmCOMPUTE_NUM_THREAD_Z, 1,
1093 mmCOMPUTE_PGM_RSRC2, 20,
1094 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1095 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1096 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1097 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1098 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1099 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1100 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1101 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1102 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1103 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1104};
1105
1106static const u32 sec_ded_counter_registers[] =
1107{
1108 mmCPC_EDC_ATC_CNT,
1109 mmCPC_EDC_SCRATCH_CNT,
1110 mmCPC_EDC_UCODE_CNT,
1111 mmCPF_EDC_ATC_CNT,
1112 mmCPF_EDC_ROQ_CNT,
1113 mmCPF_EDC_TAG_CNT,
1114 mmCPG_EDC_ATC_CNT,
1115 mmCPG_EDC_DMA_CNT,
1116 mmCPG_EDC_TAG_CNT,
1117 mmDC_EDC_CSINVOC_CNT,
1118 mmDC_EDC_RESTORE_CNT,
1119 mmDC_EDC_STATE_CNT,
1120 mmGDS_EDC_CNT,
1121 mmGDS_EDC_GRBM_CNT,
1122 mmGDS_EDC_OA_DED,
1123 mmSPI_EDC_CNT,
1124 mmSQC_ATC_EDC_GATCL1_CNT,
1125 mmSQC_EDC_CNT,
1126 mmSQ_EDC_DED_CNT,
1127 mmSQ_EDC_INFO,
1128 mmSQ_EDC_SEC_CNT,
1129 mmTCC_EDC_CNT,
1130 mmTCP_ATC_EDC_GATCL1_CNT,
1131 mmTCP_EDC_CNT,
1132 mmTD_EDC_CNT
1133};
1134
1135static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1136{
1137 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1138 struct amdgpu_ib ib;
1139 struct fence *f = NULL;
1140 int r, i;
1141 u32 tmp;
1142 unsigned total_size, vgpr_offset, sgpr_offset;
1143 u64 gpu_addr;
1144
1145 /* only supported on CZ */
1146 if (adev->asic_type != CHIP_CARRIZO)
1147 return 0;
1148
1149 /* bail if the compute ring is not ready */
1150 if (!ring->ready)
1151 return 0;
1152
1153 tmp = RREG32(mmGB_EDC_MODE);
1154 WREG32(mmGB_EDC_MODE, 0);
1155
1156 total_size =
1157 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1158 total_size +=
1159 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1160 total_size +=
1161 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1162 total_size = ALIGN(total_size, 256);
1163 vgpr_offset = total_size;
1164 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1165 sgpr_offset = total_size;
1166 total_size += sizeof(sgpr_init_compute_shader);
1167
1168 /* allocate an indirect buffer to put the commands in */
1169 memset(&ib, 0, sizeof(ib));
1170 r = amdgpu_ib_get(adev, NULL, total_size, &ib);
1171 if (r) {
1172 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1173 return r;
1174 }
1175
1176 /* load the compute shaders */
1177 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1178 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1179
1180 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1181 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1182
1183 /* init the ib length to 0 */
1184 ib.length_dw = 0;
1185
1186 /* VGPR */
1187 /* write the register state for the compute dispatch */
1188 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1189 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1190 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1191 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1192 }
1193 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1194 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1195 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1196 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1197 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1198 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1199
1200 /* write dispatch packet */
1201 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1202 ib.ptr[ib.length_dw++] = 8; /* x */
1203 ib.ptr[ib.length_dw++] = 1; /* y */
1204 ib.ptr[ib.length_dw++] = 1; /* z */
1205 ib.ptr[ib.length_dw++] =
1206 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1207
1208 /* write CS partial flush packet */
1209 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1210 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1211
1212 /* SGPR1 */
1213 /* write the register state for the compute dispatch */
1214 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1215 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1216 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1217 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1218 }
1219 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1220 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1221 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1222 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1223 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1224 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1225
1226 /* write dispatch packet */
1227 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1228 ib.ptr[ib.length_dw++] = 8; /* x */
1229 ib.ptr[ib.length_dw++] = 1; /* y */
1230 ib.ptr[ib.length_dw++] = 1; /* z */
1231 ib.ptr[ib.length_dw++] =
1232 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1233
1234 /* write CS partial flush packet */
1235 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1236 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1237
1238 /* SGPR2 */
1239 /* write the register state for the compute dispatch */
1240 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1241 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1242 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1243 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1244 }
1245 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1246 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1247 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1248 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1249 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1250 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1251
1252 /* write dispatch packet */
1253 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1254 ib.ptr[ib.length_dw++] = 8; /* x */
1255 ib.ptr[ib.length_dw++] = 1; /* y */
1256 ib.ptr[ib.length_dw++] = 1; /* z */
1257 ib.ptr[ib.length_dw++] =
1258 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1259
1260 /* write CS partial flush packet */
1261 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1262 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1263
1264 /* shedule the ib on the ring */
1265 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1266 if (r) {
1267 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1268 goto fail;
1269 }
1270
1271 /* wait for the GPU to finish processing the IB */
1272 r = fence_wait(f, false);
1273 if (r) {
1274 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1275 goto fail;
1276 }
1277
1278 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1279 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1280 WREG32(mmGB_EDC_MODE, tmp);
1281
1282 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1283 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1284 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1285
1286
1287 /* read back registers to clear the counters */
1288 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1289 RREG32(sec_ded_counter_registers[i]);
1290
1291fail:
1292 fence_put(f);
1293 amdgpu_ib_free(adev, &ib, NULL);
1294 fence_put(f);
1295
1296 return r;
1297}
1298
1299static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1300{
1301 u32 gb_addr_config;
1302 u32 mc_shared_chmap, mc_arb_ramcfg;
1303 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1304 u32 tmp;
1305
1306 switch (adev->asic_type) {
1307 case CHIP_TOPAZ:
1308 adev->gfx.config.max_shader_engines = 1;
1309 adev->gfx.config.max_tile_pipes = 2;
1310 adev->gfx.config.max_cu_per_sh = 6;
1311 adev->gfx.config.max_sh_per_se = 1;
1312 adev->gfx.config.max_backends_per_se = 2;
1313 adev->gfx.config.max_texture_channel_caches = 2;
1314 adev->gfx.config.max_gprs = 256;
1315 adev->gfx.config.max_gs_threads = 32;
1316 adev->gfx.config.max_hw_contexts = 8;
1317
1318 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1319 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1320 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1321 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1322 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1323 break;
1324 case CHIP_FIJI:
1325 adev->gfx.config.max_shader_engines = 4;
1326 adev->gfx.config.max_tile_pipes = 16;
1327 adev->gfx.config.max_cu_per_sh = 16;
1328 adev->gfx.config.max_sh_per_se = 1;
1329 adev->gfx.config.max_backends_per_se = 4;
1330 adev->gfx.config.max_texture_channel_caches = 16;
1331 adev->gfx.config.max_gprs = 256;
1332 adev->gfx.config.max_gs_threads = 32;
1333 adev->gfx.config.max_hw_contexts = 8;
1334
1335 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1336 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1337 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1338 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1339 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1340 break;
1341 case CHIP_TONGA:
1342 adev->gfx.config.max_shader_engines = 4;
1343 adev->gfx.config.max_tile_pipes = 8;
1344 adev->gfx.config.max_cu_per_sh = 8;
1345 adev->gfx.config.max_sh_per_se = 1;
1346 adev->gfx.config.max_backends_per_se = 2;
1347 adev->gfx.config.max_texture_channel_caches = 8;
1348 adev->gfx.config.max_gprs = 256;
1349 adev->gfx.config.max_gs_threads = 32;
1350 adev->gfx.config.max_hw_contexts = 8;
1351
1352 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1353 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1354 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1355 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1356 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1357 break;
1358 case CHIP_CARRIZO:
1359 adev->gfx.config.max_shader_engines = 1;
1360 adev->gfx.config.max_tile_pipes = 2;
1361 adev->gfx.config.max_sh_per_se = 1;
1362 adev->gfx.config.max_backends_per_se = 2;
1363
1364 switch (adev->pdev->revision) {
1365 case 0xc4:
1366 case 0x84:
1367 case 0xc8:
1368 case 0xcc:
1369 case 0xe1:
1370 case 0xe3:
1371 /* B10 */
1372 adev->gfx.config.max_cu_per_sh = 8;
1373 break;
1374 case 0xc5:
1375 case 0x81:
1376 case 0x85:
1377 case 0xc9:
1378 case 0xcd:
1379 case 0xe2:
1380 case 0xe4:
1381 /* B8 */
1382 adev->gfx.config.max_cu_per_sh = 6;
1383 break;
1384 case 0xc6:
1385 case 0xca:
1386 case 0xce:
1387 case 0x88:
1388 /* B6 */
1389 adev->gfx.config.max_cu_per_sh = 6;
1390 break;
1391 case 0xc7:
1392 case 0x87:
1393 case 0xcb:
1394 case 0xe5:
1395 case 0x89:
1396 default:
1397 /* B4 */
1398 adev->gfx.config.max_cu_per_sh = 4;
1399 break;
1400 }
1401
1402 adev->gfx.config.max_texture_channel_caches = 2;
1403 adev->gfx.config.max_gprs = 256;
1404 adev->gfx.config.max_gs_threads = 32;
1405 adev->gfx.config.max_hw_contexts = 8;
1406
1407 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1408 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1409 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1410 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1411 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1412 break;
1413 case CHIP_STONEY:
1414 adev->gfx.config.max_shader_engines = 1;
1415 adev->gfx.config.max_tile_pipes = 2;
1416 adev->gfx.config.max_sh_per_se = 1;
1417 adev->gfx.config.max_backends_per_se = 1;
1418
1419 switch (adev->pdev->revision) {
1420 case 0xc0:
1421 case 0xc1:
1422 case 0xc2:
1423 case 0xc4:
1424 case 0xc8:
1425 case 0xc9:
1426 adev->gfx.config.max_cu_per_sh = 3;
1427 break;
1428 case 0xd0:
1429 case 0xd1:
1430 case 0xd2:
1431 default:
1432 adev->gfx.config.max_cu_per_sh = 2;
1433 break;
1434 }
1435
1436 adev->gfx.config.max_texture_channel_caches = 2;
1437 adev->gfx.config.max_gprs = 256;
1438 adev->gfx.config.max_gs_threads = 16;
1439 adev->gfx.config.max_hw_contexts = 8;
1440
1441 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1442 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1443 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1444 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1445 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1446 break;
1447 default:
1448 adev->gfx.config.max_shader_engines = 2;
1449 adev->gfx.config.max_tile_pipes = 4;
1450 adev->gfx.config.max_cu_per_sh = 2;
1451 adev->gfx.config.max_sh_per_se = 1;
1452 adev->gfx.config.max_backends_per_se = 2;
1453 adev->gfx.config.max_texture_channel_caches = 4;
1454 adev->gfx.config.max_gprs = 256;
1455 adev->gfx.config.max_gs_threads = 32;
1456 adev->gfx.config.max_hw_contexts = 8;
1457
1458 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1459 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1460 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1461 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1462 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1463 break;
1464 }
1465
1466 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1467 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1468 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1469
1470 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1471 adev->gfx.config.mem_max_burst_length_bytes = 256;
1472 if (adev->flags & AMD_IS_APU) {
1473 /* Get memory bank mapping mode. */
1474 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1475 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1476 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1477
1478 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1479 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1480 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1481
1482 /* Validate settings in case only one DIMM installed. */
1483 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1484 dimm00_addr_map = 0;
1485 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1486 dimm01_addr_map = 0;
1487 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1488 dimm10_addr_map = 0;
1489 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1490 dimm11_addr_map = 0;
1491
1492 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1493 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1494 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1495 adev->gfx.config.mem_row_size_in_kb = 2;
1496 else
1497 adev->gfx.config.mem_row_size_in_kb = 1;
1498 } else {
1499 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1500 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1501 if (adev->gfx.config.mem_row_size_in_kb > 4)
1502 adev->gfx.config.mem_row_size_in_kb = 4;
1503 }
1504
1505 adev->gfx.config.shader_engine_tile_size = 32;
1506 adev->gfx.config.num_gpus = 1;
1507 adev->gfx.config.multi_gpu_tile_size = 64;
1508
1509 /* fix up row size */
1510 switch (adev->gfx.config.mem_row_size_in_kb) {
1511 case 1:
1512 default:
1513 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1514 break;
1515 case 2:
1516 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1517 break;
1518 case 4:
1519 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1520 break;
1521 }
1522 adev->gfx.config.gb_addr_config = gb_addr_config;
1523}
1524
1525static int gfx_v8_0_sw_init(void *handle)
1526{
1527 int i, r;
1528 struct amdgpu_ring *ring;
1529 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1530
1531 /* EOP Event */
1532 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1533 if (r)
1534 return r;
1535
1536 /* Privileged reg */
1537 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1538 if (r)
1539 return r;
1540
1541 /* Privileged inst */
1542 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
1543 if (r)
1544 return r;
1545
1546 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1547
1548 gfx_v8_0_scratch_init(adev);
1549
1550 r = gfx_v8_0_init_microcode(adev);
1551 if (r) {
1552 DRM_ERROR("Failed to load gfx firmware!\n");
1553 return r;
1554 }
1555
1556 r = gfx_v8_0_mec_init(adev);
1557 if (r) {
1558 DRM_ERROR("Failed to init MEC BOs!\n");
1559 return r;
1560 }
1561
1562 /* set up the gfx ring */
1563 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1564 ring = &adev->gfx.gfx_ring[i];
1565 ring->ring_obj = NULL;
1566 sprintf(ring->name, "gfx");
1567 /* no gfx doorbells on iceland */
1568 if (adev->asic_type != CHIP_TOPAZ) {
1569 ring->use_doorbell = true;
1570 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
1571 }
1572
1573 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1574 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1575 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
1576 AMDGPU_RING_TYPE_GFX);
1577 if (r)
1578 return r;
1579 }
1580
1581 /* set up the compute queues */
1582 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1583 unsigned irq_type;
1584
1585 /* max 32 queues per MEC */
1586 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1587 DRM_ERROR("Too many (%d) compute rings!\n", i);
1588 break;
1589 }
1590 ring = &adev->gfx.compute_ring[i];
1591 ring->ring_obj = NULL;
1592 ring->use_doorbell = true;
1593 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
1594 ring->me = 1; /* first MEC */
1595 ring->pipe = i / 8;
1596 ring->queue = i % 8;
1597 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1598 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1599 /* type-2 packets are deprecated on MEC, use type-3 instead */
1600 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1601 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1602 &adev->gfx.eop_irq, irq_type,
1603 AMDGPU_RING_TYPE_COMPUTE);
1604 if (r)
1605 return r;
1606 }
1607
1608 /* reserve GDS, GWS and OA resource for gfx */
1609 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
1610 PAGE_SIZE, true,
1611 AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
1612 NULL, &adev->gds.gds_gfx_bo);
1613 if (r)
1614 return r;
1615
1616 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1617 PAGE_SIZE, true,
1618 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
1619 NULL, &adev->gds.gws_gfx_bo);
1620 if (r)
1621 return r;
1622
1623 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1624 PAGE_SIZE, true,
1625 AMDGPU_GEM_DOMAIN_OA, 0, NULL,
1626 NULL, &adev->gds.oa_gfx_bo);
1627 if (r)
1628 return r;
1629
1630 adev->gfx.ce_ram_size = 0x8000;
1631
1632 gfx_v8_0_gpu_early_init(adev);
1633
1634 return 0;
1635}
1636
1637static int gfx_v8_0_sw_fini(void *handle)
1638{
1639 int i;
1640 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1641
1642 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1643 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1644 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1645
1646 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1647 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1648 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1649 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1650
1651 gfx_v8_0_mec_fini(adev);
1652
1653 return 0;
1654}
1655
1656static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1657{
1658 uint32_t *modearray, *mod2array;
1659 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1660 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1661 u32 reg_offset;
1662
1663 modearray = adev->gfx.config.tile_mode_array;
1664 mod2array = adev->gfx.config.macrotile_mode_array;
1665
1666 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1667 modearray[reg_offset] = 0;
1668
1669 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1670 mod2array[reg_offset] = 0;
1671
1672 switch (adev->asic_type) {
1673 case CHIP_TOPAZ:
1674 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1675 PIPE_CONFIG(ADDR_SURF_P2) |
1676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1677 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1678 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1679 PIPE_CONFIG(ADDR_SURF_P2) |
1680 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1681 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1682 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1683 PIPE_CONFIG(ADDR_SURF_P2) |
1684 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1685 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1686 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1687 PIPE_CONFIG(ADDR_SURF_P2) |
1688 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1689 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1690 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1691 PIPE_CONFIG(ADDR_SURF_P2) |
1692 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1693 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1694 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1695 PIPE_CONFIG(ADDR_SURF_P2) |
1696 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1697 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1698 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1699 PIPE_CONFIG(ADDR_SURF_P2) |
1700 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1701 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1702 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1703 PIPE_CONFIG(ADDR_SURF_P2));
1704 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1705 PIPE_CONFIG(ADDR_SURF_P2) |
1706 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1707 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1708 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1709 PIPE_CONFIG(ADDR_SURF_P2) |
1710 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1711 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1712 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1713 PIPE_CONFIG(ADDR_SURF_P2) |
1714 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1715 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1716 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1717 PIPE_CONFIG(ADDR_SURF_P2) |
1718 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1719 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1720 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1721 PIPE_CONFIG(ADDR_SURF_P2) |
1722 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1723 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1724 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1725 PIPE_CONFIG(ADDR_SURF_P2) |
1726 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1727 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1728 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1729 PIPE_CONFIG(ADDR_SURF_P2) |
1730 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1731 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1732 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1733 PIPE_CONFIG(ADDR_SURF_P2) |
1734 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1735 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1736 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1737 PIPE_CONFIG(ADDR_SURF_P2) |
1738 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1739 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1740 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1741 PIPE_CONFIG(ADDR_SURF_P2) |
1742 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1743 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1744 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1745 PIPE_CONFIG(ADDR_SURF_P2) |
1746 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1747 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1748 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1749 PIPE_CONFIG(ADDR_SURF_P2) |
1750 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1751 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1752 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1753 PIPE_CONFIG(ADDR_SURF_P2) |
1754 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1755 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1756 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1757 PIPE_CONFIG(ADDR_SURF_P2) |
1758 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1759 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1760 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1761 PIPE_CONFIG(ADDR_SURF_P2) |
1762 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1763 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1764 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1765 PIPE_CONFIG(ADDR_SURF_P2) |
1766 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1767 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1768 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1769 PIPE_CONFIG(ADDR_SURF_P2) |
1770 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1771 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1772 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1773 PIPE_CONFIG(ADDR_SURF_P2) |
1774 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1775 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1776
1777 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1778 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1779 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1780 NUM_BANKS(ADDR_SURF_8_BANK));
1781 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1782 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1783 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1784 NUM_BANKS(ADDR_SURF_8_BANK));
1785 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1786 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1787 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1788 NUM_BANKS(ADDR_SURF_8_BANK));
1789 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1790 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1791 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1792 NUM_BANKS(ADDR_SURF_8_BANK));
1793 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1796 NUM_BANKS(ADDR_SURF_8_BANK));
1797 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1800 NUM_BANKS(ADDR_SURF_8_BANK));
1801 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1802 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1803 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1804 NUM_BANKS(ADDR_SURF_8_BANK));
1805 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1808 NUM_BANKS(ADDR_SURF_16_BANK));
1809 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1810 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1811 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1812 NUM_BANKS(ADDR_SURF_16_BANK));
1813 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1816 NUM_BANKS(ADDR_SURF_16_BANK));
1817 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1820 NUM_BANKS(ADDR_SURF_16_BANK));
1821 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1824 NUM_BANKS(ADDR_SURF_16_BANK));
1825 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1828 NUM_BANKS(ADDR_SURF_16_BANK));
1829 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1830 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1831 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1832 NUM_BANKS(ADDR_SURF_8_BANK));
1833
1834 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1835 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
1836 reg_offset != 23)
1837 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
1838
1839 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1840 if (reg_offset != 7)
1841 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
1842
1843 break;
1844 case CHIP_FIJI:
1845 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1846 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1848 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1849 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1850 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1851 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1852 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1853 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1854 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1855 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1856 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1857 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1858 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1859 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1860 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1861 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1862 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1863 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1864 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1865 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1866 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1867 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1868 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1869 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1870 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1871 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1872 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1873 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1874 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1875 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1876 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1877 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1878 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1879 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1880 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1881 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1882 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1883 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1884 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1885 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1886 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1887 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1888 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1889 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1890 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1891 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1892 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1893 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1894 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1895 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1896 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1897 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1898 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1899 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1900 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1901 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1902 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1903 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1904 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1905 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1906 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1907 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1908 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1909 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1910 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1911 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1912 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1913 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1914 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1915 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1916 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1917 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1918 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1919 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1920 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1921 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1922 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1923 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1924 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1925 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1926 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1927 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1928 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1929 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1930 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1931 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1932 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1933 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1934 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1935 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1936 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1937 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1938 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1939 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1940 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1941 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1942 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1943 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1944 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1945 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1946 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1947 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1948 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1949 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1950 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1951 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1952 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1953 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1954 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1955 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1956 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1957 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1958 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1959 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1960 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1961 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1962 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1963 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1964 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1965 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1966 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1967
1968 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1971 NUM_BANKS(ADDR_SURF_8_BANK));
1972 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1973 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1974 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1975 NUM_BANKS(ADDR_SURF_8_BANK));
1976 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1977 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1978 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1979 NUM_BANKS(ADDR_SURF_8_BANK));
1980 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1983 NUM_BANKS(ADDR_SURF_8_BANK));
1984 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1985 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1986 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1987 NUM_BANKS(ADDR_SURF_8_BANK));
1988 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1991 NUM_BANKS(ADDR_SURF_8_BANK));
1992 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1993 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1994 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1995 NUM_BANKS(ADDR_SURF_8_BANK));
1996 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1999 NUM_BANKS(ADDR_SURF_8_BANK));
2000 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2003 NUM_BANKS(ADDR_SURF_8_BANK));
2004 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2005 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2006 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2007 NUM_BANKS(ADDR_SURF_8_BANK));
2008 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2009 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2010 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2011 NUM_BANKS(ADDR_SURF_8_BANK));
2012 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2013 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2014 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2015 NUM_BANKS(ADDR_SURF_8_BANK));
2016 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2017 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2018 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2019 NUM_BANKS(ADDR_SURF_8_BANK));
2020 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2023 NUM_BANKS(ADDR_SURF_4_BANK));
2024
2025 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2026 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2027
2028 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2029 if (reg_offset != 7)
2030 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2031
2032 break;
2033 case CHIP_TONGA:
2034 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2035 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2037 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2038 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2039 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2040 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2041 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2042 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2043 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2044 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2045 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2046 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2047 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2049 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2050 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2051 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2052 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2053 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2054 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2055 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2056 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2057 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2058 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2059 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2060 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2061 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2062 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2063 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2064 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2065 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2066 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2067 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2068 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2069 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2070 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2071 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2072 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2073 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2074 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2075 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2076 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2077 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2078 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2079 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2080 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2081 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2082 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2083 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2084 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2085 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2086 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2087 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2088 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2089 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2090 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2091 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2092 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2093 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2094 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2095 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2096 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2097 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2098 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2099 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2100 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2101 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2102 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2103 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2104 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2105 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2106 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2107 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2108 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2109 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2110 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2111 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2112 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2113 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2114 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2115 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2116 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2117 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2118 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2119 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2120 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2121 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2122 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2123 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2124 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2125 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2126 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2127 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2128 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2129 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2130 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2131 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2132 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2133 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2134 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2135 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2136 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2137 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2138 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2139 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2140 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2141 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2142 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2143 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2144 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2145 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2146 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2147 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2148 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2149 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2150 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2151 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2152 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2153 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2154 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2155 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2156
2157 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2160 NUM_BANKS(ADDR_SURF_16_BANK));
2161 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2164 NUM_BANKS(ADDR_SURF_16_BANK));
2165 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2166 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2167 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2168 NUM_BANKS(ADDR_SURF_16_BANK));
2169 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2172 NUM_BANKS(ADDR_SURF_16_BANK));
2173 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2174 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2175 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2176 NUM_BANKS(ADDR_SURF_16_BANK));
2177 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2178 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2179 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2180 NUM_BANKS(ADDR_SURF_16_BANK));
2181 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2182 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2183 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2184 NUM_BANKS(ADDR_SURF_16_BANK));
2185 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2186 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2187 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2188 NUM_BANKS(ADDR_SURF_16_BANK));
2189 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2190 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2191 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2192 NUM_BANKS(ADDR_SURF_16_BANK));
2193 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2194 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2195 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2196 NUM_BANKS(ADDR_SURF_16_BANK));
2197 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2200 NUM_BANKS(ADDR_SURF_16_BANK));
2201 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2202 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2203 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2204 NUM_BANKS(ADDR_SURF_8_BANK));
2205 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2208 NUM_BANKS(ADDR_SURF_4_BANK));
2209 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2212 NUM_BANKS(ADDR_SURF_4_BANK));
2213
2214 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2215 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2216
2217 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2218 if (reg_offset != 7)
2219 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2220
2221 break;
2222 case CHIP_STONEY:
2223 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2224 PIPE_CONFIG(ADDR_SURF_P2) |
2225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2227 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2228 PIPE_CONFIG(ADDR_SURF_P2) |
2229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2231 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2232 PIPE_CONFIG(ADDR_SURF_P2) |
2233 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2235 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2236 PIPE_CONFIG(ADDR_SURF_P2) |
2237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2239 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2240 PIPE_CONFIG(ADDR_SURF_P2) |
2241 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2243 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2244 PIPE_CONFIG(ADDR_SURF_P2) |
2245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2247 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2248 PIPE_CONFIG(ADDR_SURF_P2) |
2249 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2251 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2252 PIPE_CONFIG(ADDR_SURF_P2));
2253 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2254 PIPE_CONFIG(ADDR_SURF_P2) |
2255 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2256 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2257 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2258 PIPE_CONFIG(ADDR_SURF_P2) |
2259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2261 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2262 PIPE_CONFIG(ADDR_SURF_P2) |
2263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2265 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2266 PIPE_CONFIG(ADDR_SURF_P2) |
2267 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2269 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2270 PIPE_CONFIG(ADDR_SURF_P2) |
2271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2272 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2273 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2274 PIPE_CONFIG(ADDR_SURF_P2) |
2275 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2276 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2277 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2278 PIPE_CONFIG(ADDR_SURF_P2) |
2279 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2280 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2281 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2282 PIPE_CONFIG(ADDR_SURF_P2) |
2283 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2284 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2285 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2286 PIPE_CONFIG(ADDR_SURF_P2) |
2287 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2288 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2289 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2290 PIPE_CONFIG(ADDR_SURF_P2) |
2291 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2292 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2293 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2294 PIPE_CONFIG(ADDR_SURF_P2) |
2295 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2296 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2297 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2298 PIPE_CONFIG(ADDR_SURF_P2) |
2299 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2300 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2301 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2302 PIPE_CONFIG(ADDR_SURF_P2) |
2303 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2304 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2305 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2306 PIPE_CONFIG(ADDR_SURF_P2) |
2307 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2308 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2309 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2310 PIPE_CONFIG(ADDR_SURF_P2) |
2311 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2312 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2313 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2314 PIPE_CONFIG(ADDR_SURF_P2) |
2315 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2316 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2317 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2318 PIPE_CONFIG(ADDR_SURF_P2) |
2319 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2320 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2321 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2322 PIPE_CONFIG(ADDR_SURF_P2) |
2323 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2324 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2325
2326 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2327 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2328 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2329 NUM_BANKS(ADDR_SURF_8_BANK));
2330 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2331 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2332 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2333 NUM_BANKS(ADDR_SURF_8_BANK));
2334 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2335 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2336 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2337 NUM_BANKS(ADDR_SURF_8_BANK));
2338 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2339 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2340 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2341 NUM_BANKS(ADDR_SURF_8_BANK));
2342 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2343 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2344 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2345 NUM_BANKS(ADDR_SURF_8_BANK));
2346 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2349 NUM_BANKS(ADDR_SURF_8_BANK));
2350 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2351 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2352 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2353 NUM_BANKS(ADDR_SURF_8_BANK));
2354 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2355 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2356 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2357 NUM_BANKS(ADDR_SURF_16_BANK));
2358 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2359 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2360 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2361 NUM_BANKS(ADDR_SURF_16_BANK));
2362 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2363 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2364 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2365 NUM_BANKS(ADDR_SURF_16_BANK));
2366 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2367 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2368 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2369 NUM_BANKS(ADDR_SURF_16_BANK));
2370 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2371 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2372 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2373 NUM_BANKS(ADDR_SURF_16_BANK));
2374 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2375 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2376 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2377 NUM_BANKS(ADDR_SURF_16_BANK));
2378 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2379 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2380 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2381 NUM_BANKS(ADDR_SURF_8_BANK));
2382
2383 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2384 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2385 reg_offset != 23)
2386 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2387
2388 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2389 if (reg_offset != 7)
2390 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2391
2392 break;
2393 default:
2394 dev_warn(adev->dev,
2395 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
2396 adev->asic_type);
2397
2398 case CHIP_CARRIZO:
2399 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2400 PIPE_CONFIG(ADDR_SURF_P2) |
2401 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2403 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2404 PIPE_CONFIG(ADDR_SURF_P2) |
2405 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2407 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2408 PIPE_CONFIG(ADDR_SURF_P2) |
2409 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2410 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2411 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2412 PIPE_CONFIG(ADDR_SURF_P2) |
2413 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2414 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2415 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2416 PIPE_CONFIG(ADDR_SURF_P2) |
2417 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2418 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2419 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2420 PIPE_CONFIG(ADDR_SURF_P2) |
2421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2423 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2424 PIPE_CONFIG(ADDR_SURF_P2) |
2425 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2426 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2427 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2428 PIPE_CONFIG(ADDR_SURF_P2));
2429 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2430 PIPE_CONFIG(ADDR_SURF_P2) |
2431 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2432 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2433 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2434 PIPE_CONFIG(ADDR_SURF_P2) |
2435 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2436 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2437 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2438 PIPE_CONFIG(ADDR_SURF_P2) |
2439 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2440 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2441 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2442 PIPE_CONFIG(ADDR_SURF_P2) |
2443 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2444 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2445 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2446 PIPE_CONFIG(ADDR_SURF_P2) |
2447 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2448 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2449 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2450 PIPE_CONFIG(ADDR_SURF_P2) |
2451 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2452 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2453 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2454 PIPE_CONFIG(ADDR_SURF_P2) |
2455 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2456 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2457 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2458 PIPE_CONFIG(ADDR_SURF_P2) |
2459 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2460 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2461 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2462 PIPE_CONFIG(ADDR_SURF_P2) |
2463 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2464 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2465 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2466 PIPE_CONFIG(ADDR_SURF_P2) |
2467 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2468 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2469 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2470 PIPE_CONFIG(ADDR_SURF_P2) |
2471 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2472 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2473 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2474 PIPE_CONFIG(ADDR_SURF_P2) |
2475 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2476 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2477 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2478 PIPE_CONFIG(ADDR_SURF_P2) |
2479 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2480 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2481 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2482 PIPE_CONFIG(ADDR_SURF_P2) |
2483 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2484 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2485 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2486 PIPE_CONFIG(ADDR_SURF_P2) |
2487 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2488 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2489 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2490 PIPE_CONFIG(ADDR_SURF_P2) |
2491 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2492 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2493 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2494 PIPE_CONFIG(ADDR_SURF_P2) |
2495 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2496 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2497 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2498 PIPE_CONFIG(ADDR_SURF_P2) |
2499 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2500 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2501
2502 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2505 NUM_BANKS(ADDR_SURF_8_BANK));
2506 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2509 NUM_BANKS(ADDR_SURF_8_BANK));
2510 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2513 NUM_BANKS(ADDR_SURF_8_BANK));
2514 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2517 NUM_BANKS(ADDR_SURF_8_BANK));
2518 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2521 NUM_BANKS(ADDR_SURF_8_BANK));
2522 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2523 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2524 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2525 NUM_BANKS(ADDR_SURF_8_BANK));
2526 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2529 NUM_BANKS(ADDR_SURF_8_BANK));
2530 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2531 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2532 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2533 NUM_BANKS(ADDR_SURF_16_BANK));
2534 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2537 NUM_BANKS(ADDR_SURF_16_BANK));
2538 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2541 NUM_BANKS(ADDR_SURF_16_BANK));
2542 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2543 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2544 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2545 NUM_BANKS(ADDR_SURF_16_BANK));
2546 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2547 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2548 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2549 NUM_BANKS(ADDR_SURF_16_BANK));
2550 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2553 NUM_BANKS(ADDR_SURF_16_BANK));
2554 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2555 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2556 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2557 NUM_BANKS(ADDR_SURF_8_BANK));
2558
2559 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2560 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2561 reg_offset != 23)
2562 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2563
2564 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2565 if (reg_offset != 7)
2566 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2567
2568 break;
2569 }
2570}
2571
2572void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
2573{
2574 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2575
2576 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
2577 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2578 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2579 } else if (se_num == 0xffffffff) {
2580 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2581 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2582 } else if (sh_num == 0xffffffff) {
2583 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2584 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2585 } else {
2586 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2587 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2588 }
2589 WREG32(mmGRBM_GFX_INDEX, data);
2590}
2591
2592static u32 gfx_v8_0_create_bitmask(u32 bit_width)
2593{
2594 return (u32)((1ULL << bit_width) - 1);
2595}
2596
2597static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
2598{
2599 u32 data, mask;
2600
2601 data = RREG32(mmCC_RB_BACKEND_DISABLE);
2602 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
2603
2604 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
2605 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2606
2607 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
2608 adev->gfx.config.max_sh_per_se);
2609
2610 return (~data) & mask;
2611}
2612
2613static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
2614{
2615 int i, j;
2616 u32 data;
2617 u32 active_rbs = 0;
2618 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
2619 adev->gfx.config.max_sh_per_se;
2620
2621 mutex_lock(&adev->grbm_idx_mutex);
2622 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2623 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2624 gfx_v8_0_select_se_sh(adev, i, j);
2625 data = gfx_v8_0_get_rb_active_bitmap(adev);
2626 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
2627 rb_bitmap_width_per_sh);
2628 }
2629 }
2630 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2631 mutex_unlock(&adev->grbm_idx_mutex);
2632
2633 adev->gfx.config.backend_enable_mask = active_rbs;
2634 adev->gfx.config.num_rbs = hweight32(active_rbs);
2635}
2636
2637/**
2638 * gfx_v8_0_init_compute_vmid - gart enable
2639 *
2640 * @rdev: amdgpu_device pointer
2641 *
2642 * Initialize compute vmid sh_mem registers
2643 *
2644 */
2645#define DEFAULT_SH_MEM_BASES (0x6000)
2646#define FIRST_COMPUTE_VMID (8)
2647#define LAST_COMPUTE_VMID (16)
2648static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2649{
2650 int i;
2651 uint32_t sh_mem_config;
2652 uint32_t sh_mem_bases;
2653
2654 /*
2655 * Configure apertures:
2656 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
2657 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
2658 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
2659 */
2660 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2661
2662 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2663 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2664 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2665 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2666 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2667 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2668
2669 mutex_lock(&adev->srbm_mutex);
2670 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2671 vi_srbm_select(adev, 0, 0, 0, i);
2672 /* CP and shaders */
2673 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2674 WREG32(mmSH_MEM_APE1_BASE, 1);
2675 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2676 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2677 }
2678 vi_srbm_select(adev, 0, 0, 0, 0);
2679 mutex_unlock(&adev->srbm_mutex);
2680}
2681
2682static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2683{
2684 u32 tmp;
2685 int i;
2686
2687 tmp = RREG32(mmGRBM_CNTL);
2688 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2689 WREG32(mmGRBM_CNTL, tmp);
2690
2691 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2692 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2693 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
2694
2695 gfx_v8_0_tiling_mode_table_init(adev);
2696
2697 gfx_v8_0_setup_rb(adev);
2698
2699 /* XXX SH_MEM regs */
2700 /* where to put LDS, scratch, GPUVM in FSA64 space */
2701 mutex_lock(&adev->srbm_mutex);
2702 for (i = 0; i < 16; i++) {
2703 vi_srbm_select(adev, 0, 0, 0, i);
2704 /* CP and shaders */
2705 if (i == 0) {
2706 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2707 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2708 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2709 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2710 WREG32(mmSH_MEM_CONFIG, tmp);
2711 } else {
2712 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2713 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2714 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2715 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2716 WREG32(mmSH_MEM_CONFIG, tmp);
2717 }
2718
2719 WREG32(mmSH_MEM_APE1_BASE, 1);
2720 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2721 WREG32(mmSH_MEM_BASES, 0);
2722 }
2723 vi_srbm_select(adev, 0, 0, 0, 0);
2724 mutex_unlock(&adev->srbm_mutex);
2725
2726 gfx_v8_0_init_compute_vmid(adev);
2727
2728 mutex_lock(&adev->grbm_idx_mutex);
2729 /*
2730 * making sure that the following register writes will be broadcasted
2731 * to all the shaders
2732 */
2733 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2734
2735 WREG32(mmPA_SC_FIFO_SIZE,
2736 (adev->gfx.config.sc_prim_fifo_size_frontend <<
2737 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2738 (adev->gfx.config.sc_prim_fifo_size_backend <<
2739 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2740 (adev->gfx.config.sc_hiz_tile_fifo_size <<
2741 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2742 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2743 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2744 mutex_unlock(&adev->grbm_idx_mutex);
2745
2746}
2747
2748static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2749{
2750 u32 i, j, k;
2751 u32 mask;
2752
2753 mutex_lock(&adev->grbm_idx_mutex);
2754 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2755 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2756 gfx_v8_0_select_se_sh(adev, i, j);
2757 for (k = 0; k < adev->usec_timeout; k++) {
2758 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2759 break;
2760 udelay(1);
2761 }
2762 }
2763 }
2764 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2765 mutex_unlock(&adev->grbm_idx_mutex);
2766
2767 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2768 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2769 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2770 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2771 for (k = 0; k < adev->usec_timeout; k++) {
2772 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2773 break;
2774 udelay(1);
2775 }
2776}
2777
2778static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2779 bool enable)
2780{
2781 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2782
2783 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
2784 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
2785 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
2786 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
2787
2788 WREG32(mmCP_INT_CNTL_RING0, tmp);
2789}
2790
2791void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2792{
2793 u32 tmp = RREG32(mmRLC_CNTL);
2794
2795 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2796 WREG32(mmRLC_CNTL, tmp);
2797
2798 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2799
2800 gfx_v8_0_wait_for_rlc_serdes(adev);
2801}
2802
2803static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2804{
2805 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2806
2807 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2808 WREG32(mmGRBM_SOFT_RESET, tmp);
2809 udelay(50);
2810 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2811 WREG32(mmGRBM_SOFT_RESET, tmp);
2812 udelay(50);
2813}
2814
2815static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2816{
2817 u32 tmp = RREG32(mmRLC_CNTL);
2818
2819 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2820 WREG32(mmRLC_CNTL, tmp);
2821
2822 /* carrizo do enable cp interrupt after cp inited */
2823 if (!(adev->flags & AMD_IS_APU))
2824 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2825
2826 udelay(50);
2827}
2828
2829static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2830{
2831 const struct rlc_firmware_header_v2_0 *hdr;
2832 const __le32 *fw_data;
2833 unsigned i, fw_size;
2834
2835 if (!adev->gfx.rlc_fw)
2836 return -EINVAL;
2837
2838 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2839 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2840
2841 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2842 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2843 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2844
2845 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2846 for (i = 0; i < fw_size; i++)
2847 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2848 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2849
2850 return 0;
2851}
2852
2853static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2854{
2855 int r;
2856
2857 gfx_v8_0_rlc_stop(adev);
2858
2859 /* disable CG */
2860 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2861
2862 /* disable PG */
2863 WREG32(mmRLC_PG_CNTL, 0);
2864
2865 gfx_v8_0_rlc_reset(adev);
2866
2867 if (!adev->pp_enabled) {
2868 if (!adev->firmware.smu_load) {
2869 /* legacy rlc firmware loading */
2870 r = gfx_v8_0_rlc_load_microcode(adev);
2871 if (r)
2872 return r;
2873 } else {
2874 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2875 AMDGPU_UCODE_ID_RLC_G);
2876 if (r)
2877 return -EINVAL;
2878 }
2879 }
2880
2881 gfx_v8_0_rlc_start(adev);
2882
2883 return 0;
2884}
2885
2886static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2887{
2888 int i;
2889 u32 tmp = RREG32(mmCP_ME_CNTL);
2890
2891 if (enable) {
2892 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2893 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2894 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2895 } else {
2896 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2897 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2898 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2899 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2900 adev->gfx.gfx_ring[i].ready = false;
2901 }
2902 WREG32(mmCP_ME_CNTL, tmp);
2903 udelay(50);
2904}
2905
2906static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2907{
2908 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2909 const struct gfx_firmware_header_v1_0 *ce_hdr;
2910 const struct gfx_firmware_header_v1_0 *me_hdr;
2911 const __le32 *fw_data;
2912 unsigned i, fw_size;
2913
2914 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2915 return -EINVAL;
2916
2917 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2918 adev->gfx.pfp_fw->data;
2919 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2920 adev->gfx.ce_fw->data;
2921 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2922 adev->gfx.me_fw->data;
2923
2924 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2925 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2926 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2927
2928 gfx_v8_0_cp_gfx_enable(adev, false);
2929
2930 /* PFP */
2931 fw_data = (const __le32 *)
2932 (adev->gfx.pfp_fw->data +
2933 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2934 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2935 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2936 for (i = 0; i < fw_size; i++)
2937 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2938 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2939
2940 /* CE */
2941 fw_data = (const __le32 *)
2942 (adev->gfx.ce_fw->data +
2943 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2944 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2945 WREG32(mmCP_CE_UCODE_ADDR, 0);
2946 for (i = 0; i < fw_size; i++)
2947 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2948 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2949
2950 /* ME */
2951 fw_data = (const __le32 *)
2952 (adev->gfx.me_fw->data +
2953 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2954 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2955 WREG32(mmCP_ME_RAM_WADDR, 0);
2956 for (i = 0; i < fw_size; i++)
2957 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2958 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2959
2960 return 0;
2961}
2962
2963static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2964{
2965 u32 count = 0;
2966 const struct cs_section_def *sect = NULL;
2967 const struct cs_extent_def *ext = NULL;
2968
2969 /* begin clear state */
2970 count += 2;
2971 /* context control state */
2972 count += 3;
2973
2974 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2975 for (ext = sect->section; ext->extent != NULL; ++ext) {
2976 if (sect->id == SECT_CONTEXT)
2977 count += 2 + ext->reg_count;
2978 else
2979 return 0;
2980 }
2981 }
2982 /* pa_sc_raster_config/pa_sc_raster_config1 */
2983 count += 4;
2984 /* end clear state */
2985 count += 2;
2986 /* clear state */
2987 count += 2;
2988
2989 return count;
2990}
2991
2992static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2993{
2994 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2995 const struct cs_section_def *sect = NULL;
2996 const struct cs_extent_def *ext = NULL;
2997 int r, i;
2998
2999 /* init the CP */
3000 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
3001 WREG32(mmCP_ENDIAN_SWAP, 0);
3002 WREG32(mmCP_DEVICE_ID, 1);
3003
3004 gfx_v8_0_cp_gfx_enable(adev, true);
3005
3006 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
3007 if (r) {
3008 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3009 return r;
3010 }
3011
3012 /* clear state buffer */
3013 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3014 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3015
3016 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3017 amdgpu_ring_write(ring, 0x80000000);
3018 amdgpu_ring_write(ring, 0x80000000);
3019
3020 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
3021 for (ext = sect->section; ext->extent != NULL; ++ext) {
3022 if (sect->id == SECT_CONTEXT) {
3023 amdgpu_ring_write(ring,
3024 PACKET3(PACKET3_SET_CONTEXT_REG,
3025 ext->reg_count));
3026 amdgpu_ring_write(ring,
3027 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3028 for (i = 0; i < ext->reg_count; i++)
3029 amdgpu_ring_write(ring, ext->extent[i]);
3030 }
3031 }
3032 }
3033
3034 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3035 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
3036 switch (adev->asic_type) {
3037 case CHIP_TONGA:
3038 amdgpu_ring_write(ring, 0x16000012);
3039 amdgpu_ring_write(ring, 0x0000002A);
3040 break;
3041 case CHIP_FIJI:
3042 amdgpu_ring_write(ring, 0x3a00161a);
3043 amdgpu_ring_write(ring, 0x0000002e);
3044 break;
3045 case CHIP_TOPAZ:
3046 case CHIP_CARRIZO:
3047 amdgpu_ring_write(ring, 0x00000002);
3048 amdgpu_ring_write(ring, 0x00000000);
3049 break;
3050 case CHIP_STONEY:
3051 amdgpu_ring_write(ring, 0x00000000);
3052 amdgpu_ring_write(ring, 0x00000000);
3053 break;
3054 default:
3055 BUG();
3056 }
3057
3058 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3059 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3060
3061 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3062 amdgpu_ring_write(ring, 0);
3063
3064 /* init the CE partitions */
3065 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3066 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3067 amdgpu_ring_write(ring, 0x8000);
3068 amdgpu_ring_write(ring, 0x8000);
3069
3070 amdgpu_ring_commit(ring);
3071
3072 return 0;
3073}
3074
3075static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
3076{
3077 struct amdgpu_ring *ring;
3078 u32 tmp;
3079 u32 rb_bufsz;
3080 u64 rb_addr, rptr_addr;
3081 int r;
3082
3083 /* Set the write pointer delay */
3084 WREG32(mmCP_RB_WPTR_DELAY, 0);
3085
3086 /* set the RB to use vmid 0 */
3087 WREG32(mmCP_RB_VMID, 0);
3088
3089 /* Set ring buffer size */
3090 ring = &adev->gfx.gfx_ring[0];
3091 rb_bufsz = order_base_2(ring->ring_size / 8);
3092 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3093 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3094 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
3095 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
3096#ifdef __BIG_ENDIAN
3097 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3098#endif
3099 WREG32(mmCP_RB0_CNTL, tmp);
3100
3101 /* Initialize the ring buffer's read and write pointers */
3102 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
3103 ring->wptr = 0;
3104 WREG32(mmCP_RB0_WPTR, ring->wptr);
3105
3106 /* set the wb address wether it's enabled or not */
3107 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3108 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3109 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
3110
3111 mdelay(1);
3112 WREG32(mmCP_RB0_CNTL, tmp);
3113
3114 rb_addr = ring->gpu_addr >> 8;
3115 WREG32(mmCP_RB0_BASE, rb_addr);
3116 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3117
3118 /* no gfx doorbells on iceland */
3119 if (adev->asic_type != CHIP_TOPAZ) {
3120 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
3121 if (ring->use_doorbell) {
3122 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3123 DOORBELL_OFFSET, ring->doorbell_index);
3124 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3125 DOORBELL_EN, 1);
3126 } else {
3127 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3128 DOORBELL_EN, 0);
3129 }
3130 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
3131
3132 if (adev->asic_type == CHIP_TONGA) {
3133 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3134 DOORBELL_RANGE_LOWER,
3135 AMDGPU_DOORBELL_GFX_RING0);
3136 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
3137
3138 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
3139 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3140 }
3141
3142 }
3143
3144 /* start the ring */
3145 gfx_v8_0_cp_gfx_start(adev);
3146 ring->ready = true;
3147 r = amdgpu_ring_test_ring(ring);
3148 if (r) {
3149 ring->ready = false;
3150 return r;
3151 }
3152
3153 return 0;
3154}
3155
3156static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3157{
3158 int i;
3159
3160 if (enable) {
3161 WREG32(mmCP_MEC_CNTL, 0);
3162 } else {
3163 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
3164 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3165 adev->gfx.compute_ring[i].ready = false;
3166 }
3167 udelay(50);
3168}
3169
3170static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3171{
3172 const struct gfx_firmware_header_v1_0 *mec_hdr;
3173 const __le32 *fw_data;
3174 unsigned i, fw_size;
3175
3176 if (!adev->gfx.mec_fw)
3177 return -EINVAL;
3178
3179 gfx_v8_0_cp_compute_enable(adev, false);
3180
3181 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3182 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3183
3184 fw_data = (const __le32 *)
3185 (adev->gfx.mec_fw->data +
3186 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3187 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
3188
3189 /* MEC1 */
3190 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3191 for (i = 0; i < fw_size; i++)
3192 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
3193 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3194
3195 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3196 if (adev->gfx.mec2_fw) {
3197 const struct gfx_firmware_header_v1_0 *mec2_hdr;
3198
3199 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3200 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
3201
3202 fw_data = (const __le32 *)
3203 (adev->gfx.mec2_fw->data +
3204 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
3205 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
3206
3207 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3208 for (i = 0; i < fw_size; i++)
3209 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
3210 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
3211 }
3212
3213 return 0;
3214}
3215
3216struct vi_mqd {
3217 uint32_t header; /* ordinal0 */
3218 uint32_t compute_dispatch_initiator; /* ordinal1 */
3219 uint32_t compute_dim_x; /* ordinal2 */
3220 uint32_t compute_dim_y; /* ordinal3 */
3221 uint32_t compute_dim_z; /* ordinal4 */
3222 uint32_t compute_start_x; /* ordinal5 */
3223 uint32_t compute_start_y; /* ordinal6 */
3224 uint32_t compute_start_z; /* ordinal7 */
3225 uint32_t compute_num_thread_x; /* ordinal8 */
3226 uint32_t compute_num_thread_y; /* ordinal9 */
3227 uint32_t compute_num_thread_z; /* ordinal10 */
3228 uint32_t compute_pipelinestat_enable; /* ordinal11 */
3229 uint32_t compute_perfcount_enable; /* ordinal12 */
3230 uint32_t compute_pgm_lo; /* ordinal13 */
3231 uint32_t compute_pgm_hi; /* ordinal14 */
3232 uint32_t compute_tba_lo; /* ordinal15 */
3233 uint32_t compute_tba_hi; /* ordinal16 */
3234 uint32_t compute_tma_lo; /* ordinal17 */
3235 uint32_t compute_tma_hi; /* ordinal18 */
3236 uint32_t compute_pgm_rsrc1; /* ordinal19 */
3237 uint32_t compute_pgm_rsrc2; /* ordinal20 */
3238 uint32_t compute_vmid; /* ordinal21 */
3239 uint32_t compute_resource_limits; /* ordinal22 */
3240 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
3241 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
3242 uint32_t compute_tmpring_size; /* ordinal25 */
3243 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
3244 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
3245 uint32_t compute_restart_x; /* ordinal28 */
3246 uint32_t compute_restart_y; /* ordinal29 */
3247 uint32_t compute_restart_z; /* ordinal30 */
3248 uint32_t compute_thread_trace_enable; /* ordinal31 */
3249 uint32_t compute_misc_reserved; /* ordinal32 */
3250 uint32_t compute_dispatch_id; /* ordinal33 */
3251 uint32_t compute_threadgroup_id; /* ordinal34 */
3252 uint32_t compute_relaunch; /* ordinal35 */
3253 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
3254 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
3255 uint32_t compute_wave_restore_control; /* ordinal38 */
3256 uint32_t reserved9; /* ordinal39 */
3257 uint32_t reserved10; /* ordinal40 */
3258 uint32_t reserved11; /* ordinal41 */
3259 uint32_t reserved12; /* ordinal42 */
3260 uint32_t reserved13; /* ordinal43 */
3261 uint32_t reserved14; /* ordinal44 */
3262 uint32_t reserved15; /* ordinal45 */
3263 uint32_t reserved16; /* ordinal46 */
3264 uint32_t reserved17; /* ordinal47 */
3265 uint32_t reserved18; /* ordinal48 */
3266 uint32_t reserved19; /* ordinal49 */
3267 uint32_t reserved20; /* ordinal50 */
3268 uint32_t reserved21; /* ordinal51 */
3269 uint32_t reserved22; /* ordinal52 */
3270 uint32_t reserved23; /* ordinal53 */
3271 uint32_t reserved24; /* ordinal54 */
3272 uint32_t reserved25; /* ordinal55 */
3273 uint32_t reserved26; /* ordinal56 */
3274 uint32_t reserved27; /* ordinal57 */
3275 uint32_t reserved28; /* ordinal58 */
3276 uint32_t reserved29; /* ordinal59 */
3277 uint32_t reserved30; /* ordinal60 */
3278 uint32_t reserved31; /* ordinal61 */
3279 uint32_t reserved32; /* ordinal62 */
3280 uint32_t reserved33; /* ordinal63 */
3281 uint32_t reserved34; /* ordinal64 */
3282 uint32_t compute_user_data_0; /* ordinal65 */
3283 uint32_t compute_user_data_1; /* ordinal66 */
3284 uint32_t compute_user_data_2; /* ordinal67 */
3285 uint32_t compute_user_data_3; /* ordinal68 */
3286 uint32_t compute_user_data_4; /* ordinal69 */
3287 uint32_t compute_user_data_5; /* ordinal70 */
3288 uint32_t compute_user_data_6; /* ordinal71 */
3289 uint32_t compute_user_data_7; /* ordinal72 */
3290 uint32_t compute_user_data_8; /* ordinal73 */
3291 uint32_t compute_user_data_9; /* ordinal74 */
3292 uint32_t compute_user_data_10; /* ordinal75 */
3293 uint32_t compute_user_data_11; /* ordinal76 */
3294 uint32_t compute_user_data_12; /* ordinal77 */
3295 uint32_t compute_user_data_13; /* ordinal78 */
3296 uint32_t compute_user_data_14; /* ordinal79 */
3297 uint32_t compute_user_data_15; /* ordinal80 */
3298 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
3299 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
3300 uint32_t reserved35; /* ordinal83 */
3301 uint32_t reserved36; /* ordinal84 */
3302 uint32_t reserved37; /* ordinal85 */
3303 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
3304 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
3305 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
3306 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
3307 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
3308 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
3309 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
3310 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
3311 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
3312 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
3313 uint32_t reserved38; /* ordinal96 */
3314 uint32_t reserved39; /* ordinal97 */
3315 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
3316 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
3317 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
3318 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
3319 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
3320 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
3321 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
3322 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
3323 uint32_t reserved40; /* ordinal106 */
3324 uint32_t reserved41; /* ordinal107 */
3325 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
3326 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
3327 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
3328 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
3329 uint32_t reserved42; /* ordinal112 */
3330 uint32_t reserved43; /* ordinal113 */
3331 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
3332 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
3333 uint32_t cp_packet_id_lo; /* ordinal116 */
3334 uint32_t cp_packet_id_hi; /* ordinal117 */
3335 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
3336 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
3337 uint32_t gds_save_base_addr_lo; /* ordinal120 */
3338 uint32_t gds_save_base_addr_hi; /* ordinal121 */
3339 uint32_t gds_save_mask_lo; /* ordinal122 */
3340 uint32_t gds_save_mask_hi; /* ordinal123 */
3341 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
3342 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
3343 uint32_t reserved44; /* ordinal126 */
3344 uint32_t reserved45; /* ordinal127 */
3345 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
3346 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
3347 uint32_t cp_hqd_active; /* ordinal130 */
3348 uint32_t cp_hqd_vmid; /* ordinal131 */
3349 uint32_t cp_hqd_persistent_state; /* ordinal132 */
3350 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
3351 uint32_t cp_hqd_queue_priority; /* ordinal134 */
3352 uint32_t cp_hqd_quantum; /* ordinal135 */
3353 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
3354 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
3355 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
3356 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
3357 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
3358 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
3359 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
3360 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
3361 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
3362 uint32_t cp_hqd_pq_control; /* ordinal145 */
3363 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
3364 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
3365 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
3366 uint32_t cp_hqd_ib_control; /* ordinal149 */
3367 uint32_t cp_hqd_iq_timer; /* ordinal150 */
3368 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
3369 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
3370 uint32_t cp_hqd_dma_offload; /* ordinal153 */
3371 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
3372 uint32_t cp_hqd_msg_type; /* ordinal155 */
3373 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
3374 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
3375 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
3376 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
3377 uint32_t cp_hqd_hq_status0; /* ordinal160 */
3378 uint32_t cp_hqd_hq_control0; /* ordinal161 */
3379 uint32_t cp_mqd_control; /* ordinal162 */
3380 uint32_t cp_hqd_hq_status1; /* ordinal163 */
3381 uint32_t cp_hqd_hq_control1; /* ordinal164 */
3382 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
3383 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
3384 uint32_t cp_hqd_eop_control; /* ordinal167 */
3385 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
3386 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
3387 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
3388 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
3389 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
3390 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
3391 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
3392 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
3393 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
3394 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
3395 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
3396 uint32_t cp_hqd_error; /* ordinal179 */
3397 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
3398 uint32_t cp_hqd_eop_dones; /* ordinal181 */
3399 uint32_t reserved46; /* ordinal182 */
3400 uint32_t reserved47; /* ordinal183 */
3401 uint32_t reserved48; /* ordinal184 */
3402 uint32_t reserved49; /* ordinal185 */
3403 uint32_t reserved50; /* ordinal186 */
3404 uint32_t reserved51; /* ordinal187 */
3405 uint32_t reserved52; /* ordinal188 */
3406 uint32_t reserved53; /* ordinal189 */
3407 uint32_t reserved54; /* ordinal190 */
3408 uint32_t reserved55; /* ordinal191 */
3409 uint32_t iqtimer_pkt_header; /* ordinal192 */
3410 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
3411 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
3412 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
3413 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
3414 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
3415 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
3416 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
3417 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
3418 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
3419 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
3420 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
3421 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
3422 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
3423 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
3424 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
3425 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
3426 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
3427 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
3428 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
3429 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
3430 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
3431 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
3432 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
3433 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
3434 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
3435 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
3436 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
3437 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
3438 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
3439 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
3440 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
3441 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
3442 uint32_t reserved56; /* ordinal225 */
3443 uint32_t reserved57; /* ordinal226 */
3444 uint32_t reserved58; /* ordinal227 */
3445 uint32_t set_resources_header; /* ordinal228 */
3446 uint32_t set_resources_dw1; /* ordinal229 */
3447 uint32_t set_resources_dw2; /* ordinal230 */
3448 uint32_t set_resources_dw3; /* ordinal231 */
3449 uint32_t set_resources_dw4; /* ordinal232 */
3450 uint32_t set_resources_dw5; /* ordinal233 */
3451 uint32_t set_resources_dw6; /* ordinal234 */
3452 uint32_t set_resources_dw7; /* ordinal235 */
3453 uint32_t reserved59; /* ordinal236 */
3454 uint32_t reserved60; /* ordinal237 */
3455 uint32_t reserved61; /* ordinal238 */
3456 uint32_t reserved62; /* ordinal239 */
3457 uint32_t reserved63; /* ordinal240 */
3458 uint32_t reserved64; /* ordinal241 */
3459 uint32_t reserved65; /* ordinal242 */
3460 uint32_t reserved66; /* ordinal243 */
3461 uint32_t reserved67; /* ordinal244 */
3462 uint32_t reserved68; /* ordinal245 */
3463 uint32_t reserved69; /* ordinal246 */
3464 uint32_t reserved70; /* ordinal247 */
3465 uint32_t reserved71; /* ordinal248 */
3466 uint32_t reserved72; /* ordinal249 */
3467 uint32_t reserved73; /* ordinal250 */
3468 uint32_t reserved74; /* ordinal251 */
3469 uint32_t reserved75; /* ordinal252 */
3470 uint32_t reserved76; /* ordinal253 */
3471 uint32_t reserved77; /* ordinal254 */
3472 uint32_t reserved78; /* ordinal255 */
3473
3474 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3475};
3476
3477static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3478{
3479 int i, r;
3480
3481 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3482 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3483
3484 if (ring->mqd_obj) {
3485 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3486 if (unlikely(r != 0))
3487 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3488
3489 amdgpu_bo_unpin(ring->mqd_obj);
3490 amdgpu_bo_unreserve(ring->mqd_obj);
3491
3492 amdgpu_bo_unref(&ring->mqd_obj);
3493 ring->mqd_obj = NULL;
3494 }
3495 }
3496}
3497
3498static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3499{
3500 int r, i, j;
3501 u32 tmp;
3502 bool use_doorbell = true;
3503 u64 hqd_gpu_addr;
3504 u64 mqd_gpu_addr;
3505 u64 eop_gpu_addr;
3506 u64 wb_gpu_addr;
3507 u32 *buf;
3508 struct vi_mqd *mqd;
3509
3510 /* init the pipes */
3511 mutex_lock(&adev->srbm_mutex);
3512 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3513 int me = (i < 4) ? 1 : 2;
3514 int pipe = (i < 4) ? i : (i - 4);
3515
3516 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3517 eop_gpu_addr >>= 8;
3518
3519 vi_srbm_select(adev, me, pipe, 0, 0);
3520
3521 /* write the EOP addr */
3522 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3523 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3524
3525 /* set the VMID assigned */
3526 WREG32(mmCP_HQD_VMID, 0);
3527
3528 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3529 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3530 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3531 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3532 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3533 }
3534 vi_srbm_select(adev, 0, 0, 0, 0);
3535 mutex_unlock(&adev->srbm_mutex);
3536
3537 /* init the queues. Just two for now. */
3538 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3539 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3540
3541 if (ring->mqd_obj == NULL) {
3542 r = amdgpu_bo_create(adev,
3543 sizeof(struct vi_mqd),
3544 PAGE_SIZE, true,
3545 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3546 NULL, &ring->mqd_obj);
3547 if (r) {
3548 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3549 return r;
3550 }
3551 }
3552
3553 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3554 if (unlikely(r != 0)) {
3555 gfx_v8_0_cp_compute_fini(adev);
3556 return r;
3557 }
3558 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3559 &mqd_gpu_addr);
3560 if (r) {
3561 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3562 gfx_v8_0_cp_compute_fini(adev);
3563 return r;
3564 }
3565 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3566 if (r) {
3567 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3568 gfx_v8_0_cp_compute_fini(adev);
3569 return r;
3570 }
3571
3572 /* init the mqd struct */
3573 memset(buf, 0, sizeof(struct vi_mqd));
3574
3575 mqd = (struct vi_mqd *)buf;
3576 mqd->header = 0xC0310800;
3577 mqd->compute_pipelinestat_enable = 0x00000001;
3578 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3579 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3580 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3581 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3582 mqd->compute_misc_reserved = 0x00000003;
3583
3584 mutex_lock(&adev->srbm_mutex);
3585 vi_srbm_select(adev, ring->me,
3586 ring->pipe,
3587 ring->queue, 0);
3588
3589 /* disable wptr polling */
3590 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3591 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3592 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3593
3594 mqd->cp_hqd_eop_base_addr_lo =
3595 RREG32(mmCP_HQD_EOP_BASE_ADDR);
3596 mqd->cp_hqd_eop_base_addr_hi =
3597 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3598
3599 /* enable doorbell? */
3600 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3601 if (use_doorbell) {
3602 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3603 } else {
3604 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3605 }
3606 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3607 mqd->cp_hqd_pq_doorbell_control = tmp;
3608
3609 /* disable the queue if it's active */
3610 mqd->cp_hqd_dequeue_request = 0;
3611 mqd->cp_hqd_pq_rptr = 0;
3612 mqd->cp_hqd_pq_wptr= 0;
3613 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3614 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3615 for (j = 0; j < adev->usec_timeout; j++) {
3616 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3617 break;
3618 udelay(1);
3619 }
3620 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3621 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3622 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3623 }
3624
3625 /* set the pointer to the MQD */
3626 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3627 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3628 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3629 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3630
3631 /* set MQD vmid to 0 */
3632 tmp = RREG32(mmCP_MQD_CONTROL);
3633 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3634 WREG32(mmCP_MQD_CONTROL, tmp);
3635 mqd->cp_mqd_control = tmp;
3636
3637 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3638 hqd_gpu_addr = ring->gpu_addr >> 8;
3639 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3640 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3641 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3642 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3643
3644 /* set up the HQD, this is similar to CP_RB0_CNTL */
3645 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3646 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3647 (order_base_2(ring->ring_size / 4) - 1));
3648 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3649 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3650#ifdef __BIG_ENDIAN
3651 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3652#endif
3653 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3654 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3655 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3656 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3657 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3658 mqd->cp_hqd_pq_control = tmp;
3659
3660 /* set the wb address wether it's enabled or not */
3661 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3662 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3663 mqd->cp_hqd_pq_rptr_report_addr_hi =
3664 upper_32_bits(wb_gpu_addr) & 0xffff;
3665 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3666 mqd->cp_hqd_pq_rptr_report_addr_lo);
3667 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3668 mqd->cp_hqd_pq_rptr_report_addr_hi);
3669
3670 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3671 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3672 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3673 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3674 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3675 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3676 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3677
3678 /* enable the doorbell if requested */
3679 if (use_doorbell) {
3680 if ((adev->asic_type == CHIP_CARRIZO) ||
3681 (adev->asic_type == CHIP_FIJI) ||
3682 (adev->asic_type == CHIP_STONEY)) {
3683 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3684 AMDGPU_DOORBELL_KIQ << 2);
3685 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3686 AMDGPU_DOORBELL_MEC_RING7 << 2);
3687 }
3688 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3689 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3690 DOORBELL_OFFSET, ring->doorbell_index);
3691 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3692 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3693 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3694 mqd->cp_hqd_pq_doorbell_control = tmp;
3695
3696 } else {
3697 mqd->cp_hqd_pq_doorbell_control = 0;
3698 }
3699 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3700 mqd->cp_hqd_pq_doorbell_control);
3701
3702 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3703 ring->wptr = 0;
3704 mqd->cp_hqd_pq_wptr = ring->wptr;
3705 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3706 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3707
3708 /* set the vmid for the queue */
3709 mqd->cp_hqd_vmid = 0;
3710 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3711
3712 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3713 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3714 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3715 mqd->cp_hqd_persistent_state = tmp;
3716 if (adev->asic_type == CHIP_STONEY) {
3717 tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
3718 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
3719 WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
3720 }
3721
3722 /* activate the queue */
3723 mqd->cp_hqd_active = 1;
3724 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3725
3726 vi_srbm_select(adev, 0, 0, 0, 0);
3727 mutex_unlock(&adev->srbm_mutex);
3728
3729 amdgpu_bo_kunmap(ring->mqd_obj);
3730 amdgpu_bo_unreserve(ring->mqd_obj);
3731 }
3732
3733 if (use_doorbell) {
3734 tmp = RREG32(mmCP_PQ_STATUS);
3735 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3736 WREG32(mmCP_PQ_STATUS, tmp);
3737 }
3738
3739 gfx_v8_0_cp_compute_enable(adev, true);
3740
3741 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3742 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3743
3744 ring->ready = true;
3745 r = amdgpu_ring_test_ring(ring);
3746 if (r)
3747 ring->ready = false;
3748 }
3749
3750 return 0;
3751}
3752
3753static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3754{
3755 int r;
3756
3757 if (!(adev->flags & AMD_IS_APU))
3758 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3759
3760 if (!adev->pp_enabled) {
3761 if (!adev->firmware.smu_load) {
3762 /* legacy firmware loading */
3763 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3764 if (r)
3765 return r;
3766
3767 r = gfx_v8_0_cp_compute_load_microcode(adev);
3768 if (r)
3769 return r;
3770 } else {
3771 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3772 AMDGPU_UCODE_ID_CP_CE);
3773 if (r)
3774 return -EINVAL;
3775
3776 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3777 AMDGPU_UCODE_ID_CP_PFP);
3778 if (r)
3779 return -EINVAL;
3780
3781 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3782 AMDGPU_UCODE_ID_CP_ME);
3783 if (r)
3784 return -EINVAL;
3785
3786 if (adev->asic_type == CHIP_TOPAZ) {
3787 r = gfx_v8_0_cp_compute_load_microcode(adev);
3788 if (r)
3789 return r;
3790 } else {
3791 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3792 AMDGPU_UCODE_ID_CP_MEC1);
3793 if (r)
3794 return -EINVAL;
3795 }
3796 }
3797 }
3798
3799 r = gfx_v8_0_cp_gfx_resume(adev);
3800 if (r)
3801 return r;
3802
3803 r = gfx_v8_0_cp_compute_resume(adev);
3804 if (r)
3805 return r;
3806
3807 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3808
3809 return 0;
3810}
3811
3812static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3813{
3814 gfx_v8_0_cp_gfx_enable(adev, enable);
3815 gfx_v8_0_cp_compute_enable(adev, enable);
3816}
3817
3818static int gfx_v8_0_hw_init(void *handle)
3819{
3820 int r;
3821 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3822
3823 gfx_v8_0_init_golden_registers(adev);
3824
3825 gfx_v8_0_gpu_init(adev);
3826
3827 r = gfx_v8_0_rlc_resume(adev);
3828 if (r)
3829 return r;
3830
3831 r = gfx_v8_0_cp_resume(adev);
3832 if (r)
3833 return r;
3834
3835 return r;
3836}
3837
3838static int gfx_v8_0_hw_fini(void *handle)
3839{
3840 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3841
3842 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3843 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3844 gfx_v8_0_cp_enable(adev, false);
3845 gfx_v8_0_rlc_stop(adev);
3846 gfx_v8_0_cp_compute_fini(adev);
3847
3848 return 0;
3849}
3850
3851static int gfx_v8_0_suspend(void *handle)
3852{
3853 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3854
3855 return gfx_v8_0_hw_fini(adev);
3856}
3857
3858static int gfx_v8_0_resume(void *handle)
3859{
3860 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3861
3862 return gfx_v8_0_hw_init(adev);
3863}
3864
3865static bool gfx_v8_0_is_idle(void *handle)
3866{
3867 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3868
3869 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3870 return false;
3871 else
3872 return true;
3873}
3874
3875static int gfx_v8_0_wait_for_idle(void *handle)
3876{
3877 unsigned i;
3878 u32 tmp;
3879 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3880
3881 for (i = 0; i < adev->usec_timeout; i++) {
3882 /* read MC_STATUS */
3883 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3884
3885 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3886 return 0;
3887 udelay(1);
3888 }
3889 return -ETIMEDOUT;
3890}
3891
3892static void gfx_v8_0_print_status(void *handle)
3893{
3894 int i;
3895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3896
3897 dev_info(adev->dev, "GFX 8.x registers\n");
3898 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
3899 RREG32(mmGRBM_STATUS));
3900 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
3901 RREG32(mmGRBM_STATUS2));
3902 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
3903 RREG32(mmGRBM_STATUS_SE0));
3904 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
3905 RREG32(mmGRBM_STATUS_SE1));
3906 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
3907 RREG32(mmGRBM_STATUS_SE2));
3908 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
3909 RREG32(mmGRBM_STATUS_SE3));
3910 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3911 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
3912 RREG32(mmCP_STALLED_STAT1));
3913 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
3914 RREG32(mmCP_STALLED_STAT2));
3915 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
3916 RREG32(mmCP_STALLED_STAT3));
3917 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
3918 RREG32(mmCP_CPF_BUSY_STAT));
3919 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
3920 RREG32(mmCP_CPF_STALLED_STAT1));
3921 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3922 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3923 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
3924 RREG32(mmCP_CPC_STALLED_STAT1));
3925 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3926
3927 for (i = 0; i < 32; i++) {
3928 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
3929 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3930 }
3931 for (i = 0; i < 16; i++) {
3932 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
3933 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3934 }
3935 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3936 dev_info(adev->dev, " se: %d\n", i);
3937 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3938 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
3939 RREG32(mmPA_SC_RASTER_CONFIG));
3940 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
3941 RREG32(mmPA_SC_RASTER_CONFIG_1));
3942 }
3943 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3944
3945 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
3946 RREG32(mmGB_ADDR_CONFIG));
3947 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
3948 RREG32(mmHDP_ADDR_CONFIG));
3949 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
3950 RREG32(mmDMIF_ADDR_CALC));
3951
3952 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
3953 RREG32(mmCP_MEQ_THRESHOLDS));
3954 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
3955 RREG32(mmSX_DEBUG_1));
3956 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
3957 RREG32(mmTA_CNTL_AUX));
3958 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
3959 RREG32(mmSPI_CONFIG_CNTL));
3960 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
3961 RREG32(mmSQ_CONFIG));
3962 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
3963 RREG32(mmDB_DEBUG));
3964 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
3965 RREG32(mmDB_DEBUG2));
3966 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
3967 RREG32(mmDB_DEBUG3));
3968 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
3969 RREG32(mmCB_HW_CONTROL));
3970 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
3971 RREG32(mmSPI_CONFIG_CNTL_1));
3972 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
3973 RREG32(mmPA_SC_FIFO_SIZE));
3974 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
3975 RREG32(mmVGT_NUM_INSTANCES));
3976 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
3977 RREG32(mmCP_PERFMON_CNTL));
3978 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3979 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3980 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
3981 RREG32(mmVGT_CACHE_INVALIDATION));
3982 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
3983 RREG32(mmVGT_GS_VERTEX_REUSE));
3984 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3985 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3986 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
3987 RREG32(mmPA_CL_ENHANCE));
3988 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
3989 RREG32(mmPA_SC_ENHANCE));
3990
3991 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
3992 RREG32(mmCP_ME_CNTL));
3993 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
3994 RREG32(mmCP_MAX_CONTEXT));
3995 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
3996 RREG32(mmCP_ENDIAN_SWAP));
3997 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
3998 RREG32(mmCP_DEVICE_ID));
3999
4000 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
4001 RREG32(mmCP_SEM_WAIT_TIMER));
4002
4003 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
4004 RREG32(mmCP_RB_WPTR_DELAY));
4005 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
4006 RREG32(mmCP_RB_VMID));
4007 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4008 RREG32(mmCP_RB0_CNTL));
4009 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
4010 RREG32(mmCP_RB0_WPTR));
4011 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
4012 RREG32(mmCP_RB0_RPTR_ADDR));
4013 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
4014 RREG32(mmCP_RB0_RPTR_ADDR_HI));
4015 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4016 RREG32(mmCP_RB0_CNTL));
4017 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
4018 RREG32(mmCP_RB0_BASE));
4019 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
4020 RREG32(mmCP_RB0_BASE_HI));
4021 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
4022 RREG32(mmCP_MEC_CNTL));
4023 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
4024 RREG32(mmCP_CPF_DEBUG));
4025
4026 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
4027 RREG32(mmSCRATCH_ADDR));
4028 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
4029 RREG32(mmSCRATCH_UMSK));
4030
4031 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
4032 RREG32(mmCP_INT_CNTL_RING0));
4033 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4034 RREG32(mmRLC_LB_CNTL));
4035 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
4036 RREG32(mmRLC_CNTL));
4037 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
4038 RREG32(mmRLC_CGCG_CGLS_CTRL));
4039 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
4040 RREG32(mmRLC_LB_CNTR_INIT));
4041 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
4042 RREG32(mmRLC_LB_CNTR_MAX));
4043 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
4044 RREG32(mmRLC_LB_INIT_CU_MASK));
4045 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
4046 RREG32(mmRLC_LB_PARAMS));
4047 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4048 RREG32(mmRLC_LB_CNTL));
4049 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
4050 RREG32(mmRLC_MC_CNTL));
4051 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
4052 RREG32(mmRLC_UCODE_CNTL));
4053
4054 mutex_lock(&adev->srbm_mutex);
4055 for (i = 0; i < 16; i++) {
4056 vi_srbm_select(adev, 0, 0, 0, i);
4057 dev_info(adev->dev, " VM %d:\n", i);
4058 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
4059 RREG32(mmSH_MEM_CONFIG));
4060 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
4061 RREG32(mmSH_MEM_APE1_BASE));
4062 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
4063 RREG32(mmSH_MEM_APE1_LIMIT));
4064 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
4065 RREG32(mmSH_MEM_BASES));
4066 }
4067 vi_srbm_select(adev, 0, 0, 0, 0);
4068 mutex_unlock(&adev->srbm_mutex);
4069}
4070
4071static int gfx_v8_0_soft_reset(void *handle)
4072{
4073 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4074 u32 tmp;
4075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4076
4077 /* GRBM_STATUS */
4078 tmp = RREG32(mmGRBM_STATUS);
4079 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4080 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4081 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4082 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4083 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4084 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
4085 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4086 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4087 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4088 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4089 }
4090
4091 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4092 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4093 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4094 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4095 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4096 }
4097
4098 /* GRBM_STATUS2 */
4099 tmp = RREG32(mmGRBM_STATUS2);
4100 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4101 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4102 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4103
4104 /* SRBM_STATUS */
4105 tmp = RREG32(mmSRBM_STATUS);
4106 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4107 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4108 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4109
4110 if (grbm_soft_reset || srbm_soft_reset) {
4111 gfx_v8_0_print_status((void *)adev);
4112 /* stop the rlc */
4113 gfx_v8_0_rlc_stop(adev);
4114
4115 /* Disable GFX parsing/prefetching */
4116 gfx_v8_0_cp_gfx_enable(adev, false);
4117
4118 /* Disable MEC parsing/prefetching */
4119 gfx_v8_0_cp_compute_enable(adev, false);
4120
4121 if (grbm_soft_reset || srbm_soft_reset) {
4122 tmp = RREG32(mmGMCON_DEBUG);
4123 tmp = REG_SET_FIELD(tmp,
4124 GMCON_DEBUG, GFX_STALL, 1);
4125 tmp = REG_SET_FIELD(tmp,
4126 GMCON_DEBUG, GFX_CLEAR, 1);
4127 WREG32(mmGMCON_DEBUG, tmp);
4128
4129 udelay(50);
4130 }
4131
4132 if (grbm_soft_reset) {
4133 tmp = RREG32(mmGRBM_SOFT_RESET);
4134 tmp |= grbm_soft_reset;
4135 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4136 WREG32(mmGRBM_SOFT_RESET, tmp);
4137 tmp = RREG32(mmGRBM_SOFT_RESET);
4138
4139 udelay(50);
4140
4141 tmp &= ~grbm_soft_reset;
4142 WREG32(mmGRBM_SOFT_RESET, tmp);
4143 tmp = RREG32(mmGRBM_SOFT_RESET);
4144 }
4145
4146 if (srbm_soft_reset) {
4147 tmp = RREG32(mmSRBM_SOFT_RESET);
4148 tmp |= srbm_soft_reset;
4149 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4150 WREG32(mmSRBM_SOFT_RESET, tmp);
4151 tmp = RREG32(mmSRBM_SOFT_RESET);
4152
4153 udelay(50);
4154
4155 tmp &= ~srbm_soft_reset;
4156 WREG32(mmSRBM_SOFT_RESET, tmp);
4157 tmp = RREG32(mmSRBM_SOFT_RESET);
4158 }
4159
4160 if (grbm_soft_reset || srbm_soft_reset) {
4161 tmp = RREG32(mmGMCON_DEBUG);
4162 tmp = REG_SET_FIELD(tmp,
4163 GMCON_DEBUG, GFX_STALL, 0);
4164 tmp = REG_SET_FIELD(tmp,
4165 GMCON_DEBUG, GFX_CLEAR, 0);
4166 WREG32(mmGMCON_DEBUG, tmp);
4167 }
4168
4169 /* Wait a little for things to settle down */
4170 udelay(50);
4171 gfx_v8_0_print_status((void *)adev);
4172 }
4173 return 0;
4174}
4175
4176/**
4177 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
4178 *
4179 * @adev: amdgpu_device pointer
4180 *
4181 * Fetches a GPU clock counter snapshot.
4182 * Returns the 64 bit clock counter snapshot.
4183 */
4184uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4185{
4186 uint64_t clock;
4187
4188 mutex_lock(&adev->gfx.gpu_clock_mutex);
4189 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4190 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4191 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4192 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4193 return clock;
4194}
4195
4196static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4197 uint32_t vmid,
4198 uint32_t gds_base, uint32_t gds_size,
4199 uint32_t gws_base, uint32_t gws_size,
4200 uint32_t oa_base, uint32_t oa_size)
4201{
4202 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4203 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4204
4205 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4206 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4207
4208 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4209 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4210
4211 /* GDS Base */
4212 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4213 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4214 WRITE_DATA_DST_SEL(0)));
4215 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4216 amdgpu_ring_write(ring, 0);
4217 amdgpu_ring_write(ring, gds_base);
4218
4219 /* GDS Size */
4220 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4221 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4222 WRITE_DATA_DST_SEL(0)));
4223 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4224 amdgpu_ring_write(ring, 0);
4225 amdgpu_ring_write(ring, gds_size);
4226
4227 /* GWS */
4228 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4229 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4230 WRITE_DATA_DST_SEL(0)));
4231 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4232 amdgpu_ring_write(ring, 0);
4233 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4234
4235 /* OA */
4236 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4237 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4238 WRITE_DATA_DST_SEL(0)));
4239 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4240 amdgpu_ring_write(ring, 0);
4241 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4242}
4243
4244static int gfx_v8_0_early_init(void *handle)
4245{
4246 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4247
4248 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
4249 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
4250 gfx_v8_0_set_ring_funcs(adev);
4251 gfx_v8_0_set_irq_funcs(adev);
4252 gfx_v8_0_set_gds_init(adev);
4253
4254 return 0;
4255}
4256
4257static int gfx_v8_0_late_init(void *handle)
4258{
4259 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4260 int r;
4261
4262 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4263 if (r)
4264 return r;
4265
4266 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4267 if (r)
4268 return r;
4269
4270 /* requires IBs so do in late init after IB pool is initialized */
4271 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
4272 if (r)
4273 return r;
4274
4275 return 0;
4276}
4277
4278static int gfx_v8_0_set_powergating_state(void *handle,
4279 enum amd_powergating_state state)
4280{
4281 return 0;
4282}
4283
4284static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
4285 uint32_t reg_addr, uint32_t cmd)
4286{
4287 uint32_t data;
4288
4289 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4290
4291 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4292 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4293
4294 data = RREG32(mmRLC_SERDES_WR_CTRL);
4295 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
4296 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
4297 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
4298 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
4299 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
4300 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
4301 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
4302 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
4303 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
4304 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
4305 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
4306 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
4307 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
4308 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
4309 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
4310
4311 WREG32(mmRLC_SERDES_WR_CTRL, data);
4312}
4313
4314static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4315 bool enable)
4316{
4317 uint32_t temp, data;
4318
4319 /* It is disabled by HW by default */
4320 if (enable) {
4321 /* 1 - RLC memory Light sleep */
4322 temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
4323 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4324 if (temp != data)
4325 WREG32(mmRLC_MEM_SLP_CNTL, data);
4326
4327 /* 2 - CP memory Light sleep */
4328 temp = data = RREG32(mmCP_MEM_SLP_CNTL);
4329 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4330 if (temp != data)
4331 WREG32(mmCP_MEM_SLP_CNTL, data);
4332
4333 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
4334 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4335 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
4336 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
4337 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
4338 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
4339
4340 if (temp != data)
4341 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4342
4343 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4344 gfx_v8_0_wait_for_rlc_serdes(adev);
4345
4346 /* 5 - clear mgcg override */
4347 fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
4348
4349 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
4350 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
4351 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
4352 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
4353 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
4354 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
4355 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
4356 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
4357 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
4358 if (temp != data)
4359 WREG32(mmCGTS_SM_CTRL_REG, data);
4360 udelay(50);
4361
4362 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4363 gfx_v8_0_wait_for_rlc_serdes(adev);
4364 } else {
4365 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
4366 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4367 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
4368 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
4369 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
4370 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
4371 if (temp != data)
4372 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4373
4374 /* 2 - disable MGLS in RLC */
4375 data = RREG32(mmRLC_MEM_SLP_CNTL);
4376 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4377 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4378 WREG32(mmRLC_MEM_SLP_CNTL, data);
4379 }
4380
4381 /* 3 - disable MGLS in CP */
4382 data = RREG32(mmCP_MEM_SLP_CNTL);
4383 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4384 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4385 WREG32(mmCP_MEM_SLP_CNTL, data);
4386 }
4387
4388 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
4389 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
4390 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
4391 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
4392 if (temp != data)
4393 WREG32(mmCGTS_SM_CTRL_REG, data);
4394
4395 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4396 gfx_v8_0_wait_for_rlc_serdes(adev);
4397
4398 /* 6 - set mgcg override */
4399 fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
4400
4401 udelay(50);
4402
4403 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4404 gfx_v8_0_wait_for_rlc_serdes(adev);
4405 }
4406}
4407
4408static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4409 bool enable)
4410{
4411 uint32_t temp, temp1, data, data1;
4412
4413 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
4414
4415 if (enable) {
4416 /* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
4417 * Cmp_busy/GFX_Idle interrupts
4418 */
4419 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4420
4421 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4422 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
4423 if (temp1 != data1)
4424 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
4425
4426 /* 2 wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4427 gfx_v8_0_wait_for_rlc_serdes(adev);
4428
4429 /* 3 - clear cgcg override */
4430 fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
4431
4432 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4433 gfx_v8_0_wait_for_rlc_serdes(adev);
4434
4435 /* 4 - write cmd to set CGLS */
4436 fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
4437
4438 /* 5 - enable cgcg */
4439 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4440
4441 /* enable cgls*/
4442 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4443
4444 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4445 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
4446
4447 if (temp1 != data1)
4448 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
4449
4450 if (temp != data)
4451 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
4452 } else {
4453 /* disable cntx_empty_int_enable & GFX Idle interrupt */
4454 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4455
4456 /* TEST CGCG */
4457 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4458 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
4459 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
4460 if (temp1 != data1)
4461 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
4462
4463 /* read gfx register to wake up cgcg */
4464 RREG32(mmCB_CGTT_SCLK_CTRL);
4465 RREG32(mmCB_CGTT_SCLK_CTRL);
4466 RREG32(mmCB_CGTT_SCLK_CTRL);
4467 RREG32(mmCB_CGTT_SCLK_CTRL);
4468
4469 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4470 gfx_v8_0_wait_for_rlc_serdes(adev);
4471
4472 /* write cmd to Set CGCG Overrride */
4473 fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
4474
4475 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
4476 gfx_v8_0_wait_for_rlc_serdes(adev);
4477
4478 /* write cmd to Clear CGLS */
4479 fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
4480
4481 /* disable cgcg, cgls should be disabled too. */
4482 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
4483 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4484 if (temp != data)
4485 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
4486 }
4487}
4488static int fiji_update_gfx_clock_gating(struct amdgpu_device *adev,
4489 bool enable)
4490{
4491 if (enable) {
4492 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
4493 * === MGCG + MGLS + TS(CG/LS) ===
4494 */
4495 fiji_update_medium_grain_clock_gating(adev, enable);
4496 fiji_update_coarse_grain_clock_gating(adev, enable);
4497 } else {
4498 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
4499 * === CGCG + CGLS ===
4500 */
4501 fiji_update_coarse_grain_clock_gating(adev, enable);
4502 fiji_update_medium_grain_clock_gating(adev, enable);
4503 }
4504 return 0;
4505}
4506
4507static int gfx_v8_0_set_clockgating_state(void *handle,
4508 enum amd_clockgating_state state)
4509{
4510 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4511
4512 switch (adev->asic_type) {
4513 case CHIP_FIJI:
4514 fiji_update_gfx_clock_gating(adev,
4515 state == AMD_CG_STATE_GATE ? true : false);
4516 break;
4517 default:
4518 break;
4519 }
4520 return 0;
4521}
4522
4523static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4524{
4525 u32 rptr;
4526
4527 rptr = ring->adev->wb.wb[ring->rptr_offs];
4528
4529 return rptr;
4530}
4531
4532static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4533{
4534 struct amdgpu_device *adev = ring->adev;
4535 u32 wptr;
4536
4537 if (ring->use_doorbell)
4538 /* XXX check if swapping is necessary on BE */
4539 wptr = ring->adev->wb.wb[ring->wptr_offs];
4540 else
4541 wptr = RREG32(mmCP_RB0_WPTR);
4542
4543 return wptr;
4544}
4545
4546static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4547{
4548 struct amdgpu_device *adev = ring->adev;
4549
4550 if (ring->use_doorbell) {
4551 /* XXX check if swapping is necessary on BE */
4552 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4553 WDOORBELL32(ring->doorbell_index, ring->wptr);
4554 } else {
4555 WREG32(mmCP_RB0_WPTR, ring->wptr);
4556 (void)RREG32(mmCP_RB0_WPTR);
4557 }
4558}
4559
4560static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4561{
4562 u32 ref_and_mask, reg_mem_engine;
4563
4564 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
4565 switch (ring->me) {
4566 case 1:
4567 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
4568 break;
4569 case 2:
4570 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
4571 break;
4572 default:
4573 return;
4574 }
4575 reg_mem_engine = 0;
4576 } else {
4577 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
4578 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
4579 }
4580
4581 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4582 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
4583 WAIT_REG_MEM_FUNCTION(3) | /* == */
4584 reg_mem_engine));
4585 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
4586 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
4587 amdgpu_ring_write(ring, ref_and_mask);
4588 amdgpu_ring_write(ring, ref_and_mask);
4589 amdgpu_ring_write(ring, 0x20); /* poll interval */
4590}
4591
4592static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
4593{
4594 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4595 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4596 WRITE_DATA_DST_SEL(0) |
4597 WR_CONFIRM));
4598 amdgpu_ring_write(ring, mmHDP_DEBUG0);
4599 amdgpu_ring_write(ring, 0);
4600 amdgpu_ring_write(ring, 1);
4601
4602}
4603
4604static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4605 struct amdgpu_ib *ib)
4606{
4607 bool need_ctx_switch = ring->current_ctx != ib->ctx;
4608 u32 header, control = 0;
4609 u32 next_rptr = ring->wptr + 5;
4610
4611 /* drop the CE preamble IB for the same context */
4612 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
4613 return;
4614
4615 if (need_ctx_switch)
4616 next_rptr += 2;
4617
4618 next_rptr += 4;
4619 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4620 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4621 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4622 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4623 amdgpu_ring_write(ring, next_rptr);
4624
4625 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
4626 if (need_ctx_switch) {
4627 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4628 amdgpu_ring_write(ring, 0);
4629 }
4630
4631 if (ib->flags & AMDGPU_IB_FLAG_CE)
4632 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
4633 else
4634 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4635
4636 control |= ib->length_dw | (ib->vm_id << 24);
4637
4638 amdgpu_ring_write(ring, header);
4639 amdgpu_ring_write(ring,
4640#ifdef __BIG_ENDIAN
4641 (2 << 0) |
4642#endif
4643 (ib->gpu_addr & 0xFFFFFFFC));
4644 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4645 amdgpu_ring_write(ring, control);
4646}
4647
4648static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4649 struct amdgpu_ib *ib)
4650{
4651 u32 header, control = 0;
4652 u32 next_rptr = ring->wptr + 5;
4653
4654 control |= INDIRECT_BUFFER_VALID;
4655
4656 next_rptr += 4;
4657 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4658 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4659 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4660 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4661 amdgpu_ring_write(ring, next_rptr);
4662
4663 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4664
4665 control |= ib->length_dw | (ib->vm_id << 24);
4666
4667 amdgpu_ring_write(ring, header);
4668 amdgpu_ring_write(ring,
4669#ifdef __BIG_ENDIAN
4670 (2 << 0) |
4671#endif
4672 (ib->gpu_addr & 0xFFFFFFFC));
4673 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4674 amdgpu_ring_write(ring, control);
4675}
4676
4677static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
4678 u64 seq, unsigned flags)
4679{
4680 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4681 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4682
4683 /* EVENT_WRITE_EOP - flush caches, send int */
4684 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
4685 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4686 EOP_TC_ACTION_EN |
4687 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4688 EVENT_INDEX(5)));
4689 amdgpu_ring_write(ring, addr & 0xfffffffc);
4690 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
4691 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4692 amdgpu_ring_write(ring, lower_32_bits(seq));
4693 amdgpu_ring_write(ring, upper_32_bits(seq));
4694
4695}
4696
4697static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4698{
4699 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4700 uint32_t seq = ring->fence_drv.sync_seq;
4701 uint64_t addr = ring->fence_drv.gpu_addr;
4702
4703 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4704 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4705 WAIT_REG_MEM_FUNCTION(3) | /* equal */
4706 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
4707 amdgpu_ring_write(ring, addr & 0xfffffffc);
4708 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
4709 amdgpu_ring_write(ring, seq);
4710 amdgpu_ring_write(ring, 0xffffffff);
4711 amdgpu_ring_write(ring, 4); /* poll interval */
4712
4713 if (usepfp) {
4714 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4715 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4716 amdgpu_ring_write(ring, 0);
4717 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4718 amdgpu_ring_write(ring, 0);
4719 }
4720}
4721
4722static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4723 unsigned vm_id, uint64_t pd_addr)
4724{
4725 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4726
4727 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4728 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4729 WRITE_DATA_DST_SEL(0)) |
4730 WR_CONFIRM);
4731 if (vm_id < 8) {
4732 amdgpu_ring_write(ring,
4733 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4734 } else {
4735 amdgpu_ring_write(ring,
4736 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4737 }
4738 amdgpu_ring_write(ring, 0);
4739 amdgpu_ring_write(ring, pd_addr >> 12);
4740
4741 /* bits 0-15 are the VM contexts0-15 */
4742 /* invalidate the cache */
4743 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4744 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4745 WRITE_DATA_DST_SEL(0)));
4746 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4747 amdgpu_ring_write(ring, 0);
4748 amdgpu_ring_write(ring, 1 << vm_id);
4749
4750 /* wait for the invalidate to complete */
4751 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4752 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4753 WAIT_REG_MEM_FUNCTION(0) | /* always */
4754 WAIT_REG_MEM_ENGINE(0))); /* me */
4755 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4756 amdgpu_ring_write(ring, 0);
4757 amdgpu_ring_write(ring, 0); /* ref */
4758 amdgpu_ring_write(ring, 0); /* mask */
4759 amdgpu_ring_write(ring, 0x20); /* poll interval */
4760
4761 /* compute doesn't have PFP */
4762 if (usepfp) {
4763 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4764 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4765 amdgpu_ring_write(ring, 0x0);
4766 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4767 amdgpu_ring_write(ring, 0);
4768 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4769 amdgpu_ring_write(ring, 0);
4770 }
4771}
4772
4773static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4774{
4775 return ring->adev->wb.wb[ring->rptr_offs];
4776}
4777
4778static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4779{
4780 return ring->adev->wb.wb[ring->wptr_offs];
4781}
4782
4783static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4784{
4785 struct amdgpu_device *adev = ring->adev;
4786
4787 /* XXX check if swapping is necessary on BE */
4788 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4789 WDOORBELL32(ring->doorbell_index, ring->wptr);
4790}
4791
4792static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4793 u64 addr, u64 seq,
4794 unsigned flags)
4795{
4796 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4797 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4798
4799 /* RELEASE_MEM - flush caches, send int */
4800 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4801 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4802 EOP_TC_ACTION_EN |
4803 EOP_TC_WB_ACTION_EN |
4804 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4805 EVENT_INDEX(5)));
4806 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4807 amdgpu_ring_write(ring, addr & 0xfffffffc);
4808 amdgpu_ring_write(ring, upper_32_bits(addr));
4809 amdgpu_ring_write(ring, lower_32_bits(seq));
4810 amdgpu_ring_write(ring, upper_32_bits(seq));
4811}
4812
4813static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4814 enum amdgpu_interrupt_state state)
4815{
4816 u32 cp_int_cntl;
4817
4818 switch (state) {
4819 case AMDGPU_IRQ_STATE_DISABLE:
4820 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4821 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4822 TIME_STAMP_INT_ENABLE, 0);
4823 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4824 break;
4825 case AMDGPU_IRQ_STATE_ENABLE:
4826 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4827 cp_int_cntl =
4828 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4829 TIME_STAMP_INT_ENABLE, 1);
4830 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4831 break;
4832 default:
4833 break;
4834 }
4835}
4836
4837static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4838 int me, int pipe,
4839 enum amdgpu_interrupt_state state)
4840{
4841 u32 mec_int_cntl, mec_int_cntl_reg;
4842
4843 /*
4844 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4845 * handles the setting of interrupts for this specific pipe. All other
4846 * pipes' interrupts are set by amdkfd.
4847 */
4848
4849 if (me == 1) {
4850 switch (pipe) {
4851 case 0:
4852 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4853 break;
4854 default:
4855 DRM_DEBUG("invalid pipe %d\n", pipe);
4856 return;
4857 }
4858 } else {
4859 DRM_DEBUG("invalid me %d\n", me);
4860 return;
4861 }
4862
4863 switch (state) {
4864 case AMDGPU_IRQ_STATE_DISABLE:
4865 mec_int_cntl = RREG32(mec_int_cntl_reg);
4866 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4867 TIME_STAMP_INT_ENABLE, 0);
4868 WREG32(mec_int_cntl_reg, mec_int_cntl);
4869 break;
4870 case AMDGPU_IRQ_STATE_ENABLE:
4871 mec_int_cntl = RREG32(mec_int_cntl_reg);
4872 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4873 TIME_STAMP_INT_ENABLE, 1);
4874 WREG32(mec_int_cntl_reg, mec_int_cntl);
4875 break;
4876 default:
4877 break;
4878 }
4879}
4880
4881static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4882 struct amdgpu_irq_src *source,
4883 unsigned type,
4884 enum amdgpu_interrupt_state state)
4885{
4886 u32 cp_int_cntl;
4887
4888 switch (state) {
4889 case AMDGPU_IRQ_STATE_DISABLE:
4890 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4891 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4892 PRIV_REG_INT_ENABLE, 0);
4893 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4894 break;
4895 case AMDGPU_IRQ_STATE_ENABLE:
4896 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4897 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4898 PRIV_REG_INT_ENABLE, 1);
4899 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4900 break;
4901 default:
4902 break;
4903 }
4904
4905 return 0;
4906}
4907
4908static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4909 struct amdgpu_irq_src *source,
4910 unsigned type,
4911 enum amdgpu_interrupt_state state)
4912{
4913 u32 cp_int_cntl;
4914
4915 switch (state) {
4916 case AMDGPU_IRQ_STATE_DISABLE:
4917 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4918 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4919 PRIV_INSTR_INT_ENABLE, 0);
4920 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4921 break;
4922 case AMDGPU_IRQ_STATE_ENABLE:
4923 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4924 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4925 PRIV_INSTR_INT_ENABLE, 1);
4926 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4927 break;
4928 default:
4929 break;
4930 }
4931
4932 return 0;
4933}
4934
4935static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4936 struct amdgpu_irq_src *src,
4937 unsigned type,
4938 enum amdgpu_interrupt_state state)
4939{
4940 switch (type) {
4941 case AMDGPU_CP_IRQ_GFX_EOP:
4942 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4943 break;
4944 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4945 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4946 break;
4947 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4948 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4949 break;
4950 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4951 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4952 break;
4953 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4954 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4955 break;
4956 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4957 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4958 break;
4959 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4960 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4961 break;
4962 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4963 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4964 break;
4965 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4966 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4967 break;
4968 default:
4969 break;
4970 }
4971 return 0;
4972}
4973
4974static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4975 struct amdgpu_irq_src *source,
4976 struct amdgpu_iv_entry *entry)
4977{
4978 int i;
4979 u8 me_id, pipe_id, queue_id;
4980 struct amdgpu_ring *ring;
4981
4982 DRM_DEBUG("IH: CP EOP\n");
4983 me_id = (entry->ring_id & 0x0c) >> 2;
4984 pipe_id = (entry->ring_id & 0x03) >> 0;
4985 queue_id = (entry->ring_id & 0x70) >> 4;
4986
4987 switch (me_id) {
4988 case 0:
4989 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4990 break;
4991 case 1:
4992 case 2:
4993 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4994 ring = &adev->gfx.compute_ring[i];
4995 /* Per-queue interrupt is supported for MEC starting from VI.
4996 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4997 */
4998 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4999 amdgpu_fence_process(ring);
5000 }
5001 break;
5002 }
5003 return 0;
5004}
5005
5006static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
5007 struct amdgpu_irq_src *source,
5008 struct amdgpu_iv_entry *entry)
5009{
5010 DRM_ERROR("Illegal register access in command stream\n");
5011 schedule_work(&adev->reset_work);
5012 return 0;
5013}
5014
5015static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
5016 struct amdgpu_irq_src *source,
5017 struct amdgpu_iv_entry *entry)
5018{
5019 DRM_ERROR("Illegal instruction in command stream\n");
5020 schedule_work(&adev->reset_work);
5021 return 0;
5022}
5023
5024const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
5025 .early_init = gfx_v8_0_early_init,
5026 .late_init = gfx_v8_0_late_init,
5027 .sw_init = gfx_v8_0_sw_init,
5028 .sw_fini = gfx_v8_0_sw_fini,
5029 .hw_init = gfx_v8_0_hw_init,
5030 .hw_fini = gfx_v8_0_hw_fini,
5031 .suspend = gfx_v8_0_suspend,
5032 .resume = gfx_v8_0_resume,
5033 .is_idle = gfx_v8_0_is_idle,
5034 .wait_for_idle = gfx_v8_0_wait_for_idle,
5035 .soft_reset = gfx_v8_0_soft_reset,
5036 .print_status = gfx_v8_0_print_status,
5037 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
5038 .set_powergating_state = gfx_v8_0_set_powergating_state,
5039};
5040
5041static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
5042 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
5043 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
5044 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
5045 .parse_cs = NULL,
5046 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
5047 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
5048 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
5049 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
5050 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
5051 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
5052 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
5053 .test_ring = gfx_v8_0_ring_test_ring,
5054 .test_ib = gfx_v8_0_ring_test_ib,
5055 .insert_nop = amdgpu_ring_insert_nop,
5056 .pad_ib = amdgpu_ring_generic_pad_ib,
5057};
5058
5059static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
5060 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
5061 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
5062 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
5063 .parse_cs = NULL,
5064 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
5065 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
5066 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
5067 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
5068 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
5069 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
5070 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
5071 .test_ring = gfx_v8_0_ring_test_ring,
5072 .test_ib = gfx_v8_0_ring_test_ib,
5073 .insert_nop = amdgpu_ring_insert_nop,
5074 .pad_ib = amdgpu_ring_generic_pad_ib,
5075};
5076
5077static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
5078{
5079 int i;
5080
5081 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5082 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
5083
5084 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5085 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
5086}
5087
5088static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
5089 .set = gfx_v8_0_set_eop_interrupt_state,
5090 .process = gfx_v8_0_eop_irq,
5091};
5092
5093static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
5094 .set = gfx_v8_0_set_priv_reg_fault_state,
5095 .process = gfx_v8_0_priv_reg_irq,
5096};
5097
5098static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
5099 .set = gfx_v8_0_set_priv_inst_fault_state,
5100 .process = gfx_v8_0_priv_inst_irq,
5101};
5102
5103static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
5104{
5105 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5106 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
5107
5108 adev->gfx.priv_reg_irq.num_types = 1;
5109 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
5110
5111 adev->gfx.priv_inst_irq.num_types = 1;
5112 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
5113}
5114
5115static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
5116{
5117 /* init asci gds info */
5118 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5119 adev->gds.gws.total_size = 64;
5120 adev->gds.oa.total_size = 16;
5121
5122 if (adev->gds.mem.total_size == 64 * 1024) {
5123 adev->gds.mem.gfx_partition_size = 4096;
5124 adev->gds.mem.cs_partition_size = 4096;
5125
5126 adev->gds.gws.gfx_partition_size = 4;
5127 adev->gds.gws.cs_partition_size = 4;
5128
5129 adev->gds.oa.gfx_partition_size = 4;
5130 adev->gds.oa.cs_partition_size = 1;
5131 } else {
5132 adev->gds.mem.gfx_partition_size = 1024;
5133 adev->gds.mem.cs_partition_size = 1024;
5134
5135 adev->gds.gws.gfx_partition_size = 16;
5136 adev->gds.gws.cs_partition_size = 16;
5137
5138 adev->gds.oa.gfx_partition_size = 4;
5139 adev->gds.oa.cs_partition_size = 4;
5140 }
5141}
5142
5143static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
5144{
5145 u32 data, mask;
5146
5147 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
5148 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
5149
5150 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
5151 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
5152
5153 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
5154
5155 return (~data) & mask;
5156}
5157
5158int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
5159 struct amdgpu_cu_info *cu_info)
5160{
5161 int i, j, k, counter, active_cu_number = 0;
5162 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5163
5164 if (!adev || !cu_info)
5165 return -EINVAL;
5166
5167 memset(cu_info, 0, sizeof(*cu_info));
5168
5169 mutex_lock(&adev->grbm_idx_mutex);
5170 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5171 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5172 mask = 1;
5173 ao_bitmap = 0;
5174 counter = 0;
5175 gfx_v8_0_select_se_sh(adev, i, j);
5176 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
5177 cu_info->bitmap[i][j] = bitmap;
5178
5179 for (k = 0; k < 16; k ++) {
5180 if (bitmap & mask) {
5181 if (counter < 2)
5182 ao_bitmap |= mask;
5183 counter ++;
5184 }
5185 mask <<= 1;
5186 }
5187 active_cu_number += counter;
5188 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5189 }
5190 }
5191 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5192 mutex_unlock(&adev->grbm_idx_mutex);
5193
5194 cu_info->number = active_cu_number;
5195 cu_info->ao_cu_mask = ao_cu_mask;
5196
5197 return 0;
5198}