1/*
   2 * Copyright 2007-8 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26
  27#include <drm/amdgpu_drm.h>
  28#include "amdgpu.h"
  29#include "amdgpu_i2c.h"
  30#include "atom.h"
  31#include "amdgpu_connectors.h"
  32#include "amdgpu_display.h"
  33#include <asm/div64.h>
  34
  35#include <linux/pci.h>
  36#include <linux/pm_runtime.h>
  37#include <drm/drm_crtc_helper.h>
  38#include <drm/drm_edid.h>
  39#include <drm/drm_gem_framebuffer_helper.h>
  40#include <drm/drm_fb_helper.h>
  41#include <drm/drm_fourcc.h>
  42#include <drm/drm_vblank.h>
  43
  44static void amdgpu_display_flip_callback(struct dma_fence *f,
  45					 struct dma_fence_cb *cb)
  46{
  47	struct amdgpu_flip_work *work =
  48		container_of(cb, struct amdgpu_flip_work, cb);
  49
  50	dma_fence_put(f);
  51	schedule_work(&work->flip_work.work);
  52}
  53
  54static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
  55					     struct dma_fence **f)
  56{
  57	struct dma_fence *fence= *f;
  58
  59	if (fence == NULL)
  60		return false;
  61
  62	*f = NULL;
  63
  64	if (!dma_fence_add_callback(fence, &work->cb,
  65				    amdgpu_display_flip_callback))
  66		return true;
  67
  68	dma_fence_put(fence);
  69	return false;
  70}
  71
  72static void amdgpu_display_flip_work_func(struct work_struct *__work)
  73{
  74	struct delayed_work *delayed_work =
  75		container_of(__work, struct delayed_work, work);
  76	struct amdgpu_flip_work *work =
  77		container_of(delayed_work, struct amdgpu_flip_work, flip_work);
  78	struct amdgpu_device *adev = work->adev;
  79	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
  80
  81	struct drm_crtc *crtc = &amdgpu_crtc->base;
  82	unsigned long flags;
  83	unsigned i;
  84	int vpos, hpos;
 
  85
  86	if (amdgpu_display_flip_handle_fence(work, &work->excl))
  87		return;
  88
  89	for (i = 0; i < work->shared_count; ++i)
  90		if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
  91			return;
  92
  93	/* Wait until we're out of the vertical blank period before the one
  94	 * targeted by the flip
  95	 */
  96	if (amdgpu_crtc->enabled &&
  97	    (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
  98						&vpos, &hpos, NULL, NULL,
  99						&crtc->hwmode)
 100	     & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 101	    (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 102	    (int)(work->target_vblank -
 103		  amdgpu_get_vblank_counter_kms(crtc)) > 0) {
 104		schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
 105		return;
 106	}
 107
 108	/* We borrow the event spin lock for protecting flip_status */
 109	spin_lock_irqsave(&crtc->dev->event_lock, flags);
 110
 111	/* Do the flip (mmio) */
 112	adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 113
 114	/* Set the flip status */
 115	amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 116	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 
 
 
 
 
 
 
 
 117
 
 
 
 
 
 
 118
 119	DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 120					 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 
 121
 
 
 122}
 123
 124/*
 125 * Handle unpin events outside the interrupt handler proper.
 126 */
 127static void amdgpu_display_unpin_work_func(struct work_struct *__work)
 128{
 129	struct amdgpu_flip_work *work =
 130		container_of(__work, struct amdgpu_flip_work, unpin_work);
 131	int r;
 132
 133	/* unpin of the old buffer */
 134	r = amdgpu_bo_reserve(work->old_abo, true);
 135	if (likely(r == 0)) {
 136		amdgpu_bo_unpin(work->old_abo);
 137		amdgpu_bo_unreserve(work->old_abo);
 
 
 
 138	} else
 139		DRM_ERROR("failed to reserve buffer after flip\n");
 140
 141	amdgpu_bo_unref(&work->old_abo);
 142	kfree(work->shared);
 143	kfree(work);
 144}
 145
 146int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 147				struct drm_framebuffer *fb,
 148				struct drm_pending_vblank_event *event,
 149				uint32_t page_flip_flags, uint32_t target,
 150				struct drm_modeset_acquire_ctx *ctx)
 151{
 152	struct drm_device *dev = crtc->dev;
 153	struct amdgpu_device *adev = drm_to_adev(dev);
 154	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 
 
 155	struct drm_gem_object *obj;
 156	struct amdgpu_flip_work *work;
 157	struct amdgpu_bo *new_abo;
 158	unsigned long flags;
 159	u64 tiling_flags;
 
 160	int i, r;
 161
 162	work = kzalloc(sizeof *work, GFP_KERNEL);
 163	if (work == NULL)
 164		return -ENOMEM;
 165
 166	INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
 167	INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
 168
 169	work->event = event;
 170	work->adev = adev;
 171	work->crtc_id = amdgpu_crtc->crtc_id;
 172	work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 173
 174	/* schedule unpin of the old buffer */
 175	obj = crtc->primary->fb->obj[0];
 
 176
 177	/* take a reference to the old object */
 178	work->old_abo = gem_to_amdgpu_bo(obj);
 179	amdgpu_bo_ref(work->old_abo);
 180
 181	obj = fb->obj[0];
 182	new_abo = gem_to_amdgpu_bo(obj);
 
 183
 184	/* pin the new buffer */
 185	r = amdgpu_bo_reserve(new_abo, false);
 186	if (unlikely(r != 0)) {
 187		DRM_ERROR("failed to reserve new abo buffer before flip\n");
 188		goto cleanup;
 189	}
 190
 191	if (!adev->enable_virtual_display) {
 192		r = amdgpu_bo_pin(new_abo,
 193				  amdgpu_display_supported_domains(adev, new_abo->flags));
 194		if (unlikely(r != 0)) {
 195			DRM_ERROR("failed to pin new abo buffer before flip\n");
 196			goto unreserve;
 197		}
 198	}
 199
 200	r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
 201	if (unlikely(r != 0)) {
 202		DRM_ERROR("%p bind failed\n", new_abo);
 203		goto unpin;
 
 
 204	}
 205
 206	r = dma_resv_get_fences(new_abo->tbo.base.resv, &work->excl,
 207				&work->shared_count, &work->shared);
 
 208	if (unlikely(r != 0)) {
 
 209		DRM_ERROR("failed to get fences for buffer\n");
 210		goto unpin;
 211	}
 212
 213	amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 214	amdgpu_bo_unreserve(new_abo);
 215
 216	if (!adev->enable_virtual_display)
 217		work->base = amdgpu_bo_gpu_offset(new_abo);
 218	work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 219		amdgpu_get_vblank_counter_kms(crtc);
 
 
 
 220
 221	/* we borrow the event spin lock for protecting flip_wrok */
 222	spin_lock_irqsave(&crtc->dev->event_lock, flags);
 223	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 224		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 225		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 226		r = -EBUSY;
 227		goto pflip_cleanup;
 228	}
 229
 230	amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 231	amdgpu_crtc->pflip_works = work;
 232
 233
 234	DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 235					 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 236	/* update crtc fb */
 237	crtc->primary->fb = fb;
 238	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 239	amdgpu_display_flip_work_func(&work->flip_work.work);
 240	return 0;
 241
 
 
 
 242pflip_cleanup:
 243	if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 244		DRM_ERROR("failed to reserve new abo in error path\n");
 245		goto cleanup;
 246	}
 247unpin:
 248	if (!adev->enable_virtual_display)
 249		amdgpu_bo_unpin(new_abo);
 250
 251unreserve:
 252	amdgpu_bo_unreserve(new_abo);
 253
 254cleanup:
 255	amdgpu_bo_unref(&work->old_abo);
 256	dma_fence_put(work->excl);
 257	for (i = 0; i < work->shared_count; ++i)
 258		dma_fence_put(work->shared[i]);
 259	kfree(work->shared);
 260	kfree(work);
 261
 262	return r;
 263}
 264
 265int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 266				   struct drm_modeset_acquire_ctx *ctx)
 267{
 268	struct drm_device *dev;
 269	struct amdgpu_device *adev;
 270	struct drm_crtc *crtc;
 271	bool active = false;
 272	int ret;
 273
 274	if (!set || !set->crtc)
 275		return -EINVAL;
 276
 277	dev = set->crtc->dev;
 278
 279	ret = pm_runtime_get_sync(dev->dev);
 280	if (ret < 0)
 281		goto out;
 282
 283	ret = drm_crtc_helper_set_config(set, ctx);
 284
 285	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 286		if (crtc->enabled)
 287			active = true;
 288
 289	pm_runtime_mark_last_busy(dev->dev);
 290
 291	adev = drm_to_adev(dev);
 292	/* if we have active crtcs and we don't have a power ref,
 293	   take the current one */
 294	if (active && !adev->have_disp_power_ref) {
 295		adev->have_disp_power_ref = true;
 296		return ret;
 297	}
 298	/* if we have no active crtcs, then drop the power ref
 299	   we got before */
 300	if (!active && adev->have_disp_power_ref) {
 301		pm_runtime_put_autosuspend(dev->dev);
 302		adev->have_disp_power_ref = false;
 303	}
 304
 305out:
 306	/* drop the power reference we got coming in here */
 307	pm_runtime_put_autosuspend(dev->dev);
 308	return ret;
 309}
 310
 311static const char *encoder_names[41] = {
 312	"NONE",
 313	"INTERNAL_LVDS",
 314	"INTERNAL_TMDS1",
 315	"INTERNAL_TMDS2",
 316	"INTERNAL_DAC1",
 317	"INTERNAL_DAC2",
 318	"INTERNAL_SDVOA",
 319	"INTERNAL_SDVOB",
 320	"SI170B",
 321	"CH7303",
 322	"CH7301",
 323	"INTERNAL_DVO1",
 324	"EXTERNAL_SDVOA",
 325	"EXTERNAL_SDVOB",
 326	"TITFP513",
 327	"INTERNAL_LVTM1",
 328	"VT1623",
 329	"HDMI_SI1930",
 330	"HDMI_INTERNAL",
 331	"INTERNAL_KLDSCP_TMDS1",
 332	"INTERNAL_KLDSCP_DVO1",
 333	"INTERNAL_KLDSCP_DAC1",
 334	"INTERNAL_KLDSCP_DAC2",
 335	"SI178",
 336	"MVPU_FPGA",
 337	"INTERNAL_DDI",
 338	"VT1625",
 339	"HDMI_SI1932",
 340	"DP_AN9801",
 341	"DP_DP501",
 342	"INTERNAL_UNIPHY",
 343	"INTERNAL_KLDSCP_LVTMA",
 344	"INTERNAL_UNIPHY1",
 345	"INTERNAL_UNIPHY2",
 346	"NUTMEG",
 347	"TRAVIS",
 348	"INTERNAL_VCE",
 349	"INTERNAL_UNIPHY3",
 350	"HDMI_ANX9805",
 351	"INTERNAL_AMCLK",
 352	"VIRTUAL",
 353};
 354
 355static const char *hpd_names[6] = {
 356	"HPD1",
 357	"HPD2",
 358	"HPD3",
 359	"HPD4",
 360	"HPD5",
 361	"HPD6",
 362};
 363
 364void amdgpu_display_print_display_setup(struct drm_device *dev)
 365{
 366	struct drm_connector *connector;
 367	struct amdgpu_connector *amdgpu_connector;
 368	struct drm_encoder *encoder;
 369	struct amdgpu_encoder *amdgpu_encoder;
 370	struct drm_connector_list_iter iter;
 371	uint32_t devices;
 372	int i = 0;
 373
 374	drm_connector_list_iter_begin(dev, &iter);
 375	DRM_INFO("AMDGPU Display Connectors\n");
 376	drm_for_each_connector_iter(connector, &iter) {
 377		amdgpu_connector = to_amdgpu_connector(connector);
 378		DRM_INFO("Connector %d:\n", i);
 379		DRM_INFO("  %s\n", connector->name);
 380		if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 381			DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 382		if (amdgpu_connector->ddc_bus) {
 383			DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 384				 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 385				 amdgpu_connector->ddc_bus->rec.mask_data_reg,
 386				 amdgpu_connector->ddc_bus->rec.a_clk_reg,
 387				 amdgpu_connector->ddc_bus->rec.a_data_reg,
 388				 amdgpu_connector->ddc_bus->rec.en_clk_reg,
 389				 amdgpu_connector->ddc_bus->rec.en_data_reg,
 390				 amdgpu_connector->ddc_bus->rec.y_clk_reg,
 391				 amdgpu_connector->ddc_bus->rec.y_data_reg);
 392			if (amdgpu_connector->router.ddc_valid)
 393				DRM_INFO("  DDC Router 0x%x/0x%x\n",
 394					 amdgpu_connector->router.ddc_mux_control_pin,
 395					 amdgpu_connector->router.ddc_mux_state);
 396			if (amdgpu_connector->router.cd_valid)
 397				DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 398					 amdgpu_connector->router.cd_mux_control_pin,
 399					 amdgpu_connector->router.cd_mux_state);
 400		} else {
 401			if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 402			    connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 403			    connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 404			    connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 405			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 406			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 407				DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 408		}
 409		DRM_INFO("  Encoders:\n");
 410		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 411			amdgpu_encoder = to_amdgpu_encoder(encoder);
 412			devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 413			if (devices) {
 414				if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 415					DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 416				if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 417					DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 418				if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 419					DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 420				if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 421					DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 422				if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 423					DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 424				if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 425					DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 426				if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 427					DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 428				if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 429					DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 430				if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 431					DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 432				if (devices & ATOM_DEVICE_TV1_SUPPORT)
 433					DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 434				if (devices & ATOM_DEVICE_CV_SUPPORT)
 435					DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 436			}
 437		}
 438		i++;
 439	}
 440	drm_connector_list_iter_end(&iter);
 441}
 442
 443bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 444			      bool use_aux)
 
 
 
 
 445{
 446	u8 out = 0x0;
 447	u8 buf[8];
 448	int ret;
 449	struct i2c_msg msgs[] = {
 450		{
 451			.addr = DDC_ADDR,
 452			.flags = 0,
 453			.len = 1,
 454			.buf = &out,
 455		},
 456		{
 457			.addr = DDC_ADDR,
 458			.flags = I2C_M_RD,
 459			.len = 8,
 460			.buf = buf,
 461		}
 462	};
 463
 464	/* on hw with routers, select right port */
 465	if (amdgpu_connector->router.ddc_valid)
 466		amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 467
 468	if (use_aux) {
 469		ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 470	} else {
 471		ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 472	}
 473
 474	if (ret != 2)
 475		/* Couldn't find an accessible DDC on this connector */
 476		return false;
 477	/* Probe also for valid EDID header
 478	 * EDID header starts with:
 479	 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 480	 * Only the first 6 bytes must be valid as
 481	 * drm_edid_block_valid() can fix the last 2 bytes */
 482	if (drm_edid_header_is_valid(buf) < 6) {
 483		/* Couldn't find an accessible EDID on this
 484		 * connector */
 485		return false;
 486	}
 487	return true;
 488}
 489
 490static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 491	.destroy = drm_gem_fb_destroy,
 492	.create_handle = drm_gem_fb_create_handle,
 493};
 494
 495uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 496					  uint64_t bo_flags)
 497{
 498	uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 499
 500#if defined(CONFIG_DRM_AMD_DC)
 501	/*
 502	 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
 503	 * is not supported for this board. But this mapping is required
 504	 * to avoid hang caused by placement of scanout BO in GTT on certain
 505	 * APUs. So force the BO placement to VRAM in case this architecture
 506	 * will not allow USWC mappings.
 507	 * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
 508	 */
 509	if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 510	    amdgpu_bo_support_uswc(bo_flags) &&
 511	    amdgpu_device_asic_has_dc_support(adev->asic_type)) {
 512		switch (adev->asic_type) {
 513		case CHIP_CARRIZO:
 514		case CHIP_STONEY:
 515			domain |= AMDGPU_GEM_DOMAIN_GTT;
 516			break;
 517		case CHIP_RAVEN:
 518			/* enable S/G on PCO and RV2 */
 519			if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
 520			    (adev->apu_flags & AMD_APU_IS_PICASSO))
 521				domain |= AMDGPU_GEM_DOMAIN_GTT;
 522			break;
 523		case CHIP_RENOIR:
 524		case CHIP_VANGOGH:
 525		case CHIP_YELLOW_CARP:
 526			domain |= AMDGPU_GEM_DOMAIN_GTT;
 527			break;
 528
 529		default:
 530			break;
 531		}
 532	}
 533#endif
 534
 535	return domain;
 536}
 537
 538static const struct drm_format_info dcc_formats[] = {
 539	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 540	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 541	 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 542	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 543	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 544	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 545	   .has_alpha = true, },
 546	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 547	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 548	  .has_alpha = true, },
 549	{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
 550	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 551	  .has_alpha = true, },
 552	{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
 553	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 554	{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
 555	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 556	{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
 557	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 558	  .has_alpha = true, },
 559	{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
 560	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 561	  .has_alpha = true, },
 562	{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
 563	  .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 564};
 565
 566static const struct drm_format_info dcc_retile_formats[] = {
 567	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
 568	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 569	 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 570	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 571	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 572	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 573	   .has_alpha = true, },
 574	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 575	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 576	  .has_alpha = true, },
 577	{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
 578	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 579	  .has_alpha = true, },
 580	{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
 581	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 582	{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
 583	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 584	{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
 585	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 586	  .has_alpha = true, },
 587	{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
 588	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 589	  .has_alpha = true, },
 590	{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
 591	  .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 592};
 593
 594static const struct drm_format_info *
 595lookup_format_info(const struct drm_format_info formats[],
 596		  int num_formats, u32 format)
 597{
 598	int i;
 599
 600	for (i = 0; i < num_formats; i++) {
 601		if (formats[i].format == format)
 602			return &formats[i];
 603	}
 604
 605	return NULL;
 606}
 607
 608const struct drm_format_info *
 609amdgpu_lookup_format_info(u32 format, uint64_t modifier)
 610{
 611	if (!IS_AMD_FMT_MOD(modifier))
 612		return NULL;
 613
 614	if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
 615		return lookup_format_info(dcc_retile_formats,
 616					  ARRAY_SIZE(dcc_retile_formats),
 617					  format);
 618
 619	if (AMD_FMT_MOD_GET(DCC, modifier))
 620		return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
 621					  format);
 622
 623	/* returning NULL will cause the default format structs to be used. */
 624	return NULL;
 625}
 626
 627
 628/*
 629 * Tries to extract the renderable DCC offset from the opaque metadata attached
 630 * to the buffer.
 631 */
 632static int
 633extract_render_dcc_offset(struct amdgpu_device *adev,
 634			  struct drm_gem_object *obj,
 635			  uint64_t *offset)
 636{
 637	struct amdgpu_bo *rbo;
 638	int r = 0;
 639	uint32_t metadata[10]; /* Something that fits a descriptor + header. */
 640	uint32_t size;
 641
 642	rbo = gem_to_amdgpu_bo(obj);
 643	r = amdgpu_bo_reserve(rbo, false);
 644
 645	if (unlikely(r)) {
 646		/* Don't show error message when returning -ERESTARTSYS */
 647		if (r != -ERESTARTSYS)
 648			DRM_ERROR("Unable to reserve buffer: %d\n", r);
 649		return r;
 650	}
 651
 652	r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
 653	amdgpu_bo_unreserve(rbo);
 654
 655	if (r)
 656		return r;
 657
 658	/*
 659	 * The first word is the metadata version, and we need space for at least
 660	 * the version + pci vendor+device id + 8 words for a descriptor.
 661	 */
 662	if (size < 40  || metadata[0] != 1)
 663		return -EINVAL;
 664
 665	if (adev->family >= AMDGPU_FAMILY_NV) {
 666		/* resource word 6/7 META_DATA_ADDRESS{_LO} */
 667		*offset = ((u64)metadata[9] << 16u) |
 668			  ((metadata[8] & 0xFF000000u) >> 16);
 669	} else {
 670		/* resource word 5/7 META_DATA_ADDRESS */
 671		*offset = ((u64)metadata[9] << 8u) |
 672			  ((u64)(metadata[7] & 0x1FE0000u) << 23);
 673	}
 674
 675	return 0;
 676}
 677
 678static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 679{
 680	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 681	uint64_t modifier = 0;
 682
 683	if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 684		modifier = DRM_FORMAT_MOD_LINEAR;
 685	} else {
 686		int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
 687		bool has_xor = swizzle >= 16;
 688		int block_size_bits;
 689		int version;
 690		int pipe_xor_bits = 0;
 691		int bank_xor_bits = 0;
 692		int packers = 0;
 693		int rb = 0;
 694		int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
 695		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 696
 697		switch (swizzle >> 2) {
 698		case 0: /* 256B */
 699			block_size_bits = 8;
 700			break;
 701		case 1: /* 4KiB */
 702		case 5: /* 4KiB _X */
 703			block_size_bits = 12;
 704			break;
 705		case 2: /* 64KiB */
 706		case 4: /* 64 KiB _T */
 707		case 6: /* 64 KiB _X */
 708			block_size_bits = 16;
 709			break;
 710		default:
 711			/* RESERVED or VAR */
 712			return -EINVAL;
 713		}
 714
 715		if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 716			version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 717		else if (adev->family == AMDGPU_FAMILY_NV)
 718			version = AMD_FMT_MOD_TILE_VER_GFX10;
 719		else
 720			version = AMD_FMT_MOD_TILE_VER_GFX9;
 721
 722		switch (swizzle & 3) {
 723		case 0: /* Z microtiling */
 724			return -EINVAL;
 725		case 1: /* S microtiling */
 726			if (!has_xor)
 727				version = AMD_FMT_MOD_TILE_VER_GFX9;
 728			break;
 729		case 2:
 730			if (!has_xor && afb->base.format->cpp[0] != 4)
 731				version = AMD_FMT_MOD_TILE_VER_GFX9;
 732			break;
 733		case 3:
 734			break;
 735		}
 736
 737		if (has_xor) {
 738			switch (version) {
 739			case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 740				pipe_xor_bits = min(block_size_bits - 8, pipes);
 741				packers = min(block_size_bits - 8 - pipe_xor_bits,
 742					      ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
 743				break;
 744			case AMD_FMT_MOD_TILE_VER_GFX10:
 745				pipe_xor_bits = min(block_size_bits - 8, pipes);
 746				break;
 747			case AMD_FMT_MOD_TILE_VER_GFX9:
 748				rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
 749				     ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
 750				pipe_xor_bits = min(block_size_bits - 8, pipes +
 751						    ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
 752				bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
 753						    ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
 754				break;
 755			}
 756		}
 757
 758		modifier = AMD_FMT_MOD |
 759			   AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
 760			   AMD_FMT_MOD_SET(TILE_VERSION, version) |
 761			   AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
 762			   AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
 763			   AMD_FMT_MOD_SET(PACKERS, packers);
 764
 765		if (dcc_offset != 0) {
 766			bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
 767			bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 768			const struct drm_format_info *format_info;
 769			u64 render_dcc_offset;
 770
 771			/* Enable constant encode on RAVEN2 and later. */
 772			bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
 773						   (adev->asic_type == CHIP_RAVEN &&
 774						    adev->external_rev_id >= 0x81);
 775
 776			int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 777					      dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
 778					      AMD_FMT_MOD_DCC_BLOCK_256B;
 779
 780			modifier |= AMD_FMT_MOD_SET(DCC, 1) |
 781				    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
 782				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
 783				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
 784				    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
 785
 786			afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
 787			afb->base.pitches[1] =
 788				AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
 789
 790			/*
 791			 * If the userspace driver uses retiling the tiling flags do not contain
 792			 * info on the renderable DCC buffer. Luckily the opaque metadata contains
 793			 * the info so we can try to extract it. The kernel does not use this info
 794			 * but we should convert it to a modifier plane for getfb2, so the
 795			 * userspace driver that gets it doesn't have to juggle around another DCC
 796			 * plane internally.
 797			 */
 798			if (extract_render_dcc_offset(adev, afb->base.obj[0],
 799						      &render_dcc_offset) == 0 &&
 800			    render_dcc_offset != 0 &&
 801			    render_dcc_offset != afb->base.offsets[1] &&
 802			    render_dcc_offset < UINT_MAX) {
 803				uint32_t dcc_block_bits;  /* of base surface data */
 804
 805				modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
 806				afb->base.offsets[2] = render_dcc_offset;
 807
 808				if (adev->family >= AMDGPU_FAMILY_NV) {
 809					int extra_pipe = 0;
 810
 811					if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
 812					    pipes == packers && pipes > 1)
 813						extra_pipe = 1;
 814
 815					dcc_block_bits = max(20, 16 + pipes + extra_pipe);
 816				} else {
 817					modifier |= AMD_FMT_MOD_SET(RB, rb) |
 818						    AMD_FMT_MOD_SET(PIPE, pipes);
 819					dcc_block_bits = max(20, 18 + rb);
 820				}
 821
 822				dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
 823				afb->base.pitches[2] = ALIGN(afb->base.width,
 824							     1u << ((dcc_block_bits + 1) / 2));
 825			}
 826			format_info = amdgpu_lookup_format_info(afb->base.format->format,
 827								modifier);
 828			if (!format_info)
 829				return -EINVAL;
 830
 831			afb->base.format = format_info;
 832		}
 833	}
 834
 835	afb->base.modifier = modifier;
 836	afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 837	return 0;
 838}
 839
 840/* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
 841static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
 842{
 843	u64 micro_tile_mode;
 844
 845	/* Zero swizzle mode means linear */
 846	if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
 847		return 0;
 848
 849	micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
 850	switch (micro_tile_mode) {
 851	case 0: /* DISPLAY */
 852	case 3: /* RENDER */
 853		return 0;
 854	default:
 855		drm_dbg_kms(afb->base.dev,
 856			    "Micro tile mode %llu not supported for scanout\n",
 857			    micro_tile_mode);
 858		return -EINVAL;
 859	}
 860}
 861
 862static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
 863				 unsigned int *width, unsigned int *height)
 864{
 865	unsigned int cpp_log2 = ilog2(cpp);
 866	unsigned int pixel_log2 = block_log2 - cpp_log2;
 867	unsigned int width_log2 = (pixel_log2 + 1) / 2;
 868	unsigned int height_log2 = pixel_log2 - width_log2;
 869
 870	*width = 1 << width_log2;
 871	*height = 1 << height_log2;
 872}
 873
 874static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
 875				       bool pipe_aligned)
 876{
 877	unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
 878
 879	switch (ver) {
 880	case AMD_FMT_MOD_TILE_VER_GFX9: {
 881		/*
 882		 * TODO: for pipe aligned we may need to check the alignment of the
 883		 * total size of the surface, which may need to be bigger than the
 884		 * natural alignment due to some HW workarounds
 885		 */
 886		return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
 887	}
 888	case AMD_FMT_MOD_TILE_VER_GFX10:
 889	case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: {
 890		int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 891
 892		if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
 893		    AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
 894			++pipes_log2;
 895
 896		return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
 897	}
 898	default:
 899		return 0;
 900	}
 901}
 902
 903static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
 904				       const struct drm_format_info *format,
 905				       unsigned int block_width, unsigned int block_height,
 906				       unsigned int block_size_log2)
 907{
 908	unsigned int width = rfb->base.width /
 909		((plane && plane < format->num_planes) ? format->hsub : 1);
 910	unsigned int height = rfb->base.height /
 911		((plane && plane < format->num_planes) ? format->vsub : 1);
 912	unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
 913	unsigned int block_pitch = block_width * cpp;
 914	unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
 915	unsigned int block_size = 1 << block_size_log2;
 916	uint64_t size;
 917
 918	if (rfb->base.pitches[plane] % block_pitch) {
 919		drm_dbg_kms(rfb->base.dev,
 920			    "pitch %d for plane %d is not a multiple of block pitch %d\n",
 921			    rfb->base.pitches[plane], plane, block_pitch);
 922		return -EINVAL;
 923	}
 924	if (rfb->base.pitches[plane] < min_pitch) {
 925		drm_dbg_kms(rfb->base.dev,
 926			    "pitch %d for plane %d is less than minimum pitch %d\n",
 927			    rfb->base.pitches[plane], plane, min_pitch);
 928		return -EINVAL;
 929	}
 930
 931	/* Force at least natural alignment. */
 932	if (rfb->base.offsets[plane] % block_size) {
 933		drm_dbg_kms(rfb->base.dev,
 934			    "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
 935			    rfb->base.offsets[plane], plane, block_size);
 936		return -EINVAL;
 937	}
 938
 939	size = rfb->base.offsets[plane] +
 940		(uint64_t)rfb->base.pitches[plane] / block_pitch *
 941		block_size * DIV_ROUND_UP(height, block_height);
 942
 943	if (rfb->base.obj[0]->size < size) {
 944		drm_dbg_kms(rfb->base.dev,
 945			    "BO size 0x%zx is less than 0x%llx required for plane %d\n",
 946			    rfb->base.obj[0]->size, size, plane);
 947		return -EINVAL;
 948	}
 949
 950	return 0;
 951}
 952
 953
 954static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
 955{
 956	const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
 957	uint64_t modifier = rfb->base.modifier;
 958	int ret;
 959	unsigned int i, block_width, block_height, block_size_log2;
 960
 961	if (!rfb->base.dev->mode_config.allow_fb_modifiers)
 962		return 0;
 963
 964	for (i = 0; i < format_info->num_planes; ++i) {
 965		if (modifier == DRM_FORMAT_MOD_LINEAR) {
 966			block_width = 256 / format_info->cpp[i];
 967			block_height = 1;
 968			block_size_log2 = 8;
 969		} else {
 970			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
 971
 972			switch ((swizzle & ~3) + 1) {
 973			case DC_SW_256B_S:
 974				block_size_log2 = 8;
 975				break;
 976			case DC_SW_4KB_S:
 977			case DC_SW_4KB_S_X:
 978				block_size_log2 = 12;
 979				break;
 980			case DC_SW_64KB_S:
 981			case DC_SW_64KB_S_T:
 982			case DC_SW_64KB_S_X:
 983				block_size_log2 = 16;
 984				break;
 985			default:
 986				drm_dbg_kms(rfb->base.dev,
 987					    "Swizzle mode with unknown block size: %d\n", swizzle);
 988				return -EINVAL;
 989			}
 990
 991			get_block_dimensions(block_size_log2, format_info->cpp[i],
 992					     &block_width, &block_height);
 993		}
 994
 995		ret = amdgpu_display_verify_plane(rfb, i, format_info,
 996						  block_width, block_height, block_size_log2);
 997		if (ret)
 998			return ret;
 999	}
1000
1001	if (AMD_FMT_MOD_GET(DCC, modifier)) {
1002		if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1003			block_size_log2 = get_dcc_block_size(modifier, false, false);
1004			get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1005					     &block_width, &block_height);
1006			ret = amdgpu_display_verify_plane(rfb, i, format_info,
1007							  block_width, block_height,
1008							  block_size_log2);
1009			if (ret)
1010				return ret;
1011
1012			++i;
1013			block_size_log2 = get_dcc_block_size(modifier, true, true);
1014		} else {
1015			bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1016
1017			block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1018		}
1019		get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1020				     &block_width, &block_height);
1021		ret = amdgpu_display_verify_plane(rfb, i, format_info,
1022						  block_width, block_height, block_size_log2);
1023		if (ret)
1024			return ret;
1025	}
1026
1027	return 0;
1028}
1029
1030static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1031				      uint64_t *tiling_flags, bool *tmz_surface)
 
1032{
1033	struct amdgpu_bo *rbo;
1034	int r;
1035
1036	if (!amdgpu_fb) {
1037		*tiling_flags = 0;
1038		*tmz_surface = false;
1039		return 0;
1040	}
1041
1042	rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1043	r = amdgpu_bo_reserve(rbo, false);
1044
1045	if (unlikely(r)) {
1046		/* Don't show error message when returning -ERESTARTSYS */
1047		if (r != -ERESTARTSYS)
1048			DRM_ERROR("Unable to reserve buffer: %d\n", r);
1049		return r;
1050	}
1051
1052	if (tiling_flags)
1053		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1054
1055	if (tmz_surface)
1056		*tmz_surface = amdgpu_bo_encrypted(rbo);
1057
1058	amdgpu_bo_unreserve(rbo);
1059
1060	return r;
1061}
1062
1063int amdgpu_display_gem_fb_init(struct drm_device *dev,
1064			       struct amdgpu_framebuffer *rfb,
1065			       const struct drm_mode_fb_cmd2 *mode_cmd,
1066			       struct drm_gem_object *obj)
1067{
1068	int ret;
1069
1070	rfb->base.obj[0] = obj;
1071	drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1072
1073	ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1074	if (ret)
1075		goto err;
1076
1077	ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1078	if (ret)
1079		goto err;
1080
1081	return 0;
1082err:
1083	drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);
1084	rfb->base.obj[0] = NULL;
1085	return ret;
1086}
1087
1088int amdgpu_display_gem_fb_verify_and_init(
1089	struct drm_device *dev, struct amdgpu_framebuffer *rfb,
1090	struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
1091	struct drm_gem_object *obj)
 
1092{
1093	int ret;
1094
1095	rfb->base.obj[0] = obj;
1096	drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1097	/* Verify that the modifier is supported. */
1098	if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1099				      mode_cmd->modifier[0])) {
1100		drm_dbg_kms(dev,
1101			    "unsupported pixel format %p4cc / modifier 0x%llx\n",
1102			    &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1103
1104		ret = -EINVAL;
1105		goto err;
1106	}
1107
1108	ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1109	if (ret)
1110		goto err;
1111
1112	ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1113	if (ret)
1114		goto err;
1115
1116	return 0;
1117err:
1118	drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1119	rfb->base.obj[0] = NULL;
1120	return ret;
1121}
1122
1123int amdgpu_display_framebuffer_init(struct drm_device *dev,
1124				    struct amdgpu_framebuffer *rfb,
1125				    const struct drm_mode_fb_cmd2 *mode_cmd,
1126				    struct drm_gem_object *obj)
1127{
1128	struct amdgpu_device *adev = drm_to_adev(dev);
1129	int ret, i;
1130
1131	/*
1132	 * This needs to happen before modifier conversion as that might change
1133	 * the number of planes.
1134	 */
1135	for (i = 1; i < rfb->base.format->num_planes; ++i) {
1136		if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1137			drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1138				    i, mode_cmd->handles[0], mode_cmd->handles[i]);
1139			ret = -EINVAL;
1140			return ret;
1141		}
1142	}
1143
1144	ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1145	if (ret)
1146		return ret;
1147
1148	if (!dev->mode_config.allow_fb_modifiers) {
1149		drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1150			      "GFX9+ requires FB check based on format modifier\n");
1151		ret = check_tiling_flags_gfx6(rfb);
1152		if (ret)
1153			return ret;
1154	}
1155
1156	if (dev->mode_config.allow_fb_modifiers &&
1157	    !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1158		ret = convert_tiling_flags_to_modifier(rfb);
1159		if (ret) {
1160			drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1161				    rfb->tiling_flags);
1162			return ret;
1163		}
1164	}
1165
1166	ret = amdgpu_display_verify_sizes(rfb);
1167	if (ret)
1168		return ret;
1169
1170	for (i = 0; i < rfb->base.format->num_planes; ++i) {
1171		drm_gem_object_get(rfb->base.obj[0]);
1172		rfb->base.obj[i] = rfb->base.obj[0];
1173	}
1174
1175	return 0;
1176}
1177
1178struct drm_framebuffer *
1179amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1180				       struct drm_file *file_priv,
1181				       const struct drm_mode_fb_cmd2 *mode_cmd)
1182{
1183	struct amdgpu_framebuffer *amdgpu_fb;
1184	struct drm_gem_object *obj;
1185	struct amdgpu_bo *bo;
1186	uint32_t domains;
1187	int ret;
1188
1189	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1190	if (obj ==  NULL) {
1191		drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
1192			    "can't create framebuffer\n", mode_cmd->handles[0]);
1193		return ERR_PTR(-ENOENT);
1194	}
1195
1196	/* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1197	bo = gem_to_amdgpu_bo(obj);
1198	domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1199	if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1200		drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1201		drm_gem_object_put(obj);
1202		return ERR_PTR(-EINVAL);
1203	}
1204
1205	amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1206	if (amdgpu_fb == NULL) {
1207		drm_gem_object_put(obj);
1208		return ERR_PTR(-ENOMEM);
1209	}
1210
1211	ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1212						    mode_cmd, obj);
1213	if (ret) {
1214		kfree(amdgpu_fb);
1215		drm_gem_object_put(obj);
1216		return ERR_PTR(ret);
1217	}
1218
1219	drm_gem_object_put(obj);
1220	return &amdgpu_fb->base;
1221}
1222
 
 
 
 
 
 
1223const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1224	.fb_create = amdgpu_display_user_framebuffer_create,
1225	.output_poll_changed = drm_fb_helper_output_poll_changed,
1226};
1227
1228static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1229{	{ UNDERSCAN_OFF, "off" },
1230	{ UNDERSCAN_ON, "on" },
1231	{ UNDERSCAN_AUTO, "auto" },
1232};
1233
1234static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1235{	{ AMDGPU_AUDIO_DISABLE, "off" },
1236	{ AMDGPU_AUDIO_ENABLE, "on" },
1237	{ AMDGPU_AUDIO_AUTO, "auto" },
1238};
1239
1240/* XXX support different dither options? spatial, temporal, both, etc. */
1241static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1242{	{ AMDGPU_FMT_DITHER_DISABLE, "off" },
1243	{ AMDGPU_FMT_DITHER_ENABLE, "on" },
1244};
1245
1246int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1247{
1248	int sz;
1249
1250	adev->mode_info.coherent_mode_property =
1251		drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1252	if (!adev->mode_info.coherent_mode_property)
1253		return -ENOMEM;
 
 
1254
1255	adev->mode_info.load_detect_property =
1256		drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1257	if (!adev->mode_info.load_detect_property)
1258		return -ENOMEM;
1259
1260	drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1261
1262	sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1263	adev->mode_info.underscan_property =
1264		drm_property_create_enum(adev_to_drm(adev), 0,
1265					 "underscan",
1266					 amdgpu_underscan_enum_list, sz);
1267
1268	adev->mode_info.underscan_hborder_property =
1269		drm_property_create_range(adev_to_drm(adev), 0,
1270					  "underscan hborder", 0, 128);
1271	if (!adev->mode_info.underscan_hborder_property)
1272		return -ENOMEM;
1273
1274	adev->mode_info.underscan_vborder_property =
1275		drm_property_create_range(adev_to_drm(adev), 0,
1276					  "underscan vborder", 0, 128);
1277	if (!adev->mode_info.underscan_vborder_property)
1278		return -ENOMEM;
1279
1280	sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1281	adev->mode_info.audio_property =
1282		drm_property_create_enum(adev_to_drm(adev), 0,
1283					 "audio",
1284					 amdgpu_audio_enum_list, sz);
1285
1286	sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1287	adev->mode_info.dither_property =
1288		drm_property_create_enum(adev_to_drm(adev), 0,
1289					 "dither",
1290					 amdgpu_dither_enum_list, sz);
1291
1292	if (amdgpu_device_has_dc_support(adev)) {
1293		adev->mode_info.abm_level_property =
1294			drm_property_create_range(adev_to_drm(adev), 0,
1295						  "abm level", 0, 4);
1296		if (!adev->mode_info.abm_level_property)
1297			return -ENOMEM;
1298	}
1299
1300	return 0;
1301}
1302
1303void amdgpu_display_update_priority(struct amdgpu_device *adev)
1304{
1305	/* adjustment options for the display watermarks */
1306	if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1307		adev->mode_info.disp_priority = 0;
1308	else
1309		adev->mode_info.disp_priority = amdgpu_disp_priority;
1310
1311}
1312
1313static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1314{
1315	/* try and guess if this is a tv or a monitor */
1316	if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1317	    (mode->vdisplay == 576) || /* 576p */
1318	    (mode->vdisplay == 720) || /* 720p */
1319	    (mode->vdisplay == 1080)) /* 1080p */
1320		return true;
1321	else
1322		return false;
1323}
1324
1325bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1326					const struct drm_display_mode *mode,
1327					struct drm_display_mode *adjusted_mode)
1328{
1329	struct drm_device *dev = crtc->dev;
1330	struct drm_encoder *encoder;
1331	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1332	struct amdgpu_encoder *amdgpu_encoder;
1333	struct drm_connector *connector;
 
1334	u32 src_v = 1, dst_v = 1;
1335	u32 src_h = 1, dst_h = 1;
1336
1337	amdgpu_crtc->h_border = 0;
1338	amdgpu_crtc->v_border = 0;
1339
1340	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1341		if (encoder->crtc != crtc)
1342			continue;
1343		amdgpu_encoder = to_amdgpu_encoder(encoder);
1344		connector = amdgpu_get_connector_for_encoder(encoder);
 
1345
1346		/* set scaling */
1347		if (amdgpu_encoder->rmx_type == RMX_OFF)
1348			amdgpu_crtc->rmx_type = RMX_OFF;
1349		else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1350			 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1351			amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1352		else
1353			amdgpu_crtc->rmx_type = RMX_OFF;
1354		/* copy native mode */
1355		memcpy(&amdgpu_crtc->native_mode,
1356		       &amdgpu_encoder->native_mode,
1357		       sizeof(struct drm_display_mode));
1358		src_v = crtc->mode.vdisplay;
1359		dst_v = amdgpu_crtc->native_mode.vdisplay;
1360		src_h = crtc->mode.hdisplay;
1361		dst_h = amdgpu_crtc->native_mode.hdisplay;
1362
1363		/* fix up for overscan on hdmi */
1364		if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1365		    ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1366		     ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1367		      drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
1368		      amdgpu_display_is_hdtv_mode(mode)))) {
1369			if (amdgpu_encoder->underscan_hborder != 0)
1370				amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1371			else
1372				amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1373			if (amdgpu_encoder->underscan_vborder != 0)
1374				amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1375			else
1376				amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1377			amdgpu_crtc->rmx_type = RMX_FULL;
1378			src_v = crtc->mode.vdisplay;
1379			dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1380			src_h = crtc->mode.hdisplay;
1381			dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1382		}
1383	}
1384	if (amdgpu_crtc->rmx_type != RMX_OFF) {
1385		fixed20_12 a, b;
1386		a.full = dfixed_const(src_v);
1387		b.full = dfixed_const(dst_v);
1388		amdgpu_crtc->vsc.full = dfixed_div(a, b);
1389		a.full = dfixed_const(src_h);
1390		b.full = dfixed_const(dst_h);
1391		amdgpu_crtc->hsc.full = dfixed_div(a, b);
1392	} else {
1393		amdgpu_crtc->vsc.full = dfixed_const(1);
1394		amdgpu_crtc->hsc.full = dfixed_const(1);
1395	}
1396	return true;
1397}
1398
1399/*
1400 * Retrieve current video scanout position of crtc on a given gpu, and
1401 * an optional accurate timestamp of when query happened.
1402 *
1403 * \param dev Device to query.
1404 * \param pipe Crtc to query.
1405 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1406 *              For driver internal use only also supports these flags:
1407 *
1408 *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1409 *              of a fudged earlier start of vblank.
1410 *
1411 *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1412 *              fudged earlier start of vblank in *vpos and the distance
1413 *              to true start of vblank in *hpos.
1414 *
1415 * \param *vpos Location where vertical scanout position should be stored.
1416 * \param *hpos Location where horizontal scanout position should go.
1417 * \param *stime Target location for timestamp taken immediately before
1418 *               scanout position query. Can be NULL to skip timestamp.
1419 * \param *etime Target location for timestamp taken immediately after
1420 *               scanout position query. Can be NULL to skip timestamp.
1421 *
1422 * Returns vpos as a positive number while in active scanout area.
1423 * Returns vpos as a negative number inside vblank, counting the number
1424 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1425 * until start of active scanout / end of vblank."
1426 *
1427 * \return Flags, or'ed together as follows:
1428 *
1429 * DRM_SCANOUTPOS_VALID = Query successful.
1430 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1431 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1432 * this flag means that returned position may be offset by a constant but
1433 * unknown small number of scanlines wrt. real scanout position.
1434 *
1435 */
1436int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1437			unsigned int pipe, unsigned int flags, int *vpos,
1438			int *hpos, ktime_t *stime, ktime_t *etime,
1439			const struct drm_display_mode *mode)
1440{
1441	u32 vbl = 0, position = 0;
1442	int vbl_start, vbl_end, vtotal, ret = 0;
1443	bool in_vbl = true;
1444
1445	struct amdgpu_device *adev = drm_to_adev(dev);
1446
1447	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1448
1449	/* Get optional system timestamp before query. */
1450	if (stime)
1451		*stime = ktime_get();
1452
1453	if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1454		ret |= DRM_SCANOUTPOS_VALID;
1455
1456	/* Get optional system timestamp after query. */
1457	if (etime)
1458		*etime = ktime_get();
1459
1460	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1461
1462	/* Decode into vertical and horizontal scanout position. */
1463	*vpos = position & 0x1fff;
1464	*hpos = (position >> 16) & 0x1fff;
1465
1466	/* Valid vblank area boundaries from gpu retrieved? */
1467	if (vbl > 0) {
1468		/* Yes: Decode. */
1469		ret |= DRM_SCANOUTPOS_ACCURATE;
1470		vbl_start = vbl & 0x1fff;
1471		vbl_end = (vbl >> 16) & 0x1fff;
1472	}
1473	else {
1474		/* No: Fake something reasonable which gives at least ok results. */
1475		vbl_start = mode->crtc_vdisplay;
1476		vbl_end = 0;
1477	}
1478
1479	/* Called from driver internal vblank counter query code? */
1480	if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1481	    /* Caller wants distance from real vbl_start in *hpos */
1482	    *hpos = *vpos - vbl_start;
1483	}
1484
1485	/* Fudge vblank to start a few scanlines earlier to handle the
1486	 * problem that vblank irqs fire a few scanlines before start
1487	 * of vblank. Some driver internal callers need the true vblank
1488	 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1489	 *
1490	 * The cause of the "early" vblank irq is that the irq is triggered
1491	 * by the line buffer logic when the line buffer read position enters
1492	 * the vblank, whereas our crtc scanout position naturally lags the
1493	 * line buffer read position.
1494	 */
1495	if (!(flags & USE_REAL_VBLANKSTART))
1496		vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1497
1498	/* Test scanout position against vblank region. */
1499	if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1500		in_vbl = false;
1501
1502	/* In vblank? */
1503	if (in_vbl)
1504	    ret |= DRM_SCANOUTPOS_IN_VBLANK;
1505
1506	/* Called from driver internal vblank counter query code? */
1507	if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1508		/* Caller wants distance from fudged earlier vbl_start */
1509		*vpos -= vbl_start;
1510		return ret;
1511	}
1512
1513	/* Check if inside vblank area and apply corrective offsets:
1514	 * vpos will then be >=0 in video scanout area, but negative
1515	 * within vblank area, counting down the number of lines until
1516	 * start of scanout.
1517	 */
1518
1519	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
1520	if (in_vbl && (*vpos >= vbl_start)) {
1521		vtotal = mode->crtc_vtotal;
1522
1523		/* With variable refresh rate displays the vpos can exceed
1524		 * the vtotal value. Clamp to 0 to return -vbl_end instead
1525		 * of guessing the remaining number of lines until scanout.
1526		 */
1527		*vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1528	}
1529
1530	/* Correct for shifted end of vbl at vbl_end. */
1531	*vpos = *vpos - vbl_end;
1532
1533	return ret;
1534}
1535
1536int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1537{
1538	if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1539		return AMDGPU_CRTC_IRQ_NONE;
1540
1541	switch (crtc) {
1542	case 0:
1543		return AMDGPU_CRTC_IRQ_VBLANK1;
1544	case 1:
1545		return AMDGPU_CRTC_IRQ_VBLANK2;
1546	case 2:
1547		return AMDGPU_CRTC_IRQ_VBLANK3;
1548	case 3:
1549		return AMDGPU_CRTC_IRQ_VBLANK4;
1550	case 4:
1551		return AMDGPU_CRTC_IRQ_VBLANK5;
1552	case 5:
1553		return AMDGPU_CRTC_IRQ_VBLANK6;
1554	default:
1555		return AMDGPU_CRTC_IRQ_NONE;
1556	}
1557}
1558
1559bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1560			bool in_vblank_irq, int *vpos,
1561			int *hpos, ktime_t *stime, ktime_t *etime,
1562			const struct drm_display_mode *mode)
1563{
1564	struct drm_device *dev = crtc->dev;
1565	unsigned int pipe = crtc->index;
1566
1567	return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1568						  stime, etime, mode);
1569}
1570
1571int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1572{
1573	struct drm_device *dev = adev_to_drm(adev);
1574	struct drm_crtc *crtc;
1575	struct drm_connector *connector;
1576	struct drm_connector_list_iter iter;
1577	int r;
1578
1579	/* turn off display hw */
1580	drm_modeset_lock_all(dev);
1581	drm_connector_list_iter_begin(dev, &iter);
1582	drm_for_each_connector_iter(connector, &iter)
1583		drm_helper_connector_dpms(connector,
1584					  DRM_MODE_DPMS_OFF);
1585	drm_connector_list_iter_end(&iter);
1586	drm_modeset_unlock_all(dev);
1587	/* unpin the front buffers and cursors */
1588	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1589		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1590		struct drm_framebuffer *fb = crtc->primary->fb;
1591		struct amdgpu_bo *robj;
1592
1593		if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1594			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1595			r = amdgpu_bo_reserve(aobj, true);
1596			if (r == 0) {
1597				amdgpu_bo_unpin(aobj);
1598				amdgpu_bo_unreserve(aobj);
1599			}
1600		}
1601
1602		if (fb == NULL || fb->obj[0] == NULL) {
1603			continue;
1604		}
1605		robj = gem_to_amdgpu_bo(fb->obj[0]);
1606		/* don't unpin kernel fb objects */
1607		if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1608			r = amdgpu_bo_reserve(robj, true);
1609			if (r == 0) {
1610				amdgpu_bo_unpin(robj);
1611				amdgpu_bo_unreserve(robj);
1612			}
1613		}
1614	}
1615	return 0;
1616}
1617
1618int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1619{
1620	struct drm_device *dev = adev_to_drm(adev);
1621	struct drm_connector *connector;
1622	struct drm_connector_list_iter iter;
1623	struct drm_crtc *crtc;
1624	int r;
1625
1626	/* pin cursors */
1627	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1628		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1629
1630		if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1631			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1632			r = amdgpu_bo_reserve(aobj, true);
1633			if (r == 0) {
1634				r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1635				if (r != 0)
1636					dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1637				amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1638				amdgpu_bo_unreserve(aobj);
1639			}
1640		}
1641	}
1642
1643	drm_helper_resume_force_mode(dev);
1644
1645	/* turn on display hw */
1646	drm_modeset_lock_all(dev);
1647
1648	drm_connector_list_iter_begin(dev, &iter);
1649	drm_for_each_connector_iter(connector, &iter)
1650		drm_helper_connector_dpms(connector,
1651					  DRM_MODE_DPMS_ON);
1652	drm_connector_list_iter_end(&iter);
1653
1654	drm_modeset_unlock_all(dev);
1655
1656	return 0;
1657}
1658