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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11/dts-v1/;
12#include "fsl-ls1043a.dtsi"
13
14/ {
15 model = "LS1043A RDB Board";
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
17
18 aliases {
19 serial0 = &duart0;
20 serial1 = &duart1;
21 serial2 = &duart2;
22 serial3 = &duart3;
23 };
24
25 chosen {
26 stdout-path = "serial0:115200n8";
27 };
28};
29
30&i2c0 {
31 status = "okay";
32 ina220@40 {
33 compatible = "ti,ina220";
34 reg = <0x40>;
35 shunt-resistor = <1000>;
36 };
37 adt7461a@4c {
38 compatible = "adi,adt7461";
39 reg = <0x4c>;
40 };
41 eeprom@52 {
42 compatible = "atmel,24c512";
43 reg = <0x52>;
44 };
45 eeprom@53 {
46 compatible = "atmel,24c512";
47 reg = <0x53>;
48 };
49 rtc@68 {
50 compatible = "pericom,pt7c4338";
51 reg = <0x68>;
52 };
53};
54
55&ifc {
56 status = "okay";
57 #address-cells = <2>;
58 #size-cells = <1>;
59 /* NOR, NAND Flashes and FPGA on board */
60 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
61 0x1 0x0 0x0 0x7e800000 0x00010000
62 0x2 0x0 0x0 0x7fb00000 0x00000100>;
63
64 nor@0,0 {
65 compatible = "cfi-flash";
66 #address-cells = <1>;
67 #size-cells = <1>;
68 reg = <0x0 0x0 0x8000000>;
69 big-endian;
70 bank-width = <2>;
71 device-width = <1>;
72 };
73
74 nand@1,0 {
75 compatible = "fsl,ifc-nand";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 reg = <0x1 0x0 0x10000>;
79 };
80
81 cpld: board-control@2,0 {
82 compatible = "fsl,ls1043ardb-cpld";
83 reg = <0x2 0x0 0x0000100>;
84 };
85};
86
87&dspi0 {
88 bus-num = <0>;
89 status = "okay";
90
91 flash@0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
95 reg = <0>;
96 spi-max-frequency = <1000000>; /* input clock */
97 };
98
99 slic@2 {
100 compatible = "maxim,ds26522";
101 reg = <2>;
102 spi-max-frequency = <2000000>;
103 fsl,spi-cs-sck-delay = <100>;
104 fsl,spi-sck-cs-delay = <50>;
105 };
106
107 slic@3 {
108 compatible = "maxim,ds26522";
109 reg = <3>;
110 spi-max-frequency = <2000000>;
111 fsl,spi-cs-sck-delay = <100>;
112 fsl,spi-sck-cs-delay = <50>;
113 };
114};
115
116&duart0 {
117 status = "okay";
118};
119
120&duart1 {
121 status = "okay";
122};
123
124#include "fsl-ls1043-post.dtsi"
125
126&fman0 {
127 ethernet@e0000 {
128 phy-handle = <&qsgmii_phy1>;
129 phy-connection-type = "qsgmii";
130 };
131
132 ethernet@e2000 {
133 phy-handle = <&qsgmii_phy2>;
134 phy-connection-type = "qsgmii";
135 };
136
137 ethernet@e4000 {
138 phy-handle = <&rgmii_phy1>;
139 phy-connection-type = "rgmii-id";
140 };
141
142 ethernet@e6000 {
143 phy-handle = <&rgmii_phy2>;
144 phy-connection-type = "rgmii-id";
145 };
146
147 ethernet@e8000 {
148 phy-handle = <&qsgmii_phy3>;
149 phy-connection-type = "qsgmii";
150 };
151
152 ethernet@ea000 {
153 phy-handle = <&qsgmii_phy4>;
154 phy-connection-type = "qsgmii";
155 };
156
157 ethernet@f0000 { /* 10GEC1 */
158 phy-handle = <&aqr105_phy>;
159 phy-connection-type = "xgmii";
160 };
161
162 mdio@fc000 {
163 rgmii_phy1: ethernet-phy@1 {
164 reg = <0x1>;
165 };
166
167 rgmii_phy2: ethernet-phy@2 {
168 reg = <0x2>;
169 };
170
171 qsgmii_phy1: ethernet-phy@4 {
172 reg = <0x4>;
173 };
174
175 qsgmii_phy2: ethernet-phy@5 {
176 reg = <0x5>;
177 };
178
179 qsgmii_phy3: ethernet-phy@6 {
180 reg = <0x6>;
181 };
182
183 qsgmii_phy4: ethernet-phy@7 {
184 reg = <0x7>;
185 };
186 };
187
188 mdio@fd000 {
189 aqr105_phy: ethernet-phy@1 {
190 compatible = "ethernet-phy-ieee802.3-c45";
191 interrupts = <0 132 4>;
192 reg = <0x1>;
193 };
194 };
195};
196
197&uqe {
198 ucc_hdlc: ucc@2000 {
199 compatible = "fsl,ucc-hdlc";
200 rx-clock-name = "clk8";
201 tx-clock-name = "clk9";
202 fsl,rx-sync-clock = "rsync_pin";
203 fsl,tx-sync-clock = "tsync_pin";
204 fsl,tx-timeslot-mask = <0xfffffffe>;
205 fsl,rx-timeslot-mask = <0xfffffffe>;
206 fsl,tdm-framer-type = "e1";
207 fsl,tdm-id = <0>;
208 fsl,siram-entry-id = <0>;
209 fsl,tdm-interface;
210 };
211};
212
213&usb0 {
214 status = "okay";
215};
216
217&usb1 {
218 status = "okay";
219};
1/*
2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
3 *
4 * Copyright 2014-2015, Freescale Semiconductor
5 *
6 * Mingkai Hu <Mingkai.hu@freescale.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48/include/ "fsl-ls1043a.dtsi"
49
50/ {
51 model = "LS1043A RDB Board";
52};
53
54&i2c0 {
55 status = "okay";
56 ina220@40 {
57 compatible = "ti,ina220";
58 reg = <0x40>;
59 shunt-resistor = <1000>;
60 };
61 adt7461a@4c {
62 compatible = "adi,adt7461";
63 reg = <0x4c>;
64 };
65 eeprom@52 {
66 compatible = "at24,24c512";
67 reg = <0x52>;
68 };
69 eeprom@53 {
70 compatible = "at24,24c512";
71 reg = <0x53>;
72 };
73 rtc@68 {
74 compatible = "pericom,pt7c4338";
75 reg = <0x68>;
76 };
77};
78
79&ifc {
80 status = "okay";
81 #address-cells = <2>;
82 #size-cells = <1>;
83 /* NOR, NAND Flashes and FPGA on board */
84 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
85 0x1 0x0 0x0 0x7e800000 0x00010000
86 0x2 0x0 0x0 0x7fb00000 0x00000100>;
87
88 nor@0,0 {
89 compatible = "cfi-flash";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 reg = <0x0 0x0 0x8000000>;
93 bank-width = <2>;
94 device-width = <1>;
95 };
96
97 nand@1,0 {
98 compatible = "fsl,ifc-nand";
99 #address-cells = <1>;
100 #size-cells = <1>;
101 reg = <0x1 0x0 0x10000>;
102 };
103
104 cpld: board-control@2,0 {
105 compatible = "fsl,ls1043ardb-cpld";
106 reg = <0x2 0x0 0x0000100>;
107 };
108};
109
110&duart0 {
111 status = "okay";
112};
113
114&duart1 {
115 status = "okay";
116};