1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (c) 2019 BayLibre, SAS
  4 * Author: Neil Armstrong <narmstrong@baylibre.com>
  5 */
  6
  7#include "meson-g12.dtsi"
  8
  9/ {
 10	compatible = "amlogic,g12b";
 11
 12	cpus {
 13		#address-cells = <0x2>;
 14		#size-cells = <0x0>;
 15
 16		cpu-map {
 17			cluster0 {
 18				core0 {
 19					cpu = <&cpu0>;
 20				};
 21
 22				core1 {
 23					cpu = <&cpu1>;
 24				};
 25			};
 26
 27			cluster1 {
 28				core0 {
 29					cpu = <&cpu100>;
 30				};
 31
 32				core1 {
 33					cpu = <&cpu101>;
 34				};
 35
 36				core2 {
 37					cpu = <&cpu102>;
 38				};
 39
 40				core3 {
 41					cpu = <&cpu103>;
 42				};
 43			};
 44		};
 45
 46		cpu0: cpu@0 {
 47			device_type = "cpu";
 48			compatible = "arm,cortex-a53";
 49			reg = <0x0 0x0>;
 50			enable-method = "psci";
 51			capacity-dmips-mhz = <592>;
 52			next-level-cache = <&l2>;
 53			#cooling-cells = <2>;
 54		};
 55
 56		cpu1: cpu@1 {
 57			device_type = "cpu";
 58			compatible = "arm,cortex-a53";
 59			reg = <0x0 0x1>;
 60			enable-method = "psci";
 61			capacity-dmips-mhz = <592>;
 62			next-level-cache = <&l2>;
 63			#cooling-cells = <2>;
 64		};
 65
 66		cpu100: cpu@100 {
 67			device_type = "cpu";
 68			compatible = "arm,cortex-a73";
 69			reg = <0x0 0x100>;
 70			enable-method = "psci";
 71			capacity-dmips-mhz = <1024>;
 72			next-level-cache = <&l2>;
 73			#cooling-cells = <2>;
 74		};
 75
 76		cpu101: cpu@101 {
 77			device_type = "cpu";
 78			compatible = "arm,cortex-a73";
 79			reg = <0x0 0x101>;
 80			enable-method = "psci";
 81			capacity-dmips-mhz = <1024>;
 82			next-level-cache = <&l2>;
 83			#cooling-cells = <2>;
 84		};
 85
 86		cpu102: cpu@102 {
 87			device_type = "cpu";
 88			compatible = "arm,cortex-a73";
 89			reg = <0x0 0x102>;
 90			enable-method = "psci";
 91			capacity-dmips-mhz = <1024>;
 92			next-level-cache = <&l2>;
 93			#cooling-cells = <2>;
 94		};
 95
 96		cpu103: cpu@103 {
 97			device_type = "cpu";
 98			compatible = "arm,cortex-a73";
 99			reg = <0x0 0x103>;
100			enable-method = "psci";
101			capacity-dmips-mhz = <1024>;
102			next-level-cache = <&l2>;
103			#cooling-cells = <2>;
104		};
105
106		l2: l2-cache0 {
107			compatible = "cache";
108		};
109	};
110};
111
112&clkc {
113	compatible = "amlogic,g12b-clkc";
114};
115
116&cpu_thermal {
117	cooling-maps {
118		map0 {
119			trip = <&cpu_passive>;
120			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
121					 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
122					 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
123					 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
124					 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
125					 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
126		};
127		map1 {
128			trip = <&cpu_hot>;
129			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
130					 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
131					 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
132					 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
133					 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
134					 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
135		};
136	};
137};
138
139&mali {
140	dma-coherent;
141};