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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 */
7
8/ {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 compatible = "wm,wm8650";
12
13 cpus {
14 #address-cells = <0>;
15 #size-cells = <0>;
16
17 cpu {
18 device_type = "cpu";
19 compatible = "arm,arm926ej-s";
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x0 0x0>;
26 };
27
28 aliases {
29 serial0 = &uart0;
30 serial1 = &uart1;
31 };
32
33 soc {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "simple-bus";
37 ranges;
38 interrupt-parent = <&intc0>;
39
40 intc0: interrupt-controller@d8140000 {
41 compatible = "via,vt8500-intc";
42 interrupt-controller;
43 reg = <0xd8140000 0x10000>;
44 #interrupt-cells = <1>;
45 };
46
47 /* Secondary IC cascaded to intc0 */
48 intc1: interrupt-controller@d8150000 {
49 compatible = "via,vt8500-intc";
50 interrupt-controller;
51 #interrupt-cells = <1>;
52 reg = <0xD8150000 0x10000>;
53 interrupts = <56 57 58 59 60 61 62 63>;
54 };
55
56 pinctrl: pinctrl@d8110000 {
57 compatible = "wm,wm8650-pinctrl";
58 reg = <0xd8110000 0x10000>;
59 interrupt-controller;
60 #interrupt-cells = <2>;
61 gpio-controller;
62 #gpio-cells = <2>;
63 };
64
65 pmc@d8130000 {
66 compatible = "via,vt8500-pmc";
67 reg = <0xd8130000 0x1000>;
68
69 clocks {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 ref25: ref25M {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <25000000>;
77 };
78
79 ref24: ref24M {
80 #clock-cells = <0>;
81 compatible = "fixed-clock";
82 clock-frequency = <24000000>;
83 };
84
85 plla: plla {
86 #clock-cells = <0>;
87 compatible = "wm,wm8650-pll-clock";
88 clocks = <&ref25>;
89 reg = <0x200>;
90 };
91
92 pllb: pllb {
93 #clock-cells = <0>;
94 compatible = "wm,wm8650-pll-clock";
95 clocks = <&ref25>;
96 reg = <0x204>;
97 };
98
99 pllc: pllc {
100 #clock-cells = <0>;
101 compatible = "wm,wm8650-pll-clock";
102 clocks = <&ref25>;
103 reg = <0x208>;
104 };
105
106 plld: plld {
107 #clock-cells = <0>;
108 compatible = "wm,wm8650-pll-clock";
109 clocks = <&ref25>;
110 reg = <0x20c>;
111 };
112
113 plle: plle {
114 #clock-cells = <0>;
115 compatible = "wm,wm8650-pll-clock";
116 clocks = <&ref25>;
117 reg = <0x210>;
118 };
119
120 clkarm: arm {
121 #clock-cells = <0>;
122 compatible = "via,vt8500-device-clock";
123 clocks = <&plla>;
124 divisor-reg = <0x300>;
125 };
126
127 clkahb: ahb {
128 #clock-cells = <0>;
129 compatible = "via,vt8500-device-clock";
130 clocks = <&pllb>;
131 divisor-reg = <0x304>;
132 };
133
134 clkapb: apb {
135 #clock-cells = <0>;
136 compatible = "via,vt8500-device-clock";
137 clocks = <&pllb>;
138 divisor-reg = <0x320>;
139 };
140
141 clkddr: ddr {
142 #clock-cells = <0>;
143 compatible = "via,vt8500-device-clock";
144 clocks = <&plld>;
145 divisor-reg = <0x310>;
146 };
147
148 clkuart0: uart0 {
149 #clock-cells = <0>;
150 compatible = "via,vt8500-device-clock";
151 clocks = <&ref24>;
152 enable-reg = <0x250>;
153 enable-bit = <1>;
154 };
155
156 clkuart1: uart1 {
157 #clock-cells = <0>;
158 compatible = "via,vt8500-device-clock";
159 clocks = <&ref24>;
160 enable-reg = <0x250>;
161 enable-bit = <2>;
162 };
163
164 clksdhc: sdhc {
165 #clock-cells = <0>;
166 compatible = "via,vt8500-device-clock";
167 clocks = <&pllb>;
168 divisor-reg = <0x328>;
169 divisor-mask = <0x3f>;
170 enable-reg = <0x254>;
171 enable-bit = <18>;
172 };
173 };
174 };
175
176 timer@d8130100 {
177 compatible = "via,vt8500-timer";
178 reg = <0xd8130100 0x28>;
179 interrupts = <36>;
180 };
181
182 ehci@d8007900 {
183 compatible = "via,vt8500-ehci";
184 reg = <0xd8007900 0x200>;
185 interrupts = <43>;
186 };
187
188 uhci@d8007b00 {
189 compatible = "platform-uhci";
190 reg = <0xd8007b00 0x200>;
191 interrupts = <43>;
192 };
193
194 sdhc@d800a000 {
195 compatible = "wm,wm8505-sdhc";
196 reg = <0xd800a000 0x400>;
197 interrupts = <20>, <21>;
198 clocks = <&clksdhc>;
199 bus-width = <4>;
200 sdon-inverted;
201 };
202
203 fb: fb@d8050800 {
204 compatible = "wm,wm8505-fb";
205 reg = <0xd8050800 0x200>;
206 };
207
208 ge_rops@d8050400 {
209 compatible = "wm,prizm-ge-rops";
210 reg = <0xd8050400 0x100>;
211 };
212
213 uart0: serial@d8200000 {
214 compatible = "via,vt8500-uart";
215 reg = <0xd8200000 0x1040>;
216 interrupts = <32>;
217 clocks = <&clkuart0>;
218 status = "disabled";
219 };
220
221 uart1: serial@d82b0000 {
222 compatible = "via,vt8500-uart";
223 reg = <0xd82b0000 0x1040>;
224 interrupts = <33>;
225 clocks = <&clkuart1>;
226 status = "disabled";
227 };
228
229 rtc@d8100000 {
230 compatible = "via,vt8500-rtc";
231 reg = <0xd8100000 0x10000>;
232 interrupts = <48>;
233 };
234
235 ethernet@d8004000 {
236 compatible = "via,vt8500-rhine";
237 reg = <0xd8004000 0x100>;
238 interrupts = <10>;
239 };
240 };
241};
1/*
2 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8650";
13
14 cpus {
15 #address-cells = <0>;
16 #size-cells = <0>;
17
18 cpu {
19 device_type = "cpu";
20 compatible = "arm,arm926ej-s";
21 };
22 };
23
24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 };
28
29 soc {
30 #address-cells = <1>;
31 #size-cells = <1>;
32 compatible = "simple-bus";
33 ranges;
34 interrupt-parent = <&intc0>;
35
36 intc0: interrupt-controller@d8140000 {
37 compatible = "via,vt8500-intc";
38 interrupt-controller;
39 reg = <0xd8140000 0x10000>;
40 #interrupt-cells = <1>;
41 };
42
43 /* Secondary IC cascaded to intc0 */
44 intc1: interrupt-controller@d8150000 {
45 compatible = "via,vt8500-intc";
46 interrupt-controller;
47 #interrupt-cells = <1>;
48 reg = <0xD8150000 0x10000>;
49 interrupts = <56 57 58 59 60 61 62 63>;
50 };
51
52 pinctrl: pinctrl@d8110000 {
53 compatible = "wm,wm8650-pinctrl";
54 reg = <0xd8110000 0x10000>;
55 interrupt-controller;
56 #interrupt-cells = <2>;
57 gpio-controller;
58 #gpio-cells = <2>;
59 };
60
61 pmc@d8130000 {
62 compatible = "via,vt8500-pmc";
63 reg = <0xd8130000 0x1000>;
64
65 clocks {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 ref25: ref25M {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <25000000>;
73 };
74
75 ref24: ref24M {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <24000000>;
79 };
80
81 plla: plla {
82 #clock-cells = <0>;
83 compatible = "wm,wm8650-pll-clock";
84 clocks = <&ref25>;
85 reg = <0x200>;
86 };
87
88 pllb: pllb {
89 #clock-cells = <0>;
90 compatible = "wm,wm8650-pll-clock";
91 clocks = <&ref25>;
92 reg = <0x204>;
93 };
94
95 pllc: pllc {
96 #clock-cells = <0>;
97 compatible = "wm,wm8650-pll-clock";
98 clocks = <&ref25>;
99 reg = <0x208>;
100 };
101
102 plld: plld {
103 #clock-cells = <0>;
104 compatible = "wm,wm8650-pll-clock";
105 clocks = <&ref25>;
106 reg = <0x20c>;
107 };
108
109 plle: plle {
110 #clock-cells = <0>;
111 compatible = "wm,wm8650-pll-clock";
112 clocks = <&ref25>;
113 reg = <0x210>;
114 };
115
116 clkarm: arm {
117 #clock-cells = <0>;
118 compatible = "via,vt8500-device-clock";
119 clocks = <&plla>;
120 divisor-reg = <0x300>;
121 };
122
123 clkahb: ahb {
124 #clock-cells = <0>;
125 compatible = "via,vt8500-device-clock";
126 clocks = <&pllb>;
127 divisor-reg = <0x304>;
128 };
129
130 clkapb: apb {
131 #clock-cells = <0>;
132 compatible = "via,vt8500-device-clock";
133 clocks = <&pllb>;
134 divisor-reg = <0x320>;
135 };
136
137 clkddr: ddr {
138 #clock-cells = <0>;
139 compatible = "via,vt8500-device-clock";
140 clocks = <&plld>;
141 divisor-reg = <0x310>;
142 };
143
144 clkuart0: uart0 {
145 #clock-cells = <0>;
146 compatible = "via,vt8500-device-clock";
147 clocks = <&ref24>;
148 enable-reg = <0x250>;
149 enable-bit = <1>;
150 };
151
152 clkuart1: uart1 {
153 #clock-cells = <0>;
154 compatible = "via,vt8500-device-clock";
155 clocks = <&ref24>;
156 enable-reg = <0x250>;
157 enable-bit = <2>;
158 };
159
160 clksdhc: sdhc {
161 #clock-cells = <0>;
162 compatible = "via,vt8500-device-clock";
163 clocks = <&pllb>;
164 divisor-reg = <0x328>;
165 divisor-mask = <0x3f>;
166 enable-reg = <0x254>;
167 enable-bit = <18>;
168 };
169 };
170 };
171
172 timer@d8130100 {
173 compatible = "via,vt8500-timer";
174 reg = <0xd8130100 0x28>;
175 interrupts = <36>;
176 };
177
178 ehci@d8007900 {
179 compatible = "via,vt8500-ehci";
180 reg = <0xd8007900 0x200>;
181 interrupts = <43>;
182 };
183
184 uhci@d8007b00 {
185 compatible = "platform-uhci";
186 reg = <0xd8007b00 0x200>;
187 interrupts = <43>;
188 };
189
190 sdhc@d800a000 {
191 compatible = "wm,wm8505-sdhc";
192 reg = <0xd800a000 0x400>;
193 interrupts = <20>, <21>;
194 clocks = <&clksdhc>;
195 bus-width = <4>;
196 sdon-inverted;
197 };
198
199 fb: fb@d8050800 {
200 compatible = "wm,wm8505-fb";
201 reg = <0xd8050800 0x200>;
202 };
203
204 ge_rops@d8050400 {
205 compatible = "wm,prizm-ge-rops";
206 reg = <0xd8050400 0x100>;
207 };
208
209 uart0: serial@d8200000 {
210 compatible = "via,vt8500-uart";
211 reg = <0xd8200000 0x1040>;
212 interrupts = <32>;
213 clocks = <&clkuart0>;
214 status = "disabled";
215 };
216
217 uart1: serial@d82b0000 {
218 compatible = "via,vt8500-uart";
219 reg = <0xd82b0000 0x1040>;
220 interrupts = <33>;
221 clocks = <&clkuart1>;
222 status = "disabled";
223 };
224
225 rtc@d8100000 {
226 compatible = "via,vt8500-rtc";
227 reg = <0xd8100000 0x10000>;
228 interrupts = <48>;
229 };
230
231 ethernet@d8004000 {
232 compatible = "via,vt8500-rhine";
233 reg = <0xd8004000 0x100>;
234 interrupts = <10>;
235 };
236 };
237};