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1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra124-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra124-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/reset/tegra124-car.h>
8#include <dt-bindings/thermal/tegra124-soctherm.h>
9#include <dt-bindings/soc/tegra-pmc.h>
10
11#include "tegra124-peripherals-opp.dtsi"
12
13/ {
14 compatible = "nvidia,tegra124";
15 interrupt-parent = <&lic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 memory@80000000 {
20 device_type = "memory";
21 reg = <0x0 0x80000000 0x0 0x0>;
22 };
23
24 pcie@1003000 {
25 compatible = "nvidia,tegra124-pcie";
26 device_type = "pci";
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 reg-names = "pads", "afi", "cs";
31 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
32 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
33 interrupt-names = "intr", "msi";
34
35 #interrupt-cells = <1>;
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38
39 bus-range = <0x00 0xff>;
40 #address-cells = <3>;
41 #size-cells = <2>;
42
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
48
49 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
50 <&tegra_car TEGRA124_CLK_AFI>,
51 <&tegra_car TEGRA124_CLK_PLL_E>,
52 <&tegra_car TEGRA124_CLK_CML0>;
53 clock-names = "pex", "afi", "pll_e", "cml";
54 resets = <&tegra_car 70>,
55 <&tegra_car 72>,
56 <&tegra_car 74>;
57 reset-names = "pex", "afi", "pcie_x";
58 status = "disabled";
59
60 pci@1,0 {
61 device_type = "pci";
62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
63 reg = <0x000800 0 0 0 0>;
64 bus-range = <0x00 0xff>;
65 status = "disabled";
66
67 #address-cells = <3>;
68 #size-cells = <2>;
69 ranges;
70
71 nvidia,num-lanes = <2>;
72 };
73
74 pci@2,0 {
75 device_type = "pci";
76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
77 reg = <0x001000 0 0 0 0>;
78 bus-range = <0x00 0xff>;
79 status = "disabled";
80
81 #address-cells = <3>;
82 #size-cells = <2>;
83 ranges;
84
85 nvidia,num-lanes = <1>;
86 };
87 };
88
89 host1x@50000000 {
90 compatible = "nvidia,tegra124-host1x";
91 reg = <0x0 0x50000000 0x0 0x00034000>;
92 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
93 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
94 interrupt-names = "syncpt", "host1x";
95 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
96 clock-names = "host1x";
97 resets = <&tegra_car 28>;
98 reset-names = "host1x";
99 iommus = <&mc TEGRA_SWGROUP_HC>;
100
101 #address-cells = <2>;
102 #size-cells = <2>;
103
104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
105
106 dc@54200000 {
107 compatible = "nvidia,tegra124-dc";
108 reg = <0x0 0x54200000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car TEGRA124_CLK_DISP1>;
111 clock-names = "dc";
112 resets = <&tegra_car 27>;
113 reset-names = "dc";
114
115 iommus = <&mc TEGRA_SWGROUP_DC>;
116
117 nvidia,head = <0>;
118
119 interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>,
120 <&mc TEGRA124_MC_DISPLAY0B &emc>,
121 <&mc TEGRA124_MC_DISPLAY0C &emc>,
122 <&mc TEGRA124_MC_DISPLAYHC &emc>,
123 <&mc TEGRA124_MC_DISPLAYD &emc>,
124 <&mc TEGRA124_MC_DISPLAYT &emc>;
125 interconnect-names = "wina",
126 "winb",
127 "winc",
128 "cursor",
129 "wind",
130 "wint";
131 };
132
133 dc@54240000 {
134 compatible = "nvidia,tegra124-dc";
135 reg = <0x0 0x54240000 0x0 0x00040000>;
136 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&tegra_car TEGRA124_CLK_DISP2>;
138 clock-names = "dc";
139 resets = <&tegra_car 26>;
140 reset-names = "dc";
141
142 iommus = <&mc TEGRA_SWGROUP_DCB>;
143
144 nvidia,head = <1>;
145
146 interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>,
147 <&mc TEGRA124_MC_DISPLAY0BB &emc>,
148 <&mc TEGRA124_MC_DISPLAY0CB &emc>,
149 <&mc TEGRA124_MC_DISPLAYHCB &emc>;
150 interconnect-names = "wina",
151 "winb",
152 "winc",
153 "cursor";
154 };
155
156 hdmi: hdmi@54280000 {
157 compatible = "nvidia,tegra124-hdmi";
158 reg = <0x0 0x54280000 0x0 0x00040000>;
159 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
161 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
162 clock-names = "hdmi", "parent";
163 resets = <&tegra_car 51>;
164 reset-names = "hdmi";
165 status = "disabled";
166 };
167
168 vic@54340000 {
169 compatible = "nvidia,tegra124-vic";
170 reg = <0x0 0x54340000 0x0 0x00040000>;
171 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&tegra_car TEGRA124_CLK_VIC03>;
173 clock-names = "vic";
174 resets = <&tegra_car 178>;
175 reset-names = "vic";
176
177 iommus = <&mc TEGRA_SWGROUP_VIC>;
178 };
179
180 sor@54540000 {
181 compatible = "nvidia,tegra124-sor";
182 reg = <0x0 0x54540000 0x0 0x00040000>;
183 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
185 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
186 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
187 <&tegra_car TEGRA124_CLK_PLL_DP>,
188 <&tegra_car TEGRA124_CLK_CLK_M>;
189 clock-names = "sor", "out", "parent", "dp", "safe";
190 resets = <&tegra_car 182>;
191 reset-names = "sor";
192 status = "disabled";
193 };
194
195 dpaux: dpaux@545c0000 {
196 compatible = "nvidia,tegra124-dpaux";
197 reg = <0x0 0x545c0000 0x0 0x00040000>;
198 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
200 <&tegra_car TEGRA124_CLK_PLL_DP>;
201 clock-names = "dpaux", "parent";
202 resets = <&tegra_car 181>;
203 reset-names = "dpaux";
204 status = "disabled";
205
206 i2c-bus {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 };
210 };
211 };
212
213 gic: interrupt-controller@50041000 {
214 compatible = "arm,cortex-a15-gic";
215 #interrupt-cells = <3>;
216 interrupt-controller;
217 reg = <0x0 0x50041000 0x0 0x1000>,
218 <0x0 0x50042000 0x0 0x1000>,
219 <0x0 0x50044000 0x0 0x2000>,
220 <0x0 0x50046000 0x0 0x2000>;
221 interrupts = <GIC_PPI 9
222 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
223 interrupt-parent = <&gic>;
224 };
225
226 /*
227 * Please keep the following 0, notation in place as a former mainline
228 * U-Boot version was looking for that particular notation in order to
229 * perform required fix-ups on that GPU node.
230 */
231 gpu@0,57000000 {
232 compatible = "nvidia,gk20a";
233 reg = <0x0 0x57000000 0x0 0x01000000>,
234 <0x0 0x58000000 0x0 0x01000000>;
235 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-names = "stall", "nonstall";
238 clocks = <&tegra_car TEGRA124_CLK_GPU>,
239 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
240 clock-names = "gpu", "pwr";
241 resets = <&tegra_car 184>;
242 reset-names = "gpu";
243
244 iommus = <&mc TEGRA_SWGROUP_GPU>;
245
246 status = "disabled";
247 };
248
249 lic: interrupt-controller@60004000 {
250 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
251 reg = <0x0 0x60004000 0x0 0x100>,
252 <0x0 0x60004100 0x0 0x100>,
253 <0x0 0x60004200 0x0 0x100>,
254 <0x0 0x60004300 0x0 0x100>,
255 <0x0 0x60004400 0x0 0x100>;
256 interrupt-controller;
257 #interrupt-cells = <3>;
258 interrupt-parent = <&gic>;
259 };
260
261 timer@60005000 {
262 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
263 reg = <0x0 0x60005000 0x0 0x400>;
264 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
271 };
272
273 tegra_car: clock@60006000 {
274 compatible = "nvidia,tegra124-car";
275 reg = <0x0 0x60006000 0x0 0x1000>;
276 #clock-cells = <1>;
277 #reset-cells = <1>;
278 nvidia,external-memory-controller = <&emc>;
279 };
280
281 flow-controller@60007000 {
282 compatible = "nvidia,tegra124-flowctrl";
283 reg = <0x0 0x60007000 0x0 0x1000>;
284 };
285
286 actmon: actmon@6000c800 {
287 compatible = "nvidia,tegra124-actmon";
288 reg = <0x0 0x6000c800 0x0 0x400>;
289 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
291 <&tegra_car TEGRA124_CLK_EMC>;
292 clock-names = "actmon", "emc";
293 resets = <&tegra_car 119>;
294 reset-names = "actmon";
295 operating-points-v2 = <&emc_bw_dfs_opp_table>;
296 interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
297 interconnect-names = "cpu-read";
298 #cooling-cells = <2>;
299 };
300
301 gpio: gpio@6000d000 {
302 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
303 reg = <0x0 0x6000d000 0x0 0x1000>;
304 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
312 #gpio-cells = <2>;
313 gpio-controller;
314 #interrupt-cells = <2>;
315 interrupt-controller;
316 /*
317 gpio-ranges = <&pinmux 0 0 251>;
318 */
319 };
320
321 apbdma: dma@60020000 {
322 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
323 reg = <0x0 0x60020000 0x0 0x1400>;
324 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
357 resets = <&tegra_car 34>;
358 reset-names = "dma";
359 #dma-cells = <1>;
360 };
361
362 apbmisc@70000800 {
363 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
364 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
365 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
366 };
367
368 pinmux: pinmux@70000868 {
369 compatible = "nvidia,tegra124-pinmux";
370 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
371 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
372 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
373 };
374
375 /*
376 * There are two serial driver i.e. 8250 based simple serial
377 * driver and APB DMA based serial driver for higher baudrate
378 * and performace. To enable the 8250 based driver, the compatible
379 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
380 * the APB DMA based serial driver, the compatible is
381 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
382 */
383 uarta: serial@70006000 {
384 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
385 reg = <0x0 0x70006000 0x0 0x40>;
386 reg-shift = <2>;
387 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
389 resets = <&tegra_car 6>;
390 reset-names = "serial";
391 dmas = <&apbdma 8>, <&apbdma 8>;
392 dma-names = "rx", "tx";
393 status = "disabled";
394 };
395
396 uartb: serial@70006040 {
397 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
398 reg = <0x0 0x70006040 0x0 0x40>;
399 reg-shift = <2>;
400 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
402 resets = <&tegra_car 7>;
403 reset-names = "serial";
404 dmas = <&apbdma 9>, <&apbdma 9>;
405 dma-names = "rx", "tx";
406 status = "disabled";
407 };
408
409 uartc: serial@70006200 {
410 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
411 reg = <0x0 0x70006200 0x0 0x40>;
412 reg-shift = <2>;
413 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
415 resets = <&tegra_car 55>;
416 reset-names = "serial";
417 dmas = <&apbdma 10>, <&apbdma 10>;
418 dma-names = "rx", "tx";
419 status = "disabled";
420 };
421
422 uartd: serial@70006300 {
423 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
424 reg = <0x0 0x70006300 0x0 0x40>;
425 reg-shift = <2>;
426 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
428 resets = <&tegra_car 65>;
429 reset-names = "serial";
430 dmas = <&apbdma 19>, <&apbdma 19>;
431 dma-names = "rx", "tx";
432 status = "disabled";
433 };
434
435 pwm: pwm@7000a000 {
436 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
437 reg = <0x0 0x7000a000 0x0 0x100>;
438 #pwm-cells = <2>;
439 clocks = <&tegra_car TEGRA124_CLK_PWM>;
440 resets = <&tegra_car 17>;
441 reset-names = "pwm";
442 status = "disabled";
443 };
444
445 i2c@7000c000 {
446 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
447 reg = <0x0 0x7000c000 0x0 0x100>;
448 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
452 clock-names = "div-clk";
453 resets = <&tegra_car 12>;
454 reset-names = "i2c";
455 dmas = <&apbdma 21>, <&apbdma 21>;
456 dma-names = "rx", "tx";
457 status = "disabled";
458 };
459
460 i2c@7000c400 {
461 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
462 reg = <0x0 0x7000c400 0x0 0x100>;
463 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
467 clock-names = "div-clk";
468 resets = <&tegra_car 54>;
469 reset-names = "i2c";
470 dmas = <&apbdma 22>, <&apbdma 22>;
471 dma-names = "rx", "tx";
472 status = "disabled";
473 };
474
475 i2c@7000c500 {
476 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
477 reg = <0x0 0x7000c500 0x0 0x100>;
478 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
482 clock-names = "div-clk";
483 resets = <&tegra_car 67>;
484 reset-names = "i2c";
485 dmas = <&apbdma 23>, <&apbdma 23>;
486 dma-names = "rx", "tx";
487 status = "disabled";
488 };
489
490 i2c@7000c700 {
491 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
492 reg = <0x0 0x7000c700 0x0 0x100>;
493 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
495 #size-cells = <0>;
496 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
497 clock-names = "div-clk";
498 resets = <&tegra_car 103>;
499 reset-names = "i2c";
500 dmas = <&apbdma 26>, <&apbdma 26>;
501 dma-names = "rx", "tx";
502 status = "disabled";
503 };
504
505 i2c@7000d000 {
506 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
507 reg = <0x0 0x7000d000 0x0 0x100>;
508 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
512 clock-names = "div-clk";
513 resets = <&tegra_car 47>;
514 reset-names = "i2c";
515 dmas = <&apbdma 24>, <&apbdma 24>;
516 dma-names = "rx", "tx";
517 status = "disabled";
518 };
519
520 i2c@7000d100 {
521 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
522 reg = <0x0 0x7000d100 0x0 0x100>;
523 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
524 #address-cells = <1>;
525 #size-cells = <0>;
526 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
527 clock-names = "div-clk";
528 resets = <&tegra_car 166>;
529 reset-names = "i2c";
530 dmas = <&apbdma 30>, <&apbdma 30>;
531 dma-names = "rx", "tx";
532 status = "disabled";
533 };
534
535 spi@7000d400 {
536 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
537 reg = <0x0 0x7000d400 0x0 0x200>;
538 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
539 #address-cells = <1>;
540 #size-cells = <0>;
541 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
542 clock-names = "spi";
543 resets = <&tegra_car 41>;
544 reset-names = "spi";
545 dmas = <&apbdma 15>, <&apbdma 15>;
546 dma-names = "rx", "tx";
547 status = "disabled";
548 };
549
550 spi@7000d600 {
551 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
552 reg = <0x0 0x7000d600 0x0 0x200>;
553 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
555 #size-cells = <0>;
556 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
557 clock-names = "spi";
558 resets = <&tegra_car 44>;
559 reset-names = "spi";
560 dmas = <&apbdma 16>, <&apbdma 16>;
561 dma-names = "rx", "tx";
562 status = "disabled";
563 };
564
565 spi@7000d800 {
566 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
567 reg = <0x0 0x7000d800 0x0 0x200>;
568 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
569 #address-cells = <1>;
570 #size-cells = <0>;
571 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
572 clock-names = "spi";
573 resets = <&tegra_car 46>;
574 reset-names = "spi";
575 dmas = <&apbdma 17>, <&apbdma 17>;
576 dma-names = "rx", "tx";
577 status = "disabled";
578 };
579
580 spi@7000da00 {
581 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
582 reg = <0x0 0x7000da00 0x0 0x200>;
583 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
584 #address-cells = <1>;
585 #size-cells = <0>;
586 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
587 clock-names = "spi";
588 resets = <&tegra_car 68>;
589 reset-names = "spi";
590 dmas = <&apbdma 18>, <&apbdma 18>;
591 dma-names = "rx", "tx";
592 status = "disabled";
593 };
594
595 spi@7000dc00 {
596 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
597 reg = <0x0 0x7000dc00 0x0 0x200>;
598 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
599 #address-cells = <1>;
600 #size-cells = <0>;
601 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
602 clock-names = "spi";
603 resets = <&tegra_car 104>;
604 reset-names = "spi";
605 dmas = <&apbdma 27>, <&apbdma 27>;
606 dma-names = "rx", "tx";
607 status = "disabled";
608 };
609
610 spi@7000de00 {
611 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
612 reg = <0x0 0x7000de00 0x0 0x200>;
613 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
614 #address-cells = <1>;
615 #size-cells = <0>;
616 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
617 clock-names = "spi";
618 resets = <&tegra_car 105>;
619 reset-names = "spi";
620 dmas = <&apbdma 28>, <&apbdma 28>;
621 dma-names = "rx", "tx";
622 status = "disabled";
623 };
624
625 rtc@7000e000 {
626 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
627 reg = <0x0 0x7000e000 0x0 0x100>;
628 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&tegra_car TEGRA124_CLK_RTC>;
630 };
631
632 tegra_pmc: pmc@7000e400 {
633 compatible = "nvidia,tegra124-pmc";
634 reg = <0x0 0x7000e400 0x0 0x400>;
635 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
636 clock-names = "pclk", "clk32k_in";
637 #clock-cells = <1>;
638 };
639
640 fuse@7000f800 {
641 compatible = "nvidia,tegra124-efuse";
642 reg = <0x0 0x7000f800 0x0 0x400>;
643 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
644 clock-names = "fuse";
645 resets = <&tegra_car 39>;
646 reset-names = "fuse";
647 };
648
649 mc: memory-controller@70019000 {
650 compatible = "nvidia,tegra124-mc";
651 reg = <0x0 0x70019000 0x0 0x1000>;
652 clocks = <&tegra_car TEGRA124_CLK_MC>;
653 clock-names = "mc";
654
655 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
656
657 #iommu-cells = <1>;
658 #reset-cells = <1>;
659 #interconnect-cells = <1>;
660 };
661
662 emc: external-memory-controller@7001b000 {
663 compatible = "nvidia,tegra124-emc";
664 reg = <0x0 0x7001b000 0x0 0x1000>;
665 clocks = <&tegra_car TEGRA124_CLK_EMC>;
666 clock-names = "emc";
667
668 nvidia,memory-controller = <&mc>;
669 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
670
671 #interconnect-cells = <0>;
672 };
673
674 sata@70020000 {
675 compatible = "nvidia,tegra124-ahci";
676 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
677 <0x0 0x70020000 0x0 0x7000>; /* SATA */
678 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&tegra_car TEGRA124_CLK_SATA>,
680 <&tegra_car TEGRA124_CLK_SATA_OOB>,
681 <&tegra_car TEGRA124_CLK_CML1>,
682 <&tegra_car TEGRA124_CLK_PLL_E>;
683 clock-names = "sata", "sata-oob", "cml1", "pll_e";
684 resets = <&tegra_car 124>,
685 <&tegra_car 129>,
686 <&tegra_car 123>;
687 reset-names = "sata", "sata-cold", "sata-oob";
688 status = "disabled";
689 };
690
691 hda@70030000 {
692 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
693 reg = <0x0 0x70030000 0x0 0x10000>;
694 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&tegra_car TEGRA124_CLK_HDA>,
696 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
697 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
698 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
699 resets = <&tegra_car 125>, /* hda */
700 <&tegra_car 128>, /* hda2hdmi */
701 <&tegra_car 111>; /* hda2codec_2x */
702 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
703 status = "disabled";
704 };
705
706 usb@70090000 {
707 compatible = "nvidia,tegra124-xusb";
708 reg = <0x0 0x70090000 0x0 0x8000>,
709 <0x0 0x70098000 0x0 0x1000>,
710 <0x0 0x70099000 0x0 0x1000>;
711 reg-names = "hcd", "fpci", "ipfs";
712
713 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
715
716 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
717 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
718 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
719 <&tegra_car TEGRA124_CLK_XUSB_SS>,
720 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
721 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
722 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
723 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
724 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
725 <&tegra_car TEGRA124_CLK_CLK_M>,
726 <&tegra_car TEGRA124_CLK_PLL_E>;
727 clock-names = "xusb_host", "xusb_host_src",
728 "xusb_falcon_src", "xusb_ss",
729 "xusb_ss_src", "xusb_ss_div2",
730 "xusb_hs_src", "xusb_fs_src",
731 "pll_u_480m", "clk_m", "pll_e";
732 resets = <&tegra_car 89>, <&tegra_car 156>,
733 <&tegra_car 143>;
734 reset-names = "xusb_host", "xusb_ss", "xusb_src";
735
736 nvidia,xusb-padctl = <&padctl>;
737
738 status = "disabled";
739 };
740
741 padctl: padctl@7009f000 {
742 compatible = "nvidia,tegra124-xusb-padctl";
743 reg = <0x0 0x7009f000 0x0 0x1000>;
744 resets = <&tegra_car 142>;
745 reset-names = "padctl";
746
747 pads {
748 usb2 {
749 status = "disabled";
750
751 lanes {
752 usb2-0 {
753 status = "disabled";
754 #phy-cells = <0>;
755 };
756
757 usb2-1 {
758 status = "disabled";
759 #phy-cells = <0>;
760 };
761
762 usb2-2 {
763 status = "disabled";
764 #phy-cells = <0>;
765 };
766 };
767 };
768
769 ulpi {
770 status = "disabled";
771
772 lanes {
773 ulpi-0 {
774 status = "disabled";
775 #phy-cells = <0>;
776 };
777 };
778 };
779
780 hsic {
781 status = "disabled";
782
783 lanes {
784 hsic-0 {
785 status = "disabled";
786 #phy-cells = <0>;
787 };
788
789 hsic-1 {
790 status = "disabled";
791 #phy-cells = <0>;
792 };
793 };
794 };
795
796 pcie {
797 status = "disabled";
798
799 lanes {
800 pcie-0 {
801 status = "disabled";
802 #phy-cells = <0>;
803 };
804
805 pcie-1 {
806 status = "disabled";
807 #phy-cells = <0>;
808 };
809
810 pcie-2 {
811 status = "disabled";
812 #phy-cells = <0>;
813 };
814
815 pcie-3 {
816 status = "disabled";
817 #phy-cells = <0>;
818 };
819
820 pcie-4 {
821 status = "disabled";
822 #phy-cells = <0>;
823 };
824 };
825 };
826
827 sata {
828 status = "disabled";
829
830 lanes {
831 sata-0 {
832 status = "disabled";
833 #phy-cells = <0>;
834 };
835 };
836 };
837 };
838
839 ports {
840 usb2-0 {
841 status = "disabled";
842 };
843
844 usb2-1 {
845 status = "disabled";
846 };
847
848 usb2-2 {
849 status = "disabled";
850 };
851
852 ulpi-0 {
853 status = "disabled";
854 };
855
856 hsic-0 {
857 status = "disabled";
858 };
859
860 hsic-1 {
861 status = "disabled";
862 };
863
864 usb3-0 {
865 status = "disabled";
866 };
867
868 usb3-1 {
869 status = "disabled";
870 };
871 };
872 };
873
874 mmc@700b0000 {
875 compatible = "nvidia,tegra124-sdhci";
876 reg = <0x0 0x700b0000 0x0 0x200>;
877 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
878 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
879 clock-names = "sdhci";
880 resets = <&tegra_car 14>;
881 reset-names = "sdhci";
882 status = "disabled";
883 };
884
885 mmc@700b0200 {
886 compatible = "nvidia,tegra124-sdhci";
887 reg = <0x0 0x700b0200 0x0 0x200>;
888 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
890 clock-names = "sdhci";
891 resets = <&tegra_car 9>;
892 reset-names = "sdhci";
893 status = "disabled";
894 };
895
896 mmc@700b0400 {
897 compatible = "nvidia,tegra124-sdhci";
898 reg = <0x0 0x700b0400 0x0 0x200>;
899 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
901 clock-names = "sdhci";
902 resets = <&tegra_car 69>;
903 reset-names = "sdhci";
904 status = "disabled";
905 };
906
907 mmc@700b0600 {
908 compatible = "nvidia,tegra124-sdhci";
909 reg = <0x0 0x700b0600 0x0 0x200>;
910 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
912 clock-names = "sdhci";
913 resets = <&tegra_car 15>;
914 reset-names = "sdhci";
915 status = "disabled";
916 };
917
918 cec@70015000 {
919 compatible = "nvidia,tegra124-cec";
920 reg = <0x0 0x70015000 0x0 0x00001000>;
921 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&tegra_car TEGRA124_CLK_CEC>;
923 clock-names = "cec";
924 status = "disabled";
925 hdmi-phandle = <&hdmi>;
926 };
927
928 soctherm: thermal-sensor@700e2000 {
929 compatible = "nvidia,tegra124-soctherm";
930 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
931 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
932 reg-names = "soctherm-reg", "car-reg";
933 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
935 interrupt-names = "thermal", "edp";
936 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
937 <&tegra_car TEGRA124_CLK_SOC_THERM>;
938 clock-names = "tsensor", "soctherm";
939 resets = <&tegra_car 78>;
940 reset-names = "soctherm";
941 #thermal-sensor-cells = <1>;
942
943 throttle-cfgs {
944 throttle_heavy: heavy {
945 nvidia,priority = <100>;
946 nvidia,cpu-throt-percent = <85>;
947 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
948
949 #cooling-cells = <2>;
950 };
951 };
952 };
953
954 dfll: clock@70110000 {
955 compatible = "nvidia,tegra124-dfll";
956 reg = <0 0x70110000 0 0x100>, /* DFLL control */
957 <0 0x70110000 0 0x100>, /* I2C output control */
958 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
959 <0 0x70110200 0 0x100>; /* Look-up table RAM */
960 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
962 <&tegra_car TEGRA124_CLK_DFLL_REF>,
963 <&tegra_car TEGRA124_CLK_I2C5>;
964 clock-names = "soc", "ref", "i2c";
965 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
966 reset-names = "dvco";
967 #clock-cells = <0>;
968 clock-output-names = "dfllCPU_out";
969 nvidia,sample-rate = <12500>;
970 nvidia,droop-ctrl = <0x00000f00>;
971 nvidia,force-mode = <1>;
972 nvidia,cf = <10>;
973 nvidia,ci = <0>;
974 nvidia,cg = <2>;
975 status = "disabled";
976 };
977
978 ahub@70300000 {
979 compatible = "nvidia,tegra124-ahub";
980 reg = <0x0 0x70300000 0x0 0x200>,
981 <0x0 0x70300800 0x0 0x800>,
982 <0x0 0x70300200 0x0 0x600>;
983 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
985 <&tegra_car TEGRA124_CLK_APBIF>;
986 clock-names = "d_audio", "apbif";
987 resets = <&tegra_car 106>, /* d_audio */
988 <&tegra_car 107>, /* apbif */
989 <&tegra_car 30>, /* i2s0 */
990 <&tegra_car 11>, /* i2s1 */
991 <&tegra_car 18>, /* i2s2 */
992 <&tegra_car 101>, /* i2s3 */
993 <&tegra_car 102>, /* i2s4 */
994 <&tegra_car 108>, /* dam0 */
995 <&tegra_car 109>, /* dam1 */
996 <&tegra_car 110>, /* dam2 */
997 <&tegra_car 10>, /* spdif */
998 <&tegra_car 153>, /* amx */
999 <&tegra_car 185>, /* amx1 */
1000 <&tegra_car 154>, /* adx */
1001 <&tegra_car 180>, /* adx1 */
1002 <&tegra_car 186>, /* afc0 */
1003 <&tegra_car 187>, /* afc1 */
1004 <&tegra_car 188>, /* afc2 */
1005 <&tegra_car 189>, /* afc3 */
1006 <&tegra_car 190>, /* afc4 */
1007 <&tegra_car 191>; /* afc5 */
1008 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1009 "i2s3", "i2s4", "dam0", "dam1", "dam2",
1010 "spdif", "amx", "amx1", "adx", "adx1",
1011 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
1012 dmas = <&apbdma 1>, <&apbdma 1>,
1013 <&apbdma 2>, <&apbdma 2>,
1014 <&apbdma 3>, <&apbdma 3>,
1015 <&apbdma 4>, <&apbdma 4>,
1016 <&apbdma 6>, <&apbdma 6>,
1017 <&apbdma 7>, <&apbdma 7>,
1018 <&apbdma 12>, <&apbdma 12>,
1019 <&apbdma 13>, <&apbdma 13>,
1020 <&apbdma 14>, <&apbdma 14>,
1021 <&apbdma 29>, <&apbdma 29>;
1022 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1023 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
1024 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
1025 "rx9", "tx9";
1026 ranges;
1027 #address-cells = <2>;
1028 #size-cells = <2>;
1029
1030 tegra_i2s0: i2s@70301000 {
1031 compatible = "nvidia,tegra124-i2s";
1032 reg = <0x0 0x70301000 0x0 0x100>;
1033 nvidia,ahub-cif-ids = <4 4>;
1034 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
1035 resets = <&tegra_car 30>;
1036 reset-names = "i2s";
1037 status = "disabled";
1038 };
1039
1040 tegra_i2s1: i2s@70301100 {
1041 compatible = "nvidia,tegra124-i2s";
1042 reg = <0x0 0x70301100 0x0 0x100>;
1043 nvidia,ahub-cif-ids = <5 5>;
1044 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
1045 resets = <&tegra_car 11>;
1046 reset-names = "i2s";
1047 status = "disabled";
1048 };
1049
1050 tegra_i2s2: i2s@70301200 {
1051 compatible = "nvidia,tegra124-i2s";
1052 reg = <0x0 0x70301200 0x0 0x100>;
1053 nvidia,ahub-cif-ids = <6 6>;
1054 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1055 resets = <&tegra_car 18>;
1056 reset-names = "i2s";
1057 status = "disabled";
1058 };
1059
1060 tegra_i2s3: i2s@70301300 {
1061 compatible = "nvidia,tegra124-i2s";
1062 reg = <0x0 0x70301300 0x0 0x100>;
1063 nvidia,ahub-cif-ids = <7 7>;
1064 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1065 resets = <&tegra_car 101>;
1066 reset-names = "i2s";
1067 status = "disabled";
1068 };
1069
1070 tegra_i2s4: i2s@70301400 {
1071 compatible = "nvidia,tegra124-i2s";
1072 reg = <0x0 0x70301400 0x0 0x100>;
1073 nvidia,ahub-cif-ids = <8 8>;
1074 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1075 resets = <&tegra_car 102>;
1076 reset-names = "i2s";
1077 status = "disabled";
1078 };
1079 };
1080
1081 usb@7d000000 {
1082 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1083 reg = <0x0 0x7d000000 0x0 0x4000>;
1084 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1085 phy_type = "utmi";
1086 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1087 resets = <&tegra_car 22>;
1088 reset-names = "usb";
1089 nvidia,phy = <&phy1>;
1090 status = "disabled";
1091 };
1092
1093 phy1: usb-phy@7d000000 {
1094 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1095 reg = <0x0 0x7d000000 0x0 0x4000>,
1096 <0x0 0x7d000000 0x0 0x4000>;
1097 phy_type = "utmi";
1098 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1099 <&tegra_car TEGRA124_CLK_PLL_U>,
1100 <&tegra_car TEGRA124_CLK_USBD>;
1101 clock-names = "reg", "pll_u", "utmi-pads";
1102 resets = <&tegra_car 22>, <&tegra_car 22>;
1103 reset-names = "usb", "utmi-pads";
1104 #phy-cells = <0>;
1105 nvidia,hssync-start-delay = <0>;
1106 nvidia,idle-wait-delay = <17>;
1107 nvidia,elastic-limit = <16>;
1108 nvidia,term-range-adj = <6>;
1109 nvidia,xcvr-setup = <9>;
1110 nvidia,xcvr-lsfslew = <0>;
1111 nvidia,xcvr-lsrslew = <3>;
1112 nvidia,hssquelch-level = <2>;
1113 nvidia,hsdiscon-level = <5>;
1114 nvidia,xcvr-hsslew = <12>;
1115 nvidia,has-utmi-pad-registers;
1116 status = "disabled";
1117 };
1118
1119 usb@7d004000 {
1120 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1121 reg = <0x0 0x7d004000 0x0 0x4000>;
1122 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1123 phy_type = "utmi";
1124 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1125 resets = <&tegra_car 58>;
1126 reset-names = "usb";
1127 nvidia,phy = <&phy2>;
1128 status = "disabled";
1129 };
1130
1131 phy2: usb-phy@7d004000 {
1132 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1133 reg = <0x0 0x7d004000 0x0 0x4000>,
1134 <0x0 0x7d000000 0x0 0x4000>;
1135 phy_type = "utmi";
1136 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1137 <&tegra_car TEGRA124_CLK_PLL_U>,
1138 <&tegra_car TEGRA124_CLK_USBD>;
1139 clock-names = "reg", "pll_u", "utmi-pads";
1140 resets = <&tegra_car 58>, <&tegra_car 22>;
1141 reset-names = "usb", "utmi-pads";
1142 #phy-cells = <0>;
1143 nvidia,hssync-start-delay = <0>;
1144 nvidia,idle-wait-delay = <17>;
1145 nvidia,elastic-limit = <16>;
1146 nvidia,term-range-adj = <6>;
1147 nvidia,xcvr-setup = <9>;
1148 nvidia,xcvr-lsfslew = <0>;
1149 nvidia,xcvr-lsrslew = <3>;
1150 nvidia,hssquelch-level = <2>;
1151 nvidia,hsdiscon-level = <5>;
1152 nvidia,xcvr-hsslew = <12>;
1153 status = "disabled";
1154 };
1155
1156 usb@7d008000 {
1157 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1158 reg = <0x0 0x7d008000 0x0 0x4000>;
1159 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1160 phy_type = "utmi";
1161 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1162 resets = <&tegra_car 59>;
1163 reset-names = "usb";
1164 nvidia,phy = <&phy3>;
1165 status = "disabled";
1166 };
1167
1168 phy3: usb-phy@7d008000 {
1169 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1170 reg = <0x0 0x7d008000 0x0 0x4000>,
1171 <0x0 0x7d000000 0x0 0x4000>;
1172 phy_type = "utmi";
1173 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1174 <&tegra_car TEGRA124_CLK_PLL_U>,
1175 <&tegra_car TEGRA124_CLK_USBD>;
1176 clock-names = "reg", "pll_u", "utmi-pads";
1177 resets = <&tegra_car 59>, <&tegra_car 22>;
1178 reset-names = "usb", "utmi-pads";
1179 #phy-cells = <0>;
1180 nvidia,hssync-start-delay = <0>;
1181 nvidia,idle-wait-delay = <17>;
1182 nvidia,elastic-limit = <16>;
1183 nvidia,term-range-adj = <6>;
1184 nvidia,xcvr-setup = <9>;
1185 nvidia,xcvr-lsfslew = <0>;
1186 nvidia,xcvr-lsrslew = <3>;
1187 nvidia,hssquelch-level = <2>;
1188 nvidia,hsdiscon-level = <5>;
1189 nvidia,xcvr-hsslew = <12>;
1190 status = "disabled";
1191 };
1192
1193 cpus {
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1196
1197 cpu@0 {
1198 device_type = "cpu";
1199 compatible = "arm,cortex-a15";
1200 reg = <0>;
1201
1202 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1203 <&tegra_car TEGRA124_CLK_CCLK_LP>,
1204 <&tegra_car TEGRA124_CLK_PLL_X>,
1205 <&tegra_car TEGRA124_CLK_PLL_P>,
1206 <&dfll>;
1207 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1208 /* FIXME: what's the actual transition time? */
1209 clock-latency = <300000>;
1210 };
1211
1212 cpu@1 {
1213 device_type = "cpu";
1214 compatible = "arm,cortex-a15";
1215 reg = <1>;
1216 };
1217
1218 cpu@2 {
1219 device_type = "cpu";
1220 compatible = "arm,cortex-a15";
1221 reg = <2>;
1222 };
1223
1224 cpu@3 {
1225 device_type = "cpu";
1226 compatible = "arm,cortex-a15";
1227 reg = <3>;
1228 };
1229 };
1230
1231 pmu {
1232 compatible = "arm,cortex-a15-pmu";
1233 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1237 interrupt-affinity = <&{/cpus/cpu@0}>,
1238 <&{/cpus/cpu@1}>,
1239 <&{/cpus/cpu@2}>,
1240 <&{/cpus/cpu@3}>;
1241 };
1242
1243 thermal-zones {
1244 cpu {
1245 polling-delay-passive = <1000>;
1246 polling-delay = <1000>;
1247
1248 thermal-sensors =
1249 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1250
1251 trips {
1252 cpu-shutdown-trip {
1253 temperature = <103000>;
1254 hysteresis = <0>;
1255 type = "critical";
1256 };
1257 cpu_throttle_trip: throttle-trip {
1258 temperature = <100000>;
1259 hysteresis = <1000>;
1260 type = "hot";
1261 };
1262 };
1263
1264 cooling-maps {
1265 map0 {
1266 trip = <&cpu_throttle_trip>;
1267 cooling-device = <&throttle_heavy 1 1>;
1268 };
1269 };
1270 };
1271
1272 mem {
1273 polling-delay-passive = <1000>;
1274 polling-delay = <1000>;
1275
1276 thermal-sensors =
1277 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1278
1279 trips {
1280 mem-shutdown-trip {
1281 temperature = <103000>;
1282 hysteresis = <0>;
1283 type = "critical";
1284 };
1285 mem-throttle-trip {
1286 temperature = <99000>;
1287 hysteresis = <1000>;
1288 type = "hot";
1289 };
1290 };
1291
1292 cooling-maps {
1293 /*
1294 * There are currently no cooling maps,
1295 * because there are no cooling devices.
1296 */
1297 };
1298 };
1299
1300 gpu {
1301 polling-delay-passive = <1000>;
1302 polling-delay = <1000>;
1303
1304 thermal-sensors =
1305 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1306
1307 trips {
1308 gpu-shutdown-trip {
1309 temperature = <101000>;
1310 hysteresis = <0>;
1311 type = "critical";
1312 };
1313 gpu_throttle_trip: throttle-trip {
1314 temperature = <99000>;
1315 hysteresis = <1000>;
1316 type = "hot";
1317 };
1318 };
1319
1320 cooling-maps {
1321 map0 {
1322 trip = <&gpu_throttle_trip>;
1323 cooling-device = <&throttle_heavy 1 1>;
1324 };
1325 };
1326 };
1327
1328 pllx {
1329 polling-delay-passive = <1000>;
1330 polling-delay = <1000>;
1331
1332 thermal-sensors =
1333 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1334
1335 trips {
1336 pllx-shutdown-trip {
1337 temperature = <103000>;
1338 hysteresis = <0>;
1339 type = "critical";
1340 };
1341 pllx-throttle-trip {
1342 temperature = <99000>;
1343 hysteresis = <1000>;
1344 type = "hot";
1345 };
1346 };
1347
1348 cooling-maps {
1349 /*
1350 * There are currently no cooling maps,
1351 * because there are no cooling devices.
1352 */
1353 };
1354 };
1355 };
1356
1357 timer {
1358 compatible = "arm,armv7-timer";
1359 interrupts = <GIC_PPI 13
1360 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1361 <GIC_PPI 14
1362 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1363 <GIC_PPI 11
1364 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1365 <GIC_PPI 10
1366 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1367 interrupt-parent = <&gic>;
1368 };
1369};
1#include <dt-bindings/clock/tegra124-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/memory/tegra124-mc.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/reset/tegra124-car.h>
8#include <dt-bindings/thermal/tegra124-soctherm.h>
9
10#include "skeleton.dtsi"
11
12/ {
13 compatible = "nvidia,tegra124";
14 interrupt-parent = <&lic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 pcie-controller@0,01003000 {
19 compatible = "nvidia,tegra124-pcie";
20 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
22 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
23 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi";
28
29 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32
33 bus-range = <0x00 0xff>;
34 #address-cells = <3>;
35 #size-cells = <2>;
36
37 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
38 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
39 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
40 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
41 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42
43 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
44 <&tegra_car TEGRA124_CLK_AFI>,
45 <&tegra_car TEGRA124_CLK_PLL_E>,
46 <&tegra_car TEGRA124_CLK_CML0>;
47 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>,
49 <&tegra_car 72>,
50 <&tegra_car 74>;
51 reset-names = "pex", "afi", "pcie_x";
52 status = "disabled";
53
54 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
55 phy-names = "pcie";
56
57 pci@1,0 {
58 device_type = "pci";
59 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
61 status = "disabled";
62
63 #address-cells = <3>;
64 #size-cells = <2>;
65 ranges;
66
67 nvidia,num-lanes = <2>;
68 };
69
70 pci@2,0 {
71 device_type = "pci";
72 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
73 reg = <0x001000 0 0 0 0>;
74 status = "disabled";
75
76 #address-cells = <3>;
77 #size-cells = <2>;
78 ranges;
79
80 nvidia,num-lanes = <1>;
81 };
82 };
83
84 host1x@0,50000000 {
85 compatible = "nvidia,tegra124-host1x", "simple-bus";
86 reg = <0x0 0x50000000 0x0 0x00034000>;
87 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
88 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
90 resets = <&tegra_car 28>;
91 reset-names = "host1x";
92
93 #address-cells = <2>;
94 #size-cells = <2>;
95
96 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
97
98 dc@0,54200000 {
99 compatible = "nvidia,tegra124-dc";
100 reg = <0x0 0x54200000 0x0 0x00040000>;
101 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
103 <&tegra_car TEGRA124_CLK_PLL_P>;
104 clock-names = "dc", "parent";
105 resets = <&tegra_car 27>;
106 reset-names = "dc";
107
108 iommus = <&mc TEGRA_SWGROUP_DC>;
109
110 nvidia,head = <0>;
111 };
112
113 dc@0,54240000 {
114 compatible = "nvidia,tegra124-dc";
115 reg = <0x0 0x54240000 0x0 0x00040000>;
116 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
118 <&tegra_car TEGRA124_CLK_PLL_P>;
119 clock-names = "dc", "parent";
120 resets = <&tegra_car 26>;
121 reset-names = "dc";
122
123 iommus = <&mc TEGRA_SWGROUP_DCB>;
124
125 nvidia,head = <1>;
126 };
127
128 hdmi@0,54280000 {
129 compatible = "nvidia,tegra124-hdmi";
130 reg = <0x0 0x54280000 0x0 0x00040000>;
131 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
133 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
134 clock-names = "hdmi", "parent";
135 resets = <&tegra_car 51>;
136 reset-names = "hdmi";
137 status = "disabled";
138 };
139
140 sor@0,54540000 {
141 compatible = "nvidia,tegra124-sor";
142 reg = <0x0 0x54540000 0x0 0x00040000>;
143 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
145 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
146 <&tegra_car TEGRA124_CLK_PLL_DP>,
147 <&tegra_car TEGRA124_CLK_CLK_M>;
148 clock-names = "sor", "parent", "dp", "safe";
149 resets = <&tegra_car 182>;
150 reset-names = "sor";
151 status = "disabled";
152 };
153
154 dpaux: dpaux@0,545c0000 {
155 compatible = "nvidia,tegra124-dpaux";
156 reg = <0x0 0x545c0000 0x0 0x00040000>;
157 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
159 <&tegra_car TEGRA124_CLK_PLL_DP>;
160 clock-names = "dpaux", "parent";
161 resets = <&tegra_car 181>;
162 reset-names = "dpaux";
163 status = "disabled";
164 };
165 };
166
167 gic: interrupt-controller@0,50041000 {
168 compatible = "arm,cortex-a15-gic";
169 #interrupt-cells = <3>;
170 interrupt-controller;
171 reg = <0x0 0x50041000 0x0 0x1000>,
172 <0x0 0x50042000 0x0 0x1000>,
173 <0x0 0x50044000 0x0 0x2000>,
174 <0x0 0x50046000 0x0 0x2000>;
175 interrupts = <GIC_PPI 9
176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 interrupt-parent = <&gic>;
178 };
179
180 gpu@0,57000000 {
181 compatible = "nvidia,gk20a";
182 reg = <0x0 0x57000000 0x0 0x01000000>,
183 <0x0 0x58000000 0x0 0x01000000>;
184 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-names = "stall", "nonstall";
187 clocks = <&tegra_car TEGRA124_CLK_GPU>,
188 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
189 clock-names = "gpu", "pwr";
190 resets = <&tegra_car 184>;
191 reset-names = "gpu";
192
193 iommus = <&mc TEGRA_SWGROUP_GPU>;
194
195 status = "disabled";
196 };
197
198 lic: interrupt-controller@60004000 {
199 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
200 reg = <0x0 0x60004000 0x0 0x100>,
201 <0x0 0x60004100 0x0 0x100>,
202 <0x0 0x60004200 0x0 0x100>,
203 <0x0 0x60004300 0x0 0x100>,
204 <0x0 0x60004400 0x0 0x100>;
205 interrupt-controller;
206 #interrupt-cells = <3>;
207 interrupt-parent = <&gic>;
208 };
209
210 timer@0,60005000 {
211 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
212 reg = <0x0 0x60005000 0x0 0x400>;
213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
220 };
221
222 tegra_car: clock@0,60006000 {
223 compatible = "nvidia,tegra124-car";
224 reg = <0x0 0x60006000 0x0 0x1000>;
225 #clock-cells = <1>;
226 #reset-cells = <1>;
227 nvidia,external-memory-controller = <&emc>;
228 };
229
230 flow-controller@0,60007000 {
231 compatible = "nvidia,tegra124-flowctrl";
232 reg = <0x0 0x60007000 0x0 0x1000>;
233 };
234
235 actmon@0,6000c800 {
236 compatible = "nvidia,tegra124-actmon";
237 reg = <0x0 0x6000c800 0x0 0x400>;
238 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
240 <&tegra_car TEGRA124_CLK_EMC>;
241 clock-names = "actmon", "emc";
242 resets = <&tegra_car 119>;
243 reset-names = "actmon";
244 };
245
246 gpio: gpio@0,6000d000 {
247 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
248 reg = <0x0 0x6000d000 0x0 0x1000>;
249 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
257 #gpio-cells = <2>;
258 gpio-controller;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 /*
262 gpio-ranges = <&pinmux 0 0 251>;
263 */
264 };
265
266 apbdma: dma@0,60020000 {
267 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
268 reg = <0x0 0x60020000 0x0 0x1400>;
269 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
302 resets = <&tegra_car 34>;
303 reset-names = "dma";
304 #dma-cells = <1>;
305 };
306
307 apbmisc@0,70000800 {
308 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
309 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
310 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
311 };
312
313 pinmux: pinmux@0,70000868 {
314 compatible = "nvidia,tegra124-pinmux";
315 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
316 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
317 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
318 };
319
320 /*
321 * There are two serial driver i.e. 8250 based simple serial
322 * driver and APB DMA based serial driver for higher baudrate
323 * and performace. To enable the 8250 based driver, the compatible
324 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
325 * the APB DMA based serial driver, the comptible is
326 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
327 */
328 uarta: serial@0,70006000 {
329 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
330 reg = <0x0 0x70006000 0x0 0x40>;
331 reg-shift = <2>;
332 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
334 resets = <&tegra_car 6>;
335 reset-names = "serial";
336 dmas = <&apbdma 8>, <&apbdma 8>;
337 dma-names = "rx", "tx";
338 status = "disabled";
339 };
340
341 uartb: serial@0,70006040 {
342 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
343 reg = <0x0 0x70006040 0x0 0x40>;
344 reg-shift = <2>;
345 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
347 resets = <&tegra_car 7>;
348 reset-names = "serial";
349 dmas = <&apbdma 9>, <&apbdma 9>;
350 dma-names = "rx", "tx";
351 status = "disabled";
352 };
353
354 uartc: serial@0,70006200 {
355 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
356 reg = <0x0 0x70006200 0x0 0x40>;
357 reg-shift = <2>;
358 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
360 resets = <&tegra_car 55>;
361 reset-names = "serial";
362 dmas = <&apbdma 10>, <&apbdma 10>;
363 dma-names = "rx", "tx";
364 status = "disabled";
365 };
366
367 uartd: serial@0,70006300 {
368 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
369 reg = <0x0 0x70006300 0x0 0x40>;
370 reg-shift = <2>;
371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
373 resets = <&tegra_car 65>;
374 reset-names = "serial";
375 dmas = <&apbdma 19>, <&apbdma 19>;
376 dma-names = "rx", "tx";
377 status = "disabled";
378 };
379
380 pwm: pwm@0,7000a000 {
381 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
382 reg = <0x0 0x7000a000 0x0 0x100>;
383 #pwm-cells = <2>;
384 clocks = <&tegra_car TEGRA124_CLK_PWM>;
385 resets = <&tegra_car 17>;
386 reset-names = "pwm";
387 status = "disabled";
388 };
389
390 i2c@0,7000c000 {
391 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
392 reg = <0x0 0x7000c000 0x0 0x100>;
393 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
394 #address-cells = <1>;
395 #size-cells = <0>;
396 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
397 clock-names = "div-clk";
398 resets = <&tegra_car 12>;
399 reset-names = "i2c";
400 dmas = <&apbdma 21>, <&apbdma 21>;
401 dma-names = "rx", "tx";
402 status = "disabled";
403 };
404
405 i2c@0,7000c400 {
406 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
407 reg = <0x0 0x7000c400 0x0 0x100>;
408 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
409 #address-cells = <1>;
410 #size-cells = <0>;
411 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
412 clock-names = "div-clk";
413 resets = <&tegra_car 54>;
414 reset-names = "i2c";
415 dmas = <&apbdma 22>, <&apbdma 22>;
416 dma-names = "rx", "tx";
417 status = "disabled";
418 };
419
420 i2c@0,7000c500 {
421 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
422 reg = <0x0 0x7000c500 0x0 0x100>;
423 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
424 #address-cells = <1>;
425 #size-cells = <0>;
426 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
427 clock-names = "div-clk";
428 resets = <&tegra_car 67>;
429 reset-names = "i2c";
430 dmas = <&apbdma 23>, <&apbdma 23>;
431 dma-names = "rx", "tx";
432 status = "disabled";
433 };
434
435 i2c@0,7000c700 {
436 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
437 reg = <0x0 0x7000c700 0x0 0x100>;
438 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
442 clock-names = "div-clk";
443 resets = <&tegra_car 103>;
444 reset-names = "i2c";
445 dmas = <&apbdma 26>, <&apbdma 26>;
446 dma-names = "rx", "tx";
447 status = "disabled";
448 };
449
450 i2c@0,7000d000 {
451 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
452 reg = <0x0 0x7000d000 0x0 0x100>;
453 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
457 clock-names = "div-clk";
458 resets = <&tegra_car 47>;
459 reset-names = "i2c";
460 dmas = <&apbdma 24>, <&apbdma 24>;
461 dma-names = "rx", "tx";
462 status = "disabled";
463 };
464
465 i2c@0,7000d100 {
466 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
467 reg = <0x0 0x7000d100 0x0 0x100>;
468 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
469 #address-cells = <1>;
470 #size-cells = <0>;
471 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
472 clock-names = "div-clk";
473 resets = <&tegra_car 166>;
474 reset-names = "i2c";
475 dmas = <&apbdma 30>, <&apbdma 30>;
476 dma-names = "rx", "tx";
477 status = "disabled";
478 };
479
480 spi@0,7000d400 {
481 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
482 reg = <0x0 0x7000d400 0x0 0x200>;
483 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
484 #address-cells = <1>;
485 #size-cells = <0>;
486 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
487 clock-names = "spi";
488 resets = <&tegra_car 41>;
489 reset-names = "spi";
490 dmas = <&apbdma 15>, <&apbdma 15>;
491 dma-names = "rx", "tx";
492 status = "disabled";
493 };
494
495 spi@0,7000d600 {
496 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
497 reg = <0x0 0x7000d600 0x0 0x200>;
498 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>;
500 #size-cells = <0>;
501 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
502 clock-names = "spi";
503 resets = <&tegra_car 44>;
504 reset-names = "spi";
505 dmas = <&apbdma 16>, <&apbdma 16>;
506 dma-names = "rx", "tx";
507 status = "disabled";
508 };
509
510 spi@0,7000d800 {
511 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
512 reg = <0x0 0x7000d800 0x0 0x200>;
513 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
517 clock-names = "spi";
518 resets = <&tegra_car 46>;
519 reset-names = "spi";
520 dmas = <&apbdma 17>, <&apbdma 17>;
521 dma-names = "rx", "tx";
522 status = "disabled";
523 };
524
525 spi@0,7000da00 {
526 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
527 reg = <0x0 0x7000da00 0x0 0x200>;
528 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
529 #address-cells = <1>;
530 #size-cells = <0>;
531 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
532 clock-names = "spi";
533 resets = <&tegra_car 68>;
534 reset-names = "spi";
535 dmas = <&apbdma 18>, <&apbdma 18>;
536 dma-names = "rx", "tx";
537 status = "disabled";
538 };
539
540 spi@0,7000dc00 {
541 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
542 reg = <0x0 0x7000dc00 0x0 0x200>;
543 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
544 #address-cells = <1>;
545 #size-cells = <0>;
546 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
547 clock-names = "spi";
548 resets = <&tegra_car 104>;
549 reset-names = "spi";
550 dmas = <&apbdma 27>, <&apbdma 27>;
551 dma-names = "rx", "tx";
552 status = "disabled";
553 };
554
555 spi@0,7000de00 {
556 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
557 reg = <0x0 0x7000de00 0x0 0x200>;
558 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
562 clock-names = "spi";
563 resets = <&tegra_car 105>;
564 reset-names = "spi";
565 dmas = <&apbdma 28>, <&apbdma 28>;
566 dma-names = "rx", "tx";
567 status = "disabled";
568 };
569
570 rtc@0,7000e000 {
571 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
572 reg = <0x0 0x7000e000 0x0 0x100>;
573 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&tegra_car TEGRA124_CLK_RTC>;
575 };
576
577 pmc@0,7000e400 {
578 compatible = "nvidia,tegra124-pmc";
579 reg = <0x0 0x7000e400 0x0 0x400>;
580 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
581 clock-names = "pclk", "clk32k_in";
582 };
583
584 fuse@0,7000f800 {
585 compatible = "nvidia,tegra124-efuse";
586 reg = <0x0 0x7000f800 0x0 0x400>;
587 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
588 clock-names = "fuse";
589 resets = <&tegra_car 39>;
590 reset-names = "fuse";
591 };
592
593 mc: memory-controller@0,70019000 {
594 compatible = "nvidia,tegra124-mc";
595 reg = <0x0 0x70019000 0x0 0x1000>;
596 clocks = <&tegra_car TEGRA124_CLK_MC>;
597 clock-names = "mc";
598
599 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
600
601 #iommu-cells = <1>;
602 };
603
604 emc: emc@0,7001b000 {
605 compatible = "nvidia,tegra124-emc";
606 reg = <0x0 0x7001b000 0x0 0x1000>;
607
608 nvidia,memory-controller = <&mc>;
609 };
610
611 sata@0,70020000 {
612 compatible = "nvidia,tegra124-ahci";
613 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
614 <0x0 0x70020000 0x0 0x7000>; /* SATA */
615 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&tegra_car TEGRA124_CLK_SATA>,
617 <&tegra_car TEGRA124_CLK_SATA_OOB>,
618 <&tegra_car TEGRA124_CLK_CML1>,
619 <&tegra_car TEGRA124_CLK_PLL_E>;
620 clock-names = "sata", "sata-oob", "cml1", "pll_e";
621 resets = <&tegra_car 124>,
622 <&tegra_car 123>,
623 <&tegra_car 129>;
624 reset-names = "sata", "sata-oob", "sata-cold";
625 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
626 phy-names = "sata-phy";
627 status = "disabled";
628 };
629
630 hda@0,70030000 {
631 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
632 reg = <0x0 0x70030000 0x0 0x10000>;
633 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&tegra_car TEGRA124_CLK_HDA>,
635 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
636 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
637 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
638 resets = <&tegra_car 125>, /* hda */
639 <&tegra_car 128>, /* hda2hdmi */
640 <&tegra_car 111>; /* hda2codec_2x */
641 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
642 status = "disabled";
643 };
644
645 padctl: padctl@0,7009f000 {
646 compatible = "nvidia,tegra124-xusb-padctl";
647 reg = <0x0 0x7009f000 0x0 0x1000>;
648 resets = <&tegra_car 142>;
649 reset-names = "padctl";
650
651 #phy-cells = <1>;
652 };
653
654 sdhci@0,700b0000 {
655 compatible = "nvidia,tegra124-sdhci";
656 reg = <0x0 0x700b0000 0x0 0x200>;
657 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
659 resets = <&tegra_car 14>;
660 reset-names = "sdhci";
661 status = "disabled";
662 };
663
664 sdhci@0,700b0200 {
665 compatible = "nvidia,tegra124-sdhci";
666 reg = <0x0 0x700b0200 0x0 0x200>;
667 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
669 resets = <&tegra_car 9>;
670 reset-names = "sdhci";
671 status = "disabled";
672 };
673
674 sdhci@0,700b0400 {
675 compatible = "nvidia,tegra124-sdhci";
676 reg = <0x0 0x700b0400 0x0 0x200>;
677 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
679 resets = <&tegra_car 69>;
680 reset-names = "sdhci";
681 status = "disabled";
682 };
683
684 sdhci@0,700b0600 {
685 compatible = "nvidia,tegra124-sdhci";
686 reg = <0x0 0x700b0600 0x0 0x200>;
687 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
689 resets = <&tegra_car 15>;
690 reset-names = "sdhci";
691 status = "disabled";
692 };
693
694 soctherm: thermal-sensor@0,700e2000 {
695 compatible = "nvidia,tegra124-soctherm";
696 reg = <0x0 0x700e2000 0x0 0x1000>;
697 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
699 <&tegra_car TEGRA124_CLK_SOC_THERM>;
700 clock-names = "tsensor", "soctherm";
701 resets = <&tegra_car 78>;
702 reset-names = "soctherm";
703 #thermal-sensor-cells = <1>;
704 };
705
706 dfll: clock@0,70110000 {
707 compatible = "nvidia,tegra124-dfll";
708 reg = <0 0x70110000 0 0x100>, /* DFLL control */
709 <0 0x70110000 0 0x100>, /* I2C output control */
710 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
711 <0 0x70110200 0 0x100>; /* Look-up table RAM */
712 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
714 <&tegra_car TEGRA124_CLK_DFLL_REF>,
715 <&tegra_car TEGRA124_CLK_I2C5>;
716 clock-names = "soc", "ref", "i2c";
717 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
718 reset-names = "dvco";
719 #clock-cells = <0>;
720 clock-output-names = "dfllCPU_out";
721 nvidia,sample-rate = <12500>;
722 nvidia,droop-ctrl = <0x00000f00>;
723 nvidia,force-mode = <1>;
724 nvidia,cf = <10>;
725 nvidia,ci = <0>;
726 nvidia,cg = <2>;
727 status = "disabled";
728 };
729
730 ahub@0,70300000 {
731 compatible = "nvidia,tegra124-ahub";
732 reg = <0x0 0x70300000 0x0 0x200>,
733 <0x0 0x70300800 0x0 0x800>,
734 <0x0 0x70300200 0x0 0x600>;
735 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
737 <&tegra_car TEGRA124_CLK_APBIF>;
738 clock-names = "d_audio", "apbif";
739 resets = <&tegra_car 106>, /* d_audio */
740 <&tegra_car 107>, /* apbif */
741 <&tegra_car 30>, /* i2s0 */
742 <&tegra_car 11>, /* i2s1 */
743 <&tegra_car 18>, /* i2s2 */
744 <&tegra_car 101>, /* i2s3 */
745 <&tegra_car 102>, /* i2s4 */
746 <&tegra_car 108>, /* dam0 */
747 <&tegra_car 109>, /* dam1 */
748 <&tegra_car 110>, /* dam2 */
749 <&tegra_car 10>, /* spdif */
750 <&tegra_car 153>, /* amx */
751 <&tegra_car 185>, /* amx1 */
752 <&tegra_car 154>, /* adx */
753 <&tegra_car 180>, /* adx1 */
754 <&tegra_car 186>, /* afc0 */
755 <&tegra_car 187>, /* afc1 */
756 <&tegra_car 188>, /* afc2 */
757 <&tegra_car 189>, /* afc3 */
758 <&tegra_car 190>, /* afc4 */
759 <&tegra_car 191>; /* afc5 */
760 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
761 "i2s3", "i2s4", "dam0", "dam1", "dam2",
762 "spdif", "amx", "amx1", "adx", "adx1",
763 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
764 dmas = <&apbdma 1>, <&apbdma 1>,
765 <&apbdma 2>, <&apbdma 2>,
766 <&apbdma 3>, <&apbdma 3>,
767 <&apbdma 4>, <&apbdma 4>,
768 <&apbdma 6>, <&apbdma 6>,
769 <&apbdma 7>, <&apbdma 7>,
770 <&apbdma 12>, <&apbdma 12>,
771 <&apbdma 13>, <&apbdma 13>,
772 <&apbdma 14>, <&apbdma 14>,
773 <&apbdma 29>, <&apbdma 29>;
774 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
775 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
776 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
777 "rx9", "tx9";
778 ranges;
779 #address-cells = <2>;
780 #size-cells = <2>;
781
782 tegra_i2s0: i2s@0,70301000 {
783 compatible = "nvidia,tegra124-i2s";
784 reg = <0x0 0x70301000 0x0 0x100>;
785 nvidia,ahub-cif-ids = <4 4>;
786 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
787 resets = <&tegra_car 30>;
788 reset-names = "i2s";
789 status = "disabled";
790 };
791
792 tegra_i2s1: i2s@0,70301100 {
793 compatible = "nvidia,tegra124-i2s";
794 reg = <0x0 0x70301100 0x0 0x100>;
795 nvidia,ahub-cif-ids = <5 5>;
796 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
797 resets = <&tegra_car 11>;
798 reset-names = "i2s";
799 status = "disabled";
800 };
801
802 tegra_i2s2: i2s@0,70301200 {
803 compatible = "nvidia,tegra124-i2s";
804 reg = <0x0 0x70301200 0x0 0x100>;
805 nvidia,ahub-cif-ids = <6 6>;
806 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
807 resets = <&tegra_car 18>;
808 reset-names = "i2s";
809 status = "disabled";
810 };
811
812 tegra_i2s3: i2s@0,70301300 {
813 compatible = "nvidia,tegra124-i2s";
814 reg = <0x0 0x70301300 0x0 0x100>;
815 nvidia,ahub-cif-ids = <7 7>;
816 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
817 resets = <&tegra_car 101>;
818 reset-names = "i2s";
819 status = "disabled";
820 };
821
822 tegra_i2s4: i2s@0,70301400 {
823 compatible = "nvidia,tegra124-i2s";
824 reg = <0x0 0x70301400 0x0 0x100>;
825 nvidia,ahub-cif-ids = <8 8>;
826 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
827 resets = <&tegra_car 102>;
828 reset-names = "i2s";
829 status = "disabled";
830 };
831 };
832
833 usb@0,7d000000 {
834 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
835 reg = <0x0 0x7d000000 0x0 0x4000>;
836 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
837 phy_type = "utmi";
838 clocks = <&tegra_car TEGRA124_CLK_USBD>;
839 resets = <&tegra_car 22>;
840 reset-names = "usb";
841 nvidia,phy = <&phy1>;
842 status = "disabled";
843 };
844
845 phy1: usb-phy@0,7d000000 {
846 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
847 reg = <0x0 0x7d000000 0x0 0x4000>,
848 <0x0 0x7d000000 0x0 0x4000>;
849 phy_type = "utmi";
850 clocks = <&tegra_car TEGRA124_CLK_USBD>,
851 <&tegra_car TEGRA124_CLK_PLL_U>,
852 <&tegra_car TEGRA124_CLK_USBD>;
853 clock-names = "reg", "pll_u", "utmi-pads";
854 resets = <&tegra_car 22>, <&tegra_car 22>;
855 reset-names = "usb", "utmi-pads";
856 nvidia,hssync-start-delay = <0>;
857 nvidia,idle-wait-delay = <17>;
858 nvidia,elastic-limit = <16>;
859 nvidia,term-range-adj = <6>;
860 nvidia,xcvr-setup = <9>;
861 nvidia,xcvr-lsfslew = <0>;
862 nvidia,xcvr-lsrslew = <3>;
863 nvidia,hssquelch-level = <2>;
864 nvidia,hsdiscon-level = <5>;
865 nvidia,xcvr-hsslew = <12>;
866 nvidia,has-utmi-pad-registers;
867 status = "disabled";
868 };
869
870 usb@0,7d004000 {
871 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
872 reg = <0x0 0x7d004000 0x0 0x4000>;
873 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
874 phy_type = "utmi";
875 clocks = <&tegra_car TEGRA124_CLK_USB2>;
876 resets = <&tegra_car 58>;
877 reset-names = "usb";
878 nvidia,phy = <&phy2>;
879 status = "disabled";
880 };
881
882 phy2: usb-phy@0,7d004000 {
883 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
884 reg = <0x0 0x7d004000 0x0 0x4000>,
885 <0x0 0x7d000000 0x0 0x4000>;
886 phy_type = "utmi";
887 clocks = <&tegra_car TEGRA124_CLK_USB2>,
888 <&tegra_car TEGRA124_CLK_PLL_U>,
889 <&tegra_car TEGRA124_CLK_USBD>;
890 clock-names = "reg", "pll_u", "utmi-pads";
891 resets = <&tegra_car 58>, <&tegra_car 22>;
892 reset-names = "usb", "utmi-pads";
893 nvidia,hssync-start-delay = <0>;
894 nvidia,idle-wait-delay = <17>;
895 nvidia,elastic-limit = <16>;
896 nvidia,term-range-adj = <6>;
897 nvidia,xcvr-setup = <9>;
898 nvidia,xcvr-lsfslew = <0>;
899 nvidia,xcvr-lsrslew = <3>;
900 nvidia,hssquelch-level = <2>;
901 nvidia,hsdiscon-level = <5>;
902 nvidia,xcvr-hsslew = <12>;
903 status = "disabled";
904 };
905
906 usb@0,7d008000 {
907 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
908 reg = <0x0 0x7d008000 0x0 0x4000>;
909 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
910 phy_type = "utmi";
911 clocks = <&tegra_car TEGRA124_CLK_USB3>;
912 resets = <&tegra_car 59>;
913 reset-names = "usb";
914 nvidia,phy = <&phy3>;
915 status = "disabled";
916 };
917
918 phy3: usb-phy@0,7d008000 {
919 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
920 reg = <0x0 0x7d008000 0x0 0x4000>,
921 <0x0 0x7d000000 0x0 0x4000>;
922 phy_type = "utmi";
923 clocks = <&tegra_car TEGRA124_CLK_USB3>,
924 <&tegra_car TEGRA124_CLK_PLL_U>,
925 <&tegra_car TEGRA124_CLK_USBD>;
926 clock-names = "reg", "pll_u", "utmi-pads";
927 resets = <&tegra_car 59>, <&tegra_car 22>;
928 reset-names = "usb", "utmi-pads";
929 nvidia,hssync-start-delay = <0>;
930 nvidia,idle-wait-delay = <17>;
931 nvidia,elastic-limit = <16>;
932 nvidia,term-range-adj = <6>;
933 nvidia,xcvr-setup = <9>;
934 nvidia,xcvr-lsfslew = <0>;
935 nvidia,xcvr-lsrslew = <3>;
936 nvidia,hssquelch-level = <2>;
937 nvidia,hsdiscon-level = <5>;
938 nvidia,xcvr-hsslew = <12>;
939 status = "disabled";
940 };
941
942 cpus {
943 #address-cells = <1>;
944 #size-cells = <0>;
945
946 cpu@0 {
947 device_type = "cpu";
948 compatible = "arm,cortex-a15";
949 reg = <0>;
950
951 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
952 <&tegra_car TEGRA124_CLK_CCLK_LP>,
953 <&tegra_car TEGRA124_CLK_PLL_X>,
954 <&tegra_car TEGRA124_CLK_PLL_P>,
955 <&dfll>;
956 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
957 /* FIXME: what's the actual transition time? */
958 clock-latency = <300000>;
959 };
960
961 cpu@1 {
962 device_type = "cpu";
963 compatible = "arm,cortex-a15";
964 reg = <1>;
965 };
966
967 cpu@2 {
968 device_type = "cpu";
969 compatible = "arm,cortex-a15";
970 reg = <2>;
971 };
972
973 cpu@3 {
974 device_type = "cpu";
975 compatible = "arm,cortex-a15";
976 reg = <3>;
977 };
978 };
979
980 pmu {
981 compatible = "arm,cortex-a15-pmu";
982 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
986 interrupt-affinity = <&{/cpus/cpu@0}>,
987 <&{/cpus/cpu@1}>,
988 <&{/cpus/cpu@2}>,
989 <&{/cpus/cpu@3}>;
990 };
991
992 thermal-zones {
993 cpu {
994 polling-delay-passive = <1000>;
995 polling-delay = <1000>;
996
997 thermal-sensors =
998 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
999 };
1000
1001 mem {
1002 polling-delay-passive = <1000>;
1003 polling-delay = <1000>;
1004
1005 thermal-sensors =
1006 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1007 };
1008
1009 gpu {
1010 polling-delay-passive = <1000>;
1011 polling-delay = <1000>;
1012
1013 thermal-sensors =
1014 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1015 };
1016
1017 pllx {
1018 polling-delay-passive = <1000>;
1019 polling-delay = <1000>;
1020
1021 thermal-sensors =
1022 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1023 };
1024 };
1025
1026 timer {
1027 compatible = "arm,armv7-timer";
1028 interrupts = <GIC_PPI 13
1029 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1030 <GIC_PPI 14
1031 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1032 <GIC_PPI 11
1033 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1034 <GIC_PPI 10
1035 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1036 interrupt-parent = <&gic>;
1037 };
1038};