1/*
  2 * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
  3 *
  4 * This file is licensed under the terms of the GNU General Public
  5 * License version 2. This program is licensed "as is" without any
  6 * warranty of any kind, whether express or implied.
  7 */
  8
  9/dts-v1/;
 10
 11#include <dt-bindings/gpio/gpio.h>
 12#include <dt-bindings/input/input.h>
 13#include "orion5x-mv88f5181.dtsi"
 14
 15/ {
 16	model = "Netgear WNR854-t";
 17	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
 18		     "marvell,orion5x";
 19	aliases {
 20		serial0 = &uart0;
 21	};
 22
 23	memory {
 24		device_type = "memory";
 25		reg = <0x00000000 0x2000000>; /* 32 MB */
 26	};
 27
 28	chosen {
 29		stdout-path = "serial0:115200n8";
 30	};
 31
 32	soc {
 33		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
 34			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
 35			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
 36	};
 37
 38	gpio-keys {
 39		compatible = "gpio-keys";
 40		pinctrl-0 = <&pmx_reset_button>;
 41		pinctrl-names = "default";
 42
 43		reset {
 44			label = "Reset Button";
 45			linux,code = <KEY_RESTART>;
 46			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 47		};
 48	};
 49
 50	gpio-leds {
 51		compatible = "gpio-leds";
 52		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
 53		pinctrl-names = "default";
 54
 55		led@0 {
 56			label = "wnr854t:green:power";
 57			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 58		};
 59
 60		led@1 {
 61			label = "wnr854t:blink:power";
 62			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
 63		};
 64
 65		led@2 {
 66			label = "wnr854t:green:wan";
 67			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
 68		};
 69	};
 70};
 71
 72&devbus_bootcs {
 73	status = "okay";
 74
 75	devbus,keep-config;
 76
 77	flash@0 {
 78		compatible = "cfi-flash";
 79		reg = <0 0x800000>;
 80		bank-width = <2>;
 81
 82		partitions {
 83			compatible = "fixed-partitions";
 84			#address-cells = <1>;
 85			#size-cells = <1>;
 86
 87			partition@0 {
 88				label = "kernel";
 89				reg = <0x0 0x100000>;
 90			};
 91
 92			partition@100000 {
 93				label = "rootfs";
 94				reg = <0x100000 0x660000>;
 95			};
 96
 97			partition@760000 {
 98				label = "uboot_env";
 99				reg = <0x760000 0x20000>;
100			};
101
102			partition@780000 {
103				label = "uboot";
104				reg = <0x780000 0x80000>;
105				read-only;
106			};
107		};
108	};
109};
110
111&mdio {
112	status = "okay";
113
114	switch: switch@0 {
115		compatible = "marvell,mv88e6085";
116		#address-cells = <1>;
117		#size-cells = <0>;
118		reg = <0>;
119		dsa,member = <0 0>;
120
121		ports {
122			#address-cells = <1>;
123			#size-cells = <0>;
124
125			port@0 {
126				reg = <0>;
127				label = "lan3";
128				phy-handle = <&lan3phy>;
129			};
130
131			port@1 {
132				reg = <1>;
133				label = "lan4";
134				phy-handle = <&lan4phy>;
135			};
136
137			port@2 {
138				reg = <2>;
139				label = "wan";
140				phy-handle = <&wanphy>;
141			};
142
143			port@3 {
144				reg = <3>;
145				label = "cpu";
146				ethernet = <&ethport>;
147			};
148
149			port@5 {
150				reg = <5>;
151				label = "lan1";
152				phy-handle = <&lan1phy>;
153			};
154
155			port@7 {
156				reg = <7>;
157				label = "lan2";
158				phy-handle = <&lan2phy>;
159			};
160		};
161
162		mdio {
163			#address-cells = <1>;
164			#size-cells = <0>;
165
166			lan3phy: ethernet-phy@0 {
167				/* Marvell 88E1121R (port 1) */
168				compatible = "ethernet-phy-id0141.0cb0",
169					     "ethernet-phy-ieee802.3-c22";
170				reg = <0>;
171				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
172			};
173
174			lan4phy: ethernet-phy@1 {
175				/* Marvell 88E1121R (port 2) */
176				compatible = "ethernet-phy-id0141.0cb0",
177					     "ethernet-phy-ieee802.3-c22";
178				reg = <1>;
179				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
180			};
181
182			wanphy: ethernet-phy@2 {
183				/* Marvell 88E1121R (port 1) */
184				compatible = "ethernet-phy-id0141.0cb0",
185					     "ethernet-phy-ieee802.3-c22";
186				reg = <2>;
187				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
188			};
189
190			lan1phy: ethernet-phy@5 {
191				/* Marvell 88E1112 */
192				compatible = "ethernet-phy-id0141.0cb0",
193					     "ethernet-phy-ieee802.3-c22";
194				reg = <5>;
195				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
196			};
197
198			lan2phy: ethernet-phy@7 {
199				/* Marvell 88E1112 */
200				compatible = "ethernet-phy-id0141.0cb0",
201					     "ethernet-phy-ieee802.3-c22";
202				reg = <7>;
203				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
204			};
205		};
206	};
207};
208
209&eth {
210	status = "okay";
211
212	ethernet-port@0 {
213		/* Hardwired to DSA switch */
214		speed = <1000>;
215		duplex = <1>;
216	};
217};
218
219&pinctrl {
220	pinctrl-0 = <&pmx_pci_gpios>;
221	pinctrl-names = "default";
222
223	pmx_power_led: pmx-power-led {
224		marvell,pins = "mpp0";
225		marvell,function = "gpio";
226	};
227
228	pmx_reset_button: pmx-reset-button {
229		marvell,pins = "mpp1";
230		marvell,function = "gpio";
231	};
232
233	pmx_power_led_blink: pmx-power-led-blink {
234		marvell,pins = "mpp2";
235		marvell,function = "gpio";
236	};
237
238	pmx_wan_led: pmx-wan-led {
239		marvell,pins = "mpp3";
240		marvell,function = "gpio";
241	};
242
243	pmx_pci_gpios: pmx-pci-gpios {
244		marvell,pins = "mpp4";
245		marvell,function = "gpio";
246	};
247};
248
249&uart0 {
250	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
251	status = "okay";
252};