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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6#include <dt-bindings/bus/ti-sysc.h>
7#include <dt-bindings/clock/omap4.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/omap.h>
11#include <dt-bindings/clock/omap4.h>
12
13/ {
14 compatible = "ti,omap4430", "ti,omap4";
15 interrupt-parent = <&wakeupgen>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18 chosen { };
19
20 aliases {
21 i2c0 = &i2c1;
22 i2c1 = &i2c2;
23 i2c2 = &i2c3;
24 i2c3 = &i2c4;
25 mmc0 = &mmc1;
26 mmc1 = &mmc2;
27 mmc2 = &mmc3;
28 mmc3 = &mmc4;
29 mmc4 = &mmc5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 rproc0 = &dsp;
35 rproc1 = &ipu;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 cpu@0 {
43 compatible = "arm,cortex-a9";
44 device_type = "cpu";
45 next-level-cache = <&L2>;
46 reg = <0x0>;
47
48 clocks = <&dpll_mpu_ck>;
49 clock-names = "cpu";
50
51 clock-latency = <300000>; /* From omap-cpufreq driver */
52 };
53 cpu@1 {
54 compatible = "arm,cortex-a9";
55 device_type = "cpu";
56 next-level-cache = <&L2>;
57 reg = <0x1>;
58 };
59 };
60
61 /*
62 * Needed early by omap4_sram_init() for barrier, do not move to l3
63 * interconnect as simple-pm-bus probes at module_init() time.
64 */
65 ocmcram: sram@40304000 {
66 compatible = "mmio-sram";
67 reg = <0x40304000 0xa000>; /* 40k */
68 };
69
70 gic: interrupt-controller@48241000 {
71 compatible = "arm,cortex-a9-gic";
72 interrupt-controller;
73 #interrupt-cells = <3>;
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
76 interrupt-parent = <&gic>;
77 };
78
79 L2: cache-controller@48242000 {
80 compatible = "arm,pl310-cache";
81 reg = <0x48242000 0x1000>;
82 cache-unified;
83 cache-level = <2>;
84 };
85
86 local-timer@48240600 {
87 compatible = "arm,cortex-a9-twd-timer";
88 clocks = <&mpu_periphclk>;
89 reg = <0x48240600 0x20>;
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
91 interrupt-parent = <&gic>;
92 };
93
94 wakeupgen: interrupt-controller@48281000 {
95 compatible = "ti,omap4-wugen-mpu";
96 interrupt-controller;
97 #interrupt-cells = <3>;
98 reg = <0x48281000 0x1000>;
99 interrupt-parent = <&gic>;
100 };
101
102 /*
103 * XXX: Use a flat representation of the OMAP4 interconnect.
104 * The real OMAP interconnect network is quite complex.
105 * Since it will not bring real advantage to represent that in DT for
106 * the moment, just use a fake OCP bus entry to represent the whole bus
107 * hierarchy.
108 */
109 ocp {
110 compatible = "simple-pm-bus";
111 power-domains = <&prm_l4per>;
112 clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
113 <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
114 <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges;
118
119 l3-noc@44000000 {
120 compatible = "ti,omap4-l3-noc";
121 reg = <0x44000000 0x1000>,
122 <0x44800000 0x2000>,
123 <0x45000000 0x1000>;
124 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
126 };
127
128 l4_wkup: interconnect@4a300000 {
129 };
130
131 l4_cfg: interconnect@4a000000 {
132 };
133
134 l4_per: interconnect@48000000 {
135 };
136
137 target-module@48210000 {
138 compatible = "ti,sysc-omap4-simple", "ti,sysc";
139 power-domains = <&prm_mpu>;
140 clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
141 clock-names = "fck";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges = <0 0x48210000 0x1f0000>;
145
146 mpu {
147 compatible = "ti,omap4-mpu";
148 sram = <&ocmcram>;
149 };
150 };
151
152 l4_abe: interconnect@40100000 {
153 };
154
155 target-module@50000000 {
156 compatible = "ti,sysc-omap2", "ti,sysc";
157 reg = <0x50000000 4>,
158 <0x50000010 4>,
159 <0x50000014 4>;
160 reg-names = "rev", "sysc", "syss";
161 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
162 <SYSC_IDLE_NO>,
163 <SYSC_IDLE_SMART>;
164 ti,syss-mask = <1>;
165 ti,no-idle-on-init;
166 clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
167 clock-names = "fck";
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
171 <0x00000000 0x00000000 0x40000000>; /* data */
172
173 gpmc: gpmc@50000000 {
174 compatible = "ti,omap4430-gpmc";
175 reg = <0x50000000 0x1000>;
176 #address-cells = <2>;
177 #size-cells = <1>;
178 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
179 dmas = <&sdma 4>;
180 dma-names = "rxtx";
181 gpmc,num-cs = <8>;
182 gpmc,num-waitpins = <4>;
183 clocks = <&l3_div_ck>;
184 clock-names = "fck";
185 interrupt-controller;
186 #interrupt-cells = <2>;
187 gpio-controller;
188 #gpio-cells = <2>;
189 };
190 };
191
192 target-module@52000000 {
193 compatible = "ti,sysc-omap4", "ti,sysc";
194 reg = <0x52000000 0x4>,
195 <0x52000010 0x4>;
196 reg-names = "rev", "sysc";
197 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
198 ti,sysc-midle = <SYSC_IDLE_FORCE>,
199 <SYSC_IDLE_NO>,
200 <SYSC_IDLE_SMART>,
201 <SYSC_IDLE_SMART_WKUP>;
202 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
203 <SYSC_IDLE_NO>,
204 <SYSC_IDLE_SMART>,
205 <SYSC_IDLE_SMART_WKUP>;
206 ti,sysc-delay-us = <2>;
207 power-domains = <&prm_cam>;
208 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
209 clock-names = "fck";
210 #address-cells = <1>;
211 #size-cells = <1>;
212 ranges = <0 0x52000000 0x1000000>;
213
214 /* No child device binding, driver in staging */
215 };
216
217 /*
218 * Note that 4430 needs cross trigger interface (CTI) supported
219 * before we can configure the interrupts. This means sampling
220 * events are not supported for pmu. Note that 4460 does not use
221 * CTI, see also 4460.dtsi.
222 */
223 target-module@54000000 {
224 compatible = "ti,sysc-omap4-simple", "ti,sysc";
225 power-domains = <&prm_emu>;
226 clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>;
227 clock-names = "fck";
228 #address-cells = <1>;
229 #size-cells = <1>;
230 ranges = <0x0 0x54000000 0x1000000>;
231
232 pmu: pmu {
233 compatible = "arm,cortex-a9-pmu";
234 };
235 };
236
237 target-module@55082000 {
238 compatible = "ti,sysc-omap2", "ti,sysc";
239 reg = <0x55082000 0x4>,
240 <0x55082010 0x4>,
241 <0x55082014 0x4>;
242 reg-names = "rev", "sysc", "syss";
243 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
244 <SYSC_IDLE_NO>,
245 <SYSC_IDLE_SMART>;
246 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
247 SYSC_OMAP2_SOFTRESET |
248 SYSC_OMAP2_AUTOIDLE)>;
249 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
250 clock-names = "fck";
251 resets = <&prm_core 2>;
252 reset-names = "rstctrl";
253 ranges = <0x0 0x55082000 0x100>;
254 #size-cells = <1>;
255 #address-cells = <1>;
256
257 mmu_ipu: mmu@0 {
258 compatible = "ti,omap4-iommu";
259 reg = <0x0 0x100>;
260 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
261 #iommu-cells = <0>;
262 ti,iommu-bus-err-back;
263 };
264 };
265
266 target-module@4012c000 {
267 compatible = "ti,sysc-omap4", "ti,sysc";
268 reg = <0x4012c000 0x4>,
269 <0x4012c010 0x4>;
270 reg-names = "rev", "sysc";
271 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
272 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
273 <SYSC_IDLE_NO>,
274 <SYSC_IDLE_SMART>,
275 <SYSC_IDLE_SMART_WKUP>;
276 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
277 clock-names = "fck";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
281 <0x4902c000 0x4902c000 0x1000>; /* L3 */
282
283 /* No child device binding or driver in mainline */
284 };
285
286 target-module@4e000000 {
287 compatible = "ti,sysc-omap2", "ti,sysc";
288 reg = <0x4e000000 0x4>,
289 <0x4e000010 0x4>;
290 reg-names = "rev", "sysc";
291 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
292 <SYSC_IDLE_NO>,
293 <SYSC_IDLE_SMART>;
294 ranges = <0x0 0x4e000000 0x2000000>;
295 #size-cells = <1>;
296 #address-cells = <1>;
297
298 dmm@0 {
299 compatible = "ti,omap4-dmm";
300 reg = <0 0x800>;
301 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
302 };
303 };
304
305 target-module@4c000000 {
306 compatible = "ti,sysc-omap4-simple", "ti,sysc";
307 reg = <0x4c000000 0x4>;
308 reg-names = "rev";
309 clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
310 clock-names = "fck";
311 ti,no-idle;
312 #address-cells = <1>;
313 #size-cells = <1>;
314 ranges = <0x0 0x4c000000 0x1000000>;
315
316 emif1: emif@0 {
317 compatible = "ti,emif-4d";
318 reg = <0 0x100>;
319 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
320 phy-type = <1>;
321 hw-caps-read-idle-ctrl;
322 hw-caps-ll-interface;
323 hw-caps-temp-alert;
324 };
325 };
326
327 target-module@4d000000 {
328 compatible = "ti,sysc-omap4-simple", "ti,sysc";
329 reg = <0x4d000000 0x4>;
330 reg-names = "rev";
331 clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
332 clock-names = "fck";
333 ti,no-idle;
334 #address-cells = <1>;
335 #size-cells = <1>;
336 ranges = <0x0 0x4d000000 0x1000000>;
337
338 emif2: emif@0 {
339 compatible = "ti,emif-4d";
340 reg = <0 0x100>;
341 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
342 phy-type = <1>;
343 hw-caps-read-idle-ctrl;
344 hw-caps-ll-interface;
345 hw-caps-temp-alert;
346 };
347 };
348
349 dsp: dsp {
350 compatible = "ti,omap4-dsp";
351 ti,bootreg = <&scm_conf 0x304 0>;
352 iommus = <&mmu_dsp>;
353 resets = <&prm_tesla 0>;
354 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
355 firmware-name = "omap4-dsp-fw.xe64T";
356 mboxes = <&mailbox &mbox_dsp>;
357 status = "disabled";
358 };
359
360 ipu: ipu@55020000 {
361 compatible = "ti,omap4-ipu";
362 reg = <0x55020000 0x10000>;
363 reg-names = "l2ram";
364 iommus = <&mmu_ipu>;
365 resets = <&prm_core 0>, <&prm_core 1>;
366 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
367 firmware-name = "omap4-ipu-fw.xem3";
368 mboxes = <&mailbox &mbox_ipu>;
369 status = "disabled";
370 };
371
372 aes1_target: target-module@4b501000 {
373 compatible = "ti,sysc-omap2", "ti,sysc";
374 reg = <0x4b501080 0x4>,
375 <0x4b501084 0x4>,
376 <0x4b501088 0x4>;
377 reg-names = "rev", "sysc", "syss";
378 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
379 SYSC_OMAP2_AUTOIDLE)>;
380 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
381 <SYSC_IDLE_NO>,
382 <SYSC_IDLE_SMART>,
383 <SYSC_IDLE_SMART_WKUP>;
384 ti,syss-mask = <1>;
385 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
386 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
387 clock-names = "fck";
388 #address-cells = <1>;
389 #size-cells = <1>;
390 ranges = <0x0 0x4b501000 0x1000>;
391
392 aes1: aes@0 {
393 compatible = "ti,omap4-aes";
394 reg = <0 0xa0>;
395 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
396 dmas = <&sdma 111>, <&sdma 110>;
397 dma-names = "tx", "rx";
398 };
399 };
400
401 aes2_target: target-module@4b701000 {
402 compatible = "ti,sysc-omap2", "ti,sysc";
403 reg = <0x4b701080 0x4>,
404 <0x4b701084 0x4>,
405 <0x4b701088 0x4>;
406 reg-names = "rev", "sysc", "syss";
407 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
408 SYSC_OMAP2_AUTOIDLE)>;
409 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
410 <SYSC_IDLE_NO>,
411 <SYSC_IDLE_SMART>,
412 <SYSC_IDLE_SMART_WKUP>;
413 ti,syss-mask = <1>;
414 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
415 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
416 clock-names = "fck";
417 #address-cells = <1>;
418 #size-cells = <1>;
419 ranges = <0x0 0x4b701000 0x1000>;
420
421 aes2: aes@0 {
422 compatible = "ti,omap4-aes";
423 reg = <0 0xa0>;
424 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
425 dmas = <&sdma 114>, <&sdma 113>;
426 dma-names = "tx", "rx";
427 };
428 };
429
430 sham_target: target-module@4b100000 {
431 compatible = "ti,sysc-omap3-sham", "ti,sysc";
432 reg = <0x4b100100 0x4>,
433 <0x4b100110 0x4>,
434 <0x4b100114 0x4>;
435 reg-names = "rev", "sysc", "syss";
436 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
437 SYSC_OMAP2_AUTOIDLE)>;
438 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
439 <SYSC_IDLE_NO>,
440 <SYSC_IDLE_SMART>;
441 ti,syss-mask = <1>;
442 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
443 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
444 clock-names = "fck";
445 #address-cells = <1>;
446 #size-cells = <1>;
447 ranges = <0x0 0x4b100000 0x1000>;
448
449 sham: sham@0 {
450 compatible = "ti,omap4-sham";
451 reg = <0 0x300>;
452 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
453 dmas = <&sdma 119>;
454 dma-names = "rx";
455 };
456 };
457
458 abb_mpu: regulator-abb-mpu {
459 compatible = "ti,abb-v2";
460 regulator-name = "abb_mpu";
461 #address-cells = <0>;
462 #size-cells = <0>;
463 ti,tranxdone-status-mask = <0x80>;
464 clocks = <&sys_clkin_ck>;
465 ti,settling-time = <50>;
466 ti,clock-cycles = <16>;
467
468 status = "disabled";
469 };
470
471 abb_iva: regulator-abb-iva {
472 compatible = "ti,abb-v2";
473 regulator-name = "abb_iva";
474 #address-cells = <0>;
475 #size-cells = <0>;
476 ti,tranxdone-status-mask = <0x80000000>;
477 clocks = <&sys_clkin_ck>;
478 ti,settling-time = <50>;
479 ti,clock-cycles = <16>;
480
481 status = "disabled";
482 };
483
484 sgx_module: target-module@56000000 {
485 compatible = "ti,sysc-omap4", "ti,sysc";
486 reg = <0x5600fe00 0x4>,
487 <0x5600fe10 0x4>;
488 reg-names = "rev", "sysc";
489 ti,sysc-midle = <SYSC_IDLE_FORCE>,
490 <SYSC_IDLE_NO>,
491 <SYSC_IDLE_SMART>,
492 <SYSC_IDLE_SMART_WKUP>;
493 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
494 <SYSC_IDLE_NO>,
495 <SYSC_IDLE_SMART>,
496 <SYSC_IDLE_SMART_WKUP>;
497 power-domains = <&prm_gfx>;
498 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
499 clock-names = "fck";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges = <0 0x56000000 0x2000000>;
503
504 /*
505 * Closed source PowerVR driver, no child device
506 * binding or driver in mainline
507 */
508 };
509
510 /*
511 * DSS is only using l3 mapping without l4 as noted in the TRM
512 * "10.1.3 DSS Register Manual" for omap4460.
513 */
514 target-module@58000000 {
515 compatible = "ti,sysc-omap2", "ti,sysc";
516 reg = <0x58000000 4>,
517 <0x58000014 4>;
518 reg-names = "rev", "syss";
519 ti,syss-mask = <1>;
520 power-domains = <&prm_dss>;
521 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
522 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
523 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
524 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
525 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
526 #address-cells = <1>;
527 #size-cells = <1>;
528 ranges = <0 0x58000000 0x1000000>;
529
530 dss: dss@0 {
531 compatible = "ti,omap4-dss";
532 reg = <0 0x80>;
533 status = "disabled";
534 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
535 clock-names = "fck";
536 #address-cells = <1>;
537 #size-cells = <1>;
538 ranges = <0 0 0x1000000>;
539
540 target-module@1000 {
541 compatible = "ti,sysc-omap2", "ti,sysc";
542 reg = <0x1000 0x4>,
543 <0x1010 0x4>,
544 <0x1014 0x4>;
545 reg-names = "rev", "sysc", "syss";
546 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
547 <SYSC_IDLE_NO>,
548 <SYSC_IDLE_SMART>;
549 ti,sysc-midle = <SYSC_IDLE_FORCE>,
550 <SYSC_IDLE_NO>,
551 <SYSC_IDLE_SMART>;
552 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
553 SYSC_OMAP2_ENAWAKEUP |
554 SYSC_OMAP2_SOFTRESET |
555 SYSC_OMAP2_AUTOIDLE)>;
556 ti,syss-mask = <1>;
557 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
558 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
559 clock-names = "fck", "sys_clk";
560 #address-cells = <1>;
561 #size-cells = <1>;
562 ranges = <0 0x1000 0x1000>;
563
564 dispc@0 {
565 compatible = "ti,omap4-dispc";
566 reg = <0 0x1000>;
567 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
569 clock-names = "fck";
570 };
571 };
572
573 target-module@2000 {
574 compatible = "ti,sysc-omap2", "ti,sysc";
575 reg = <0x2000 0x4>,
576 <0x2010 0x4>,
577 <0x2014 0x4>;
578 reg-names = "rev", "sysc", "syss";
579 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
580 <SYSC_IDLE_NO>,
581 <SYSC_IDLE_SMART>;
582 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
583 SYSC_OMAP2_AUTOIDLE)>;
584 ti,syss-mask = <1>;
585 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
586 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
587 clock-names = "fck", "sys_clk";
588 #address-cells = <1>;
589 #size-cells = <1>;
590 ranges = <0 0x2000 0x1000>;
591
592 rfbi: encoder@0 {
593 reg = <0 0x1000>;
594 status = "disabled";
595 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
596 clock-names = "fck", "ick";
597 };
598 };
599
600 target-module@3000 {
601 compatible = "ti,sysc-omap2", "ti,sysc";
602 reg = <0x3000 0x4>;
603 reg-names = "rev";
604 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
605 clock-names = "sys_clk";
606 #address-cells = <1>;
607 #size-cells = <1>;
608 ranges = <0 0x3000 0x1000>;
609
610 venc: encoder@0 {
611 compatible = "ti,omap4-venc";
612 reg = <0 0x1000>;
613 status = "disabled";
614 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
615 clock-names = "fck";
616 };
617 };
618
619 target-module@4000 {
620 compatible = "ti,sysc-omap2", "ti,sysc";
621 reg = <0x4000 0x4>,
622 <0x4010 0x4>,
623 <0x4014 0x4>;
624 reg-names = "rev", "sysc", "syss";
625 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
626 <SYSC_IDLE_NO>,
627 <SYSC_IDLE_SMART>;
628 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
629 SYSC_OMAP2_ENAWAKEUP |
630 SYSC_OMAP2_SOFTRESET |
631 SYSC_OMAP2_AUTOIDLE)>;
632 ti,syss-mask = <1>;
633 #address-cells = <1>;
634 #size-cells = <1>;
635 ranges = <0 0x4000 0x1000>;
636
637 dsi1: encoder@0 {
638 compatible = "ti,omap4-dsi";
639 reg = <0 0x200>,
640 <0x200 0x40>,
641 <0x300 0x20>;
642 reg-names = "proto", "phy", "pll";
643 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
644 status = "disabled";
645 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
646 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
647 clock-names = "fck", "sys_clk";
648
649 #address-cells = <1>;
650 #size-cells = <0>;
651 };
652 };
653
654 target-module@5000 {
655 compatible = "ti,sysc-omap2", "ti,sysc";
656 reg = <0x5000 0x4>,
657 <0x5010 0x4>,
658 <0x5014 0x4>;
659 reg-names = "rev", "sysc", "syss";
660 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
661 <SYSC_IDLE_NO>,
662 <SYSC_IDLE_SMART>;
663 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
664 SYSC_OMAP2_ENAWAKEUP |
665 SYSC_OMAP2_SOFTRESET |
666 SYSC_OMAP2_AUTOIDLE)>;
667 ti,syss-mask = <1>;
668 #address-cells = <1>;
669 #size-cells = <1>;
670 ranges = <0 0x5000 0x1000>;
671
672 dsi2: encoder@0 {
673 compatible = "ti,omap4-dsi";
674 reg = <0 0x200>,
675 <0x200 0x40>,
676 <0x300 0x20>;
677 reg-names = "proto", "phy", "pll";
678 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
679 status = "disabled";
680 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
681 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
682 clock-names = "fck", "sys_clk";
683
684 #address-cells = <1>;
685 #size-cells = <0>;
686 };
687 };
688
689 target-module@6000 {
690 compatible = "ti,sysc-omap4", "ti,sysc";
691 reg = <0x6000 0x4>,
692 <0x6010 0x4>;
693 reg-names = "rev", "sysc";
694 /*
695 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
696 * but HDMI audio will fail with them.
697 */
698 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
699 <SYSC_IDLE_NO>;
700 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
701 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
702 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
703 clock-names = "fck", "dss_clk";
704 #address-cells = <1>;
705 #size-cells = <1>;
706 ranges = <0 0x6000 0x2000>;
707
708 hdmi: encoder@0 {
709 compatible = "ti,omap4-hdmi";
710 reg = <0 0x200>,
711 <0x200 0x100>,
712 <0x300 0x100>,
713 <0x400 0x1000>;
714 reg-names = "wp", "pll", "phy", "core";
715 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
716 status = "disabled";
717 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
718 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
719 clock-names = "fck", "sys_clk";
720 dmas = <&sdma 76>;
721 dma-names = "audio_tx";
722 };
723 };
724 };
725 };
726
727 iva_hd_target: target-module@5a000000 {
728 compatible = "ti,sysc-omap4", "ti,sysc";
729 reg = <0x5a05a400 0x4>,
730 <0x5a05a410 0x4>;
731 reg-names = "rev", "sysc";
732 ti,sysc-midle = <SYSC_IDLE_FORCE>,
733 <SYSC_IDLE_NO>,
734 <SYSC_IDLE_SMART>;
735 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
736 <SYSC_IDLE_NO>,
737 <SYSC_IDLE_SMART>;
738 power-domains = <&prm_ivahd>;
739 resets = <&prm_ivahd 2>;
740 reset-names = "rstctrl";
741 clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
742 clock-names = "fck";
743 #address-cells = <1>;
744 #size-cells = <1>;
745 ranges = <0x5a000000 0x5a000000 0x1000000>,
746 <0x5b000000 0x5b000000 0x1000000>;
747
748 iva {
749 compatible = "ti,ivahd";
750 };
751 };
752 };
753};
754
755#include "omap4-l4.dtsi"
756#include "omap4-l4-abe.dtsi"
757#include "omap44xx-clocks.dtsi"
758
759&prm {
760 prm_mpu: prm@300 {
761 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
762 reg = <0x300 0x100>;
763 #power-domain-cells = <0>;
764 };
765
766 prm_tesla: prm@400 {
767 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
768 reg = <0x400 0x100>;
769 #reset-cells = <1>;
770 #power-domain-cells = <0>;
771 };
772
773 prm_abe: prm@500 {
774 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
775 reg = <0x500 0x100>;
776 #power-domain-cells = <0>;
777 };
778
779 prm_always_on_core: prm@600 {
780 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
781 reg = <0x600 0x100>;
782 #power-domain-cells = <0>;
783 };
784
785 prm_core: prm@700 {
786 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
787 reg = <0x700 0x100>;
788 #reset-cells = <1>;
789 #power-domain-cells = <0>;
790 };
791
792 prm_ivahd: prm@f00 {
793 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
794 reg = <0xf00 0x100>;
795 #reset-cells = <1>;
796 #power-domain-cells = <0>;
797 };
798
799 prm_cam: prm@1000 {
800 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
801 reg = <0x1000 0x100>;
802 #power-domain-cells = <0>;
803 };
804
805 prm_dss: prm@1100 {
806 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
807 reg = <0x1100 0x100>;
808 #power-domain-cells = <0>;
809 };
810
811 prm_gfx: prm@1200 {
812 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
813 reg = <0x1200 0x100>;
814 #power-domain-cells = <0>;
815 };
816
817 prm_l3init: prm@1300 {
818 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
819 reg = <0x1300 0x100>;
820 #power-domain-cells = <0>;
821 };
822
823 prm_l4per: prm@1400 {
824 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
825 reg = <0x1400 0x100>;
826 #power-domain-cells = <0>;
827 };
828
829 prm_cefuse: prm@1600 {
830 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
831 reg = <0x1600 0x100>;
832 #power-domain-cells = <0>;
833 };
834
835 prm_wkup: prm@1700 {
836 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
837 reg = <0x1700 0x100>;
838 #power-domain-cells = <0>;
839 };
840
841 prm_emu: prm@1900 {
842 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
843 reg = <0x1900 0x100>;
844 #power-domain-cells = <0>;
845 };
846
847 prm_dss: prm@1100 {
848 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
849 reg = <0x1100 0x40>;
850 #power-domain-cells = <0>;
851 };
852
853 prm_device: prm@1b00 {
854 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
855 reg = <0x1b00 0x40>;
856 #reset-cells = <1>;
857 };
858};
859
860/* Preferred always-on timer for clockevent */
861&timer1_target {
862 ti,no-reset-on-init;
863 ti,no-idle;
864 timer@0 {
865 assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
866 assigned-clock-parents = <&sys_32k_ck>;
867 };
868};
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/omap.h>
12
13#include "skeleton.dtsi"
14
15/ {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&wakeupgen>;
18
19 aliases {
20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
23 i2c3 = &i2c4;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu@0 {
35 compatible = "arm,cortex-a9";
36 device_type = "cpu";
37 next-level-cache = <&L2>;
38 reg = <0x0>;
39
40 clocks = <&dpll_mpu_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
44 };
45 cpu@1 {
46 compatible = "arm,cortex-a9";
47 device_type = "cpu";
48 next-level-cache = <&L2>;
49 reg = <0x1>;
50 };
51 };
52
53 gic: interrupt-controller@48241000 {
54 compatible = "arm,cortex-a9-gic";
55 interrupt-controller;
56 #interrupt-cells = <3>;
57 reg = <0x48241000 0x1000>,
58 <0x48240100 0x0100>;
59 interrupt-parent = <&gic>;
60 };
61
62 L2: l2-cache-controller@48242000 {
63 compatible = "arm,pl310-cache";
64 reg = <0x48242000 0x1000>;
65 cache-unified;
66 cache-level = <2>;
67 };
68
69 local-timer@48240600 {
70 compatible = "arm,cortex-a9-twd-timer";
71 clocks = <&mpu_periphclk>;
72 reg = <0x48240600 0x20>;
73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
74 interrupt-parent = <&gic>;
75 };
76
77 wakeupgen: interrupt-controller@48281000 {
78 compatible = "ti,omap4-wugen-mpu";
79 interrupt-controller;
80 #interrupt-cells = <3>;
81 reg = <0x48281000 0x1000>;
82 interrupt-parent = <&gic>;
83 };
84
85 /*
86 * The soc node represents the soc top level view. It is used for IPs
87 * that are not memory mapped in the MPU view or for the MPU itself.
88 */
89 soc {
90 compatible = "ti,omap-infra";
91 mpu {
92 compatible = "ti,omap4-mpu";
93 ti,hwmods = "mpu";
94 sram = <&ocmcram>;
95 };
96
97 dsp {
98 compatible = "ti,omap3-c64";
99 ti,hwmods = "dsp";
100 };
101
102 iva {
103 compatible = "ti,ivahd";
104 ti,hwmods = "iva";
105 };
106 };
107
108 /*
109 * XXX: Use a flat representation of the OMAP4 interconnect.
110 * The real OMAP interconnect network is quite complex.
111 * Since it will not bring real advantage to represent that in DT for
112 * the moment, just use a fake OCP bus entry to represent the whole bus
113 * hierarchy.
114 */
115 ocp {
116 compatible = "ti,omap4-l3-noc", "simple-bus";
117 #address-cells = <1>;
118 #size-cells = <1>;
119 ranges;
120 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
121 reg = <0x44000000 0x1000>,
122 <0x44800000 0x2000>,
123 <0x45000000 0x1000>;
124 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
126
127 l4_cfg: l4@4a000000 {
128 compatible = "ti,omap4-l4-cfg", "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
131 ranges = <0 0x4a000000 0x1000000>;
132
133 cm1: cm1@4000 {
134 compatible = "ti,omap4-cm1";
135 reg = <0x4000 0x2000>;
136
137 cm1_clocks: clocks {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 };
141
142 cm1_clockdomains: clockdomains {
143 };
144 };
145
146 cm2: cm2@8000 {
147 compatible = "ti,omap4-cm2";
148 reg = <0x8000 0x3000>;
149
150 cm2_clocks: clocks {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 };
154
155 cm2_clockdomains: clockdomains {
156 };
157 };
158
159 omap4_scm_core: scm@2000 {
160 compatible = "ti,omap4-scm-core", "simple-bus";
161 reg = <0x2000 0x1000>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges = <0 0x2000 0x1000>;
165
166 scm_conf: scm_conf@0 {
167 compatible = "syscon";
168 reg = <0x0 0x800>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 };
172 };
173
174 omap4_padconf_core: scm@100000 {
175 compatible = "ti,omap4-scm-padconf-core",
176 "simple-bus";
177 #address-cells = <1>;
178 #size-cells = <1>;
179 ranges = <0 0x100000 0x1000>;
180
181 omap4_pmx_core: pinmux@40 {
182 compatible = "ti,omap4-padconf",
183 "pinctrl-single";
184 reg = <0x40 0x0196>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 #interrupt-cells = <1>;
188 interrupt-controller;
189 pinctrl-single,register-width = <16>;
190 pinctrl-single,function-mask = <0x7fff>;
191 };
192
193 omap4_padconf_global: omap4_padconf_global@5a0 {
194 compatible = "syscon",
195 "simple-bus";
196 reg = <0x5a0 0x170>;
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges = <0 0x5a0 0x170>;
200
201 pbias_regulator: pbias_regulator {
202 compatible = "ti,pbias-omap4", "ti,pbias-omap";
203 reg = <0x60 0x4>;
204 syscon = <&omap4_padconf_global>;
205 pbias_mmc_reg: pbias_mmc_omap4 {
206 regulator-name = "pbias_mmc_omap4";
207 regulator-min-microvolt = <1800000>;
208 regulator-max-microvolt = <3000000>;
209 };
210 };
211 };
212 };
213
214 l4_wkup: l4@300000 {
215 compatible = "ti,omap4-l4-wkup", "simple-bus";
216 #address-cells = <1>;
217 #size-cells = <1>;
218 ranges = <0 0x300000 0x40000>;
219
220 counter32k: counter@4000 {
221 compatible = "ti,omap-counter32k";
222 reg = <0x4000 0x20>;
223 ti,hwmods = "counter_32k";
224 };
225
226 prm: prm@6000 {
227 compatible = "ti,omap4-prm";
228 reg = <0x6000 0x3000>;
229 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
230
231 prm_clocks: clocks {
232 #address-cells = <1>;
233 #size-cells = <0>;
234 };
235
236 prm_clockdomains: clockdomains {
237 };
238 };
239
240 scrm: scrm@a000 {
241 compatible = "ti,omap4-scrm";
242 reg = <0xa000 0x2000>;
243
244 scrm_clocks: clocks {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 };
248
249 scrm_clockdomains: clockdomains {
250 };
251 };
252
253 omap4_pmx_wkup: pinmux@1e040 {
254 compatible = "ti,omap4-padconf",
255 "pinctrl-single";
256 reg = <0x1e040 0x0038>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259 #interrupt-cells = <1>;
260 interrupt-controller;
261 pinctrl-single,register-width = <16>;
262 pinctrl-single,function-mask = <0x7fff>;
263 };
264 };
265 };
266
267 ocmcram: ocmcram@40304000 {
268 compatible = "mmio-sram";
269 reg = <0x40304000 0xa000>; /* 40k */
270 };
271
272 sdma: dma-controller@4a056000 {
273 compatible = "ti,omap4430-sdma";
274 reg = <0x4a056000 0x1000>;
275 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
279 #dma-cells = <1>;
280 dma-channels = <32>;
281 dma-requests = <127>;
282 };
283
284 gpio1: gpio@4a310000 {
285 compatible = "ti,omap4-gpio";
286 reg = <0x4a310000 0x200>;
287 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
288 ti,hwmods = "gpio1";
289 ti,gpio-always-on;
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
293 #interrupt-cells = <2>;
294 };
295
296 gpio2: gpio@48055000 {
297 compatible = "ti,omap4-gpio";
298 reg = <0x48055000 0x200>;
299 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
300 ti,hwmods = "gpio2";
301 gpio-controller;
302 #gpio-cells = <2>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 };
306
307 gpio3: gpio@48057000 {
308 compatible = "ti,omap4-gpio";
309 reg = <0x48057000 0x200>;
310 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
311 ti,hwmods = "gpio3";
312 gpio-controller;
313 #gpio-cells = <2>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
316 };
317
318 gpio4: gpio@48059000 {
319 compatible = "ti,omap4-gpio";
320 reg = <0x48059000 0x200>;
321 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
322 ti,hwmods = "gpio4";
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 gpio5: gpio@4805b000 {
330 compatible = "ti,omap4-gpio";
331 reg = <0x4805b000 0x200>;
332 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
333 ti,hwmods = "gpio5";
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 };
339
340 gpio6: gpio@4805d000 {
341 compatible = "ti,omap4-gpio";
342 reg = <0x4805d000 0x200>;
343 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
344 ti,hwmods = "gpio6";
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 };
350
351 elm: elm@48078000 {
352 compatible = "ti,am3352-elm";
353 reg = <0x48078000 0x2000>;
354 interrupts = <4>;
355 ti,hwmods = "elm";
356 status = "disabled";
357 };
358
359 gpmc: gpmc@50000000 {
360 compatible = "ti,omap4430-gpmc";
361 reg = <0x50000000 0x1000>;
362 #address-cells = <2>;
363 #size-cells = <1>;
364 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
365 dmas = <&sdma 4>;
366 dma-names = "rxtx";
367 gpmc,num-cs = <8>;
368 gpmc,num-waitpins = <4>;
369 ti,hwmods = "gpmc";
370 ti,no-idle-on-init;
371 clocks = <&l3_div_ck>;
372 clock-names = "fck";
373 };
374
375 uart1: serial@4806a000 {
376 compatible = "ti,omap4-uart";
377 reg = <0x4806a000 0x100>;
378 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
379 ti,hwmods = "uart1";
380 clock-frequency = <48000000>;
381 };
382
383 uart2: serial@4806c000 {
384 compatible = "ti,omap4-uart";
385 reg = <0x4806c000 0x100>;
386 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
387 ti,hwmods = "uart2";
388 clock-frequency = <48000000>;
389 };
390
391 uart3: serial@48020000 {
392 compatible = "ti,omap4-uart";
393 reg = <0x48020000 0x100>;
394 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
395 ti,hwmods = "uart3";
396 clock-frequency = <48000000>;
397 };
398
399 uart4: serial@4806e000 {
400 compatible = "ti,omap4-uart";
401 reg = <0x4806e000 0x100>;
402 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
403 ti,hwmods = "uart4";
404 clock-frequency = <48000000>;
405 };
406
407 hwspinlock: spinlock@4a0f6000 {
408 compatible = "ti,omap4-hwspinlock";
409 reg = <0x4a0f6000 0x1000>;
410 ti,hwmods = "spinlock";
411 #hwlock-cells = <1>;
412 };
413
414 i2c1: i2c@48070000 {
415 compatible = "ti,omap4-i2c";
416 reg = <0x48070000 0x100>;
417 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420 ti,hwmods = "i2c1";
421 };
422
423 i2c2: i2c@48072000 {
424 compatible = "ti,omap4-i2c";
425 reg = <0x48072000 0x100>;
426 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 ti,hwmods = "i2c2";
430 };
431
432 i2c3: i2c@48060000 {
433 compatible = "ti,omap4-i2c";
434 reg = <0x48060000 0x100>;
435 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
436 #address-cells = <1>;
437 #size-cells = <0>;
438 ti,hwmods = "i2c3";
439 };
440
441 i2c4: i2c@48350000 {
442 compatible = "ti,omap4-i2c";
443 reg = <0x48350000 0x100>;
444 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
445 #address-cells = <1>;
446 #size-cells = <0>;
447 ti,hwmods = "i2c4";
448 };
449
450 mcspi1: spi@48098000 {
451 compatible = "ti,omap4-mcspi";
452 reg = <0x48098000 0x200>;
453 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 ti,hwmods = "mcspi1";
457 ti,spi-num-cs = <4>;
458 dmas = <&sdma 35>,
459 <&sdma 36>,
460 <&sdma 37>,
461 <&sdma 38>,
462 <&sdma 39>,
463 <&sdma 40>,
464 <&sdma 41>,
465 <&sdma 42>;
466 dma-names = "tx0", "rx0", "tx1", "rx1",
467 "tx2", "rx2", "tx3", "rx3";
468 };
469
470 mcspi2: spi@4809a000 {
471 compatible = "ti,omap4-mcspi";
472 reg = <0x4809a000 0x200>;
473 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 ti,hwmods = "mcspi2";
477 ti,spi-num-cs = <2>;
478 dmas = <&sdma 43>,
479 <&sdma 44>,
480 <&sdma 45>,
481 <&sdma 46>;
482 dma-names = "tx0", "rx0", "tx1", "rx1";
483 };
484
485 mcspi3: spi@480b8000 {
486 compatible = "ti,omap4-mcspi";
487 reg = <0x480b8000 0x200>;
488 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
489 #address-cells = <1>;
490 #size-cells = <0>;
491 ti,hwmods = "mcspi3";
492 ti,spi-num-cs = <2>;
493 dmas = <&sdma 15>, <&sdma 16>;
494 dma-names = "tx0", "rx0";
495 };
496
497 mcspi4: spi@480ba000 {
498 compatible = "ti,omap4-mcspi";
499 reg = <0x480ba000 0x200>;
500 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 ti,hwmods = "mcspi4";
504 ti,spi-num-cs = <1>;
505 dmas = <&sdma 70>, <&sdma 71>;
506 dma-names = "tx0", "rx0";
507 };
508
509 mmc1: mmc@4809c000 {
510 compatible = "ti,omap4-hsmmc";
511 reg = <0x4809c000 0x400>;
512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
513 ti,hwmods = "mmc1";
514 ti,dual-volt;
515 ti,needs-special-reset;
516 dmas = <&sdma 61>, <&sdma 62>;
517 dma-names = "tx", "rx";
518 pbias-supply = <&pbias_mmc_reg>;
519 };
520
521 mmc2: mmc@480b4000 {
522 compatible = "ti,omap4-hsmmc";
523 reg = <0x480b4000 0x400>;
524 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
525 ti,hwmods = "mmc2";
526 ti,needs-special-reset;
527 dmas = <&sdma 47>, <&sdma 48>;
528 dma-names = "tx", "rx";
529 };
530
531 mmc3: mmc@480ad000 {
532 compatible = "ti,omap4-hsmmc";
533 reg = <0x480ad000 0x400>;
534 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
535 ti,hwmods = "mmc3";
536 ti,needs-special-reset;
537 dmas = <&sdma 77>, <&sdma 78>;
538 dma-names = "tx", "rx";
539 };
540
541 mmc4: mmc@480d1000 {
542 compatible = "ti,omap4-hsmmc";
543 reg = <0x480d1000 0x400>;
544 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
545 ti,hwmods = "mmc4";
546 ti,needs-special-reset;
547 dmas = <&sdma 57>, <&sdma 58>;
548 dma-names = "tx", "rx";
549 };
550
551 mmc5: mmc@480d5000 {
552 compatible = "ti,omap4-hsmmc";
553 reg = <0x480d5000 0x400>;
554 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
555 ti,hwmods = "mmc5";
556 ti,needs-special-reset;
557 dmas = <&sdma 59>, <&sdma 60>;
558 dma-names = "tx", "rx";
559 };
560
561 mmu_dsp: mmu@4a066000 {
562 compatible = "ti,omap4-iommu";
563 reg = <0x4a066000 0x100>;
564 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
565 ti,hwmods = "mmu_dsp";
566 #iommu-cells = <0>;
567 };
568
569 mmu_ipu: mmu@55082000 {
570 compatible = "ti,omap4-iommu";
571 reg = <0x55082000 0x100>;
572 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
573 ti,hwmods = "mmu_ipu";
574 #iommu-cells = <0>;
575 ti,iommu-bus-err-back;
576 };
577
578 wdt2: wdt@4a314000 {
579 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
580 reg = <0x4a314000 0x80>;
581 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
582 ti,hwmods = "wd_timer2";
583 };
584
585 mcpdm: mcpdm@40132000 {
586 compatible = "ti,omap4-mcpdm";
587 reg = <0x40132000 0x7f>, /* MPU private access */
588 <0x49032000 0x7f>; /* L3 Interconnect */
589 reg-names = "mpu", "dma";
590 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
591 ti,hwmods = "mcpdm";
592 dmas = <&sdma 65>,
593 <&sdma 66>;
594 dma-names = "up_link", "dn_link";
595 status = "disabled";
596 };
597
598 dmic: dmic@4012e000 {
599 compatible = "ti,omap4-dmic";
600 reg = <0x4012e000 0x7f>, /* MPU private access */
601 <0x4902e000 0x7f>; /* L3 Interconnect */
602 reg-names = "mpu", "dma";
603 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
604 ti,hwmods = "dmic";
605 dmas = <&sdma 67>;
606 dma-names = "up_link";
607 status = "disabled";
608 };
609
610 mcbsp1: mcbsp@40122000 {
611 compatible = "ti,omap4-mcbsp";
612 reg = <0x40122000 0xff>, /* MPU private access */
613 <0x49022000 0xff>; /* L3 Interconnect */
614 reg-names = "mpu", "dma";
615 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
616 interrupt-names = "common";
617 ti,buffer-size = <128>;
618 ti,hwmods = "mcbsp1";
619 dmas = <&sdma 33>,
620 <&sdma 34>;
621 dma-names = "tx", "rx";
622 status = "disabled";
623 };
624
625 mcbsp2: mcbsp@40124000 {
626 compatible = "ti,omap4-mcbsp";
627 reg = <0x40124000 0xff>, /* MPU private access */
628 <0x49024000 0xff>; /* L3 Interconnect */
629 reg-names = "mpu", "dma";
630 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
631 interrupt-names = "common";
632 ti,buffer-size = <128>;
633 ti,hwmods = "mcbsp2";
634 dmas = <&sdma 17>,
635 <&sdma 18>;
636 dma-names = "tx", "rx";
637 status = "disabled";
638 };
639
640 mcbsp3: mcbsp@40126000 {
641 compatible = "ti,omap4-mcbsp";
642 reg = <0x40126000 0xff>, /* MPU private access */
643 <0x49026000 0xff>; /* L3 Interconnect */
644 reg-names = "mpu", "dma";
645 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
646 interrupt-names = "common";
647 ti,buffer-size = <128>;
648 ti,hwmods = "mcbsp3";
649 dmas = <&sdma 19>,
650 <&sdma 20>;
651 dma-names = "tx", "rx";
652 status = "disabled";
653 };
654
655 mcbsp4: mcbsp@48096000 {
656 compatible = "ti,omap4-mcbsp";
657 reg = <0x48096000 0xff>; /* L4 Interconnect */
658 reg-names = "mpu";
659 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
660 interrupt-names = "common";
661 ti,buffer-size = <128>;
662 ti,hwmods = "mcbsp4";
663 dmas = <&sdma 31>,
664 <&sdma 32>;
665 dma-names = "tx", "rx";
666 status = "disabled";
667 };
668
669 keypad: keypad@4a31c000 {
670 compatible = "ti,omap4-keypad";
671 reg = <0x4a31c000 0x80>;
672 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
673 reg-names = "mpu";
674 ti,hwmods = "kbd";
675 };
676
677 dmm@4e000000 {
678 compatible = "ti,omap4-dmm";
679 reg = <0x4e000000 0x800>;
680 interrupts = <0 113 0x4>;
681 ti,hwmods = "dmm";
682 };
683
684 emif1: emif@4c000000 {
685 compatible = "ti,emif-4d";
686 reg = <0x4c000000 0x100>;
687 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
688 ti,hwmods = "emif1";
689 ti,no-idle-on-init;
690 phy-type = <1>;
691 hw-caps-read-idle-ctrl;
692 hw-caps-ll-interface;
693 hw-caps-temp-alert;
694 };
695
696 emif2: emif@4d000000 {
697 compatible = "ti,emif-4d";
698 reg = <0x4d000000 0x100>;
699 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
700 ti,hwmods = "emif2";
701 ti,no-idle-on-init;
702 phy-type = <1>;
703 hw-caps-read-idle-ctrl;
704 hw-caps-ll-interface;
705 hw-caps-temp-alert;
706 };
707
708 ocp2scp@4a0ad000 {
709 compatible = "ti,omap-ocp2scp";
710 reg = <0x4a0ad000 0x1f>;
711 #address-cells = <1>;
712 #size-cells = <1>;
713 ranges;
714 ti,hwmods = "ocp2scp_usb_phy";
715 usb2_phy: usb2phy@4a0ad080 {
716 compatible = "ti,omap-usb2";
717 reg = <0x4a0ad080 0x58>;
718 ctrl-module = <&omap_control_usb2phy>;
719 clocks = <&usb_phy_cm_clk32k>;
720 clock-names = "wkupclk";
721 #phy-cells = <0>;
722 };
723 };
724
725 mailbox: mailbox@4a0f4000 {
726 compatible = "ti,omap4-mailbox";
727 reg = <0x4a0f4000 0x200>;
728 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
729 ti,hwmods = "mailbox";
730 #mbox-cells = <1>;
731 ti,mbox-num-users = <3>;
732 ti,mbox-num-fifos = <8>;
733 mbox_ipu: mbox_ipu {
734 ti,mbox-tx = <0 0 0>;
735 ti,mbox-rx = <1 0 0>;
736 };
737 mbox_dsp: mbox_dsp {
738 ti,mbox-tx = <3 0 0>;
739 ti,mbox-rx = <2 0 0>;
740 };
741 };
742
743 timer1: timer@4a318000 {
744 compatible = "ti,omap3430-timer";
745 reg = <0x4a318000 0x80>;
746 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
747 ti,hwmods = "timer1";
748 ti,timer-alwon;
749 };
750
751 timer2: timer@48032000 {
752 compatible = "ti,omap3430-timer";
753 reg = <0x48032000 0x80>;
754 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
755 ti,hwmods = "timer2";
756 };
757
758 timer3: timer@48034000 {
759 compatible = "ti,omap4430-timer";
760 reg = <0x48034000 0x80>;
761 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
762 ti,hwmods = "timer3";
763 };
764
765 timer4: timer@48036000 {
766 compatible = "ti,omap4430-timer";
767 reg = <0x48036000 0x80>;
768 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
769 ti,hwmods = "timer4";
770 };
771
772 timer5: timer@40138000 {
773 compatible = "ti,omap4430-timer";
774 reg = <0x40138000 0x80>,
775 <0x49038000 0x80>;
776 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
777 ti,hwmods = "timer5";
778 ti,timer-dsp;
779 };
780
781 timer6: timer@4013a000 {
782 compatible = "ti,omap4430-timer";
783 reg = <0x4013a000 0x80>,
784 <0x4903a000 0x80>;
785 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
786 ti,hwmods = "timer6";
787 ti,timer-dsp;
788 };
789
790 timer7: timer@4013c000 {
791 compatible = "ti,omap4430-timer";
792 reg = <0x4013c000 0x80>,
793 <0x4903c000 0x80>;
794 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
795 ti,hwmods = "timer7";
796 ti,timer-dsp;
797 };
798
799 timer8: timer@4013e000 {
800 compatible = "ti,omap4430-timer";
801 reg = <0x4013e000 0x80>,
802 <0x4903e000 0x80>;
803 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
804 ti,hwmods = "timer8";
805 ti,timer-pwm;
806 ti,timer-dsp;
807 };
808
809 timer9: timer@4803e000 {
810 compatible = "ti,omap4430-timer";
811 reg = <0x4803e000 0x80>;
812 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
813 ti,hwmods = "timer9";
814 ti,timer-pwm;
815 };
816
817 timer10: timer@48086000 {
818 compatible = "ti,omap3430-timer";
819 reg = <0x48086000 0x80>;
820 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
821 ti,hwmods = "timer10";
822 ti,timer-pwm;
823 };
824
825 timer11: timer@48088000 {
826 compatible = "ti,omap4430-timer";
827 reg = <0x48088000 0x80>;
828 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
829 ti,hwmods = "timer11";
830 ti,timer-pwm;
831 };
832
833 usbhstll: usbhstll@4a062000 {
834 compatible = "ti,usbhs-tll";
835 reg = <0x4a062000 0x1000>;
836 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
837 ti,hwmods = "usb_tll_hs";
838 };
839
840 usbhshost: usbhshost@4a064000 {
841 compatible = "ti,usbhs-host";
842 reg = <0x4a064000 0x800>;
843 ti,hwmods = "usb_host_hs";
844 #address-cells = <1>;
845 #size-cells = <1>;
846 ranges;
847 clocks = <&init_60m_fclk>,
848 <&xclk60mhsp1_ck>,
849 <&xclk60mhsp2_ck>;
850 clock-names = "refclk_60m_int",
851 "refclk_60m_ext_p1",
852 "refclk_60m_ext_p2";
853
854 usbhsohci: ohci@4a064800 {
855 compatible = "ti,ohci-omap3";
856 reg = <0x4a064800 0x400>;
857 interrupt-parent = <&gic>;
858 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
859 };
860
861 usbhsehci: ehci@4a064c00 {
862 compatible = "ti,ehci-omap";
863 reg = <0x4a064c00 0x400>;
864 interrupt-parent = <&gic>;
865 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
866 };
867 };
868
869 omap_control_usb2phy: control-phy@4a002300 {
870 compatible = "ti,control-phy-usb2";
871 reg = <0x4a002300 0x4>;
872 reg-names = "power";
873 };
874
875 omap_control_usbotg: control-phy@4a00233c {
876 compatible = "ti,control-phy-otghs";
877 reg = <0x4a00233c 0x4>;
878 reg-names = "otghs_control";
879 };
880
881 usb_otg_hs: usb_otg_hs@4a0ab000 {
882 compatible = "ti,omap4-musb";
883 reg = <0x4a0ab000 0x7ff>;
884 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
885 interrupt-names = "mc", "dma";
886 ti,hwmods = "usb_otg_hs";
887 usb-phy = <&usb2_phy>;
888 phys = <&usb2_phy>;
889 phy-names = "usb2-phy";
890 multipoint = <1>;
891 num-eps = <16>;
892 ram-bits = <12>;
893 ctrl-module = <&omap_control_usbotg>;
894 };
895
896 aes: aes@4b501000 {
897 compatible = "ti,omap4-aes";
898 ti,hwmods = "aes";
899 reg = <0x4b501000 0xa0>;
900 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
901 dmas = <&sdma 111>, <&sdma 110>;
902 dma-names = "tx", "rx";
903 };
904
905 des: des@480a5000 {
906 compatible = "ti,omap4-des";
907 ti,hwmods = "des";
908 reg = <0x480a5000 0xa0>;
909 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
910 dmas = <&sdma 117>, <&sdma 116>;
911 dma-names = "tx", "rx";
912 };
913
914 abb_mpu: regulator-abb-mpu {
915 compatible = "ti,abb-v2";
916 regulator-name = "abb_mpu";
917 #address-cells = <0>;
918 #size-cells = <0>;
919 ti,tranxdone-status-mask = <0x80>;
920 clocks = <&sys_clkin_ck>;
921 ti,settling-time = <50>;
922 ti,clock-cycles = <16>;
923
924 status = "disabled";
925 };
926
927 abb_iva: regulator-abb-iva {
928 compatible = "ti,abb-v2";
929 regulator-name = "abb_iva";
930 #address-cells = <0>;
931 #size-cells = <0>;
932 ti,tranxdone-status-mask = <0x80000000>;
933 clocks = <&sys_clkin_ck>;
934 ti,settling-time = <50>;
935 ti,clock-cycles = <16>;
936
937 status = "disabled";
938 };
939
940 dss: dss@58000000 {
941 compatible = "ti,omap4-dss";
942 reg = <0x58000000 0x80>;
943 status = "disabled";
944 ti,hwmods = "dss_core";
945 clocks = <&dss_dss_clk>;
946 clock-names = "fck";
947 #address-cells = <1>;
948 #size-cells = <1>;
949 ranges;
950
951 dispc@58001000 {
952 compatible = "ti,omap4-dispc";
953 reg = <0x58001000 0x1000>;
954 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
955 ti,hwmods = "dss_dispc";
956 clocks = <&dss_dss_clk>;
957 clock-names = "fck";
958 };
959
960 rfbi: encoder@58002000 {
961 compatible = "ti,omap4-rfbi";
962 reg = <0x58002000 0x1000>;
963 status = "disabled";
964 ti,hwmods = "dss_rfbi";
965 clocks = <&dss_dss_clk>, <&l3_div_ck>;
966 clock-names = "fck", "ick";
967 };
968
969 venc: encoder@58003000 {
970 compatible = "ti,omap4-venc";
971 reg = <0x58003000 0x1000>;
972 status = "disabled";
973 ti,hwmods = "dss_venc";
974 clocks = <&dss_tv_clk>;
975 clock-names = "fck";
976 };
977
978 dsi1: encoder@58004000 {
979 compatible = "ti,omap4-dsi";
980 reg = <0x58004000 0x200>,
981 <0x58004200 0x40>,
982 <0x58004300 0x20>;
983 reg-names = "proto", "phy", "pll";
984 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
985 status = "disabled";
986 ti,hwmods = "dss_dsi1";
987 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
988 clock-names = "fck", "sys_clk";
989 };
990
991 dsi2: encoder@58005000 {
992 compatible = "ti,omap4-dsi";
993 reg = <0x58005000 0x200>,
994 <0x58005200 0x40>,
995 <0x58005300 0x20>;
996 reg-names = "proto", "phy", "pll";
997 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
998 status = "disabled";
999 ti,hwmods = "dss_dsi2";
1000 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1001 clock-names = "fck", "sys_clk";
1002 };
1003
1004 hdmi: encoder@58006000 {
1005 compatible = "ti,omap4-hdmi";
1006 reg = <0x58006000 0x200>,
1007 <0x58006200 0x100>,
1008 <0x58006300 0x100>,
1009 <0x58006400 0x1000>;
1010 reg-names = "wp", "pll", "phy", "core";
1011 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1012 status = "disabled";
1013 ti,hwmods = "dss_hdmi";
1014 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1015 clock-names = "fck", "sys_clk";
1016 dmas = <&sdma 76>;
1017 dma-names = "audio_tx";
1018 };
1019 };
1020 };
1021};
1022
1023/include/ "omap44xx-clocks.dtsi"