Loading...
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada 39x family of SoCs.
4 *
5 * Copyright (C) 2015 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Marvell Armada 39x family SoC";
19 compatible = "marvell,armada390";
20
21 aliases {
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
34
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0>;
39 };
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a9";
43 reg = <1>;
44 };
45 };
46
47 pmu {
48 compatible = "arm,cortex-a9-pmu";
49 interrupts-extended = <&mpic 3>;
50 };
51
52 soc {
53 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
54 "simple-bus";
55 #address-cells = <2>;
56 #size-cells = <1>;
57 controller = <&mbusc>;
58 interrupt-parent = <&gic>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
61
62 bootrom {
63 compatible = "marvell,bootrom";
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
65 };
66
67 internal-regs {
68 compatible = "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
72
73 L2: cache-controller@8000 {
74 compatible = "arm,pl310-cache";
75 reg = <0x8000 0x1000>;
76 cache-unified;
77 cache-level = <2>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
80 arm,double-linefill = <0>;
81 prefetch-data = <1>;
82 };
83
84 scu@c000 {
85 compatible = "arm,cortex-a9-scu";
86 reg = <0xc000 0x100>;
87 };
88
89 timer@c600 {
90 compatible = "arm,cortex-a9-twd-timer";
91 reg = <0xc600 0x20>;
92 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
93 clocks = <&coreclk 2>;
94 };
95
96 gic: interrupt-controller@d000 {
97 compatible = "arm,cortex-a9-gic";
98 #interrupt-cells = <3>;
99 #size-cells = <0>;
100 interrupt-controller;
101 reg = <0xd000 0x1000>,
102 <0xc100 0x100>;
103 };
104
105 i2c0: i2c@11000 {
106 compatible = "marvell,mv64xxx-i2c";
107 reg = <0x11000 0x20>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
111 clocks = <&coreclk 0>;
112 status = "disabled";
113 };
114
115 i2c1: i2c@11100 {
116 compatible = "marvell,mv64xxx-i2c";
117 reg = <0x11100 0x20>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&coreclk 0>;
122 status = "disabled";
123 };
124
125 i2c2: i2c@11200 {
126 compatible = "marvell,mv64xxx-i2c";
127 reg = <0x11200 0x20>;
128 #address-cells = <1>;
129 #size-cells = <0>;
130 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&coreclk 0>;
132 status = "disabled";
133 };
134
135 i2c3: i2c@11300 {
136 compatible = "marvell,mv64xxx-i2c";
137 reg = <0x11300 0x20>;
138 #address-cells = <1>;
139 #size-cells = <0>;
140 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&coreclk 0>;
142 status = "disabled";
143 };
144
145 uart0: serial@12000 {
146 compatible = "snps,dw-apb-uart";
147 reg = <0x12000 0x100>;
148 reg-shift = <2>;
149 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
150 reg-io-width = <1>;
151 clocks = <&coreclk 0>;
152 status = "disabled";
153 };
154
155 uart1: serial@12100 {
156 compatible = "snps,dw-apb-uart";
157 reg = <0x12100 0x100>;
158 reg-shift = <2>;
159 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
160 reg-io-width = <1>;
161 clocks = <&coreclk 0>;
162 status = "disabled";
163 };
164
165 uart2: serial@12200 {
166 compatible = "snps,dw-apb-uart";
167 reg = <0x12200 0x100>;
168 reg-shift = <2>;
169 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
170 reg-io-width = <1>;
171 clocks = <&coreclk 0>;
172 status = "disabled";
173 };
174
175 uart3: serial@12300 {
176 compatible = "snps,dw-apb-uart";
177 reg = <0x12300 0x100>;
178 reg-shift = <2>;
179 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
180 reg-io-width = <1>;
181 clocks = <&coreclk 0>;
182 status = "disabled";
183 };
184
185 pinctrl@18000 {
186 i2c0_pins: i2c0-pins {
187 marvell,pins = "mpp2", "mpp3";
188 marvell,function = "i2c0";
189 };
190
191 uart0_pins: uart0-pins {
192 marvell,pins = "mpp0", "mpp1";
193 marvell,function = "ua0";
194 };
195
196 uart1_pins: uart1-pins {
197 marvell,pins = "mpp19", "mpp20";
198 marvell,function = "ua1";
199 };
200
201 spi1_pins: spi1-pins {
202 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
203 marvell,function = "spi1";
204 };
205
206 nand_pins: nand-pins {
207 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
208 "mpp38", "mpp28", "mpp40", "mpp42",
209 "mpp35", "mpp36", "mpp25", "mpp30",
210 "mpp32";
211 marvell,function = "dev";
212 };
213 };
214
215 gpio0: gpio@18100 {
216 compatible = "marvell,orion-gpio";
217 reg = <0x18100 0x40>;
218 ngpios = <32>;
219 gpio-controller;
220 #gpio-cells = <2>;
221 interrupt-controller;
222 #interrupt-cells = <2>;
223 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
227 };
228
229 gpio1: gpio@18140 {
230 compatible = "marvell,orion-gpio";
231 reg = <0x18140 0x40>;
232 ngpios = <28>;
233 gpio-controller;
234 #gpio-cells = <2>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
241 };
242
243 system-controller@18200 {
244 compatible = "marvell,armada-390-system-controller",
245 "marvell,armada-370-xp-system-controller";
246 reg = <0x18200 0x100>;
247 };
248
249 gateclk: clock-gating-control@18220 {
250 compatible = "marvell,armada-390-gating-clock";
251 reg = <0x18220 0x4>;
252 clocks = <&coreclk 0>;
253 #clock-cells = <1>;
254 };
255
256 coreclk: mvebu-sar@18600 {
257 compatible = "marvell,armada-390-core-clock";
258 reg = <0x18600 0x04>;
259 #clock-cells = <1>;
260 };
261
262 mbusc: mbus-controller@20000 {
263 compatible = "marvell,mbus-controller";
264 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
265 };
266
267 mpic: interrupt-controller@20a00 {
268 compatible = "marvell,mpic";
269 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
270 #interrupt-cells = <1>;
271 #size-cells = <1>;
272 interrupt-controller;
273 msi-controller;
274 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
275 };
276
277 timer@20300 {
278 compatible = "marvell,armada-380-timer",
279 "marvell,armada-xp-timer";
280 reg = <0x20300 0x30>, <0x21040 0x30>;
281 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
282 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
283 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
284 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
285 <&mpic 5>,
286 <&mpic 6>;
287 clocks = <&coreclk 2>, <&coreclk 5>;
288 clock-names = "nbclk", "fixed";
289 };
290
291 watchdog@20300 {
292 compatible = "marvell,armada-380-wdt";
293 reg = <0x20300 0x34>, <0x20704 0x4>,
294 <0x18260 0x4>;
295 clocks = <&coreclk 2>, <&refclk>;
296 clock-names = "nbclk", "fixed";
297 };
298
299 cpurst@20800 {
300 compatible = "marvell,armada-370-cpu-reset";
301 reg = <0x20800 0x10>;
302 };
303
304 mpcore-soc-ctrl@20d20 {
305 compatible = "marvell,armada-380-mpcore-soc-ctrl";
306 reg = <0x20d20 0x6c>;
307 };
308
309 coherency-fabric@21010 {
310 compatible = "marvell,armada-380-coherency-fabric";
311 reg = <0x21010 0x1c>;
312 };
313
314 pmsu@22000 {
315 compatible = "marvell,armada-390-pmsu",
316 "marvell,armada-380-pmsu";
317 reg = <0x22000 0x1000>;
318 };
319
320 xor@60800 {
321 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
322 reg = <0x60800 0x100
323 0x60a00 0x100>;
324 clocks = <&gateclk 22>;
325 status = "okay";
326
327 xor00 {
328 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
329 dmacap,memcpy;
330 dmacap,xor;
331 };
332 xor01 {
333 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
334 dmacap,memcpy;
335 dmacap,xor;
336 dmacap,memset;
337 };
338 };
339
340 xor@60900 {
341 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
342 reg = <0x60900 0x100
343 0x60b00 0x100>;
344 clocks = <&gateclk 28>;
345 status = "okay";
346
347 xor10 {
348 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
349 dmacap,memcpy;
350 dmacap,xor;
351 };
352 xor11 {
353 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
354 dmacap,memcpy;
355 dmacap,xor;
356 dmacap,memset;
357 };
358 };
359
360 rtc@a3800 {
361 compatible = "marvell,armada-380-rtc";
362 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
363 reg-names = "rtc", "rtc-soc";
364 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
365 };
366
367 nand_controller: nand-controller@d0000 {
368 compatible = "marvell,armada370-nand-controller";
369 reg = <0xd0000 0x54>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&coredivclk 0>;
374 status = "disabled";
375 };
376
377 sdhci@d8000 {
378 compatible = "marvell,armada-380-sdhci";
379 reg-names = "sdhci", "mbus", "conf-sdio3";
380 reg = <0xd8000 0x1000>,
381 <0xdc000 0x100>,
382 <0x18454 0x4>;
383 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&gateclk 17>;
385 mrvl,clk-delay-cycles = <0x1F>;
386 status = "disabled";
387 };
388
389 coredivclk: clock@e4250 {
390 compatible = "marvell,armada-390-corediv-clock",
391 "marvell,armada-380-corediv-clock";
392 reg = <0xe4250 0xc>;
393 #clock-cells = <1>;
394 clocks = <&mainpll>;
395 clock-output-names = "nand";
396 };
397
398 thermal@e8078 {
399 compatible = "marvell,armada380-thermal";
400 reg = <0xe4078 0x4>, <0xe4074 0x4>;
401 status = "okay";
402 };
403 };
404
405 pcie {
406 compatible = "marvell,armada-370-pcie";
407 status = "disabled";
408 device_type = "pci";
409
410 #address-cells = <3>;
411 #size-cells = <2>;
412
413 msi-parent = <&mpic>;
414 bus-range = <0x00 0xff>;
415
416 ranges =
417 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
418 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
419 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
420 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
421 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
422 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
423 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
424 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
425 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
426 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
427 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
428 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
429
430 /*
431 * This port can be either x4 or x1. When
432 * configured in x4 by the bootloader, then
433 * pcie@4,0 is not available.
434 */
435 pcie@1,0 {
436 device_type = "pci";
437 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
438 reg = <0x0800 0 0 0 0>;
439 #address-cells = <3>;
440 #size-cells = <2>;
441 #interrupt-cells = <1>;
442 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
443 0x81000000 0 0 0x81000000 0x1 0 1 0>;
444 bus-range = <0x00 0xff>;
445 interrupt-map-mask = <0 0 0 0>;
446 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
447 marvell,pcie-port = <0>;
448 marvell,pcie-lane = <0>;
449 clocks = <&gateclk 8>;
450 status = "disabled";
451 };
452
453 /* x1 port */
454 pcie@2,0 {
455 device_type = "pci";
456 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
457 reg = <0x1000 0 0 0 0>;
458 #address-cells = <3>;
459 #size-cells = <2>;
460 #interrupt-cells = <1>;
461 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
462 0x81000000 0 0 0x81000000 0x2 0 1 0>;
463 bus-range = <0x00 0xff>;
464 interrupt-map-mask = <0 0 0 0>;
465 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
466 marvell,pcie-port = <1>;
467 marvell,pcie-lane = <0>;
468 clocks = <&gateclk 5>;
469 status = "disabled";
470 };
471
472 /* x1 port */
473 pcie@3,0 {
474 device_type = "pci";
475 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
476 reg = <0x1800 0 0 0 0>;
477 #address-cells = <3>;
478 #size-cells = <2>;
479 #interrupt-cells = <1>;
480 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
481 0x81000000 0 0 0x81000000 0x3 0 1 0>;
482 bus-range = <0x00 0xff>;
483 interrupt-map-mask = <0 0 0 0>;
484 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
485 marvell,pcie-port = <2>;
486 marvell,pcie-lane = <0>;
487 clocks = <&gateclk 6>;
488 status = "disabled";
489 };
490
491 /*
492 * x1 port only available when pcie@1,0 is
493 * configured as a x1 port
494 */
495 pcie@4,0 {
496 device_type = "pci";
497 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
498 reg = <0x2000 0 0 0 0>;
499 #address-cells = <3>;
500 #size-cells = <2>;
501 #interrupt-cells = <1>;
502 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
503 0x81000000 0 0 0x81000000 0x4 0 1 0>;
504 bus-range = <0x00 0xff>;
505 interrupt-map-mask = <0 0 0 0>;
506 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
507 marvell,pcie-port = <3>;
508 marvell,pcie-lane = <0>;
509 clocks = <&gateclk 7>;
510 status = "disabled";
511 };
512 };
513
514 spi0: spi@10600 {
515 compatible = "marvell,armada-390-spi",
516 "marvell,orion-spi";
517 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 cell-index = <0>;
521 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&coreclk 0>;
523 status = "disabled";
524 };
525
526 spi1: spi@10680 {
527 compatible = "marvell,armada-390-spi",
528 "marvell,orion-spi";
529 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 cell-index = <1>;
533 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&coreclk 0>;
535 status = "disabled";
536 };
537 };
538
539 clocks {
540 /* 1 GHz fixed main PLL */
541 mainpll: mainpll {
542 compatible = "fixed-clock";
543 #clock-cells = <0>;
544 clock-frequency = <1000000000>;
545 };
546
547 /* 25 MHz reference crystal */
548 refclk: oscillator {
549 compatible = "fixed-clock";
550 #clock-cells = <0>;
551 clock-frequency = <25000000>;
552 };
553 };
554};
1/*
2 * Device Tree Include file for Marvell Armada 39x family of SoCs.
3 *
4 * Copyright (C) 2015 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include "skeleton.dtsi"
48#include <dt-bindings/interrupt-controller/arm-gic.h>
49#include <dt-bindings/interrupt-controller/irq.h>
50
51#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
52
53/ {
54 model = "Marvell Armada 39x family SoC";
55 compatible = "marvell,armada390";
56
57 aliases {
58 serial0 = &uart0;
59 serial1 = &uart1;
60 serial2 = &uart2;
61 serial3 = &uart3;
62 };
63
64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67 enable-method = "marvell,armada-390-smp";
68
69 cpu@0 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a9";
72 reg = <0>;
73 };
74 cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a9";
77 reg = <1>;
78 };
79 };
80
81 soc {
82 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
83 "simple-bus";
84 #address-cells = <2>;
85 #size-cells = <1>;
86 controller = <&mbusc>;
87 interrupt-parent = <&gic>;
88 pcie-mem-aperture = <0xe0000000 0x8000000>;
89 pcie-io-aperture = <0xe8000000 0x100000>;
90
91 bootrom {
92 compatible = "marvell,bootrom";
93 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
94 };
95
96 internal-regs {
97 compatible = "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
101
102 L2: cache-controller@8000 {
103 compatible = "arm,pl310-cache";
104 reg = <0x8000 0x1000>;
105 cache-unified;
106 cache-level = <2>;
107 arm,double-linefill-incr = <1>;
108 arm,double-linefill-wrap = <0>;
109 arm,double-linefill = <1>;
110 prefetch-data = <1>;
111 };
112
113 scu@c000 {
114 compatible = "arm,cortex-a9-scu";
115 reg = <0xc000 0x100>;
116 };
117
118 timer@c600 {
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0xc600 0x20>;
121 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
122 clocks = <&coreclk 2>;
123 };
124
125 gic: interrupt-controller@d000 {
126 compatible = "arm,cortex-a9-gic";
127 #interrupt-cells = <3>;
128 #size-cells = <0>;
129 interrupt-controller;
130 reg = <0xd000 0x1000>,
131 <0xc100 0x100>;
132 };
133
134 spi0: spi@10600 {
135 compatible = "marvell,armada-390-spi",
136 "marvell,orion-spi";
137 reg = <0x10600 0x50>;
138 #address-cells = <1>;
139 #size-cells = <0>;
140 cell-index = <0>;
141 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&coreclk 0>;
143 status = "disabled";
144 };
145
146 spi1: spi@10680 {
147 compatible = "marvell,armada-390-spi",
148 "marvell,orion-spi";
149 reg = <0x10680 0x50>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 cell-index = <1>;
153 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&coreclk 0>;
155 status = "disabled";
156 };
157
158 i2c0: i2c@11000 {
159 compatible = "marvell,mv64xxx-i2c";
160 reg = <0x11000 0x20>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
164 timeout-ms = <1000>;
165 clocks = <&coreclk 0>;
166 status = "disabled";
167 };
168
169 i2c1: i2c@11100 {
170 compatible = "marvell,mv64xxx-i2c";
171 reg = <0x11100 0x20>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
175 timeout-ms = <1000>;
176 clocks = <&coreclk 0>;
177 status = "disabled";
178 };
179
180 i2c2: i2c@11200 {
181 compatible = "marvell,mv64xxx-i2c";
182 reg = <0x11200 0x20>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
186 timeout-ms = <1000>;
187 clocks = <&coreclk 0>;
188 status = "disabled";
189 };
190
191 i2c3: i2c@11300 {
192 compatible = "marvell,mv64xxx-i2c";
193 reg = <0x11300 0x20>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
197 timeout-ms = <1000>;
198 clocks = <&coreclk 0>;
199 status = "disabled";
200 };
201
202 uart0: serial@12000 {
203 compatible = "snps,dw-apb-uart";
204 reg = <0x12000 0x100>;
205 reg-shift = <2>;
206 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
207 reg-io-width = <1>;
208 clocks = <&coreclk 0>;
209 status = "disabled";
210 };
211
212 uart1: serial@12100 {
213 compatible = "snps,dw-apb-uart";
214 reg = <0x12100 0x100>;
215 reg-shift = <2>;
216 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
217 reg-io-width = <1>;
218 clocks = <&coreclk 0>;
219 status = "disabled";
220 };
221
222 uart2: serial@12200 {
223 compatible = "snps,dw-apb-uart";
224 reg = <0x12200 0x100>;
225 reg-shift = <2>;
226 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
227 reg-io-width = <1>;
228 clocks = <&coreclk 0>;
229 status = "disabled";
230 };
231
232 uart3: serial@12300 {
233 compatible = "snps,dw-apb-uart";
234 reg = <0x12300 0x100>;
235 reg-shift = <2>;
236 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
237 reg-io-width = <1>;
238 clocks = <&coreclk 0>;
239 status = "disabled";
240 };
241
242 pinctrl@18000 {
243 i2c0_pins: i2c0-pins {
244 marvell,pins = "mpp2", "mpp3";
245 marvell,function = "i2c0";
246 };
247
248 uart0_pins: uart0-pins {
249 marvell,pins = "mpp0", "mpp1";
250 marvell,function = "ua0";
251 };
252
253 uart1_pins: uart1-pins {
254 marvell,pins = "mpp19", "mpp20";
255 marvell,function = "ua1";
256 };
257
258 spi1_pins: spi1-pins {
259 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
260 marvell,function = "spi1";
261 };
262
263 nand_pins: nand-pins {
264 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
265 "mpp38", "mpp28", "mpp40", "mpp42",
266 "mpp35", "mpp36", "mpp25", "mpp30",
267 "mpp32";
268 marvell,function = "dev";
269 };
270 };
271
272 system-controller@18200 {
273 compatible = "marvell,armada-390-system-controller",
274 "marvell,armada-370-xp-system-controller";
275 reg = <0x18200 0x100>;
276 };
277
278 gateclk: clock-gating-control@18220 {
279 compatible = "marvell,armada-390-gating-clock";
280 reg = <0x18220 0x4>;
281 clocks = <&coreclk 0>;
282 #clock-cells = <1>;
283 };
284
285 coreclk: mvebu-sar@18600 {
286 compatible = "marvell,armada-390-core-clock";
287 reg = <0x18600 0x04>;
288 #clock-cells = <1>;
289 };
290
291 mbusc: mbus-controller@20000 {
292 compatible = "marvell,mbus-controller";
293 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
294 };
295
296 mpic: interrupt-controller@20a00 {
297 compatible = "marvell,mpic";
298 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
299 #interrupt-cells = <1>;
300 #size-cells = <1>;
301 interrupt-controller;
302 msi-controller;
303 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
304 };
305
306 timer@20300 {
307 compatible = "marvell,armada-380-timer",
308 "marvell,armada-xp-timer";
309 reg = <0x20300 0x30>, <0x21040 0x30>;
310 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
311 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
312 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
313 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
314 <&mpic 5>,
315 <&mpic 6>;
316 clocks = <&coreclk 2>, <&coreclk 5>;
317 clock-names = "nbclk", "fixed";
318 };
319
320 cpurst@20800 {
321 compatible = "marvell,armada-370-cpu-reset";
322 reg = <0x20800 0x10>;
323 };
324
325 pmsu@22000 {
326 compatible = "marvell,armada-390-pmsu",
327 "marvell,armada-380-pmsu";
328 reg = <0x22000 0x1000>;
329 };
330
331 xor@60800 {
332 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
333 reg = <0x60800 0x100
334 0x60a00 0x100>;
335 clocks = <&gateclk 22>;
336 status = "okay";
337
338 xor00 {
339 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
340 dmacap,memcpy;
341 dmacap,xor;
342 };
343 xor01 {
344 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
345 dmacap,memcpy;
346 dmacap,xor;
347 dmacap,memset;
348 };
349 };
350
351 xor@60900 {
352 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
353 reg = <0x60900 0x100
354 0x60b00 0x100>;
355 clocks = <&gateclk 28>;
356 status = "okay";
357
358 xor10 {
359 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
360 dmacap,memcpy;
361 dmacap,xor;
362 };
363 xor11 {
364 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
365 dmacap,memcpy;
366 dmacap,xor;
367 dmacap,memset;
368 };
369 };
370
371 flash@d0000 {
372 compatible = "marvell,armada370-nand";
373 reg = <0xd0000 0x54>;
374 #address-cells = <1>;
375 #size-cells = <1>;
376 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&coredivclk 0>;
378 status = "disabled";
379 };
380
381 sdhci@d8000 {
382 compatible = "marvell,armada-380-sdhci";
383 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
384 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&gateclk 17>;
386 mrvl,clk-delay-cycles = <0x1F>;
387 status = "disabled";
388 };
389
390 coredivclk: clock@e4250 {
391 compatible = "marvell,armada-390-corediv-clock",
392 "marvell,armada-380-corediv-clock";
393 reg = <0xe4250 0xc>;
394 #clock-cells = <1>;
395 clocks = <&mainpll>;
396 clock-output-names = "nand";
397 };
398 };
399
400 pcie-controller {
401 compatible = "marvell,armada-370-pcie";
402 status = "disabled";
403 device_type = "pci";
404
405 #address-cells = <3>;
406 #size-cells = <2>;
407
408 msi-parent = <&mpic>;
409 bus-range = <0x00 0xff>;
410
411 ranges =
412 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
413 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
414 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
415 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
416 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
417 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
418 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
419 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
420 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
421 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
422 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
423 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
424
425 /*
426 * This port can be either x4 or x1. When
427 * configured in x4 by the bootloader, then
428 * pcie@4,0 is not available.
429 */
430 pcie@1,0 {
431 device_type = "pci";
432 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
433 reg = <0x0800 0 0 0 0>;
434 #address-cells = <3>;
435 #size-cells = <2>;
436 #interrupt-cells = <1>;
437 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
438 0x81000000 0 0 0x81000000 0x1 0 1 0>;
439 interrupt-map-mask = <0 0 0 0>;
440 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
441 marvell,pcie-port = <0>;
442 marvell,pcie-lane = <0>;
443 clocks = <&gateclk 8>;
444 status = "disabled";
445 };
446
447 /* x1 port */
448 pcie@2,0 {
449 device_type = "pci";
450 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
451 reg = <0x1000 0 0 0 0>;
452 #address-cells = <3>;
453 #size-cells = <2>;
454 #interrupt-cells = <1>;
455 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
456 0x81000000 0 0 0x81000000 0x2 0 1 0>;
457 interrupt-map-mask = <0 0 0 0>;
458 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
459 marvell,pcie-port = <1>;
460 marvell,pcie-lane = <0>;
461 clocks = <&gateclk 5>;
462 status = "disabled";
463 };
464
465 /* x1 port */
466 pcie@3,0 {
467 device_type = "pci";
468 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
469 reg = <0x1800 0 0 0 0>;
470 #address-cells = <3>;
471 #size-cells = <2>;
472 #interrupt-cells = <1>;
473 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
474 0x81000000 0 0 0x81000000 0x3 0 1 0>;
475 interrupt-map-mask = <0 0 0 0>;
476 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
477 marvell,pcie-port = <2>;
478 marvell,pcie-lane = <0>;
479 clocks = <&gateclk 6>;
480 status = "disabled";
481 };
482
483 /*
484 * x1 port only available when pcie@1,0 is
485 * configured as a x1 port
486 */
487 pcie@4,0 {
488 device_type = "pci";
489 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
490 reg = <0x2000 0 0 0 0>;
491 #address-cells = <3>;
492 #size-cells = <2>;
493 #interrupt-cells = <1>;
494 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
495 0x81000000 0 0 0x81000000 0x4 0 1 0>;
496 interrupt-map-mask = <0 0 0 0>;
497 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
498 marvell,pcie-port = <3>;
499 marvell,pcie-lane = <0>;
500 clocks = <&gateclk 7>;
501 status = "disabled";
502 };
503 };
504 };
505
506 clocks {
507 /* 2 GHz fixed main PLL */
508 mainpll: mainpll {
509 compatible = "fixed-clock";
510 #clock-cells = <0>;
511 clock-frequency = <1000000000>;
512 };
513 };
514};