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1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _HNS_ROCE_COMMON_H
34#define _HNS_ROCE_COMMON_H
35#include <linux/bitfield.h>
36
37#define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg))
38#define roce_read(dev, reg) readl((dev)->reg_base + (reg))
39#define roce_raw_write(value, addr) \
40 __raw_writel((__force u32)cpu_to_le32(value), (addr))
41
42#define roce_get_field(origin, mask, shift) \
43 ((le32_to_cpu(origin) & (mask)) >> (u32)(shift))
44
45#define roce_get_bit(origin, shift) \
46 roce_get_field((origin), (1ul << (shift)), (shift))
47
48#define roce_set_field(origin, mask, shift, val) \
49 do { \
50 (origin) &= ~cpu_to_le32(mask); \
51 (origin) |= \
52 cpu_to_le32(((u32)(val) << (u32)(shift)) & (mask)); \
53 } while (0)
54
55#define roce_set_bit(origin, shift, val) \
56 roce_set_field((origin), (1ul << (shift)), (shift), (val))
57
58#define FIELD_LOC(field_type, field_h, field_l) field_type, field_h, field_l
59
60#define _hr_reg_enable(ptr, field_type, field_h, field_l) \
61 ({ \
62 const field_type *_ptr = ptr; \
63 *((__le32 *)_ptr + (field_h) / 32) |= cpu_to_le32( \
64 BIT((field_l) % 32) + \
65 BUILD_BUG_ON_ZERO((field_h) != (field_l))); \
66 })
67
68#define hr_reg_enable(ptr, field) _hr_reg_enable(ptr, field)
69
70#define _hr_reg_clear(ptr, field_type, field_h, field_l) \
71 ({ \
72 const field_type *_ptr = ptr; \
73 BUILD_BUG_ON(((field_h) / 32) != ((field_l) / 32)); \
74 *((__le32 *)_ptr + (field_h) / 32) &= \
75 ~cpu_to_le32(GENMASK((field_h) % 32, (field_l) % 32)); \
76 })
77
78#define hr_reg_clear(ptr, field) _hr_reg_clear(ptr, field)
79
80#define _hr_reg_write_bool(ptr, field_type, field_h, field_l, val) \
81 ({ \
82 (val) ? _hr_reg_enable(ptr, field_type, field_h, field_l) : \
83 _hr_reg_clear(ptr, field_type, field_h, field_l); \
84 })
85
86#define hr_reg_write_bool(ptr, field, val) _hr_reg_write_bool(ptr, field, val)
87
88#define _hr_reg_write(ptr, field_type, field_h, field_l, val) \
89 ({ \
90 _hr_reg_clear(ptr, field_type, field_h, field_l); \
91 *((__le32 *)ptr + (field_h) / 32) |= cpu_to_le32(FIELD_PREP( \
92 GENMASK((field_h) % 32, (field_l) % 32), val)); \
93 })
94
95#define hr_reg_write(ptr, field, val) _hr_reg_write(ptr, field, val)
96
97#define _hr_reg_read(ptr, field_type, field_h, field_l) \
98 ({ \
99 const field_type *_ptr = ptr; \
100 BUILD_BUG_ON(((field_h) / 32) != ((field_l) / 32)); \
101 FIELD_GET(GENMASK((field_h) % 32, (field_l) % 32), \
102 le32_to_cpu(*((__le32 *)_ptr + (field_h) / 32))); \
103 })
104
105#define hr_reg_read(ptr, field) _hr_reg_read(ptr, field)
106
107#define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3
108#define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4
109
110#define ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S 5
111
112#define ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S 6
113
114#define ROCEE_GLB_CFG_ROCEE_PORT_ST_S 10
115#define ROCEE_GLB_CFG_ROCEE_PORT_ST_M \
116 (((1UL << 6) - 1) << ROCEE_GLB_CFG_ROCEE_PORT_ST_S)
117
118#define ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S 16
119
120#define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S 0
121#define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M \
122 (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S)
123
124#define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S 24
125#define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M \
126 (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S)
127
128#define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S 0
129#define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M \
130 (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S)
131
132#define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S 24
133#define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M \
134 (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S)
135
136#define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S 0
137#define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M \
138 (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S)
139
140#define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S 16
141#define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M \
142 (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S)
143
144#define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S 0
145#define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M \
146 (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S)
147
148#define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S 16
149#define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M \
150 (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S)
151
152#define ROCEE_RAQ_WL_ROCEE_RAQ_WL_S 0
153#define ROCEE_RAQ_WL_ROCEE_RAQ_WL_M \
154 (((1UL << 8) - 1) << ROCEE_RAQ_WL_ROCEE_RAQ_WL_S)
155
156#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S 0
157#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M \
158 (((1UL << 15) - 1) << \
159 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S)
160
161#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S 16
162#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M \
163 (((1UL << 4) - 1) << \
164 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S)
165
166#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S 20
167
168#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE 21
169
170#define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S 0
171#define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M \
172 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S)
173
174#define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S 5
175#define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M \
176 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S)
177
178#define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S 0
179#define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M \
180 (((1UL << 5) - 1) << ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S)
181
182#define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S 5
183#define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M \
184 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S)
185
186#define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S 0
187#define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M \
188 (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S)
189
190#define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S 8
191#define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M \
192 (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S)
193
194#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S 0
195#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M \
196 (((1UL << 19) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S)
197
198#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_S 19
199
200#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S 20
201#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M \
202 (((1UL << 2) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S)
203
204#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S 22
205#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M \
206 (((1UL << 5) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S)
207
208#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S 31
209
210#define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S 0
211#define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M \
212 (((1UL << 3) - 1) << ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S)
213
214#define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S 0
215#define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M \
216 (((1UL << 15) - 1) << ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S)
217
218#define ROCEE_MB6_ROCEE_MB_CMD_S 0
219#define ROCEE_MB6_ROCEE_MB_CMD_M \
220 (((1UL << 8) - 1) << ROCEE_MB6_ROCEE_MB_CMD_S)
221
222#define ROCEE_MB6_ROCEE_MB_CMD_MDF_S 8
223#define ROCEE_MB6_ROCEE_MB_CMD_MDF_M \
224 (((1UL << 4) - 1) << ROCEE_MB6_ROCEE_MB_CMD_MDF_S)
225
226#define ROCEE_MB6_ROCEE_MB_EVENT_S 14
227
228#define ROCEE_MB6_ROCEE_MB_HW_RUN_S 15
229
230#define ROCEE_MB6_ROCEE_MB_TOKEN_S 16
231#define ROCEE_MB6_ROCEE_MB_TOKEN_M \
232 (((1UL << 16) - 1) << ROCEE_MB6_ROCEE_MB_TOKEN_S)
233
234#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S 0
235#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M \
236 (((1UL << 24) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S)
237
238#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S 24
239#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M \
240 (((1UL << 4) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S)
241
242#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S 28
243#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M \
244 (((1UL << 3) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S)
245
246#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S 31
247
248#define ROCEE_SMAC_H_ROCEE_SMAC_H_S 0
249#define ROCEE_SMAC_H_ROCEE_SMAC_H_M \
250 (((1UL << 16) - 1) << ROCEE_SMAC_H_ROCEE_SMAC_H_S)
251
252#define ROCEE_SMAC_H_ROCEE_PORT_MTU_S 16
253#define ROCEE_SMAC_H_ROCEE_PORT_MTU_M \
254 (((1UL << 4) - 1) << ROCEE_SMAC_H_ROCEE_PORT_MTU_S)
255
256#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S 0
257#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M \
258 (((1UL << 2) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S)
259
260#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S 8
261#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M \
262 (((1UL << 4) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S)
263
264#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S 17
265
266#define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S 0
267#define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M \
268 (((1UL << 5) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S)
269
270#define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S 16
271#define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M \
272 (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S)
273
274#define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S 0
275#define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M \
276 (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S)
277
278#define ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S 16
279#define ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S 1
280#define ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S 0
281
282#define ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S 0
283#define ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S 1
284
285#define ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S 0
286
287#define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S 0
288#define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M \
289 (((1UL << 28) - 1) << ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S)
290
291#define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S 0
292#define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M \
293 (((1UL << 28) - 1) << ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)
294
295#define ROCEE_SDB_INV_CNT_SDB_INV_CNT_S 0
296#define ROCEE_SDB_INV_CNT_SDB_INV_CNT_M \
297 (((1UL << 16) - 1) << ROCEE_SDB_INV_CNT_SDB_INV_CNT_S)
298
299#define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S 0
300#define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M \
301 (((1UL << 16) - 1) << ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S)
302
303#define ROCEE_SDB_CNT_CMP_BITS 16
304
305#define ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S 20
306
307#define ROCEE_CNT_CLR_CE_CNT_CLR_CE_S 0
308
309/*************ROCEE_REG DEFINITION****************/
310#define ROCEE_VENDOR_ID_REG 0x0
311#define ROCEE_VENDOR_PART_ID_REG 0x4
312
313#define ROCEE_SYS_IMAGE_GUID_L_REG 0xC
314#define ROCEE_SYS_IMAGE_GUID_H_REG 0x10
315
316#define ROCEE_PORT_GID_L_0_REG 0x50
317#define ROCEE_PORT_GID_ML_0_REG 0x54
318#define ROCEE_PORT_GID_MH_0_REG 0x58
319#define ROCEE_PORT_GID_H_0_REG 0x5C
320
321#define ROCEE_BT_CMD_H_REG 0x204
322
323#define ROCEE_SMAC_L_0_REG 0x240
324#define ROCEE_SMAC_H_0_REG 0x244
325
326#define ROCEE_QP1C_CFG3_0_REG 0x27C
327
328#define ROCEE_CAEP_AEQE_CONS_IDX_REG 0x3AC
329#define ROCEE_CAEP_CEQC_CONS_IDX_0_REG 0x3BC
330
331#define ROCEE_ECC_UCERR_ALM1_REG 0xB38
332#define ROCEE_ECC_UCERR_ALM2_REG 0xB3C
333#define ROCEE_ECC_CERR_ALM1_REG 0xB44
334#define ROCEE_ECC_CERR_ALM2_REG 0xB48
335
336#define ROCEE_ACK_DELAY_REG 0x14
337#define ROCEE_GLB_CFG_REG 0x18
338
339#define ROCEE_DMAE_USER_CFG1_REG 0x40
340#define ROCEE_DMAE_USER_CFG2_REG 0x44
341
342#define ROCEE_DB_SQ_WL_REG 0x154
343#define ROCEE_DB_OTHERS_WL_REG 0x158
344#define ROCEE_RAQ_WL_REG 0x15C
345#define ROCEE_WRMS_POL_TIME_INTERVAL_REG 0x160
346#define ROCEE_EXT_DB_SQ_REG 0x164
347#define ROCEE_EXT_DB_SQ_H_REG 0x168
348#define ROCEE_EXT_DB_OTH_REG 0x16C
349
350#define ROCEE_EXT_DB_OTH_H_REG 0x170
351#define ROCEE_EXT_DB_SQ_WL_EMPTY_REG 0x174
352#define ROCEE_EXT_DB_SQ_WL_REG 0x178
353#define ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG 0x17C
354#define ROCEE_EXT_DB_OTHERS_WL_REG 0x180
355#define ROCEE_EXT_RAQ_REG 0x184
356#define ROCEE_EXT_RAQ_H_REG 0x188
357
358#define ROCEE_CAEP_CE_INTERVAL_CFG_REG 0x190
359#define ROCEE_CAEP_CE_BURST_NUM_CFG_REG 0x194
360#define ROCEE_BT_CMD_L_REG 0x200
361
362#define ROCEE_MB1_REG 0x210
363#define ROCEE_MB6_REG 0x224
364#define ROCEE_DB_SQ_L_0_REG 0x230
365#define ROCEE_DB_OTHERS_L_0_REG 0x238
366#define ROCEE_QP1C_CFG0_0_REG 0x270
367
368#define ROCEE_CAEP_AEQC_AEQE_SHIFT_REG 0x3A0
369#define ROCEE_CAEP_CEQC_SHIFT_0_REG 0x3B0
370#define ROCEE_CAEP_CE_IRQ_MASK_0_REG 0x3C0
371#define ROCEE_CAEP_CEQ_ALM_OVF_0_REG 0x3C4
372#define ROCEE_CAEP_AE_MASK_REG 0x6C8
373#define ROCEE_CAEP_AE_ST_REG 0x6CC
374
375#define ROCEE_CAEP_CQE_WCMD_EMPTY 0x850
376#define ROCEE_SCAEP_WR_CQE_CNT 0x8D0
377#define ROCEE_ECC_UCERR_ALM0_REG 0xB34
378#define ROCEE_ECC_CERR_ALM0_REG 0xB40
379
380/* V2 ROCEE REG */
381#define ROCEE_TX_CMQ_BASEADDR_L_REG 0x07000
382#define ROCEE_TX_CMQ_BASEADDR_H_REG 0x07004
383#define ROCEE_TX_CMQ_DEPTH_REG 0x07008
384#define ROCEE_TX_CMQ_PI_REG 0x07010
385#define ROCEE_TX_CMQ_CI_REG 0x07014
386
387#define ROCEE_RX_CMQ_BASEADDR_L_REG 0x07018
388#define ROCEE_RX_CMQ_BASEADDR_H_REG 0x0701c
389#define ROCEE_RX_CMQ_DEPTH_REG 0x07020
390#define ROCEE_RX_CMQ_TAIL_REG 0x07024
391#define ROCEE_RX_CMQ_HEAD_REG 0x07028
392
393#define ROCEE_VF_EQ_DB_CFG0_REG 0x238
394#define ROCEE_VF_EQ_DB_CFG1_REG 0x23C
395
396#define ROCEE_VF_ABN_INT_CFG_REG 0x13000
397#define ROCEE_VF_ABN_INT_ST_REG 0x13004
398#define ROCEE_VF_ABN_INT_EN_REG 0x13008
399#define ROCEE_VF_EVENT_INT_EN_REG 0x1300c
400
401#endif /* _HNS_ROCE_COMMON_H */