1/*
  2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 20 * DEALINGS IN THE SOFTWARE.
 21 */
 22#include "priv.h"
 23
 24#include <subdev/acr.h>
 25
 26#include <nvfw/flcn.h>
 27#include <nvfw/pmu.h>
 28
 29static int
 30gp10b_pmu_acr_bootstrap_multiple_falcons_cb(void *priv,
 31					    struct nvfw_falcon_msg *hdr)
 32{
 33	struct nv_pmu_acr_bootstrap_multiple_falcons_msg *msg =
 34		container_of(hdr, typeof(*msg), msg.hdr);
 35	return msg->falcon_mask;
 36}
 37static int
 38gp10b_pmu_acr_bootstrap_multiple_falcons(struct nvkm_falcon *falcon, u32 mask)
 39{
 40	struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);
 41	struct nv_pmu_acr_bootstrap_multiple_falcons_cmd cmd = {
 42		.cmd.hdr.unit_id = NV_PMU_UNIT_ACR,
 43		.cmd.hdr.size = sizeof(cmd),
 44		.cmd.cmd_type = NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS,
 45		.flags = NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES,
 46		.falcon_mask = mask,
 47		.wpr_lo = 0, /*XXX*/
 48		.wpr_hi = 0, /*XXX*/
 49	};
 50	int ret;
 51
 52	ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
 53				    gp10b_pmu_acr_bootstrap_multiple_falcons_cb,
 54				    &pmu->subdev, msecs_to_jiffies(1000));
 55	if (ret >= 0) {
 56		if (ret != cmd.falcon_mask)
 57			ret = -EIO;
 58		else
 59			ret = 0;
 60	}
 61
 62	return ret;
 63}
 64
 65static const struct nvkm_acr_lsf_func
 66gp10b_pmu_acr = {
 67	.flags = NVKM_ACR_LSF_DMACTL_REQ_CTX,
 68	.bld_size = sizeof(struct loader_config),
 69	.bld_write = gm20b_pmu_acr_bld_write,
 70	.bld_patch = gm20b_pmu_acr_bld_patch,
 71	.boot = gm20b_pmu_acr_boot,
 72	.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) |
 73			     BIT_ULL(NVKM_ACR_LSF_FECS) |
 74			     BIT_ULL(NVKM_ACR_LSF_GPCCS),
 75	.bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon,
 76	.bootstrap_multiple_falcons = gp10b_pmu_acr_bootstrap_multiple_falcons,
 77};
 78
 79static const struct nvkm_pmu_func
 80gp10b_pmu = {
 81	.flcn = &gt215_pmu_flcn,
 82	.enabled = gf100_pmu_enabled,
 83	.intr = gt215_pmu_intr,
 84	.recv = gm20b_pmu_recv,
 85	.initmsg = gm20b_pmu_initmsg,
 86};
 87
 88#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
 89MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin");
 90MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin");
 91MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
 92#endif
 93
 94static const struct nvkm_pmu_fwif
 95gp10b_pmu_fwif[] = {
 96	{  0, gm20b_pmu_load, &gp10b_pmu, &gp10b_pmu_acr },
 97	{ -1, gm200_pmu_nofw, &gp10b_pmu },
 98	{}
 99};
100
101int
102gp10b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
103	      struct nvkm_pmu **ppmu)
104{
105	return nvkm_pmu_new_(gp10b_pmu_fwif, device, type, inst, ppmu);
106}