Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/completion.h>
12#include <linux/delay.h>
13#include <linux/module.h>
14#include <linux/of_platform.h>
15#include <linux/regmap.h>
16#include <linux/reset.h>
17
18#include <sound/dmaengine_pcm.h>
19#include <sound/pcm_params.h>
20
21/* SPDIF-rx Register Map */
22#define STM32_SPDIFRX_CR 0x00
23#define STM32_SPDIFRX_IMR 0x04
24#define STM32_SPDIFRX_SR 0x08
25#define STM32_SPDIFRX_IFCR 0x0C
26#define STM32_SPDIFRX_DR 0x10
27#define STM32_SPDIFRX_CSR 0x14
28#define STM32_SPDIFRX_DIR 0x18
29#define STM32_SPDIFRX_VERR 0x3F4
30#define STM32_SPDIFRX_IDR 0x3F8
31#define STM32_SPDIFRX_SIDR 0x3FC
32
33/* Bit definition for SPDIF_CR register */
34#define SPDIFRX_CR_SPDIFEN_SHIFT 0
35#define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
36#define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
37
38#define SPDIFRX_CR_RXDMAEN BIT(2)
39#define SPDIFRX_CR_RXSTEO BIT(3)
40
41#define SPDIFRX_CR_DRFMT_SHIFT 4
42#define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
43#define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
44
45#define SPDIFRX_CR_PMSK BIT(6)
46#define SPDIFRX_CR_VMSK BIT(7)
47#define SPDIFRX_CR_CUMSK BIT(8)
48#define SPDIFRX_CR_PTMSK BIT(9)
49#define SPDIFRX_CR_CBDMAEN BIT(10)
50#define SPDIFRX_CR_CHSEL_SHIFT 11
51#define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
52
53#define SPDIFRX_CR_NBTR_SHIFT 12
54#define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
55#define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
56
57#define SPDIFRX_CR_WFA BIT(14)
58
59#define SPDIFRX_CR_INSEL_SHIFT 16
60#define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
61#define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
62
63#define SPDIFRX_CR_CKSEN_SHIFT 20
64#define SPDIFRX_CR_CKSEN BIT(20)
65#define SPDIFRX_CR_CKSBKPEN BIT(21)
66
67/* Bit definition for SPDIFRX_IMR register */
68#define SPDIFRX_IMR_RXNEI BIT(0)
69#define SPDIFRX_IMR_CSRNEIE BIT(1)
70#define SPDIFRX_IMR_PERRIE BIT(2)
71#define SPDIFRX_IMR_OVRIE BIT(3)
72#define SPDIFRX_IMR_SBLKIE BIT(4)
73#define SPDIFRX_IMR_SYNCDIE BIT(5)
74#define SPDIFRX_IMR_IFEIE BIT(6)
75
76#define SPDIFRX_XIMR_MASK GENMASK(6, 0)
77
78/* Bit definition for SPDIFRX_SR register */
79#define SPDIFRX_SR_RXNE BIT(0)
80#define SPDIFRX_SR_CSRNE BIT(1)
81#define SPDIFRX_SR_PERR BIT(2)
82#define SPDIFRX_SR_OVR BIT(3)
83#define SPDIFRX_SR_SBD BIT(4)
84#define SPDIFRX_SR_SYNCD BIT(5)
85#define SPDIFRX_SR_FERR BIT(6)
86#define SPDIFRX_SR_SERR BIT(7)
87#define SPDIFRX_SR_TERR BIT(8)
88
89#define SPDIFRX_SR_WIDTH5_SHIFT 16
90#define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
91#define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
92
93/* Bit definition for SPDIFRX_IFCR register */
94#define SPDIFRX_IFCR_PERRCF BIT(2)
95#define SPDIFRX_IFCR_OVRCF BIT(3)
96#define SPDIFRX_IFCR_SBDCF BIT(4)
97#define SPDIFRX_IFCR_SYNCDCF BIT(5)
98
99#define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
100
101/* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
102#define SPDIFRX_DR0_DR_SHIFT 0
103#define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
104#define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
105
106#define SPDIFRX_DR0_PE BIT(24)
107
108#define SPDIFRX_DR0_V BIT(25)
109#define SPDIFRX_DR0_U BIT(26)
110#define SPDIFRX_DR0_C BIT(27)
111
112#define SPDIFRX_DR0_PT_SHIFT 28
113#define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
114#define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
115
116/* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
117#define SPDIFRX_DR1_PE BIT(0)
118#define SPDIFRX_DR1_V BIT(1)
119#define SPDIFRX_DR1_U BIT(2)
120#define SPDIFRX_DR1_C BIT(3)
121
122#define SPDIFRX_DR1_PT_SHIFT 4
123#define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
124#define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
125
126#define SPDIFRX_DR1_DR_SHIFT 8
127#define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
128#define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
129
130/* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
131#define SPDIFRX_DR1_DRNL1_SHIFT 0
132#define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
133#define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
134
135#define SPDIFRX_DR1_DRNL2_SHIFT 16
136#define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
137#define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
138
139/* Bit definition for SPDIFRX_CSR register */
140#define SPDIFRX_CSR_USR_SHIFT 0
141#define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
142#define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
143 >> SPDIFRX_CSR_USR_SHIFT)
144
145#define SPDIFRX_CSR_CS_SHIFT 16
146#define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
147#define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
148 >> SPDIFRX_CSR_CS_SHIFT)
149
150#define SPDIFRX_CSR_SOB BIT(24)
151
152/* Bit definition for SPDIFRX_DIR register */
153#define SPDIFRX_DIR_THI_SHIFT 0
154#define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
155#define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
156
157#define SPDIFRX_DIR_TLO_SHIFT 16
158#define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
159#define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
160
161#define SPDIFRX_SPDIFEN_DISABLE 0x0
162#define SPDIFRX_SPDIFEN_SYNC 0x1
163#define SPDIFRX_SPDIFEN_ENABLE 0x3
164
165/* Bit definition for SPDIFRX_VERR register */
166#define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0)
167#define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4)
168
169/* Bit definition for SPDIFRX_IDR register */
170#define SPDIFRX_IDR_ID_MASK GENMASK(31, 0)
171
172/* Bit definition for SPDIFRX_SIDR register */
173#define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0)
174
175#define SPDIFRX_IPIDR_NUMBER 0x00130041
176
177#define SPDIFRX_IN1 0x1
178#define SPDIFRX_IN2 0x2
179#define SPDIFRX_IN3 0x3
180#define SPDIFRX_IN4 0x4
181#define SPDIFRX_IN5 0x5
182#define SPDIFRX_IN6 0x6
183#define SPDIFRX_IN7 0x7
184#define SPDIFRX_IN8 0x8
185
186#define SPDIFRX_NBTR_NONE 0x0
187#define SPDIFRX_NBTR_3 0x1
188#define SPDIFRX_NBTR_15 0x2
189#define SPDIFRX_NBTR_63 0x3
190
191#define SPDIFRX_DRFMT_RIGHT 0x0
192#define SPDIFRX_DRFMT_LEFT 0x1
193#define SPDIFRX_DRFMT_PACKED 0x2
194
195/* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
196#define SPDIFRX_CS_BYTES_NB 24
197#define SPDIFRX_UB_BYTES_NB 48
198
199/*
200 * CSR register is retrieved as a 32 bits word
201 * It contains 1 channel status byte and 2 user data bytes
202 * 2 S/PDIF frames are acquired to get all CS/UB bits
203 */
204#define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
205
206/**
207 * struct stm32_spdifrx_data - private data of SPDIFRX
208 * @pdev: device data pointer
209 * @base: mmio register base virtual address
210 * @regmap: SPDIFRX register map pointer
211 * @regmap_conf: SPDIFRX register map configuration pointer
212 * @cs_completion: channel status retrieving completion
213 * @kclk: kernel clock feeding the SPDIFRX clock generator
214 * @dma_params: dma configuration data for rx channel
215 * @substream: PCM substream data pointer
216 * @dmab: dma buffer info pointer
217 * @ctrl_chan: dma channel for S/PDIF control bits
218 * @desc:dma async transaction descriptor
219 * @slave_config: dma slave channel runtime config pointer
220 * @phys_addr: SPDIFRX registers physical base address
221 * @lock: synchronization enabling lock
222 * @irq_lock: prevent race condition with IRQ on stream state
223 * @cs: channel status buffer
224 * @ub: user data buffer
225 * @irq: SPDIFRX interrupt line
226 * @refcount: keep count of opened DMA channels
227 */
228struct stm32_spdifrx_data {
229 struct platform_device *pdev;
230 void __iomem *base;
231 struct regmap *regmap;
232 const struct regmap_config *regmap_conf;
233 struct completion cs_completion;
234 struct clk *kclk;
235 struct snd_dmaengine_dai_dma_data dma_params;
236 struct snd_pcm_substream *substream;
237 struct snd_dma_buffer *dmab;
238 struct dma_chan *ctrl_chan;
239 struct dma_async_tx_descriptor *desc;
240 struct dma_slave_config slave_config;
241 dma_addr_t phys_addr;
242 spinlock_t lock; /* Sync enabling lock */
243 spinlock_t irq_lock; /* Prevent race condition on stream state */
244 unsigned char cs[SPDIFRX_CS_BYTES_NB];
245 unsigned char ub[SPDIFRX_UB_BYTES_NB];
246 int irq;
247 int refcount;
248};
249
250static void stm32_spdifrx_dma_complete(void *data)
251{
252 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
253 struct platform_device *pdev = spdifrx->pdev;
254 u32 *p_start = (u32 *)spdifrx->dmab->area;
255 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
256 u32 *ptr = p_start;
257 u16 *ub_ptr = (short *)spdifrx->ub;
258 int i = 0;
259
260 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
261 SPDIFRX_CR_CBDMAEN,
262 (unsigned int)~SPDIFRX_CR_CBDMAEN);
263
264 if (!spdifrx->dmab->area)
265 return;
266
267 while (ptr <= p_end) {
268 if (*ptr & SPDIFRX_CSR_SOB)
269 break;
270 ptr++;
271 }
272
273 if (ptr > p_end) {
274 dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
275 return;
276 }
277
278 while (i < SPDIFRX_CS_BYTES_NB) {
279 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
280 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
281 if (ptr > p_end) {
282 dev_err(&pdev->dev, "Failed to get channel status\n");
283 return;
284 }
285 i++;
286 }
287
288 complete(&spdifrx->cs_completion);
289}
290
291static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
292{
293 dma_cookie_t cookie;
294 int err;
295
296 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
297 spdifrx->dmab->addr,
298 SPDIFRX_CSR_BUF_LENGTH,
299 DMA_DEV_TO_MEM,
300 DMA_CTRL_ACK);
301 if (!spdifrx->desc)
302 return -EINVAL;
303
304 spdifrx->desc->callback = stm32_spdifrx_dma_complete;
305 spdifrx->desc->callback_param = spdifrx;
306 cookie = dmaengine_submit(spdifrx->desc);
307 err = dma_submit_error(cookie);
308 if (err)
309 return -EINVAL;
310
311 dma_async_issue_pending(spdifrx->ctrl_chan);
312
313 return 0;
314}
315
316static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
317{
318 dmaengine_terminate_async(spdifrx->ctrl_chan);
319}
320
321static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
322{
323 int cr, cr_mask, imr, ret;
324 unsigned long flags;
325
326 /* Enable IRQs */
327 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
328 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
329 if (ret)
330 return ret;
331
332 spin_lock_irqsave(&spdifrx->lock, flags);
333
334 spdifrx->refcount++;
335
336 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
337
338 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
339 /*
340 * Start sync if SPDIFRX is still in idle state.
341 * SPDIFRX reception enabled when sync done
342 */
343 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
344
345 /*
346 * SPDIFRX configuration:
347 * Wait for activity before starting sync process. This avoid
348 * to issue sync errors when spdif signal is missing on input.
349 * Preamble, CS, user, validity and parity error bits not copied
350 * to DR register.
351 */
352 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
353 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
354 cr_mask = cr;
355
356 cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63);
357 cr_mask |= SPDIFRX_CR_NBTR_MASK;
358 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
359 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
360 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
361 cr_mask, cr);
362 if (ret < 0)
363 dev_err(&spdifrx->pdev->dev,
364 "Failed to start synchronization\n");
365 }
366
367 spin_unlock_irqrestore(&spdifrx->lock, flags);
368
369 return ret;
370}
371
372static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
373{
374 int cr, cr_mask, reg;
375 unsigned long flags;
376
377 spin_lock_irqsave(&spdifrx->lock, flags);
378
379 if (--spdifrx->refcount) {
380 spin_unlock_irqrestore(&spdifrx->lock, flags);
381 return;
382 }
383
384 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
385 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
386
387 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
388
389 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
390 SPDIFRX_XIMR_MASK, 0);
391
392 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
393 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
394
395 /* dummy read to clear CSRNE and RXNE in status register */
396 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
397 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
398
399 spin_unlock_irqrestore(&spdifrx->lock, flags);
400}
401
402static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
403 struct stm32_spdifrx_data *spdifrx)
404{
405 int ret;
406
407 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
408 if (IS_ERR(spdifrx->ctrl_chan)) {
409 if (PTR_ERR(spdifrx->ctrl_chan) != -EPROBE_DEFER)
410 dev_err(dev, "dma_request_slave_channel error %ld\n",
411 PTR_ERR(spdifrx->ctrl_chan));
412 return PTR_ERR(spdifrx->ctrl_chan);
413 }
414
415 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
416 GFP_KERNEL);
417 if (!spdifrx->dmab)
418 return -ENOMEM;
419
420 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
421 spdifrx->dmab->dev.dev = dev;
422 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
423 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
424 if (ret < 0) {
425 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
426 return ret;
427 }
428
429 spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
430 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
431 STM32_SPDIFRX_CSR);
432 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
433 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
434 spdifrx->slave_config.src_maxburst = 1;
435
436 ret = dmaengine_slave_config(spdifrx->ctrl_chan,
437 &spdifrx->slave_config);
438 if (ret < 0) {
439 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
440 spdifrx->ctrl_chan = NULL;
441 }
442
443 return ret;
444};
445
446static const char * const spdifrx_enum_input[] = {
447 "in0", "in1", "in2", "in3"
448};
449
450/* By default CS bits are retrieved from channel A */
451static const char * const spdifrx_enum_cs_channel[] = {
452 "A", "B"
453};
454
455static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
456 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
457 spdifrx_enum_input);
458
459static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
460 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
461 spdifrx_enum_cs_channel);
462
463static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_info *uinfo)
465{
466 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
467 uinfo->count = 1;
468
469 return 0;
470}
471
472static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
473 struct snd_ctl_elem_info *uinfo)
474{
475 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
476 uinfo->count = 1;
477
478 return 0;
479}
480
481static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
482{
483 int ret = 0;
484
485 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
486 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
487
488 ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
489 if (ret < 0)
490 return ret;
491
492 ret = clk_prepare_enable(spdifrx->kclk);
493 if (ret) {
494 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
495 return ret;
496 }
497
498 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
499 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
500 if (ret < 0)
501 goto end;
502
503 ret = stm32_spdifrx_start_sync(spdifrx);
504 if (ret < 0)
505 goto end;
506
507 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
508 msecs_to_jiffies(100))
509 <= 0) {
510 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
511 ret = -EAGAIN;
512 }
513
514 stm32_spdifrx_stop(spdifrx);
515 stm32_spdifrx_dma_ctrl_stop(spdifrx);
516
517end:
518 clk_disable_unprepare(spdifrx->kclk);
519
520 return ret;
521}
522
523static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
524 struct snd_ctl_elem_value *ucontrol)
525{
526 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
527 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
528
529 stm32_spdifrx_get_ctrl_data(spdifrx);
530
531 ucontrol->value.iec958.status[0] = spdifrx->cs[0];
532 ucontrol->value.iec958.status[1] = spdifrx->cs[1];
533 ucontrol->value.iec958.status[2] = spdifrx->cs[2];
534 ucontrol->value.iec958.status[3] = spdifrx->cs[3];
535 ucontrol->value.iec958.status[4] = spdifrx->cs[4];
536
537 return 0;
538}
539
540static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
541 struct snd_ctl_elem_value *ucontrol)
542{
543 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
544 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
545
546 stm32_spdifrx_get_ctrl_data(spdifrx);
547
548 ucontrol->value.iec958.status[0] = spdifrx->ub[0];
549 ucontrol->value.iec958.status[1] = spdifrx->ub[1];
550 ucontrol->value.iec958.status[2] = spdifrx->ub[2];
551 ucontrol->value.iec958.status[3] = spdifrx->ub[3];
552 ucontrol->value.iec958.status[4] = spdifrx->ub[4];
553
554 return 0;
555}
556
557static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
558 /* Channel status control */
559 {
560 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
561 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
562 .access = SNDRV_CTL_ELEM_ACCESS_READ |
563 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
564 .info = stm32_spdifrx_info,
565 .get = stm32_spdifrx_capture_get,
566 },
567 /* User bits control */
568 {
569 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
570 .name = "IEC958 User Bit Capture Default",
571 .access = SNDRV_CTL_ELEM_ACCESS_READ |
572 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
573 .info = stm32_spdifrx_ub_info,
574 .get = stm32_spdif_user_bits_get,
575 },
576};
577
578static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
579 SOC_ENUM("SPDIFRX input", ctrl_enum_input),
580 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
581};
582
583static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
584{
585 int ret;
586
587 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
588 ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
589 if (ret < 0)
590 return ret;
591
592 return snd_soc_add_component_controls(cpu_dai->component,
593 stm32_spdifrx_ctrls,
594 ARRAY_SIZE(stm32_spdifrx_ctrls));
595}
596
597static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
598{
599 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
600
601 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
602 STM32_SPDIFRX_DR);
603 spdifrx->dma_params.maxburst = 1;
604
605 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
606
607 return stm32_spdifrx_dai_register_ctrls(cpu_dai);
608}
609
610static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
611{
612 switch (reg) {
613 case STM32_SPDIFRX_CR:
614 case STM32_SPDIFRX_IMR:
615 case STM32_SPDIFRX_SR:
616 case STM32_SPDIFRX_IFCR:
617 case STM32_SPDIFRX_DR:
618 case STM32_SPDIFRX_CSR:
619 case STM32_SPDIFRX_DIR:
620 case STM32_SPDIFRX_VERR:
621 case STM32_SPDIFRX_IDR:
622 case STM32_SPDIFRX_SIDR:
623 return true;
624 default:
625 return false;
626 }
627}
628
629static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
630{
631 switch (reg) {
632 case STM32_SPDIFRX_DR:
633 case STM32_SPDIFRX_CSR:
634 case STM32_SPDIFRX_SR:
635 case STM32_SPDIFRX_DIR:
636 return true;
637 default:
638 return false;
639 }
640}
641
642static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
643{
644 switch (reg) {
645 case STM32_SPDIFRX_CR:
646 case STM32_SPDIFRX_IMR:
647 case STM32_SPDIFRX_IFCR:
648 return true;
649 default:
650 return false;
651 }
652}
653
654static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
655 .reg_bits = 32,
656 .reg_stride = 4,
657 .val_bits = 32,
658 .max_register = STM32_SPDIFRX_SIDR,
659 .readable_reg = stm32_spdifrx_readable_reg,
660 .volatile_reg = stm32_spdifrx_volatile_reg,
661 .writeable_reg = stm32_spdifrx_writeable_reg,
662 .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1,
663 .fast_io = true,
664 .cache_type = REGCACHE_FLAT,
665};
666
667static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
668{
669 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
670 struct platform_device *pdev = spdifrx->pdev;
671 unsigned int cr, mask, sr, imr;
672 unsigned int flags, sync_state;
673 int err = 0, err_xrun = 0;
674
675 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
676 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
677
678 mask = imr & SPDIFRX_XIMR_MASK;
679 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
680 if (mask & SPDIFRX_IMR_IFEIE)
681 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
682
683 flags = sr & mask;
684 if (!flags) {
685 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
686 sr, imr);
687 return IRQ_NONE;
688 }
689
690 /* Clear IRQs */
691 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
692 SPDIFRX_XIFCR_MASK, flags);
693
694 if (flags & SPDIFRX_SR_PERR) {
695 dev_dbg(&pdev->dev, "Parity error\n");
696 err_xrun = 1;
697 }
698
699 if (flags & SPDIFRX_SR_OVR) {
700 dev_dbg(&pdev->dev, "Overrun error\n");
701 err_xrun = 1;
702 }
703
704 if (flags & SPDIFRX_SR_SBD)
705 dev_dbg(&pdev->dev, "Synchronization block detected\n");
706
707 if (flags & SPDIFRX_SR_SYNCD) {
708 dev_dbg(&pdev->dev, "Synchronization done\n");
709
710 /* Enable spdifrx */
711 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
712 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
713 SPDIFRX_CR_SPDIFEN_MASK, cr);
714 }
715
716 if (flags & SPDIFRX_SR_FERR) {
717 dev_dbg(&pdev->dev, "Frame error\n");
718 err = 1;
719 }
720
721 if (flags & SPDIFRX_SR_SERR) {
722 dev_dbg(&pdev->dev, "Synchronization error\n");
723 err = 1;
724 }
725
726 if (flags & SPDIFRX_SR_TERR) {
727 dev_dbg(&pdev->dev, "Timeout error\n");
728 err = 1;
729 }
730
731 if (err) {
732 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
733 sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) &&
734 SPDIFRX_SPDIFEN_SYNC;
735
736 /* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */
737 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
738 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
739 SPDIFRX_CR_SPDIFEN_MASK, cr);
740
741 /* If SPDIFRX was in STATE_SYNC, retry synchro */
742 if (sync_state) {
743 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
744 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
745 SPDIFRX_CR_SPDIFEN_MASK, cr);
746 return IRQ_HANDLED;
747 }
748
749 spin_lock(&spdifrx->irq_lock);
750 if (spdifrx->substream)
751 snd_pcm_stop(spdifrx->substream,
752 SNDRV_PCM_STATE_DISCONNECTED);
753 spin_unlock(&spdifrx->irq_lock);
754
755 return IRQ_HANDLED;
756 }
757
758 spin_lock(&spdifrx->irq_lock);
759 if (err_xrun && spdifrx->substream)
760 snd_pcm_stop_xrun(spdifrx->substream);
761 spin_unlock(&spdifrx->irq_lock);
762
763 return IRQ_HANDLED;
764}
765
766static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
767 struct snd_soc_dai *cpu_dai)
768{
769 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
770 unsigned long flags;
771 int ret;
772
773 spin_lock_irqsave(&spdifrx->irq_lock, flags);
774 spdifrx->substream = substream;
775 spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
776
777 ret = clk_prepare_enable(spdifrx->kclk);
778 if (ret)
779 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
780
781 return ret;
782}
783
784static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
785 struct snd_pcm_hw_params *params,
786 struct snd_soc_dai *cpu_dai)
787{
788 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
789 int data_size = params_width(params);
790 int fmt;
791
792 switch (data_size) {
793 case 16:
794 fmt = SPDIFRX_DRFMT_PACKED;
795 break;
796 case 32:
797 fmt = SPDIFRX_DRFMT_LEFT;
798 break;
799 default:
800 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
801 return -EINVAL;
802 }
803
804 /*
805 * Set buswidth to 4 bytes for all data formats.
806 * Packed format: transfer 2 x 2 bytes samples
807 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
808 */
809 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
810 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
811
812 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
813 SPDIFRX_CR_DRFMT_MASK,
814 SPDIFRX_CR_DRFMTSET(fmt));
815}
816
817static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
818 struct snd_soc_dai *cpu_dai)
819{
820 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
821 int ret = 0;
822
823 switch (cmd) {
824 case SNDRV_PCM_TRIGGER_START:
825 case SNDRV_PCM_TRIGGER_RESUME:
826 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
827 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
828 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
829
830 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
831 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
832
833 ret = stm32_spdifrx_start_sync(spdifrx);
834 break;
835 case SNDRV_PCM_TRIGGER_SUSPEND:
836 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
837 case SNDRV_PCM_TRIGGER_STOP:
838 stm32_spdifrx_stop(spdifrx);
839 break;
840 default:
841 return -EINVAL;
842 }
843
844 return ret;
845}
846
847static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
848 struct snd_soc_dai *cpu_dai)
849{
850 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
851 unsigned long flags;
852
853 spin_lock_irqsave(&spdifrx->irq_lock, flags);
854 spdifrx->substream = NULL;
855 spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
856
857 clk_disable_unprepare(spdifrx->kclk);
858}
859
860static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
861 .startup = stm32_spdifrx_startup,
862 .hw_params = stm32_spdifrx_hw_params,
863 .trigger = stm32_spdifrx_trigger,
864 .shutdown = stm32_spdifrx_shutdown,
865};
866
867static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
868 {
869 .probe = stm32_spdifrx_dai_probe,
870 .capture = {
871 .stream_name = "CPU-Capture",
872 .channels_min = 1,
873 .channels_max = 2,
874 .rates = SNDRV_PCM_RATE_8000_192000,
875 .formats = SNDRV_PCM_FMTBIT_S32_LE |
876 SNDRV_PCM_FMTBIT_S16_LE,
877 },
878 .ops = &stm32_spdifrx_pcm_dai_ops,
879 }
880};
881
882static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
883 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
884 .buffer_bytes_max = 8 * PAGE_SIZE,
885 .period_bytes_min = 1024,
886 .period_bytes_max = 4 * PAGE_SIZE,
887 .periods_min = 2,
888 .periods_max = 8,
889};
890
891static const struct snd_soc_component_driver stm32_spdifrx_component = {
892 .name = "stm32-spdifrx",
893};
894
895static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
896 .pcm_hardware = &stm32_spdifrx_pcm_hw,
897 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
898};
899
900static const struct of_device_id stm32_spdifrx_ids[] = {
901 {
902 .compatible = "st,stm32h7-spdifrx",
903 .data = &stm32_h7_spdifrx_regmap_conf
904 },
905 {}
906};
907
908static int stm32_spdifrx_parse_of(struct platform_device *pdev,
909 struct stm32_spdifrx_data *spdifrx)
910{
911 struct device_node *np = pdev->dev.of_node;
912 const struct of_device_id *of_id;
913 struct resource *res;
914
915 if (!np)
916 return -ENODEV;
917
918 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
919 if (of_id)
920 spdifrx->regmap_conf =
921 (const struct regmap_config *)of_id->data;
922 else
923 return -EINVAL;
924
925 spdifrx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
926 if (IS_ERR(spdifrx->base))
927 return PTR_ERR(spdifrx->base);
928
929 spdifrx->phys_addr = res->start;
930
931 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
932 if (IS_ERR(spdifrx->kclk)) {
933 if (PTR_ERR(spdifrx->kclk) != -EPROBE_DEFER)
934 dev_err(&pdev->dev, "Could not get kclk: %ld\n",
935 PTR_ERR(spdifrx->kclk));
936 return PTR_ERR(spdifrx->kclk);
937 }
938
939 spdifrx->irq = platform_get_irq(pdev, 0);
940 if (spdifrx->irq < 0)
941 return spdifrx->irq;
942
943 return 0;
944}
945
946static int stm32_spdifrx_remove(struct platform_device *pdev)
947{
948 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
949
950 if (spdifrx->ctrl_chan)
951 dma_release_channel(spdifrx->ctrl_chan);
952
953 if (spdifrx->dmab)
954 snd_dma_free_pages(spdifrx->dmab);
955
956 snd_dmaengine_pcm_unregister(&pdev->dev);
957 snd_soc_unregister_component(&pdev->dev);
958
959 return 0;
960}
961
962static int stm32_spdifrx_probe(struct platform_device *pdev)
963{
964 struct stm32_spdifrx_data *spdifrx;
965 struct reset_control *rst;
966 const struct snd_dmaengine_pcm_config *pcm_config = NULL;
967 u32 ver, idr;
968 int ret;
969
970 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
971 if (!spdifrx)
972 return -ENOMEM;
973
974 spdifrx->pdev = pdev;
975 init_completion(&spdifrx->cs_completion);
976 spin_lock_init(&spdifrx->lock);
977 spin_lock_init(&spdifrx->irq_lock);
978
979 platform_set_drvdata(pdev, spdifrx);
980
981 ret = stm32_spdifrx_parse_of(pdev, spdifrx);
982 if (ret)
983 return ret;
984
985 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
986 spdifrx->base,
987 spdifrx->regmap_conf);
988 if (IS_ERR(spdifrx->regmap)) {
989 if (PTR_ERR(spdifrx->regmap) != -EPROBE_DEFER)
990 dev_err(&pdev->dev, "Regmap init error %ld\n",
991 PTR_ERR(spdifrx->regmap));
992 return PTR_ERR(spdifrx->regmap);
993 }
994
995 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
996 dev_name(&pdev->dev), spdifrx);
997 if (ret) {
998 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
999 return ret;
1000 }
1001
1002 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1003 if (IS_ERR(rst)) {
1004 if (PTR_ERR(rst) != -EPROBE_DEFER)
1005 dev_err(&pdev->dev, "Reset controller error %ld\n",
1006 PTR_ERR(rst));
1007 return PTR_ERR(rst);
1008 }
1009 reset_control_assert(rst);
1010 udelay(2);
1011 reset_control_deassert(rst);
1012
1013 pcm_config = &stm32_spdifrx_pcm_config;
1014 ret = snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
1015 if (ret) {
1016 if (ret != -EPROBE_DEFER)
1017 dev_err(&pdev->dev, "PCM DMA register error %d\n", ret);
1018 return ret;
1019 }
1020
1021 ret = snd_soc_register_component(&pdev->dev,
1022 &stm32_spdifrx_component,
1023 stm32_spdifrx_dai,
1024 ARRAY_SIZE(stm32_spdifrx_dai));
1025 if (ret) {
1026 snd_dmaengine_pcm_unregister(&pdev->dev);
1027 return ret;
1028 }
1029
1030 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
1031 if (ret)
1032 goto error;
1033
1034 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr);
1035 if (ret)
1036 goto error;
1037
1038 if (idr == SPDIFRX_IPIDR_NUMBER) {
1039 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver);
1040 if (ret)
1041 goto error;
1042
1043 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n",
1044 FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver),
1045 FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver));
1046 }
1047
1048 return ret;
1049
1050error:
1051 stm32_spdifrx_remove(pdev);
1052
1053 return ret;
1054}
1055
1056MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
1057
1058#ifdef CONFIG_PM_SLEEP
1059static int stm32_spdifrx_suspend(struct device *dev)
1060{
1061 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1062
1063 regcache_cache_only(spdifrx->regmap, true);
1064 regcache_mark_dirty(spdifrx->regmap);
1065
1066 return 0;
1067}
1068
1069static int stm32_spdifrx_resume(struct device *dev)
1070{
1071 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1072
1073 regcache_cache_only(spdifrx->regmap, false);
1074
1075 return regcache_sync(spdifrx->regmap);
1076}
1077#endif /* CONFIG_PM_SLEEP */
1078
1079static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
1080 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
1081};
1082
1083static struct platform_driver stm32_spdifrx_driver = {
1084 .driver = {
1085 .name = "st,stm32-spdifrx",
1086 .of_match_table = stm32_spdifrx_ids,
1087 .pm = &stm32_spdifrx_pm_ops,
1088 },
1089 .probe = stm32_spdifrx_probe,
1090 .remove = stm32_spdifrx_remove,
1091};
1092
1093module_platform_driver(stm32_spdifrx_driver);
1094
1095MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
1096MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1097MODULE_ALIAS("platform:stm32-spdifrx");
1098MODULE_LICENSE("GPL v2");
1/*
2 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
3 *
4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
6 *
7 * License terms: GPL V2.0.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
16 * details.
17 */
18
19#include <linux/clk.h>
20#include <linux/completion.h>
21#include <linux/delay.h>
22#include <linux/module.h>
23#include <linux/of_platform.h>
24#include <linux/regmap.h>
25#include <linux/reset.h>
26
27#include <sound/dmaengine_pcm.h>
28#include <sound/pcm_params.h>
29
30/* SPDIF-rx Register Map */
31#define STM32_SPDIFRX_CR 0x00
32#define STM32_SPDIFRX_IMR 0x04
33#define STM32_SPDIFRX_SR 0x08
34#define STM32_SPDIFRX_IFCR 0x0C
35#define STM32_SPDIFRX_DR 0x10
36#define STM32_SPDIFRX_CSR 0x14
37#define STM32_SPDIFRX_DIR 0x18
38
39/* Bit definition for SPDIF_CR register */
40#define SPDIFRX_CR_SPDIFEN_SHIFT 0
41#define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
42#define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
43
44#define SPDIFRX_CR_RXDMAEN BIT(2)
45#define SPDIFRX_CR_RXSTEO BIT(3)
46
47#define SPDIFRX_CR_DRFMT_SHIFT 4
48#define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
49#define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
50
51#define SPDIFRX_CR_PMSK BIT(6)
52#define SPDIFRX_CR_VMSK BIT(7)
53#define SPDIFRX_CR_CUMSK BIT(8)
54#define SPDIFRX_CR_PTMSK BIT(9)
55#define SPDIFRX_CR_CBDMAEN BIT(10)
56#define SPDIFRX_CR_CHSEL_SHIFT 11
57#define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
58
59#define SPDIFRX_CR_NBTR_SHIFT 12
60#define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
61#define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
62
63#define SPDIFRX_CR_WFA BIT(14)
64
65#define SPDIFRX_CR_INSEL_SHIFT 16
66#define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
67#define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
68
69#define SPDIFRX_CR_CKSEN_SHIFT 20
70#define SPDIFRX_CR_CKSEN BIT(20)
71#define SPDIFRX_CR_CKSBKPEN BIT(21)
72
73/* Bit definition for SPDIFRX_IMR register */
74#define SPDIFRX_IMR_RXNEI BIT(0)
75#define SPDIFRX_IMR_CSRNEIE BIT(1)
76#define SPDIFRX_IMR_PERRIE BIT(2)
77#define SPDIFRX_IMR_OVRIE BIT(3)
78#define SPDIFRX_IMR_SBLKIE BIT(4)
79#define SPDIFRX_IMR_SYNCDIE BIT(5)
80#define SPDIFRX_IMR_IFEIE BIT(6)
81
82#define SPDIFRX_XIMR_MASK GENMASK(6, 0)
83
84/* Bit definition for SPDIFRX_SR register */
85#define SPDIFRX_SR_RXNE BIT(0)
86#define SPDIFRX_SR_CSRNE BIT(1)
87#define SPDIFRX_SR_PERR BIT(2)
88#define SPDIFRX_SR_OVR BIT(3)
89#define SPDIFRX_SR_SBD BIT(4)
90#define SPDIFRX_SR_SYNCD BIT(5)
91#define SPDIFRX_SR_FERR BIT(6)
92#define SPDIFRX_SR_SERR BIT(7)
93#define SPDIFRX_SR_TERR BIT(8)
94
95#define SPDIFRX_SR_WIDTH5_SHIFT 16
96#define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
97#define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
98
99/* Bit definition for SPDIFRX_IFCR register */
100#define SPDIFRX_IFCR_PERRCF BIT(2)
101#define SPDIFRX_IFCR_OVRCF BIT(3)
102#define SPDIFRX_IFCR_SBDCF BIT(4)
103#define SPDIFRX_IFCR_SYNCDCF BIT(5)
104
105#define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
106
107/* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
108#define SPDIFRX_DR0_DR_SHIFT 0
109#define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
110#define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
111
112#define SPDIFRX_DR0_PE BIT(24)
113
114#define SPDIFRX_DR0_V BIT(25)
115#define SPDIFRX_DR0_U BIT(26)
116#define SPDIFRX_DR0_C BIT(27)
117
118#define SPDIFRX_DR0_PT_SHIFT 28
119#define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
120#define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
121
122/* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
123#define SPDIFRX_DR1_PE BIT(0)
124#define SPDIFRX_DR1_V BIT(1)
125#define SPDIFRX_DR1_U BIT(2)
126#define SPDIFRX_DR1_C BIT(3)
127
128#define SPDIFRX_DR1_PT_SHIFT 4
129#define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
130#define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
131
132#define SPDIFRX_DR1_DR_SHIFT 8
133#define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
134#define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
135
136/* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
137#define SPDIFRX_DR1_DRNL1_SHIFT 0
138#define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
139#define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
140
141#define SPDIFRX_DR1_DRNL2_SHIFT 16
142#define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
143#define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
144
145/* Bit definition for SPDIFRX_CSR register */
146#define SPDIFRX_CSR_USR_SHIFT 0
147#define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
148#define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
149 >> SPDIFRX_CSR_USR_SHIFT)
150
151#define SPDIFRX_CSR_CS_SHIFT 16
152#define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
153#define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
154 >> SPDIFRX_CSR_CS_SHIFT)
155
156#define SPDIFRX_CSR_SOB BIT(24)
157
158/* Bit definition for SPDIFRX_DIR register */
159#define SPDIFRX_DIR_THI_SHIFT 0
160#define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
161#define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
162
163#define SPDIFRX_DIR_TLO_SHIFT 16
164#define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
165#define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
166
167#define SPDIFRX_SPDIFEN_DISABLE 0x0
168#define SPDIFRX_SPDIFEN_SYNC 0x1
169#define SPDIFRX_SPDIFEN_ENABLE 0x3
170
171#define SPDIFRX_IN1 0x1
172#define SPDIFRX_IN2 0x2
173#define SPDIFRX_IN3 0x3
174#define SPDIFRX_IN4 0x4
175#define SPDIFRX_IN5 0x5
176#define SPDIFRX_IN6 0x6
177#define SPDIFRX_IN7 0x7
178#define SPDIFRX_IN8 0x8
179
180#define SPDIFRX_NBTR_NONE 0x0
181#define SPDIFRX_NBTR_3 0x1
182#define SPDIFRX_NBTR_15 0x2
183#define SPDIFRX_NBTR_63 0x3
184
185#define SPDIFRX_DRFMT_RIGHT 0x0
186#define SPDIFRX_DRFMT_LEFT 0x1
187#define SPDIFRX_DRFMT_PACKED 0x2
188
189/* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
190#define SPDIFRX_CS_BYTES_NB 24
191#define SPDIFRX_UB_BYTES_NB 48
192
193/*
194 * CSR register is retrieved as a 32 bits word
195 * It contains 1 channel status byte and 2 user data bytes
196 * 2 S/PDIF frames are acquired to get all CS/UB bits
197 */
198#define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
199
200/**
201 * struct stm32_spdifrx_data - private data of SPDIFRX
202 * @pdev: device data pointer
203 * @base: mmio register base virtual address
204 * @regmap: SPDIFRX register map pointer
205 * @regmap_conf: SPDIFRX register map configuration pointer
206 * @cs_completion: channel status retrieving completion
207 * @kclk: kernel clock feeding the SPDIFRX clock generator
208 * @dma_params: dma configuration data for rx channel
209 * @substream: PCM substream data pointer
210 * @dmab: dma buffer info pointer
211 * @ctrl_chan: dma channel for S/PDIF control bits
212 * @desc:dma async transaction descriptor
213 * @slave_config: dma slave channel runtime config pointer
214 * @phys_addr: SPDIFRX registers physical base address
215 * @lock: synchronization enabling lock
216 * @cs: channel status buffer
217 * @ub: user data buffer
218 * @irq: SPDIFRX interrupt line
219 * @refcount: keep count of opened DMA channels
220 */
221struct stm32_spdifrx_data {
222 struct platform_device *pdev;
223 void __iomem *base;
224 struct regmap *regmap;
225 const struct regmap_config *regmap_conf;
226 struct completion cs_completion;
227 struct clk *kclk;
228 struct snd_dmaengine_dai_dma_data dma_params;
229 struct snd_pcm_substream *substream;
230 struct snd_dma_buffer *dmab;
231 struct dma_chan *ctrl_chan;
232 struct dma_async_tx_descriptor *desc;
233 struct dma_slave_config slave_config;
234 dma_addr_t phys_addr;
235 spinlock_t lock; /* Sync enabling lock */
236 unsigned char cs[SPDIFRX_CS_BYTES_NB];
237 unsigned char ub[SPDIFRX_UB_BYTES_NB];
238 int irq;
239 int refcount;
240};
241
242static void stm32_spdifrx_dma_complete(void *data)
243{
244 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
245 struct platform_device *pdev = spdifrx->pdev;
246 u32 *p_start = (u32 *)spdifrx->dmab->area;
247 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
248 u32 *ptr = p_start;
249 u16 *ub_ptr = (short *)spdifrx->ub;
250 int i = 0;
251
252 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
253 SPDIFRX_CR_CBDMAEN,
254 (unsigned int)~SPDIFRX_CR_CBDMAEN);
255
256 if (!spdifrx->dmab->area)
257 return;
258
259 while (ptr <= p_end) {
260 if (*ptr & SPDIFRX_CSR_SOB)
261 break;
262 ptr++;
263 }
264
265 if (ptr > p_end) {
266 dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
267 return;
268 }
269
270 while (i < SPDIFRX_CS_BYTES_NB) {
271 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
272 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
273 if (ptr > p_end) {
274 dev_err(&pdev->dev, "Failed to get channel status\n");
275 return;
276 }
277 i++;
278 }
279
280 complete(&spdifrx->cs_completion);
281}
282
283static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
284{
285 dma_cookie_t cookie;
286 int err;
287
288 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
289 spdifrx->dmab->addr,
290 SPDIFRX_CSR_BUF_LENGTH,
291 DMA_DEV_TO_MEM,
292 DMA_CTRL_ACK);
293 if (!spdifrx->desc)
294 return -EINVAL;
295
296 spdifrx->desc->callback = stm32_spdifrx_dma_complete;
297 spdifrx->desc->callback_param = spdifrx;
298 cookie = dmaengine_submit(spdifrx->desc);
299 err = dma_submit_error(cookie);
300 if (err)
301 return -EINVAL;
302
303 dma_async_issue_pending(spdifrx->ctrl_chan);
304
305 return 0;
306}
307
308static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
309{
310 dmaengine_terminate_async(spdifrx->ctrl_chan);
311}
312
313static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
314{
315 int cr, cr_mask, imr, ret;
316
317 /* Enable IRQs */
318 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
319 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
320 if (ret)
321 return ret;
322
323 spin_lock(&spdifrx->lock);
324
325 spdifrx->refcount++;
326
327 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
328
329 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
330 /*
331 * Start sync if SPDIFRX is still in idle state.
332 * SPDIFRX reception enabled when sync done
333 */
334 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
335
336 /*
337 * SPDIFRX configuration:
338 * Wait for activity before starting sync process. This avoid
339 * to issue sync errors when spdif signal is missing on input.
340 * Preamble, CS, user, validity and parity error bits not copied
341 * to DR register.
342 */
343 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
344 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
345 cr_mask = cr;
346
347 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
348 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
349 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
350 cr_mask, cr);
351 if (ret < 0)
352 dev_err(&spdifrx->pdev->dev,
353 "Failed to start synchronization\n");
354 }
355
356 spin_unlock(&spdifrx->lock);
357
358 return ret;
359}
360
361static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
362{
363 int cr, cr_mask, reg;
364
365 spin_lock(&spdifrx->lock);
366
367 if (--spdifrx->refcount) {
368 spin_unlock(&spdifrx->lock);
369 return;
370 }
371
372 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
373 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
374
375 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
376
377 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
378 SPDIFRX_XIMR_MASK, 0);
379
380 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
381 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
382
383 /* dummy read to clear CSRNE and RXNE in status register */
384 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
385 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
386
387 spin_unlock(&spdifrx->lock);
388}
389
390static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
391 struct stm32_spdifrx_data *spdifrx)
392{
393 int ret;
394
395 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
396 if (IS_ERR(spdifrx->ctrl_chan)) {
397 dev_err(dev, "dma_request_slave_channel failed\n");
398 return PTR_ERR(spdifrx->ctrl_chan);
399 }
400
401 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
402 GFP_KERNEL);
403 if (!spdifrx->dmab)
404 return -ENOMEM;
405
406 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
407 spdifrx->dmab->dev.dev = dev;
408 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
409 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
410 if (ret < 0) {
411 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
412 return ret;
413 }
414
415 spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
416 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
417 STM32_SPDIFRX_CSR);
418 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
419 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
420 spdifrx->slave_config.src_maxburst = 1;
421
422 ret = dmaengine_slave_config(spdifrx->ctrl_chan,
423 &spdifrx->slave_config);
424 if (ret < 0) {
425 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
426 spdifrx->ctrl_chan = NULL;
427 }
428
429 return ret;
430};
431
432static const char * const spdifrx_enum_input[] = {
433 "in0", "in1", "in2", "in3"
434};
435
436/* By default CS bits are retrieved from channel A */
437static const char * const spdifrx_enum_cs_channel[] = {
438 "A", "B"
439};
440
441static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
442 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
443 spdifrx_enum_input);
444
445static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
446 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
447 spdifrx_enum_cs_channel);
448
449static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
450 struct snd_ctl_elem_info *uinfo)
451{
452 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
453 uinfo->count = 1;
454
455 return 0;
456}
457
458static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
459 struct snd_ctl_elem_info *uinfo)
460{
461 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
462 uinfo->count = 1;
463
464 return 0;
465}
466
467static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
468{
469 int ret = 0;
470
471 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
472 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
473
474 ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
475 if (ret < 0)
476 return ret;
477
478 ret = clk_prepare_enable(spdifrx->kclk);
479 if (ret) {
480 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
481 return ret;
482 }
483
484 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
485 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
486 if (ret < 0)
487 goto end;
488
489 ret = stm32_spdifrx_start_sync(spdifrx);
490 if (ret < 0)
491 goto end;
492
493 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
494 msecs_to_jiffies(100))
495 <= 0) {
496 dev_err(&spdifrx->pdev->dev, "Failed to get control data\n");
497 ret = -EAGAIN;
498 }
499
500 stm32_spdifrx_stop(spdifrx);
501 stm32_spdifrx_dma_ctrl_stop(spdifrx);
502
503end:
504 clk_disable_unprepare(spdifrx->kclk);
505
506 return ret;
507}
508
509static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
510 struct snd_ctl_elem_value *ucontrol)
511{
512 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
513 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
514
515 stm32_spdifrx_get_ctrl_data(spdifrx);
516
517 ucontrol->value.iec958.status[0] = spdifrx->cs[0];
518 ucontrol->value.iec958.status[1] = spdifrx->cs[1];
519 ucontrol->value.iec958.status[2] = spdifrx->cs[2];
520 ucontrol->value.iec958.status[3] = spdifrx->cs[3];
521 ucontrol->value.iec958.status[4] = spdifrx->cs[4];
522
523 return 0;
524}
525
526static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
527 struct snd_ctl_elem_value *ucontrol)
528{
529 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
530 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
531
532 stm32_spdifrx_get_ctrl_data(spdifrx);
533
534 ucontrol->value.iec958.status[0] = spdifrx->ub[0];
535 ucontrol->value.iec958.status[1] = spdifrx->ub[1];
536 ucontrol->value.iec958.status[2] = spdifrx->ub[2];
537 ucontrol->value.iec958.status[3] = spdifrx->ub[3];
538 ucontrol->value.iec958.status[4] = spdifrx->ub[4];
539
540 return 0;
541}
542
543static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
544 /* Channel status control */
545 {
546 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
547 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
548 .access = SNDRV_CTL_ELEM_ACCESS_READ |
549 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
550 .info = stm32_spdifrx_info,
551 .get = stm32_spdifrx_capture_get,
552 },
553 /* User bits control */
554 {
555 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
556 .name = "IEC958 User Bit Capture Default",
557 .access = SNDRV_CTL_ELEM_ACCESS_READ |
558 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
559 .info = stm32_spdifrx_ub_info,
560 .get = stm32_spdif_user_bits_get,
561 },
562};
563
564static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
565 SOC_ENUM("SPDIFRX input", ctrl_enum_input),
566 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
567};
568
569static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
570{
571 int ret;
572
573 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
574 ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
575 if (ret < 0)
576 return ret;
577
578 return snd_soc_add_component_controls(cpu_dai->component,
579 stm32_spdifrx_ctrls,
580 ARRAY_SIZE(stm32_spdifrx_ctrls));
581}
582
583static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
584{
585 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
586
587 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
588 STM32_SPDIFRX_DR);
589 spdifrx->dma_params.maxburst = 1;
590
591 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
592
593 return stm32_spdifrx_dai_register_ctrls(cpu_dai);
594}
595
596static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
597{
598 switch (reg) {
599 case STM32_SPDIFRX_CR:
600 case STM32_SPDIFRX_IMR:
601 case STM32_SPDIFRX_SR:
602 case STM32_SPDIFRX_IFCR:
603 case STM32_SPDIFRX_DR:
604 case STM32_SPDIFRX_CSR:
605 case STM32_SPDIFRX_DIR:
606 return true;
607 default:
608 return false;
609 }
610}
611
612static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
613{
614 if (reg == STM32_SPDIFRX_DR)
615 return true;
616
617 return false;
618}
619
620static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
621{
622 switch (reg) {
623 case STM32_SPDIFRX_CR:
624 case STM32_SPDIFRX_IMR:
625 case STM32_SPDIFRX_IFCR:
626 return true;
627 default:
628 return false;
629 }
630}
631
632static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
633 .reg_bits = 32,
634 .reg_stride = 4,
635 .val_bits = 32,
636 .max_register = STM32_SPDIFRX_DIR,
637 .readable_reg = stm32_spdifrx_readable_reg,
638 .volatile_reg = stm32_spdifrx_volatile_reg,
639 .writeable_reg = stm32_spdifrx_writeable_reg,
640 .fast_io = true,
641};
642
643static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
644{
645 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
646 struct snd_pcm_substream *substream = spdifrx->substream;
647 struct platform_device *pdev = spdifrx->pdev;
648 unsigned int cr, mask, sr, imr;
649 unsigned int flags;
650 int err = 0, err_xrun = 0;
651
652 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
653 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
654
655 mask = imr & SPDIFRX_XIMR_MASK;
656 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
657 if (mask & SPDIFRX_IMR_IFEIE)
658 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
659
660 flags = sr & mask;
661 if (!flags) {
662 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
663 sr, imr);
664 return IRQ_NONE;
665 }
666
667 /* Clear IRQs */
668 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
669 SPDIFRX_XIFCR_MASK, flags);
670
671 if (flags & SPDIFRX_SR_PERR) {
672 dev_dbg(&pdev->dev, "Parity error\n");
673 err_xrun = 1;
674 }
675
676 if (flags & SPDIFRX_SR_OVR) {
677 dev_dbg(&pdev->dev, "Overrun error\n");
678 err_xrun = 1;
679 }
680
681 if (flags & SPDIFRX_SR_SBD)
682 dev_dbg(&pdev->dev, "Synchronization block detected\n");
683
684 if (flags & SPDIFRX_SR_SYNCD) {
685 dev_dbg(&pdev->dev, "Synchronization done\n");
686
687 /* Enable spdifrx */
688 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
689 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
690 SPDIFRX_CR_SPDIFEN_MASK, cr);
691 }
692
693 if (flags & SPDIFRX_SR_FERR) {
694 dev_dbg(&pdev->dev, "Frame error\n");
695 err = 1;
696 }
697
698 if (flags & SPDIFRX_SR_SERR) {
699 dev_dbg(&pdev->dev, "Synchronization error\n");
700 err = 1;
701 }
702
703 if (flags & SPDIFRX_SR_TERR) {
704 dev_dbg(&pdev->dev, "Timeout error\n");
705 err = 1;
706 }
707
708 if (err) {
709 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */
710 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
711 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
712 SPDIFRX_CR_SPDIFEN_MASK, cr);
713
714 if (substream)
715 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
716
717 return IRQ_HANDLED;
718 }
719
720 if (err_xrun && substream)
721 snd_pcm_stop_xrun(substream);
722
723 return IRQ_HANDLED;
724}
725
726static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
727 struct snd_soc_dai *cpu_dai)
728{
729 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
730 int ret;
731
732 spdifrx->substream = substream;
733
734 ret = clk_prepare_enable(spdifrx->kclk);
735 if (ret)
736 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
737
738 return ret;
739}
740
741static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
742 struct snd_pcm_hw_params *params,
743 struct snd_soc_dai *cpu_dai)
744{
745 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
746 int data_size = params_width(params);
747 int fmt;
748
749 switch (data_size) {
750 case 16:
751 fmt = SPDIFRX_DRFMT_PACKED;
752 break;
753 case 32:
754 fmt = SPDIFRX_DRFMT_LEFT;
755 break;
756 default:
757 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
758 return -EINVAL;
759 }
760
761 /*
762 * Set buswidth to 4 bytes for all data formats.
763 * Packed format: transfer 2 x 2 bytes samples
764 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
765 */
766 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
767 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
768
769 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
770 SPDIFRX_CR_DRFMT_MASK,
771 SPDIFRX_CR_DRFMTSET(fmt));
772}
773
774static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
775 struct snd_soc_dai *cpu_dai)
776{
777 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
778 int ret = 0;
779
780 switch (cmd) {
781 case SNDRV_PCM_TRIGGER_START:
782 case SNDRV_PCM_TRIGGER_RESUME:
783 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
784 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
785 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
786
787 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
788 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
789
790 ret = stm32_spdifrx_start_sync(spdifrx);
791 break;
792 case SNDRV_PCM_TRIGGER_SUSPEND:
793 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
794 case SNDRV_PCM_TRIGGER_STOP:
795 stm32_spdifrx_stop(spdifrx);
796 break;
797 default:
798 return -EINVAL;
799 }
800
801 return ret;
802}
803
804static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
805 struct snd_soc_dai *cpu_dai)
806{
807 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
808
809 spdifrx->substream = NULL;
810 clk_disable_unprepare(spdifrx->kclk);
811}
812
813static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
814 .startup = stm32_spdifrx_startup,
815 .hw_params = stm32_spdifrx_hw_params,
816 .trigger = stm32_spdifrx_trigger,
817 .shutdown = stm32_spdifrx_shutdown,
818};
819
820static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
821 {
822 .probe = stm32_spdifrx_dai_probe,
823 .capture = {
824 .stream_name = "CPU-Capture",
825 .channels_min = 1,
826 .channels_max = 2,
827 .rates = SNDRV_PCM_RATE_8000_192000,
828 .formats = SNDRV_PCM_FMTBIT_S32_LE |
829 SNDRV_PCM_FMTBIT_S16_LE,
830 },
831 .ops = &stm32_spdifrx_pcm_dai_ops,
832 }
833};
834
835static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
836 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
837 .buffer_bytes_max = 8 * PAGE_SIZE,
838 .period_bytes_max = 2048, /* MDMA constraint */
839 .periods_min = 2,
840 .periods_max = 8,
841};
842
843static const struct snd_soc_component_driver stm32_spdifrx_component = {
844 .name = "stm32-spdifrx",
845};
846
847static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
848 .pcm_hardware = &stm32_spdifrx_pcm_hw,
849 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
850};
851
852static const struct of_device_id stm32_spdifrx_ids[] = {
853 {
854 .compatible = "st,stm32h7-spdifrx",
855 .data = &stm32_h7_spdifrx_regmap_conf
856 },
857 {}
858};
859
860static int stm32_spdifrx_parse_of(struct platform_device *pdev,
861 struct stm32_spdifrx_data *spdifrx)
862{
863 struct device_node *np = pdev->dev.of_node;
864 const struct of_device_id *of_id;
865 struct resource *res;
866
867 if (!np)
868 return -ENODEV;
869
870 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
871 if (of_id)
872 spdifrx->regmap_conf =
873 (const struct regmap_config *)of_id->data;
874 else
875 return -EINVAL;
876
877 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
878 spdifrx->base = devm_ioremap_resource(&pdev->dev, res);
879 if (IS_ERR(spdifrx->base))
880 return PTR_ERR(spdifrx->base);
881
882 spdifrx->phys_addr = res->start;
883
884 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
885 if (IS_ERR(spdifrx->kclk)) {
886 dev_err(&pdev->dev, "Could not get kclk\n");
887 return PTR_ERR(spdifrx->kclk);
888 }
889
890 spdifrx->irq = platform_get_irq(pdev, 0);
891 if (spdifrx->irq < 0) {
892 dev_err(&pdev->dev, "No irq for node %s\n", pdev->name);
893 return spdifrx->irq;
894 }
895
896 return 0;
897}
898
899static int stm32_spdifrx_probe(struct platform_device *pdev)
900{
901 struct stm32_spdifrx_data *spdifrx;
902 struct reset_control *rst;
903 const struct snd_dmaengine_pcm_config *pcm_config = NULL;
904 int ret;
905
906 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
907 if (!spdifrx)
908 return -ENOMEM;
909
910 spdifrx->pdev = pdev;
911 init_completion(&spdifrx->cs_completion);
912 spin_lock_init(&spdifrx->lock);
913
914 platform_set_drvdata(pdev, spdifrx);
915
916 ret = stm32_spdifrx_parse_of(pdev, spdifrx);
917 if (ret)
918 return ret;
919
920 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
921 spdifrx->base,
922 spdifrx->regmap_conf);
923 if (IS_ERR(spdifrx->regmap)) {
924 dev_err(&pdev->dev, "Regmap init failed\n");
925 return PTR_ERR(spdifrx->regmap);
926 }
927
928 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
929 dev_name(&pdev->dev), spdifrx);
930 if (ret) {
931 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
932 return ret;
933 }
934
935 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
936 if (!IS_ERR(rst)) {
937 reset_control_assert(rst);
938 udelay(2);
939 reset_control_deassert(rst);
940 }
941
942 ret = devm_snd_soc_register_component(&pdev->dev,
943 &stm32_spdifrx_component,
944 stm32_spdifrx_dai,
945 ARRAY_SIZE(stm32_spdifrx_dai));
946 if (ret)
947 return ret;
948
949 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
950 if (ret)
951 goto error;
952
953 pcm_config = &stm32_spdifrx_pcm_config;
954 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
955 if (ret) {
956 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret);
957 goto error;
958 }
959
960 return 0;
961
962error:
963 if (!IS_ERR(spdifrx->ctrl_chan))
964 dma_release_channel(spdifrx->ctrl_chan);
965 if (spdifrx->dmab)
966 snd_dma_free_pages(spdifrx->dmab);
967
968 return ret;
969}
970
971static int stm32_spdifrx_remove(struct platform_device *pdev)
972{
973 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
974
975 if (spdifrx->ctrl_chan)
976 dma_release_channel(spdifrx->ctrl_chan);
977
978 if (spdifrx->dmab)
979 snd_dma_free_pages(spdifrx->dmab);
980
981 return 0;
982}
983
984MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
985
986static struct platform_driver stm32_spdifrx_driver = {
987 .driver = {
988 .name = "st,stm32-spdifrx",
989 .of_match_table = stm32_spdifrx_ids,
990 },
991 .probe = stm32_spdifrx_probe,
992 .remove = stm32_spdifrx_remove,
993};
994
995module_platform_driver(stm32_spdifrx_driver);
996
997MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
998MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
999MODULE_ALIAS("platform:stm32-spdifrx");
1000MODULE_LICENSE("GPL v2");