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1// SPDX-License-Identifier: MIT
2
3/*
4 * Copyright © 2019 Intel Corporation
5 */
6
7#include <linux/seq_file.h>
8
9#include "debugfs_gt.h"
10#include "debugfs_gt_pm.h"
11#include "i915_drv.h"
12#include "intel_gt.h"
13#include "intel_gt_clock_utils.h"
14#include "intel_gt_pm.h"
15#include "intel_llc.h"
16#include "intel_rc6.h"
17#include "intel_rps.h"
18#include "intel_runtime_pm.h"
19#include "intel_sideband.h"
20#include "intel_uncore.h"
21
22static int fw_domains_show(struct seq_file *m, void *data)
23{
24 struct intel_gt *gt = m->private;
25 struct intel_uncore *uncore = gt->uncore;
26 struct intel_uncore_forcewake_domain *fw_domain;
27 unsigned int tmp;
28
29 seq_printf(m, "user.bypass_count = %u\n",
30 uncore->user_forcewake_count);
31
32 for_each_fw_domain(fw_domain, uncore, tmp)
33 seq_printf(m, "%s.wake_count = %u\n",
34 intel_uncore_forcewake_domain_to_str(fw_domain->id),
35 READ_ONCE(fw_domain->wake_count));
36
37 return 0;
38}
39DEFINE_GT_DEBUGFS_ATTRIBUTE(fw_domains);
40
41static void print_rc6_res(struct seq_file *m,
42 const char *title,
43 const i915_reg_t reg)
44{
45 struct intel_gt *gt = m->private;
46 intel_wakeref_t wakeref;
47
48 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
49 seq_printf(m, "%s %u (%llu us)\n", title,
50 intel_uncore_read(gt->uncore, reg),
51 intel_rc6_residency_us(>->rc6, reg));
52}
53
54static int vlv_drpc(struct seq_file *m)
55{
56 struct intel_gt *gt = m->private;
57 struct intel_uncore *uncore = gt->uncore;
58 u32 rcctl1, pw_status;
59
60 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
61 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
62
63 seq_printf(m, "RC6 Enabled: %s\n",
64 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
65 GEN6_RC_CTL_EI_MODE(1))));
66 seq_printf(m, "Render Power Well: %s\n",
67 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
68 seq_printf(m, "Media Power Well: %s\n",
69 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
70
71 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
72 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
73
74 return fw_domains_show(m, NULL);
75}
76
77static int gen6_drpc(struct seq_file *m)
78{
79 struct intel_gt *gt = m->private;
80 struct drm_i915_private *i915 = gt->i915;
81 struct intel_uncore *uncore = gt->uncore;
82 u32 gt_core_status, rcctl1, rc6vids = 0;
83 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
84
85 gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
86
87 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
88 if (GRAPHICS_VER(i915) >= 9) {
89 gen9_powergate_enable =
90 intel_uncore_read(uncore, GEN9_PG_ENABLE);
91 gen9_powergate_status =
92 intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
93 }
94
95 if (GRAPHICS_VER(i915) <= 7)
96 sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
97 &rc6vids, NULL);
98
99 seq_printf(m, "RC1e Enabled: %s\n",
100 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
101 seq_printf(m, "RC6 Enabled: %s\n",
102 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
103 if (GRAPHICS_VER(i915) >= 9) {
104 seq_printf(m, "Render Well Gating Enabled: %s\n",
105 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
106 seq_printf(m, "Media Well Gating Enabled: %s\n",
107 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
108 }
109 seq_printf(m, "Deep RC6 Enabled: %s\n",
110 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
111 seq_printf(m, "Deepest RC6 Enabled: %s\n",
112 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
113 seq_puts(m, "Current RC state: ");
114 switch (gt_core_status & GEN6_RCn_MASK) {
115 case GEN6_RC0:
116 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
117 seq_puts(m, "Core Power Down\n");
118 else
119 seq_puts(m, "on\n");
120 break;
121 case GEN6_RC3:
122 seq_puts(m, "RC3\n");
123 break;
124 case GEN6_RC6:
125 seq_puts(m, "RC6\n");
126 break;
127 case GEN6_RC7:
128 seq_puts(m, "RC7\n");
129 break;
130 default:
131 seq_puts(m, "Unknown\n");
132 break;
133 }
134
135 seq_printf(m, "Core Power Down: %s\n",
136 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
137 if (GRAPHICS_VER(i915) >= 9) {
138 seq_printf(m, "Render Power Well: %s\n",
139 (gen9_powergate_status &
140 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
141 seq_printf(m, "Media Power Well: %s\n",
142 (gen9_powergate_status &
143 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
144 }
145
146 /* Not exactly sure what this is */
147 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
148 GEN6_GT_GFX_RC6_LOCKED);
149 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
150 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
151 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
152
153 if (GRAPHICS_VER(i915) <= 7) {
154 seq_printf(m, "RC6 voltage: %dmV\n",
155 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
156 seq_printf(m, "RC6+ voltage: %dmV\n",
157 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
158 seq_printf(m, "RC6++ voltage: %dmV\n",
159 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
160 }
161
162 return fw_domains_show(m, NULL);
163}
164
165static int ilk_drpc(struct seq_file *m)
166{
167 struct intel_gt *gt = m->private;
168 struct intel_uncore *uncore = gt->uncore;
169 u32 rgvmodectl, rstdbyctl;
170 u16 crstandvid;
171
172 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
173 rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL);
174 crstandvid = intel_uncore_read16(uncore, CRSTANDVID);
175
176 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
177 seq_printf(m, "Boost freq: %d\n",
178 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
179 MEMMODE_BOOST_FREQ_SHIFT);
180 seq_printf(m, "HW control enabled: %s\n",
181 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
182 seq_printf(m, "SW control enabled: %s\n",
183 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
184 seq_printf(m, "Gated voltage change: %s\n",
185 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
186 seq_printf(m, "Starting frequency: P%d\n",
187 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
188 seq_printf(m, "Max P-state: P%d\n",
189 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
190 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
191 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
192 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
193 seq_printf(m, "Render standby enabled: %s\n",
194 yesno(!(rstdbyctl & RCX_SW_EXIT)));
195 seq_puts(m, "Current RS state: ");
196 switch (rstdbyctl & RSX_STATUS_MASK) {
197 case RSX_STATUS_ON:
198 seq_puts(m, "on\n");
199 break;
200 case RSX_STATUS_RC1:
201 seq_puts(m, "RC1\n");
202 break;
203 case RSX_STATUS_RC1E:
204 seq_puts(m, "RC1E\n");
205 break;
206 case RSX_STATUS_RS1:
207 seq_puts(m, "RS1\n");
208 break;
209 case RSX_STATUS_RS2:
210 seq_puts(m, "RS2 (RC6)\n");
211 break;
212 case RSX_STATUS_RS3:
213 seq_puts(m, "RC3 (RC6+)\n");
214 break;
215 default:
216 seq_puts(m, "unknown\n");
217 break;
218 }
219
220 return 0;
221}
222
223static int drpc_show(struct seq_file *m, void *unused)
224{
225 struct intel_gt *gt = m->private;
226 struct drm_i915_private *i915 = gt->i915;
227 intel_wakeref_t wakeref;
228 int err = -ENODEV;
229
230 with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
231 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
232 err = vlv_drpc(m);
233 else if (GRAPHICS_VER(i915) >= 6)
234 err = gen6_drpc(m);
235 else
236 err = ilk_drpc(m);
237 }
238
239 return err;
240}
241DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc);
242
243static int frequency_show(struct seq_file *m, void *unused)
244{
245 struct intel_gt *gt = m->private;
246 struct drm_i915_private *i915 = gt->i915;
247 struct intel_uncore *uncore = gt->uncore;
248 struct intel_rps *rps = >->rps;
249 intel_wakeref_t wakeref;
250
251 wakeref = intel_runtime_pm_get(uncore->rpm);
252
253 if (GRAPHICS_VER(i915) == 5) {
254 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
255 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
256
257 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
258 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
259 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
260 MEMSTAT_VID_SHIFT);
261 seq_printf(m, "Current P-state: %d\n",
262 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
263 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
264 u32 rpmodectl, freq_sts;
265
266 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
267 seq_printf(m, "Video Turbo Mode: %s\n",
268 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
269 seq_printf(m, "HW control enabled: %s\n",
270 yesno(rpmodectl & GEN6_RP_ENABLE));
271 seq_printf(m, "SW control enabled: %s\n",
272 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
273 GEN6_RP_MEDIA_SW_MODE));
274
275 vlv_punit_get(i915);
276 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
277 vlv_punit_put(i915);
278
279 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
280 seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq);
281
282 seq_printf(m, "actual GPU freq: %d MHz\n",
283 intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
284
285 seq_printf(m, "current GPU freq: %d MHz\n",
286 intel_gpu_freq(rps, rps->cur_freq));
287
288 seq_printf(m, "max GPU freq: %d MHz\n",
289 intel_gpu_freq(rps, rps->max_freq));
290
291 seq_printf(m, "min GPU freq: %d MHz\n",
292 intel_gpu_freq(rps, rps->min_freq));
293
294 seq_printf(m, "idle GPU freq: %d MHz\n",
295 intel_gpu_freq(rps, rps->idle_freq));
296
297 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
298 intel_gpu_freq(rps, rps->efficient_freq));
299 } else if (GRAPHICS_VER(i915) >= 6) {
300 u32 rp_state_limits;
301 u32 gt_perf_status;
302 u32 rp_state_cap;
303 u32 rpmodectl, rpinclimit, rpdeclimit;
304 u32 rpstat, cagf, reqf;
305 u32 rpcurupei, rpcurup, rpprevup;
306 u32 rpcurdownei, rpcurdown, rpprevdown;
307 u32 rpupei, rpupt, rpdownei, rpdownt;
308 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
309 int max_freq;
310
311 rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
312 if (IS_GEN9_LP(i915)) {
313 rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
314 gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
315 } else {
316 rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
317 gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
318 }
319
320 /* RPSTAT1 is in the GT power well */
321 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
322
323 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
324 if (GRAPHICS_VER(i915) >= 9) {
325 reqf >>= 23;
326 } else {
327 reqf &= ~GEN6_TURBO_DISABLE;
328 if (IS_HASWELL(i915) || IS_BROADWELL(i915))
329 reqf >>= 24;
330 else
331 reqf >>= 25;
332 }
333 reqf = intel_gpu_freq(rps, reqf);
334
335 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
336 rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
337 rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
338
339 rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
340 rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
341 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
342 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
343 rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
344 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
345 rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
346
347 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
348 rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
349
350 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
351 rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
352
353 cagf = intel_rps_read_actual_frequency(rps);
354
355 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
356
357 if (GRAPHICS_VER(i915) >= 11) {
358 pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
359 pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
360 /*
361 * The equivalent to the PM ISR & IIR cannot be read
362 * without affecting the current state of the system
363 */
364 pm_isr = 0;
365 pm_iir = 0;
366 } else if (GRAPHICS_VER(i915) >= 8) {
367 pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
368 pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
369 pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
370 pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
371 } else {
372 pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
373 pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
374 pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
375 pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
376 }
377 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
378
379 seq_printf(m, "Video Turbo Mode: %s\n",
380 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
381 seq_printf(m, "HW control enabled: %s\n",
382 yesno(rpmodectl & GEN6_RP_ENABLE));
383 seq_printf(m, "SW control enabled: %s\n",
384 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
385 GEN6_RP_MEDIA_SW_MODE));
386
387 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
388 pm_ier, pm_imr, pm_mask);
389 if (GRAPHICS_VER(i915) <= 10)
390 seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
391 pm_isr, pm_iir);
392 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
393 rps->pm_intrmsk_mbz);
394 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
395 seq_printf(m, "Render p-state ratio: %d\n",
396 (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
397 seq_printf(m, "Render p-state VID: %d\n",
398 gt_perf_status & 0xff);
399 seq_printf(m, "Render p-state limit: %d\n",
400 rp_state_limits & 0xff);
401 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
402 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
403 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
404 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
405 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
406 seq_printf(m, "CAGF: %dMHz\n", cagf);
407 seq_printf(m, "RP CUR UP EI: %d (%lldns)\n",
408 rpcurupei,
409 intel_gt_pm_interval_to_ns(gt, rpcurupei));
410 seq_printf(m, "RP CUR UP: %d (%lldns)\n",
411 rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
412 seq_printf(m, "RP PREV UP: %d (%lldns)\n",
413 rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
414 seq_printf(m, "Up threshold: %d%%\n",
415 rps->power.up_threshold);
416 seq_printf(m, "RP UP EI: %d (%lldns)\n",
417 rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
418 seq_printf(m, "RP UP THRESHOLD: %d (%lldns)\n",
419 rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
420
421 seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n",
422 rpcurdownei,
423 intel_gt_pm_interval_to_ns(gt, rpcurdownei));
424 seq_printf(m, "RP CUR DOWN: %d (%lldns)\n",
425 rpcurdown,
426 intel_gt_pm_interval_to_ns(gt, rpcurdown));
427 seq_printf(m, "RP PREV DOWN: %d (%lldns)\n",
428 rpprevdown,
429 intel_gt_pm_interval_to_ns(gt, rpprevdown));
430 seq_printf(m, "Down threshold: %d%%\n",
431 rps->power.down_threshold);
432 seq_printf(m, "RP DOWN EI: %d (%lldns)\n",
433 rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
434 seq_printf(m, "RP DOWN THRESHOLD: %d (%lldns)\n",
435 rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
436
437 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
438 rp_state_cap >> 16) & 0xff;
439 max_freq *= (IS_GEN9_BC(i915) ||
440 GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
441 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
442 intel_gpu_freq(rps, max_freq));
443
444 max_freq = (rp_state_cap & 0xff00) >> 8;
445 max_freq *= (IS_GEN9_BC(i915) ||
446 GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
447 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
448 intel_gpu_freq(rps, max_freq));
449
450 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
451 rp_state_cap >> 0) & 0xff;
452 max_freq *= (IS_GEN9_BC(i915) ||
453 GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
454 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
455 intel_gpu_freq(rps, max_freq));
456 seq_printf(m, "Max overclocked frequency: %dMHz\n",
457 intel_gpu_freq(rps, rps->max_freq));
458
459 seq_printf(m, "Current freq: %d MHz\n",
460 intel_gpu_freq(rps, rps->cur_freq));
461 seq_printf(m, "Actual freq: %d MHz\n", cagf);
462 seq_printf(m, "Idle freq: %d MHz\n",
463 intel_gpu_freq(rps, rps->idle_freq));
464 seq_printf(m, "Min freq: %d MHz\n",
465 intel_gpu_freq(rps, rps->min_freq));
466 seq_printf(m, "Boost freq: %d MHz\n",
467 intel_gpu_freq(rps, rps->boost_freq));
468 seq_printf(m, "Max freq: %d MHz\n",
469 intel_gpu_freq(rps, rps->max_freq));
470 seq_printf(m,
471 "efficient (RPe) frequency: %d MHz\n",
472 intel_gpu_freq(rps, rps->efficient_freq));
473 } else {
474 seq_puts(m, "no P-state info available\n");
475 }
476
477 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
478 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);
479 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
480
481 intel_runtime_pm_put(uncore->rpm, wakeref);
482
483 return 0;
484}
485DEFINE_GT_DEBUGFS_ATTRIBUTE(frequency);
486
487static int llc_show(struct seq_file *m, void *data)
488{
489 struct intel_gt *gt = m->private;
490 struct drm_i915_private *i915 = gt->i915;
491 const bool edram = GRAPHICS_VER(i915) > 8;
492 struct intel_rps *rps = >->rps;
493 unsigned int max_gpu_freq, min_gpu_freq;
494 intel_wakeref_t wakeref;
495 int gpu_freq, ia_freq;
496
497 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(i915)));
498 seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
499 i915->edram_size_mb);
500
501 min_gpu_freq = rps->min_freq;
502 max_gpu_freq = rps->max_freq;
503 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
504 /* Convert GT frequency to 50 HZ units */
505 min_gpu_freq /= GEN9_FREQ_SCALER;
506 max_gpu_freq /= GEN9_FREQ_SCALER;
507 }
508
509 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
510
511 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
512 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
513 ia_freq = gpu_freq;
514 sandybridge_pcode_read(i915,
515 GEN6_PCODE_READ_MIN_FREQ_TABLE,
516 &ia_freq, NULL);
517 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
518 intel_gpu_freq(rps,
519 (gpu_freq *
520 (IS_GEN9_BC(i915) ||
521 GRAPHICS_VER(i915) >= 10 ?
522 GEN9_FREQ_SCALER : 1))),
523 ((ia_freq >> 0) & 0xff) * 100,
524 ((ia_freq >> 8) & 0xff) * 100);
525 }
526 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
527
528 return 0;
529}
530
531static bool llc_eval(void *data)
532{
533 struct intel_gt *gt = data;
534
535 return HAS_LLC(gt->i915);
536}
537
538DEFINE_GT_DEBUGFS_ATTRIBUTE(llc);
539
540static const char *rps_power_to_str(unsigned int power)
541{
542 static const char * const strings[] = {
543 [LOW_POWER] = "low power",
544 [BETWEEN] = "mixed",
545 [HIGH_POWER] = "high power",
546 };
547
548 if (power >= ARRAY_SIZE(strings) || !strings[power])
549 return "unknown";
550
551 return strings[power];
552}
553
554static int rps_boost_show(struct seq_file *m, void *data)
555{
556 struct intel_gt *gt = m->private;
557 struct drm_i915_private *i915 = gt->i915;
558 struct intel_rps *rps = >->rps;
559
560 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
561 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
562 seq_printf(m, "GPU busy? %s, %llums\n",
563 yesno(gt->awake),
564 ktime_to_ms(intel_gt_get_awake_time(gt)));
565 seq_printf(m, "Boosts outstanding? %d\n",
566 atomic_read(&rps->num_waiters));
567 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
568 seq_printf(m, "Frequency requested %d, actual %d\n",
569 intel_gpu_freq(rps, rps->cur_freq),
570 intel_rps_read_actual_frequency(rps));
571 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
572 intel_gpu_freq(rps, rps->min_freq),
573 intel_gpu_freq(rps, rps->min_freq_softlimit),
574 intel_gpu_freq(rps, rps->max_freq_softlimit),
575 intel_gpu_freq(rps, rps->max_freq));
576 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
577 intel_gpu_freq(rps, rps->idle_freq),
578 intel_gpu_freq(rps, rps->efficient_freq),
579 intel_gpu_freq(rps, rps->boost_freq));
580
581 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
582
583 if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
584 struct intel_uncore *uncore = gt->uncore;
585 u32 rpup, rpupei;
586 u32 rpdown, rpdownei;
587
588 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
589 rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
590 rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
591 rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
592 rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
593 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
594
595 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
596 rps_power_to_str(rps->power.mode));
597 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
598 rpup && rpupei ? 100 * rpup / rpupei : 0,
599 rps->power.up_threshold);
600 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
601 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
602 rps->power.down_threshold);
603 } else {
604 seq_puts(m, "\nRPS Autotuning inactive\n");
605 }
606
607 return 0;
608}
609
610static bool rps_eval(void *data)
611{
612 struct intel_gt *gt = data;
613
614 return HAS_RPS(gt->i915);
615}
616
617DEFINE_GT_DEBUGFS_ATTRIBUTE(rps_boost);
618
619void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root)
620{
621 static const struct debugfs_gt_file files[] = {
622 { "drpc", &drpc_fops, NULL },
623 { "frequency", &frequency_fops, NULL },
624 { "forcewake", &fw_domains_fops, NULL },
625 { "llc", &llc_fops, llc_eval },
626 { "rps_boost", &rps_boost_fops, rps_eval },
627 };
628
629 intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
630}