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1/*
2 * Copyright © 2008 Intel Corporation
3 * 2014 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26#include <drm/drm_atomic.h>
27#include <drm/drm_atomic_helper.h>
28#include <drm/drm_edid.h>
29#include <drm/drm_probe_helper.h>
30
31#include "i915_drv.h"
32#include "intel_atomic.h"
33#include "intel_audio.h"
34#include "intel_connector.h"
35#include "intel_crtc.h"
36#include "intel_ddi.h"
37#include "intel_de.h"
38#include "intel_display_types.h"
39#include "intel_dp.h"
40#include "intel_dp_hdcp.h"
41#include "intel_dp_mst.h"
42#include "intel_dpio_phy.h"
43#include "intel_hdcp.h"
44#include "intel_hotplug.h"
45#include "skl_scaler.h"
46
47static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
48 struct intel_crtc_state *crtc_state,
49 struct drm_connector_state *conn_state,
50 struct link_config_limits *limits)
51{
52 struct drm_atomic_state *state = crtc_state->uapi.state;
53 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
54 struct intel_dp *intel_dp = &intel_mst->primary->dp;
55 struct intel_connector *connector =
56 to_intel_connector(conn_state->connector);
57 struct drm_i915_private *i915 = to_i915(connector->base.dev);
58 const struct drm_display_mode *adjusted_mode =
59 &crtc_state->hw.adjusted_mode;
60 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
61 int bpp, slots = -EINVAL;
62
63 crtc_state->lane_count = limits->max_lane_count;
64 crtc_state->port_clock = limits->max_clock;
65
66 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
67 crtc_state->pipe_bpp = bpp;
68
69 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
70 crtc_state->pipe_bpp,
71 false);
72
73 slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
74 connector->port,
75 crtc_state->pbn,
76 drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
77 crtc_state->port_clock,
78 crtc_state->lane_count));
79 if (slots == -EDEADLK)
80 return slots;
81 if (slots >= 0)
82 break;
83 }
84
85 if (slots < 0) {
86 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
87 slots);
88 return slots;
89 }
90
91 intel_link_compute_m_n(crtc_state->pipe_bpp,
92 crtc_state->lane_count,
93 adjusted_mode->crtc_clock,
94 crtc_state->port_clock,
95 &crtc_state->dp_m_n,
96 constant_n, crtc_state->fec_enable);
97 crtc_state->dp_m_n.tu = slots;
98
99 return 0;
100}
101
102static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
103 struct intel_crtc_state *pipe_config,
104 struct drm_connector_state *conn_state)
105{
106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
107 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
108 struct intel_dp *intel_dp = &intel_mst->primary->dp;
109 struct intel_connector *connector =
110 to_intel_connector(conn_state->connector);
111 struct intel_digital_connector_state *intel_conn_state =
112 to_intel_digital_connector_state(conn_state);
113 const struct drm_display_mode *adjusted_mode =
114 &pipe_config->hw.adjusted_mode;
115 struct link_config_limits limits;
116 int ret;
117
118 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
119 return -EINVAL;
120
121 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
122 pipe_config->has_pch_encoder = false;
123
124 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
125 pipe_config->has_audio = connector->port->has_audio;
126 else
127 pipe_config->has_audio =
128 intel_conn_state->force_audio == HDMI_AUDIO_ON;
129
130 /*
131 * for MST we always configure max link bw - the spec doesn't
132 * seem to suggest we should do otherwise.
133 */
134 limits.min_clock =
135 limits.max_clock = intel_dp_max_link_rate(intel_dp);
136
137 limits.min_lane_count =
138 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
139
140 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
141 /*
142 * FIXME: If all the streams can't fit into the link with
143 * their current pipe_bpp we should reduce pipe_bpp across
144 * the board until things start to fit. Until then we
145 * limit to <= 8bpc since that's what was hardcoded for all
146 * MST streams previously. This hack should be removed once
147 * we have the proper retry logic in place.
148 */
149 limits.max_bpp = min(pipe_config->pipe_bpp, 24);
150
151 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
152
153 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
154 conn_state, &limits);
155 if (ret)
156 return ret;
157
158 pipe_config->limited_color_range =
159 intel_dp_limited_color_range(pipe_config, conn_state);
160
161 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
162 pipe_config->lane_lat_optim_mask =
163 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
164
165 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
166
167 return 0;
168}
169
170/*
171 * Iterate over all connectors and return a mask of
172 * all CPU transcoders streaming over the same DP link.
173 */
174static unsigned int
175intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
176 struct intel_dp *mst_port)
177{
178 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
179 const struct intel_digital_connector_state *conn_state;
180 struct intel_connector *connector;
181 u8 transcoders = 0;
182 int i;
183
184 if (DISPLAY_VER(dev_priv) < 12)
185 return 0;
186
187 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
188 const struct intel_crtc_state *crtc_state;
189 struct intel_crtc *crtc;
190
191 if (connector->mst_port != mst_port || !conn_state->base.crtc)
192 continue;
193
194 crtc = to_intel_crtc(conn_state->base.crtc);
195 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
196
197 if (!crtc_state->hw.active)
198 continue;
199
200 transcoders |= BIT(crtc_state->cpu_transcoder);
201 }
202
203 return transcoders;
204}
205
206static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
207 struct intel_crtc_state *crtc_state,
208 struct drm_connector_state *conn_state)
209{
210 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
211 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
212 struct intel_dp *intel_dp = &intel_mst->primary->dp;
213
214 /* lowest numbered transcoder will be designated master */
215 crtc_state->mst_master_transcoder =
216 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
217
218 return 0;
219}
220
221/*
222 * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
223 * that shares the same MST stream as mode changed,
224 * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
225 * a fastset when possible.
226 */
227static int
228intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
229 struct intel_atomic_state *state)
230{
231 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
232 struct drm_connector_list_iter connector_list_iter;
233 struct intel_connector *connector_iter;
234
235 if (DISPLAY_VER(dev_priv) < 12)
236 return 0;
237
238 if (!intel_connector_needs_modeset(state, &connector->base))
239 return 0;
240
241 drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
242 for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
243 struct intel_digital_connector_state *conn_iter_state;
244 struct intel_crtc_state *crtc_state;
245 struct intel_crtc *crtc;
246 int ret;
247
248 if (connector_iter->mst_port != connector->mst_port ||
249 connector_iter == connector)
250 continue;
251
252 conn_iter_state = intel_atomic_get_digital_connector_state(state,
253 connector_iter);
254 if (IS_ERR(conn_iter_state)) {
255 drm_connector_list_iter_end(&connector_list_iter);
256 return PTR_ERR(conn_iter_state);
257 }
258
259 if (!conn_iter_state->base.crtc)
260 continue;
261
262 crtc = to_intel_crtc(conn_iter_state->base.crtc);
263 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
264 if (IS_ERR(crtc_state)) {
265 drm_connector_list_iter_end(&connector_list_iter);
266 return PTR_ERR(crtc_state);
267 }
268
269 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
270 if (ret) {
271 drm_connector_list_iter_end(&connector_list_iter);
272 return ret;
273 }
274 crtc_state->uapi.mode_changed = true;
275 }
276 drm_connector_list_iter_end(&connector_list_iter);
277
278 return 0;
279}
280
281static int
282intel_dp_mst_atomic_check(struct drm_connector *connector,
283 struct drm_atomic_state *_state)
284{
285 struct intel_atomic_state *state = to_intel_atomic_state(_state);
286 struct drm_connector_state *new_conn_state =
287 drm_atomic_get_new_connector_state(&state->base, connector);
288 struct drm_connector_state *old_conn_state =
289 drm_atomic_get_old_connector_state(&state->base, connector);
290 struct intel_connector *intel_connector =
291 to_intel_connector(connector);
292 struct drm_crtc *new_crtc = new_conn_state->crtc;
293 struct drm_dp_mst_topology_mgr *mgr;
294 int ret;
295
296 ret = intel_digital_connector_atomic_check(connector, &state->base);
297 if (ret)
298 return ret;
299
300 ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state);
301 if (ret)
302 return ret;
303
304 if (!old_conn_state->crtc)
305 return 0;
306
307 /* We only want to free VCPI if this state disables the CRTC on this
308 * connector
309 */
310 if (new_crtc) {
311 struct intel_crtc *intel_crtc = to_intel_crtc(new_crtc);
312 struct intel_crtc_state *crtc_state =
313 intel_atomic_get_new_crtc_state(state, intel_crtc);
314
315 if (!crtc_state ||
316 !drm_atomic_crtc_needs_modeset(&crtc_state->uapi) ||
317 crtc_state->uapi.enable)
318 return 0;
319 }
320
321 mgr = &enc_to_mst(to_intel_encoder(old_conn_state->best_encoder))->primary->dp.mst_mgr;
322 ret = drm_dp_atomic_release_vcpi_slots(&state->base, mgr,
323 intel_connector->port);
324
325 return ret;
326}
327
328static void clear_act_sent(struct intel_encoder *encoder,
329 const struct intel_crtc_state *crtc_state)
330{
331 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
332
333 intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
334 DP_TP_STATUS_ACT_SENT);
335}
336
337static void wait_for_act_sent(struct intel_encoder *encoder,
338 const struct intel_crtc_state *crtc_state)
339{
340 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
341 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
342 struct intel_dp *intel_dp = &intel_mst->primary->dp;
343
344 if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
345 DP_TP_STATUS_ACT_SENT, 1))
346 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
347
348 drm_dp_check_act_status(&intel_dp->mst_mgr);
349}
350
351static void intel_mst_disable_dp(struct intel_atomic_state *state,
352 struct intel_encoder *encoder,
353 const struct intel_crtc_state *old_crtc_state,
354 const struct drm_connector_state *old_conn_state)
355{
356 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
357 struct intel_digital_port *dig_port = intel_mst->primary;
358 struct intel_dp *intel_dp = &dig_port->dp;
359 struct intel_connector *connector =
360 to_intel_connector(old_conn_state->connector);
361 struct drm_i915_private *i915 = to_i915(connector->base.dev);
362 int ret;
363
364 drm_dbg_kms(&i915->drm, "active links %d\n",
365 intel_dp->active_mst_links);
366
367 intel_hdcp_disable(intel_mst->connector);
368
369 drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port);
370
371 ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
372 if (ret) {
373 drm_dbg_kms(&i915->drm, "failed to update payload %d\n", ret);
374 }
375 if (old_crtc_state->has_audio)
376 intel_audio_codec_disable(encoder,
377 old_crtc_state, old_conn_state);
378}
379
380static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
381 struct intel_encoder *encoder,
382 const struct intel_crtc_state *old_crtc_state,
383 const struct drm_connector_state *old_conn_state)
384{
385 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
386 struct intel_digital_port *dig_port = intel_mst->primary;
387 struct intel_dp *intel_dp = &dig_port->dp;
388 struct intel_connector *connector =
389 to_intel_connector(old_conn_state->connector);
390 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
391 bool last_mst_stream;
392 u32 val;
393
394 intel_dp->active_mst_links--;
395 last_mst_stream = intel_dp->active_mst_links == 0;
396 drm_WARN_ON(&dev_priv->drm,
397 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
398 !intel_dp_mst_is_master_trans(old_crtc_state));
399
400 intel_crtc_vblank_off(old_crtc_state);
401
402 intel_disable_pipe(old_crtc_state);
403
404 drm_dp_update_payload_part2(&intel_dp->mst_mgr);
405
406 clear_act_sent(encoder, old_crtc_state);
407
408 val = intel_de_read(dev_priv,
409 TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder));
410 val &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
411 intel_de_write(dev_priv,
412 TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
413 val);
414
415 wait_for_act_sent(encoder, old_crtc_state);
416
417 drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port);
418
419 intel_ddi_disable_transcoder_func(old_crtc_state);
420
421 if (DISPLAY_VER(dev_priv) >= 9)
422 skl_scaler_disable(old_crtc_state);
423 else
424 ilk_pfit_disable(old_crtc_state);
425
426 /*
427 * Power down mst path before disabling the port, otherwise we end
428 * up getting interrupts from the sink upon detecting link loss.
429 */
430 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
431 false);
432
433 /*
434 * BSpec 4287: disable DIP after the transcoder is disabled and before
435 * the transcoder clock select is set to none.
436 */
437 if (last_mst_stream)
438 intel_dp_set_infoframes(&dig_port->base, false,
439 old_crtc_state, NULL);
440 /*
441 * From TGL spec: "If multi-stream slave transcoder: Configure
442 * Transcoder Clock Select to direct no clock to the transcoder"
443 *
444 * From older GENs spec: "Configure Transcoder Clock Select to direct
445 * no clock to the transcoder"
446 */
447 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
448 intel_ddi_disable_pipe_clock(old_crtc_state);
449
450
451 intel_mst->connector = NULL;
452 if (last_mst_stream)
453 dig_port->base.post_disable(state, &dig_port->base,
454 old_crtc_state, NULL);
455
456 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
457 intel_dp->active_mst_links);
458}
459
460static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
461 struct intel_encoder *encoder,
462 const struct intel_crtc_state *pipe_config,
463 const struct drm_connector_state *conn_state)
464{
465 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
466 struct intel_digital_port *dig_port = intel_mst->primary;
467 struct intel_dp *intel_dp = &dig_port->dp;
468
469 if (intel_dp->active_mst_links == 0)
470 dig_port->base.pre_pll_enable(state, &dig_port->base,
471 pipe_config, NULL);
472}
473
474static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
475 struct intel_encoder *encoder,
476 const struct intel_crtc_state *pipe_config,
477 const struct drm_connector_state *conn_state)
478{
479 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
480 struct intel_digital_port *dig_port = intel_mst->primary;
481 struct intel_dp *intel_dp = &dig_port->dp;
482 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
483 struct intel_connector *connector =
484 to_intel_connector(conn_state->connector);
485 int ret;
486 bool first_mst_stream;
487
488 /* MST encoders are bound to a crtc, not to a connector,
489 * force the mapping here for get_hw_state.
490 */
491 connector->encoder = encoder;
492 intel_mst->connector = connector;
493 first_mst_stream = intel_dp->active_mst_links == 0;
494 drm_WARN_ON(&dev_priv->drm,
495 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
496 !intel_dp_mst_is_master_trans(pipe_config));
497
498 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
499 intel_dp->active_mst_links);
500
501 if (first_mst_stream)
502 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
503
504 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
505
506 if (first_mst_stream)
507 dig_port->base.pre_enable(state, &dig_port->base,
508 pipe_config, NULL);
509
510 ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr,
511 connector->port,
512 pipe_config->pbn,
513 pipe_config->dp_m_n.tu);
514 if (!ret)
515 drm_err(&dev_priv->drm, "failed to allocate vcpi\n");
516
517 intel_dp->active_mst_links++;
518
519 ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
520
521 /*
522 * Before Gen 12 this is not done as part of
523 * dig_port->base.pre_enable() and should be done here. For
524 * Gen 12+ the step in which this should be done is different for the
525 * first MST stream, so it's done on the DDI for the first stream and
526 * here for the following ones.
527 */
528 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
529 intel_ddi_enable_pipe_clock(encoder, pipe_config);
530
531 intel_ddi_set_dp_msa(pipe_config, conn_state);
532
533 intel_dp_set_m_n(pipe_config, M1_N1);
534}
535
536static void intel_mst_enable_dp(struct intel_atomic_state *state,
537 struct intel_encoder *encoder,
538 const struct intel_crtc_state *pipe_config,
539 const struct drm_connector_state *conn_state)
540{
541 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
542 struct intel_digital_port *dig_port = intel_mst->primary;
543 struct intel_dp *intel_dp = &dig_port->dp;
544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
545 u32 val;
546
547 drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
548
549 clear_act_sent(encoder, pipe_config);
550
551 intel_ddi_enable_transcoder_func(encoder, pipe_config);
552
553 val = intel_de_read(dev_priv,
554 TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
555 val |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
556 intel_de_write(dev_priv,
557 TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder),
558 val);
559
560 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
561 intel_dp->active_mst_links);
562
563 wait_for_act_sent(encoder, pipe_config);
564
565 drm_dp_update_payload_part2(&intel_dp->mst_mgr);
566
567 intel_enable_pipe(pipe_config);
568
569 intel_crtc_vblank_on(pipe_config);
570
571 if (pipe_config->has_audio)
572 intel_audio_codec_enable(encoder, pipe_config, conn_state);
573
574 /* Enable hdcp if it's desired */
575 if (conn_state->content_protection ==
576 DRM_MODE_CONTENT_PROTECTION_DESIRED)
577 intel_hdcp_enable(to_intel_connector(conn_state->connector),
578 pipe_config,
579 (u8)conn_state->hdcp_content_type);
580}
581
582static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
583 enum pipe *pipe)
584{
585 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
586 *pipe = intel_mst->pipe;
587 if (intel_mst->connector)
588 return true;
589 return false;
590}
591
592static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
593 struct intel_crtc_state *pipe_config)
594{
595 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
596 struct intel_digital_port *dig_port = intel_mst->primary;
597
598 dig_port->base.get_config(&dig_port->base, pipe_config);
599}
600
601static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
602 struct intel_crtc_state *crtc_state)
603{
604 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
605 struct intel_digital_port *dig_port = intel_mst->primary;
606
607 return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
608}
609
610static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
611{
612 struct intel_connector *intel_connector = to_intel_connector(connector);
613 struct intel_dp *intel_dp = intel_connector->mst_port;
614 struct edid *edid;
615 int ret;
616
617 if (drm_connector_is_unregistered(connector))
618 return intel_connector_update_modes(connector, NULL);
619
620 edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);
621 ret = intel_connector_update_modes(connector, edid);
622 kfree(edid);
623
624 return ret;
625}
626
627static int
628intel_dp_mst_connector_late_register(struct drm_connector *connector)
629{
630 struct intel_connector *intel_connector = to_intel_connector(connector);
631 int ret;
632
633 ret = drm_dp_mst_connector_late_register(connector,
634 intel_connector->port);
635 if (ret < 0)
636 return ret;
637
638 ret = intel_connector_register(connector);
639 if (ret < 0)
640 drm_dp_mst_connector_early_unregister(connector,
641 intel_connector->port);
642
643 return ret;
644}
645
646static void
647intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
648{
649 struct intel_connector *intel_connector = to_intel_connector(connector);
650
651 intel_connector_unregister(connector);
652 drm_dp_mst_connector_early_unregister(connector,
653 intel_connector->port);
654}
655
656static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
657 .fill_modes = drm_helper_probe_single_connector_modes,
658 .atomic_get_property = intel_digital_connector_atomic_get_property,
659 .atomic_set_property = intel_digital_connector_atomic_set_property,
660 .late_register = intel_dp_mst_connector_late_register,
661 .early_unregister = intel_dp_mst_connector_early_unregister,
662 .destroy = intel_connector_destroy,
663 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
664 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
665};
666
667static int intel_dp_mst_get_modes(struct drm_connector *connector)
668{
669 return intel_dp_mst_get_ddc_modes(connector);
670}
671
672static int
673intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
674 struct drm_display_mode *mode,
675 struct drm_modeset_acquire_ctx *ctx,
676 enum drm_mode_status *status)
677{
678 struct drm_i915_private *dev_priv = to_i915(connector->dev);
679 struct intel_connector *intel_connector = to_intel_connector(connector);
680 struct intel_dp *intel_dp = intel_connector->mst_port;
681 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
682 struct drm_dp_mst_port *port = intel_connector->port;
683 const int min_bpp = 18;
684 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
685 int max_rate, mode_rate, max_lanes, max_link_clock;
686 int ret;
687
688 if (drm_connector_is_unregistered(connector)) {
689 *status = MODE_ERROR;
690 return 0;
691 }
692
693 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
694 *status = MODE_NO_DBLESCAN;
695 return 0;
696 }
697
698 max_link_clock = intel_dp_max_link_rate(intel_dp);
699 max_lanes = intel_dp_max_lane_count(intel_dp);
700
701 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
702 mode_rate = intel_dp_link_required(mode->clock, min_bpp);
703
704 ret = drm_modeset_lock(&mgr->base.lock, ctx);
705 if (ret)
706 return ret;
707
708 if (mode_rate > max_rate || mode->clock > max_dotclk ||
709 drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
710 *status = MODE_CLOCK_HIGH;
711 return 0;
712 }
713
714 if (mode->clock < 10000) {
715 *status = MODE_CLOCK_LOW;
716 return 0;
717 }
718
719 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
720 *status = MODE_H_ILLEGAL;
721 return 0;
722 }
723
724 *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
725 return 0;
726}
727
728static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
729 struct drm_atomic_state *state)
730{
731 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
732 connector);
733 struct intel_connector *intel_connector = to_intel_connector(connector);
734 struct intel_dp *intel_dp = intel_connector->mst_port;
735 struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
736
737 return &intel_dp->mst_encoders[crtc->pipe]->base.base;
738}
739
740static int
741intel_dp_mst_detect(struct drm_connector *connector,
742 struct drm_modeset_acquire_ctx *ctx, bool force)
743{
744 struct drm_i915_private *i915 = to_i915(connector->dev);
745 struct intel_connector *intel_connector = to_intel_connector(connector);
746 struct intel_dp *intel_dp = intel_connector->mst_port;
747
748 if (!INTEL_DISPLAY_ENABLED(i915))
749 return connector_status_disconnected;
750
751 if (drm_connector_is_unregistered(connector))
752 return connector_status_disconnected;
753
754 return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
755 intel_connector->port);
756}
757
758static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
759 .get_modes = intel_dp_mst_get_modes,
760 .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
761 .atomic_best_encoder = intel_mst_atomic_best_encoder,
762 .atomic_check = intel_dp_mst_atomic_check,
763 .detect_ctx = intel_dp_mst_detect,
764};
765
766static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
767{
768 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
769
770 drm_encoder_cleanup(encoder);
771 kfree(intel_mst);
772}
773
774static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
775 .destroy = intel_dp_mst_encoder_destroy,
776};
777
778static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
779{
780 if (intel_attached_encoder(connector) && connector->base.state->crtc) {
781 enum pipe pipe;
782 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
783 return false;
784 return true;
785 }
786 return false;
787}
788
789static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop)
790{
791 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
792 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
793 struct drm_device *dev = dig_port->base.base.dev;
794 struct drm_i915_private *dev_priv = to_i915(dev);
795 struct intel_connector *intel_connector;
796 struct drm_connector *connector;
797 enum pipe pipe;
798 int ret;
799
800 intel_connector = intel_connector_alloc();
801 if (!intel_connector)
802 return NULL;
803
804 intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
805 intel_connector->mst_port = intel_dp;
806 intel_connector->port = port;
807 drm_dp_mst_get_port_malloc(port);
808
809 connector = &intel_connector->base;
810 ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
811 DRM_MODE_CONNECTOR_DisplayPort);
812 if (ret) {
813 intel_connector_free(intel_connector);
814 return NULL;
815 }
816
817 drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
818
819 for_each_pipe(dev_priv, pipe) {
820 struct drm_encoder *enc =
821 &intel_dp->mst_encoders[pipe]->base.base;
822
823 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
824 if (ret)
825 goto err;
826 }
827
828 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
829 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
830
831 ret = drm_connector_set_path_property(connector, pathprop);
832 if (ret)
833 goto err;
834
835 intel_attach_force_audio_property(connector);
836 intel_attach_broadcast_rgb_property(connector);
837
838 if (DISPLAY_VER(dev_priv) <= 12) {
839 ret = intel_dp_hdcp_init(dig_port, intel_connector);
840 if (ret)
841 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
842 connector->name, connector->base.id);
843 }
844
845 /*
846 * Reuse the prop from the SST connector because we're
847 * not allowed to create new props after device registration.
848 */
849 connector->max_bpc_property =
850 intel_dp->attached_connector->base.max_bpc_property;
851 if (connector->max_bpc_property)
852 drm_connector_attach_max_bpc_property(connector, 6, 12);
853
854 return connector;
855
856err:
857 drm_connector_cleanup(connector);
858 return NULL;
859}
860
861static void
862intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
863{
864 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
865
866 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
867}
868
869static const struct drm_dp_mst_topology_cbs mst_cbs = {
870 .add_connector = intel_dp_add_mst_connector,
871 .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
872};
873
874static struct intel_dp_mst_encoder *
875intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
876{
877 struct intel_dp_mst_encoder *intel_mst;
878 struct intel_encoder *intel_encoder;
879 struct drm_device *dev = dig_port->base.base.dev;
880
881 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
882
883 if (!intel_mst)
884 return NULL;
885
886 intel_mst->pipe = pipe;
887 intel_encoder = &intel_mst->base;
888 intel_mst->primary = dig_port;
889
890 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
891 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
892
893 intel_encoder->type = INTEL_OUTPUT_DP_MST;
894 intel_encoder->power_domain = dig_port->base.power_domain;
895 intel_encoder->port = dig_port->base.port;
896 intel_encoder->cloneable = 0;
897 /*
898 * This is wrong, but broken userspace uses the intersection
899 * of possible_crtcs of all the encoders of a given connector
900 * to figure out which crtcs can drive said connector. What
901 * should be used instead is the union of possible_crtcs.
902 * To keep such userspace functioning we must misconfigure
903 * this to make sure the intersection is not empty :(
904 */
905 intel_encoder->pipe_mask = ~0;
906
907 intel_encoder->compute_config = intel_dp_mst_compute_config;
908 intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
909 intel_encoder->disable = intel_mst_disable_dp;
910 intel_encoder->post_disable = intel_mst_post_disable_dp;
911 intel_encoder->update_pipe = intel_ddi_update_pipe;
912 intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
913 intel_encoder->pre_enable = intel_mst_pre_enable_dp;
914 intel_encoder->enable = intel_mst_enable_dp;
915 intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
916 intel_encoder->get_config = intel_dp_mst_enc_get_config;
917 intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
918
919 return intel_mst;
920
921}
922
923static bool
924intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
925{
926 struct intel_dp *intel_dp = &dig_port->dp;
927 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
928 enum pipe pipe;
929
930 for_each_pipe(dev_priv, pipe)
931 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
932 return true;
933}
934
935int
936intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
937{
938 return dig_port->dp.active_mst_links;
939}
940
941int
942intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
943{
944 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
945 struct intel_dp *intel_dp = &dig_port->dp;
946 enum port port = dig_port->base.port;
947 int ret;
948 int max_source_rate =
949 intel_dp->source_rates[intel_dp->num_source_rates - 1];
950
951 if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
952 return 0;
953
954 if (DISPLAY_VER(i915) < 12 && port == PORT_A)
955 return 0;
956
957 if (DISPLAY_VER(i915) < 11 && port == PORT_E)
958 return 0;
959
960 intel_dp->mst_mgr.cbs = &mst_cbs;
961
962 /* create encoders */
963 intel_dp_create_fake_mst_encoders(dig_port);
964 ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
965 &intel_dp->aux, 16, 3,
966 dig_port->max_lanes,
967 max_source_rate,
968 conn_base_id);
969 if (ret)
970 return ret;
971
972 intel_dp->can_mst = true;
973
974 return 0;
975}
976
977void
978intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
979{
980 struct intel_dp *intel_dp = &dig_port->dp;
981
982 if (!intel_dp->can_mst)
983 return;
984
985 drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
986 /* encoders will get killed by normal cleanup */
987}
988
989bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
990{
991 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
992}
993
994bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
995{
996 return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
997 crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
998}