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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/reset/altr,rst-mgr-a10.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a9";
20 device_type = "cpu";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 };
24 cpu1: cpu@1 {
25 compatible = "arm,cortex-a9";
26 device_type = "cpu";
27 reg = <1>;
28 next-level-cache = <&L2>;
29 };
30 };
31
32 pmu: pmu@ff111000 {
33 compatible = "arm,cortex-a9-pmu";
34 interrupt-parent = <&intc>;
35 interrupts = <0 124 4>, <0 125 4>;
36 interrupt-affinity = <&cpu0>, <&cpu1>;
37 reg = <0xff111000 0x1000>,
38 <0xff113000 0x1000>;
39 };
40
41 intc: intc@ffffd000 {
42 compatible = "arm,cortex-a9-gic";
43 #interrupt-cells = <3>;
44 interrupt-controller;
45 reg = <0xffffd000 0x1000>,
46 <0xffffc100 0x100>;
47 };
48
49 soc {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 compatible = "simple-bus";
53 device_type = "soc";
54 interrupt-parent = <&intc>;
55 ranges;
56
57 amba {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 pdma: pdma@ffda1000 {
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0xffda1000 0x1000>;
66 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
67 <0 84 IRQ_TYPE_LEVEL_HIGH>,
68 <0 85 IRQ_TYPE_LEVEL_HIGH>,
69 <0 86 IRQ_TYPE_LEVEL_HIGH>,
70 <0 87 IRQ_TYPE_LEVEL_HIGH>,
71 <0 88 IRQ_TYPE_LEVEL_HIGH>,
72 <0 89 IRQ_TYPE_LEVEL_HIGH>,
73 <0 90 IRQ_TYPE_LEVEL_HIGH>,
74 <0 91 IRQ_TYPE_LEVEL_HIGH>;
75 #dma-cells = <1>;
76 #dma-channels = <8>;
77 #dma-requests = <32>;
78 clocks = <&l4_main_clk>;
79 clock-names = "apb_pclk";
80 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
81 reset-names = "dma", "dma-ocp";
82 };
83 };
84
85 base_fpga_region {
86 #address-cells = <0x1>;
87 #size-cells = <0x1>;
88
89 compatible = "fpga-region";
90 fpga-mgr = <&fpga_mgr>;
91 };
92
93 clkmgr@ffd04000 {
94 compatible = "altr,clk-mgr";
95 reg = <0xffd04000 0x1000>;
96
97 clocks {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 };
105
106 cb_intosc_ls_clk: cb_intosc_ls_clk {
107 #clock-cells = <0>;
108 compatible = "fixed-clock";
109 };
110
111 f2s_free_clk: f2s_free_clk {
112 #clock-cells = <0>;
113 compatible = "fixed-clock";
114 };
115
116 osc1: osc1 {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 };
120
121 main_pll: main_pll@40 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 #clock-cells = <0>;
125 compatible = "altr,socfpga-a10-pll-clock";
126 clocks = <&osc1>, <&cb_intosc_ls_clk>,
127 <&f2s_free_clk>;
128 reg = <0x40>;
129
130 main_mpu_base_clk: main_mpu_base_clk {
131 #clock-cells = <0>;
132 compatible = "altr,socfpga-a10-perip-clk";
133 clocks = <&main_pll>;
134 div-reg = <0x140 0 11>;
135 };
136
137 main_noc_base_clk: main_noc_base_clk {
138 #clock-cells = <0>;
139 compatible = "altr,socfpga-a10-perip-clk";
140 clocks = <&main_pll>;
141 div-reg = <0x144 0 11>;
142 };
143
144 main_emaca_clk: main_emaca_clk@68 {
145 #clock-cells = <0>;
146 compatible = "altr,socfpga-a10-perip-clk";
147 clocks = <&main_pll>;
148 reg = <0x68>;
149 };
150
151 main_emacb_clk: main_emacb_clk@6c {
152 #clock-cells = <0>;
153 compatible = "altr,socfpga-a10-perip-clk";
154 clocks = <&main_pll>;
155 reg = <0x6C>;
156 };
157
158 main_emac_ptp_clk: main_emac_ptp_clk@70 {
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
162 reg = <0x70>;
163 };
164
165 main_gpio_db_clk: main_gpio_db_clk@74 {
166 #clock-cells = <0>;
167 compatible = "altr,socfpga-a10-perip-clk";
168 clocks = <&main_pll>;
169 reg = <0x74>;
170 };
171
172 main_sdmmc_clk: main_sdmmc_clk@78 {
173 #clock-cells = <0>;
174 compatible = "altr,socfpga-a10-perip-clk"
175;
176 clocks = <&main_pll>;
177 reg = <0x78>;
178 };
179
180 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-a10-perip-clk";
183 clocks = <&main_pll>;
184 reg = <0x7C>;
185 };
186
187 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
188 #clock-cells = <0>;
189 compatible = "altr,socfpga-a10-perip-clk";
190 clocks = <&main_pll>;
191 reg = <0x80>;
192 };
193
194 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
198 reg = <0x84>;
199 };
200
201 main_periph_ref_clk: main_periph_ref_clk@9c {
202 #clock-cells = <0>;
203 compatible = "altr,socfpga-a10-perip-clk";
204 clocks = <&main_pll>;
205 reg = <0x9C>;
206 };
207 };
208
209 periph_pll: periph_pll@c0 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 #clock-cells = <0>;
213 compatible = "altr,socfpga-a10-pll-clock";
214 clocks = <&osc1>, <&cb_intosc_ls_clk>,
215 <&f2s_free_clk>, <&main_periph_ref_clk>;
216 reg = <0xC0>;
217
218 peri_mpu_base_clk: peri_mpu_base_clk {
219 #clock-cells = <0>;
220 compatible = "altr,socfpga-a10-perip-clk";
221 clocks = <&periph_pll>;
222 div-reg = <0x140 16 11>;
223 };
224
225 peri_noc_base_clk: peri_noc_base_clk {
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-a10-perip-clk";
228 clocks = <&periph_pll>;
229 div-reg = <0x144 16 11>;
230 };
231
232 peri_emaca_clk: peri_emaca_clk@e8 {
233 #clock-cells = <0>;
234 compatible = "altr,socfpga-a10-perip-clk";
235 clocks = <&periph_pll>;
236 reg = <0xE8>;
237 };
238
239 peri_emacb_clk: peri_emacb_clk@ec {
240 #clock-cells = <0>;
241 compatible = "altr,socfpga-a10-perip-clk";
242 clocks = <&periph_pll>;
243 reg = <0xEC>;
244 };
245
246 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
247 #clock-cells = <0>;
248 compatible = "altr,socfpga-a10-perip-clk";
249 clocks = <&periph_pll>;
250 reg = <0xF0>;
251 };
252
253 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-a10-perip-clk";
256 clocks = <&periph_pll>;
257 reg = <0xF4>;
258 };
259
260 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
261 #clock-cells = <0>;
262 compatible = "altr,socfpga-a10-perip-clk";
263 clocks = <&periph_pll>;
264 reg = <0xF8>;
265 };
266
267 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
268 #clock-cells = <0>;
269 compatible = "altr,socfpga-a10-perip-clk";
270 clocks = <&periph_pll>;
271 reg = <0xFC>;
272 };
273
274 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
275 #clock-cells = <0>;
276 compatible = "altr,socfpga-a10-perip-clk";
277 clocks = <&periph_pll>;
278 reg = <0x100>;
279 };
280
281 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
282 #clock-cells = <0>;
283 compatible = "altr,socfpga-a10-perip-clk";
284 clocks = <&periph_pll>;
285 reg = <0x104>;
286 };
287 };
288
289 mpu_free_clk: mpu_free_clk@60 {
290 #clock-cells = <0>;
291 compatible = "altr,socfpga-a10-perip-clk";
292 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
293 <&osc1>, <&cb_intosc_hs_div2_clk>,
294 <&f2s_free_clk>;
295 reg = <0x60>;
296 };
297
298 noc_free_clk: noc_free_clk@64 {
299 #clock-cells = <0>;
300 compatible = "altr,socfpga-a10-perip-clk";
301 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
302 <&osc1>, <&cb_intosc_hs_div2_clk>,
303 <&f2s_free_clk>;
304 reg = <0x64>;
305 };
306
307 s2f_user1_free_clk: s2f_user1_free_clk@104 {
308 #clock-cells = <0>;
309 compatible = "altr,socfpga-a10-perip-clk";
310 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
311 <&osc1>, <&cb_intosc_hs_div2_clk>,
312 <&f2s_free_clk>;
313 reg = <0x104>;
314 };
315
316 sdmmc_free_clk: sdmmc_free_clk@f8 {
317 #clock-cells = <0>;
318 compatible = "altr,socfpga-a10-perip-clk";
319 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
320 <&osc1>, <&cb_intosc_hs_div2_clk>,
321 <&f2s_free_clk>;
322 fixed-divider = <4>;
323 reg = <0xF8>;
324 };
325
326 l4_sys_free_clk: l4_sys_free_clk {
327 #clock-cells = <0>;
328 compatible = "altr,socfpga-a10-perip-clk";
329 clocks = <&noc_free_clk>;
330 fixed-divider = <4>;
331 };
332
333 l4_main_clk: l4_main_clk {
334 #clock-cells = <0>;
335 compatible = "altr,socfpga-a10-gate-clk";
336 clocks = <&noc_free_clk>;
337 div-reg = <0xA8 0 2>;
338 clk-gate = <0x48 1>;
339 };
340
341 l4_mp_clk: l4_mp_clk {
342 #clock-cells = <0>;
343 compatible = "altr,socfpga-a10-gate-clk";
344 clocks = <&noc_free_clk>;
345 div-reg = <0xA8 8 2>;
346 clk-gate = <0x48 2>;
347 };
348
349 l4_sp_clk: l4_sp_clk {
350 #clock-cells = <0>;
351 compatible = "altr,socfpga-a10-gate-clk";
352 clocks = <&noc_free_clk>;
353 div-reg = <0xA8 16 2>;
354 clk-gate = <0x48 3>;
355 };
356
357 mpu_periph_clk: mpu_periph_clk {
358 #clock-cells = <0>;
359 compatible = "altr,socfpga-a10-gate-clk";
360 clocks = <&mpu_free_clk>;
361 fixed-divider = <4>;
362 clk-gate = <0x48 0>;
363 };
364
365 sdmmc_clk: sdmmc_clk {
366 #clock-cells = <0>;
367 compatible = "altr,socfpga-a10-gate-clk";
368 clocks = <&sdmmc_free_clk>;
369 clk-gate = <0xC8 5>;
370 clk-phase = <0 135>;
371 };
372
373 qspi_clk: qspi_clk {
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-a10-gate-clk";
376 clocks = <&l4_main_clk>;
377 clk-gate = <0xC8 11>;
378 };
379
380 nand_x_clk: nand_x_clk {
381 #clock-cells = <0>;
382 compatible = "altr,socfpga-a10-gate-clk";
383 clocks = <&l4_mp_clk>;
384 clk-gate = <0xC8 10>;
385 };
386
387 nand_ecc_clk: nand_ecc_clk {
388 #clock-cells = <0>;
389 compatible = "altr,socfpga-a10-gate-clk";
390 clocks = <&nand_x_clk>;
391 clk-gate = <0xC8 10>;
392 };
393
394 nand_clk: nand_clk {
395 #clock-cells = <0>;
396 compatible = "altr,socfpga-a10-gate-clk";
397 clocks = <&nand_x_clk>;
398 fixed-divider = <4>;
399 clk-gate = <0xC8 10>;
400 };
401
402 spi_m_clk: spi_m_clk {
403 #clock-cells = <0>;
404 compatible = "altr,socfpga-a10-gate-clk";
405 clocks = <&l4_main_clk>;
406 clk-gate = <0xC8 9>;
407 };
408
409 usb_clk: usb_clk {
410 #clock-cells = <0>;
411 compatible = "altr,socfpga-a10-gate-clk";
412 clocks = <&l4_mp_clk>;
413 clk-gate = <0xC8 8>;
414 };
415
416 s2f_usr1_clk: s2f_usr1_clk {
417 #clock-cells = <0>;
418 compatible = "altr,socfpga-a10-gate-clk";
419 clocks = <&peri_s2f_usr1_clk>;
420 clk-gate = <0xC8 6>;
421 };
422 };
423 };
424
425 socfpga_axi_setup: stmmac-axi-config {
426 snps,wr_osr_lmt = <0xf>;
427 snps,rd_osr_lmt = <0xf>;
428 snps,blen = <0 0 0 0 16 0 0>;
429 };
430
431 gmac0: ethernet@ff800000 {
432 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
433 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
434 reg = <0xff800000 0x2000>;
435 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
436 interrupt-names = "macirq";
437 /* Filled in by bootloader */
438 mac-address = [00 00 00 00 00 00];
439 snps,multicast-filter-bins = <256>;
440 snps,perfect-filter-entries = <128>;
441 tx-fifo-depth = <4096>;
442 rx-fifo-depth = <16384>;
443 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
444 clock-names = "stmmaceth", "ptp_ref";
445 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
446 reset-names = "stmmaceth", "stmmaceth-ocp";
447 snps,axi-config = <&socfpga_axi_setup>;
448 status = "disabled";
449 };
450
451 gmac1: ethernet@ff802000 {
452 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
453 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
454 reg = <0xff802000 0x2000>;
455 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
456 interrupt-names = "macirq";
457 /* Filled in by bootloader */
458 mac-address = [00 00 00 00 00 00];
459 snps,multicast-filter-bins = <256>;
460 snps,perfect-filter-entries = <128>;
461 tx-fifo-depth = <4096>;
462 rx-fifo-depth = <16384>;
463 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
464 clock-names = "stmmaceth", "ptp_ref";
465 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
466 reset-names = "stmmaceth", "stmmaceth-ocp";
467 snps,axi-config = <&socfpga_axi_setup>;
468 status = "disabled";
469 };
470
471 gmac2: ethernet@ff804000 {
472 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
473 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
474 reg = <0xff804000 0x2000>;
475 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "macirq";
477 /* Filled in by bootloader */
478 mac-address = [00 00 00 00 00 00];
479 snps,multicast-filter-bins = <256>;
480 snps,perfect-filter-entries = <128>;
481 tx-fifo-depth = <4096>;
482 rx-fifo-depth = <16384>;
483 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
484 clock-names = "stmmaceth", "ptp_ref";
485 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
486 reset-names = "stmmaceth", "stmmaceth-ocp";
487 snps,axi-config = <&socfpga_axi_setup>;
488 status = "disabled";
489 };
490
491 gpio0: gpio@ffc02900 {
492 #address-cells = <1>;
493 #size-cells = <0>;
494 compatible = "snps,dw-apb-gpio";
495 reg = <0xffc02900 0x100>;
496 resets = <&rst GPIO0_RESET>;
497 status = "disabled";
498
499 porta: gpio-controller@0 {
500 compatible = "snps,dw-apb-gpio-port";
501 gpio-controller;
502 #gpio-cells = <2>;
503 snps,nr-gpios = <29>;
504 reg = <0>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
508 };
509 };
510
511 gpio1: gpio@ffc02a00 {
512 #address-cells = <1>;
513 #size-cells = <0>;
514 compatible = "snps,dw-apb-gpio";
515 reg = <0xffc02a00 0x100>;
516 resets = <&rst GPIO1_RESET>;
517 status = "disabled";
518
519 portb: gpio-controller@0 {
520 compatible = "snps,dw-apb-gpio-port";
521 gpio-controller;
522 #gpio-cells = <2>;
523 snps,nr-gpios = <29>;
524 reg = <0>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
528 };
529 };
530
531 gpio2: gpio@ffc02b00 {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "snps,dw-apb-gpio";
535 reg = <0xffc02b00 0x100>;
536 resets = <&rst GPIO2_RESET>;
537 status = "disabled";
538
539 portc: gpio-controller@0 {
540 compatible = "snps,dw-apb-gpio-port";
541 gpio-controller;
542 #gpio-cells = <2>;
543 snps,nr-gpios = <27>;
544 reg = <0>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
548 };
549 };
550
551 fpga_mgr: fpga-mgr@ffd03000 {
552 compatible = "altr,socfpga-a10-fpga-mgr";
553 reg = <0xffd03000 0x100
554 0xffcfe400 0x20>;
555 clocks = <&l4_mp_clk>;
556 resets = <&rst FPGAMGR_RESET>;
557 reset-names = "fpgamgr";
558 };
559
560 i2c0: i2c@ffc02200 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "snps,designware-i2c";
564 reg = <0xffc02200 0x100>;
565 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&l4_sp_clk>;
567 resets = <&rst I2C0_RESET>;
568 status = "disabled";
569 };
570
571 i2c1: i2c@ffc02300 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 compatible = "snps,designware-i2c";
575 reg = <0xffc02300 0x100>;
576 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&l4_sp_clk>;
578 resets = <&rst I2C1_RESET>;
579 status = "disabled";
580 };
581
582 i2c2: i2c@ffc02400 {
583 #address-cells = <1>;
584 #size-cells = <0>;
585 compatible = "snps,designware-i2c";
586 reg = <0xffc02400 0x100>;
587 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&l4_sp_clk>;
589 resets = <&rst I2C2_RESET>;
590 status = "disabled";
591 };
592
593 i2c3: i2c@ffc02500 {
594 #address-cells = <1>;
595 #size-cells = <0>;
596 compatible = "snps,designware-i2c";
597 reg = <0xffc02500 0x100>;
598 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&l4_sp_clk>;
600 resets = <&rst I2C3_RESET>;
601 status = "disabled";
602 };
603
604 i2c4: i2c@ffc02600 {
605 #address-cells = <1>;
606 #size-cells = <0>;
607 compatible = "snps,designware-i2c";
608 reg = <0xffc02600 0x100>;
609 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&l4_sp_clk>;
611 resets = <&rst I2C4_RESET>;
612 status = "disabled";
613 };
614
615 spi0: spi@ffda4000 {
616 compatible = "snps,dw-apb-ssi";
617 #address-cells = <1>;
618 #size-cells = <0>;
619 reg = <0xffda4000 0x100>;
620 interrupts = <0 101 4>;
621 num-cs = <4>;
622 /*32bit_access;*/
623 clocks = <&spi_m_clk>;
624 resets = <&rst SPIM0_RESET>;
625 reset-names = "spi";
626 status = "disabled";
627 };
628
629 spi1: spi@ffda5000 {
630 compatible = "snps,dw-apb-ssi";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 reg = <0xffda5000 0x100>;
634 interrupts = <0 102 4>;
635 num-cs = <4>;
636 /*32bit_access;*/
637 tx-dma-channel = <&pdma 16>;
638 rx-dma-channel = <&pdma 17>;
639 clocks = <&spi_m_clk>;
640 resets = <&rst SPIM1_RESET>;
641 reset-names = "spi";
642 status = "disabled";
643 };
644
645 sdr: sdr@ffcfb100 {
646 compatible = "altr,sdr-ctl", "syscon";
647 reg = <0xffcfb100 0x80>;
648 };
649
650 L2: cache-controller@fffff000 {
651 compatible = "arm,pl310-cache";
652 reg = <0xfffff000 0x1000>;
653 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
654 cache-unified;
655 cache-level = <2>;
656 prefetch-data = <1>;
657 prefetch-instr = <1>;
658 arm,shared-override;
659 };
660
661 mmc: dwmmc0@ff808000 {
662 #address-cells = <1>;
663 #size-cells = <0>;
664 compatible = "altr,socfpga-dw-mshc";
665 reg = <0xff808000 0x1000>;
666 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
667 fifo-depth = <0x400>;
668 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
669 clock-names = "biu", "ciu";
670 resets = <&rst SDMMC_RESET>;
671 status = "disabled";
672 };
673
674 nand: nand@ffb90000 {
675 #address-cells = <1>;
676 #size-cells = <0>;
677 compatible = "altr,socfpga-denali-nand";
678 reg = <0xffb90000 0x72000>,
679 <0xffb80000 0x10000>;
680 reg-names = "nand_data", "denali_reg";
681 interrupts = <0 99 4>;
682 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
683 clock-names = "nand", "nand_x", "ecc";
684 resets = <&rst NAND_RESET>;
685 status = "disabled";
686 };
687
688 ocram: sram@ffe00000 {
689 compatible = "mmio-sram";
690 reg = <0xffe00000 0x40000>;
691 };
692
693 eccmgr: eccmgr {
694 compatible = "altr,socfpga-a10-ecc-manager";
695 altr,sysmgr-syscon = <&sysmgr>;
696 #address-cells = <1>;
697 #size-cells = <1>;
698 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
699 <0 0 IRQ_TYPE_LEVEL_HIGH>;
700 interrupt-controller;
701 #interrupt-cells = <2>;
702 ranges;
703
704 sdramedac {
705 compatible = "altr,sdram-edac-a10";
706 altr,sdr-syscon = <&sdr>;
707 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
708 <49 IRQ_TYPE_LEVEL_HIGH>;
709 };
710
711 l2-ecc@ffd06010 {
712 compatible = "altr,socfpga-a10-l2-ecc";
713 reg = <0xffd06010 0x4>;
714 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
715 <32 IRQ_TYPE_LEVEL_HIGH>;
716 };
717
718 ocram-ecc@ff8c3000 {
719 compatible = "altr,socfpga-a10-ocram-ecc";
720 reg = <0xff8c3000 0x400>;
721 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
722 <33 IRQ_TYPE_LEVEL_HIGH>;
723 };
724
725 emac0-rx-ecc@ff8c0800 {
726 compatible = "altr,socfpga-eth-mac-ecc";
727 reg = <0xff8c0800 0x400>;
728 altr,ecc-parent = <&gmac0>;
729 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
730 <36 IRQ_TYPE_LEVEL_HIGH>;
731 };
732
733 emac0-tx-ecc@ff8c0c00 {
734 compatible = "altr,socfpga-eth-mac-ecc";
735 reg = <0xff8c0c00 0x400>;
736 altr,ecc-parent = <&gmac0>;
737 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
738 <37 IRQ_TYPE_LEVEL_HIGH>;
739 };
740
741 dma-ecc@ff8c8000 {
742 compatible = "altr,socfpga-dma-ecc";
743 reg = <0xff8c8000 0x400>;
744 altr,ecc-parent = <&pdma>;
745 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
746 <42 IRQ_TYPE_LEVEL_HIGH>;
747 };
748
749 usb0-ecc@ff8c8800 {
750 compatible = "altr,socfpga-usb-ecc";
751 reg = <0xff8c8800 0x400>;
752 altr,ecc-parent = <&usb0>;
753 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
754 <34 IRQ_TYPE_LEVEL_HIGH>;
755 };
756 };
757
758 qspi: spi@ff809000 {
759 compatible = "cdns,qspi-nor";
760 #address-cells = <1>;
761 #size-cells = <0>;
762 reg = <0xff809000 0x100>,
763 <0xffa00000 0x100000>;
764 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
765 cdns,fifo-depth = <128>;
766 cdns,fifo-width = <4>;
767 cdns,trigger-address = <0x00000000>;
768 clocks = <&qspi_clk>;
769 resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
770 reset-names = "qspi", "qspi-ocp";
771 status = "disabled";
772 };
773
774 rst: rstmgr@ffd05000 {
775 #reset-cells = <1>;
776 compatible = "altr,rst-mgr";
777 reg = <0xffd05000 0x100>;
778 altr,modrst-offset = <0x20>;
779 };
780
781 scu: snoop-control-unit@ffffc000 {
782 compatible = "arm,cortex-a9-scu";
783 reg = <0xffffc000 0x100>;
784 };
785
786 sysmgr: sysmgr@ffd06000 {
787 compatible = "altr,sys-mgr", "syscon";
788 reg = <0xffd06000 0x300>;
789 cpu1-start-addr = <0xffd06230>;
790 };
791
792 /* Local timer */
793 timer@ffffc600 {
794 compatible = "arm,cortex-a9-twd-timer";
795 reg = <0xffffc600 0x100>;
796 interrupts = <1 13 0xf01>;
797 clocks = <&mpu_periph_clk>;
798 };
799
800 timer0: timer0@ffc02700 {
801 compatible = "snps,dw-apb-timer";
802 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0xffc02700 0x100>;
804 clocks = <&l4_sp_clk>;
805 clock-names = "timer";
806 resets = <&rst SPTIMER0_RESET>;
807 reset-names = "timer";
808 };
809
810 timer1: timer1@ffc02800 {
811 compatible = "snps,dw-apb-timer";
812 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
813 reg = <0xffc02800 0x100>;
814 clocks = <&l4_sp_clk>;
815 clock-names = "timer";
816 resets = <&rst SPTIMER1_RESET>;
817 reset-names = "timer";
818 };
819
820 timer2: timer2@ffd00000 {
821 compatible = "snps,dw-apb-timer";
822 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
823 reg = <0xffd00000 0x100>;
824 clocks = <&l4_sys_free_clk>;
825 clock-names = "timer";
826 resets = <&rst L4SYSTIMER0_RESET>;
827 reset-names = "timer";
828 };
829
830 timer3: timer3@ffd00100 {
831 compatible = "snps,dw-apb-timer";
832 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
833 reg = <0xffd00100 0x100>;
834 clocks = <&l4_sys_free_clk>;
835 clock-names = "timer";
836 resets = <&rst L4SYSTIMER1_RESET>;
837 reset-names = "timer";
838 };
839
840 uart0: serial0@ffc02000 {
841 compatible = "snps,dw-apb-uart";
842 reg = <0xffc02000 0x100>;
843 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
844 reg-shift = <2>;
845 reg-io-width = <4>;
846 clocks = <&l4_sp_clk>;
847 resets = <&rst UART0_RESET>;
848 status = "disabled";
849 };
850
851 uart1: serial1@ffc02100 {
852 compatible = "snps,dw-apb-uart";
853 reg = <0xffc02100 0x100>;
854 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
855 reg-shift = <2>;
856 reg-io-width = <4>;
857 clocks = <&l4_sp_clk>;
858 resets = <&rst UART1_RESET>;
859 status = "disabled";
860 };
861
862 usbphy0: usbphy {
863 #phy-cells = <0>;
864 compatible = "usb-nop-xceiv";
865 status = "okay";
866 };
867
868 usb0: usb@ffb00000 {
869 compatible = "snps,dwc2";
870 reg = <0xffb00000 0xffff>;
871 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&usb_clk>;
873 clock-names = "otg";
874 resets = <&rst USB0_RESET>;
875 reset-names = "dwc2";
876 phys = <&usbphy0>;
877 phy-names = "usb2-phy";
878 status = "disabled";
879 };
880
881 usb1: usb@ffb40000 {
882 compatible = "snps,dwc2";
883 reg = <0xffb40000 0xffff>;
884 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&usb_clk>;
886 clock-names = "otg";
887 resets = <&rst USB1_RESET>;
888 reset-names = "dwc2";
889 phys = <&usbphy0>;
890 phy-names = "usb2-phy";
891 status = "disabled";
892 };
893
894 watchdog0: watchdog@ffd00200 {
895 compatible = "snps,dw-wdt";
896 reg = <0xffd00200 0x100>;
897 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&l4_sys_free_clk>;
899 resets = <&rst L4WD0_RESET>;
900 status = "disabled";
901 };
902
903 watchdog1: watchdog@ffd00300 {
904 compatible = "snps,dw-wdt";
905 reg = <0xffd00300 0x100>;
906 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&l4_sys_free_clk>;
908 resets = <&rst L4WD1_RESET>;
909 status = "disabled";
910 };
911 };
912};
1/*
2 * Copyright Altera Corporation (C) 2014. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <dt-bindings/interrupt-controller/arm-gic.h>
18#include <dt-bindings/reset/altr,rst-mgr-a10.h>
19
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "altr,socfpga-a10-smp";
28
29 cpu@0 {
30 compatible = "arm,cortex-a9";
31 device_type = "cpu";
32 reg = <0>;
33 next-level-cache = <&L2>;
34 };
35 cpu@1 {
36 compatible = "arm,cortex-a9";
37 device_type = "cpu";
38 reg = <1>;
39 next-level-cache = <&L2>;
40 };
41 };
42
43 intc: intc@ffffd000 {
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
46 interrupt-controller;
47 reg = <0xffffd000 0x1000>,
48 <0xffffc100 0x100>;
49 };
50
51 soc {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 compatible = "simple-bus";
55 device_type = "soc";
56 interrupt-parent = <&intc>;
57 ranges;
58
59 amba {
60 compatible = "simple-bus";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 pdma: pdma@ffda1000 {
66 compatible = "arm,pl330", "arm,primecell";
67 reg = <0xffda1000 0x1000>;
68 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
69 <0 84 IRQ_TYPE_LEVEL_HIGH>,
70 <0 85 IRQ_TYPE_LEVEL_HIGH>,
71 <0 86 IRQ_TYPE_LEVEL_HIGH>,
72 <0 87 IRQ_TYPE_LEVEL_HIGH>,
73 <0 88 IRQ_TYPE_LEVEL_HIGH>,
74 <0 89 IRQ_TYPE_LEVEL_HIGH>,
75 <0 90 IRQ_TYPE_LEVEL_HIGH>,
76 <0 91 IRQ_TYPE_LEVEL_HIGH>;
77 #dma-cells = <1>;
78 #dma-channels = <8>;
79 #dma-requests = <32>;
80 clocks = <&l4_main_clk>;
81 clock-names = "apb_pclk";
82 };
83 };
84
85 base_fpga_region {
86 #address-cells = <0x1>;
87 #size-cells = <0x1>;
88
89 compatible = "fpga-region";
90 fpga-mgr = <&fpga_mgr>;
91 };
92
93 clkmgr@ffd04000 {
94 compatible = "altr,clk-mgr";
95 reg = <0xffd04000 0x1000>;
96
97 clocks {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 };
105
106 cb_intosc_ls_clk: cb_intosc_ls_clk {
107 #clock-cells = <0>;
108 compatible = "fixed-clock";
109 };
110
111 f2s_free_clk: f2s_free_clk {
112 #clock-cells = <0>;
113 compatible = "fixed-clock";
114 };
115
116 osc1: osc1 {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 };
120
121 main_pll: main_pll@40 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 #clock-cells = <0>;
125 compatible = "altr,socfpga-a10-pll-clock";
126 clocks = <&osc1>, <&cb_intosc_ls_clk>,
127 <&f2s_free_clk>;
128 reg = <0x40>;
129
130 main_mpu_base_clk: main_mpu_base_clk {
131 #clock-cells = <0>;
132 compatible = "altr,socfpga-a10-perip-clk";
133 clocks = <&main_pll>;
134 div-reg = <0x140 0 11>;
135 };
136
137 main_noc_base_clk: main_noc_base_clk {
138 #clock-cells = <0>;
139 compatible = "altr,socfpga-a10-perip-clk";
140 clocks = <&main_pll>;
141 div-reg = <0x144 0 11>;
142 };
143
144 main_emaca_clk: main_emaca_clk@68 {
145 #clock-cells = <0>;
146 compatible = "altr,socfpga-a10-perip-clk";
147 clocks = <&main_pll>;
148 reg = <0x68>;
149 };
150
151 main_emacb_clk: main_emacb_clk@6c {
152 #clock-cells = <0>;
153 compatible = "altr,socfpga-a10-perip-clk";
154 clocks = <&main_pll>;
155 reg = <0x6C>;
156 };
157
158 main_emac_ptp_clk: main_emac_ptp_clk@70 {
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
162 reg = <0x70>;
163 };
164
165 main_gpio_db_clk: main_gpio_db_clk@74 {
166 #clock-cells = <0>;
167 compatible = "altr,socfpga-a10-perip-clk";
168 clocks = <&main_pll>;
169 reg = <0x74>;
170 };
171
172 main_sdmmc_clk: main_sdmmc_clk@78 {
173 #clock-cells = <0>;
174 compatible = "altr,socfpga-a10-perip-clk"
175;
176 clocks = <&main_pll>;
177 reg = <0x78>;
178 };
179
180 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-a10-perip-clk";
183 clocks = <&main_pll>;
184 reg = <0x7C>;
185 };
186
187 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
188 #clock-cells = <0>;
189 compatible = "altr,socfpga-a10-perip-clk";
190 clocks = <&main_pll>;
191 reg = <0x80>;
192 };
193
194 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
198 reg = <0x84>;
199 };
200
201 main_periph_ref_clk: main_periph_ref_clk@9c {
202 #clock-cells = <0>;
203 compatible = "altr,socfpga-a10-perip-clk";
204 clocks = <&main_pll>;
205 reg = <0x9C>;
206 };
207 };
208
209 periph_pll: periph_pll@c0 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 #clock-cells = <0>;
213 compatible = "altr,socfpga-a10-pll-clock";
214 clocks = <&osc1>, <&cb_intosc_ls_clk>,
215 <&f2s_free_clk>, <&main_periph_ref_clk>;
216 reg = <0xC0>;
217
218 peri_mpu_base_clk: peri_mpu_base_clk {
219 #clock-cells = <0>;
220 compatible = "altr,socfpga-a10-perip-clk";
221 clocks = <&periph_pll>;
222 div-reg = <0x140 16 11>;
223 };
224
225 peri_noc_base_clk: peri_noc_base_clk {
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-a10-perip-clk";
228 clocks = <&periph_pll>;
229 div-reg = <0x144 16 11>;
230 };
231
232 peri_emaca_clk: peri_emaca_clk@e8 {
233 #clock-cells = <0>;
234 compatible = "altr,socfpga-a10-perip-clk";
235 clocks = <&periph_pll>;
236 reg = <0xE8>;
237 };
238
239 peri_emacb_clk: peri_emacb_clk@ec {
240 #clock-cells = <0>;
241 compatible = "altr,socfpga-a10-perip-clk";
242 clocks = <&periph_pll>;
243 reg = <0xEC>;
244 };
245
246 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
247 #clock-cells = <0>;
248 compatible = "altr,socfpga-a10-perip-clk";
249 clocks = <&periph_pll>;
250 reg = <0xF0>;
251 };
252
253 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-a10-perip-clk";
256 clocks = <&periph_pll>;
257 reg = <0xF4>;
258 };
259
260 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
261 #clock-cells = <0>;
262 compatible = "altr,socfpga-a10-perip-clk";
263 clocks = <&periph_pll>;
264 reg = <0xF8>;
265 };
266
267 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
268 #clock-cells = <0>;
269 compatible = "altr,socfpga-a10-perip-clk";
270 clocks = <&periph_pll>;
271 reg = <0xFC>;
272 };
273
274 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
275 #clock-cells = <0>;
276 compatible = "altr,socfpga-a10-perip-clk";
277 clocks = <&periph_pll>;
278 reg = <0x100>;
279 };
280
281 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
282 #clock-cells = <0>;
283 compatible = "altr,socfpga-a10-perip-clk";
284 clocks = <&periph_pll>;
285 reg = <0x104>;
286 };
287 };
288
289 mpu_free_clk: mpu_free_clk@60 {
290 #clock-cells = <0>;
291 compatible = "altr,socfpga-a10-perip-clk";
292 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
293 <&osc1>, <&cb_intosc_hs_div2_clk>,
294 <&f2s_free_clk>;
295 reg = <0x60>;
296 };
297
298 noc_free_clk: noc_free_clk@64 {
299 #clock-cells = <0>;
300 compatible = "altr,socfpga-a10-perip-clk";
301 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
302 <&osc1>, <&cb_intosc_hs_div2_clk>,
303 <&f2s_free_clk>;
304 reg = <0x64>;
305 };
306
307 s2f_user1_free_clk: s2f_user1_free_clk@104 {
308 #clock-cells = <0>;
309 compatible = "altr,socfpga-a10-perip-clk";
310 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
311 <&osc1>, <&cb_intosc_hs_div2_clk>,
312 <&f2s_free_clk>;
313 reg = <0x104>;
314 };
315
316 sdmmc_free_clk: sdmmc_free_clk@f8 {
317 #clock-cells = <0>;
318 compatible = "altr,socfpga-a10-perip-clk";
319 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
320 <&osc1>, <&cb_intosc_hs_div2_clk>,
321 <&f2s_free_clk>;
322 fixed-divider = <4>;
323 reg = <0xF8>;
324 };
325
326 l4_sys_free_clk: l4_sys_free_clk {
327 #clock-cells = <0>;
328 compatible = "altr,socfpga-a10-perip-clk";
329 clocks = <&noc_free_clk>;
330 fixed-divider = <4>;
331 };
332
333 l4_main_clk: l4_main_clk {
334 #clock-cells = <0>;
335 compatible = "altr,socfpga-a10-gate-clk";
336 clocks = <&noc_free_clk>;
337 div-reg = <0xA8 0 2>;
338 clk-gate = <0x48 1>;
339 };
340
341 l4_mp_clk: l4_mp_clk {
342 #clock-cells = <0>;
343 compatible = "altr,socfpga-a10-gate-clk";
344 clocks = <&noc_free_clk>;
345 div-reg = <0xA8 8 2>;
346 clk-gate = <0x48 2>;
347 };
348
349 l4_sp_clk: l4_sp_clk {
350 #clock-cells = <0>;
351 compatible = "altr,socfpga-a10-gate-clk";
352 clocks = <&noc_free_clk>;
353 div-reg = <0xA8 16 2>;
354 clk-gate = <0x48 3>;
355 };
356
357 mpu_periph_clk: mpu_periph_clk {
358 #clock-cells = <0>;
359 compatible = "altr,socfpga-a10-gate-clk";
360 clocks = <&mpu_free_clk>;
361 fixed-divider = <4>;
362 clk-gate = <0x48 0>;
363 };
364
365 sdmmc_clk: sdmmc_clk {
366 #clock-cells = <0>;
367 compatible = "altr,socfpga-a10-gate-clk";
368 clocks = <&sdmmc_free_clk>;
369 clk-gate = <0xC8 5>;
370 clk-phase = <0 135>;
371 };
372
373 qspi_clk: qspi_clk {
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-a10-gate-clk";
376 clocks = <&l4_main_clk>;
377 clk-gate = <0xC8 11>;
378 };
379
380 nand_clk: nand_clk {
381 #clock-cells = <0>;
382 compatible = "altr,socfpga-a10-gate-clk";
383 clocks = <&l4_mp_clk>;
384 clk-gate = <0xC8 10>;
385 };
386
387 spi_m_clk: spi_m_clk {
388 #clock-cells = <0>;
389 compatible = "altr,socfpga-a10-gate-clk";
390 clocks = <&l4_main_clk>;
391 clk-gate = <0xC8 9>;
392 };
393
394 usb_clk: usb_clk {
395 #clock-cells = <0>;
396 compatible = "altr,socfpga-a10-gate-clk";
397 clocks = <&l4_mp_clk>;
398 clk-gate = <0xC8 8>;
399 };
400
401 s2f_usr1_clk: s2f_usr1_clk {
402 #clock-cells = <0>;
403 compatible = "altr,socfpga-a10-gate-clk";
404 clocks = <&peri_s2f_usr1_clk>;
405 clk-gate = <0xC8 6>;
406 };
407 };
408 };
409
410 socfpga_axi_setup: stmmac-axi-config {
411 snps,wr_osr_lmt = <0xf>;
412 snps,rd_osr_lmt = <0xf>;
413 snps,blen = <0 0 0 0 16 0 0>;
414 };
415
416 gmac0: ethernet@ff800000 {
417 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
418 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
419 reg = <0xff800000 0x2000>;
420 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
421 interrupt-names = "macirq";
422 /* Filled in by bootloader */
423 mac-address = [00 00 00 00 00 00];
424 snps,multicast-filter-bins = <256>;
425 snps,perfect-filter-entries = <128>;
426 tx-fifo-depth = <4096>;
427 rx-fifo-depth = <16384>;
428 clocks = <&l4_mp_clk>;
429 clock-names = "stmmaceth";
430 resets = <&rst EMAC0_RESET>;
431 reset-names = "stmmaceth";
432 snps,axi-config = <&socfpga_axi_setup>;
433 status = "disabled";
434 };
435
436 gmac1: ethernet@ff802000 {
437 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
438 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
439 reg = <0xff802000 0x2000>;
440 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-names = "macirq";
442 /* Filled in by bootloader */
443 mac-address = [00 00 00 00 00 00];
444 snps,multicast-filter-bins = <256>;
445 snps,perfect-filter-entries = <128>;
446 tx-fifo-depth = <4096>;
447 rx-fifo-depth = <16384>;
448 clocks = <&l4_mp_clk>;
449 clock-names = "stmmaceth";
450 resets = <&rst EMAC1_RESET>;
451 reset-names = "stmmaceth";
452 snps,axi-config = <&socfpga_axi_setup>;
453 status = "disabled";
454 };
455
456 gmac2: ethernet@ff804000 {
457 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
458 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
459 reg = <0xff804000 0x2000>;
460 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "macirq";
462 /* Filled in by bootloader */
463 mac-address = [00 00 00 00 00 00];
464 snps,multicast-filter-bins = <256>;
465 snps,perfect-filter-entries = <128>;
466 tx-fifo-depth = <4096>;
467 rx-fifo-depth = <16384>;
468 clocks = <&l4_mp_clk>;
469 clock-names = "stmmaceth";
470 snps,axi-config = <&socfpga_axi_setup>;
471 status = "disabled";
472 };
473
474 gpio0: gpio@ffc02900 {
475 #address-cells = <1>;
476 #size-cells = <0>;
477 compatible = "snps,dw-apb-gpio";
478 reg = <0xffc02900 0x100>;
479 status = "disabled";
480
481 porta: gpio-controller@0 {
482 compatible = "snps,dw-apb-gpio-port";
483 gpio-controller;
484 #gpio-cells = <2>;
485 snps,nr-gpios = <29>;
486 reg = <0>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
490 };
491 };
492
493 gpio1: gpio@ffc02a00 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "snps,dw-apb-gpio";
497 reg = <0xffc02a00 0x100>;
498 status = "disabled";
499
500 portb: gpio-controller@0 {
501 compatible = "snps,dw-apb-gpio-port";
502 gpio-controller;
503 #gpio-cells = <2>;
504 snps,nr-gpios = <29>;
505 reg = <0>;
506 interrupt-controller;
507 #interrupt-cells = <2>;
508 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
509 };
510 };
511
512 gpio2: gpio@ffc02b00 {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 compatible = "snps,dw-apb-gpio";
516 reg = <0xffc02b00 0x100>;
517 status = "disabled";
518
519 portc: gpio-controller@0 {
520 compatible = "snps,dw-apb-gpio-port";
521 gpio-controller;
522 #gpio-cells = <2>;
523 snps,nr-gpios = <27>;
524 reg = <0>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
528 };
529 };
530
531 fpga_mgr: fpga-mgr@ffd03000 {
532 compatible = "altr,socfpga-a10-fpga-mgr";
533 reg = <0xffd03000 0x100
534 0xffcfe400 0x20>;
535 clocks = <&l4_mp_clk>;
536 resets = <&rst FPGAMGR_RESET>;
537 reset-names = "fpgamgr";
538 };
539
540 i2c0: i2c@ffc02200 {
541 #address-cells = <1>;
542 #size-cells = <0>;
543 compatible = "snps,designware-i2c";
544 reg = <0xffc02200 0x100>;
545 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&l4_sp_clk>;
547 status = "disabled";
548 };
549
550 i2c1: i2c@ffc02300 {
551 #address-cells = <1>;
552 #size-cells = <0>;
553 compatible = "snps,designware-i2c";
554 reg = <0xffc02300 0x100>;
555 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&l4_sp_clk>;
557 status = "disabled";
558 };
559
560 i2c2: i2c@ffc02400 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "snps,designware-i2c";
564 reg = <0xffc02400 0x100>;
565 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&l4_sp_clk>;
567 status = "disabled";
568 };
569
570 i2c3: i2c@ffc02500 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 compatible = "snps,designware-i2c";
574 reg = <0xffc02500 0x100>;
575 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&l4_sp_clk>;
577 status = "disabled";
578 };
579
580 i2c4: i2c@ffc02600 {
581 #address-cells = <1>;
582 #size-cells = <0>;
583 compatible = "snps,designware-i2c";
584 reg = <0xffc02600 0x100>;
585 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&l4_sp_clk>;
587 status = "disabled";
588 };
589
590 spi1: spi@ffda5000 {
591 compatible = "snps,dw-apb-ssi";
592 #address-cells = <1>;
593 #size-cells = <0>;
594 reg = <0xffda5000 0x100>;
595 interrupts = <0 102 4>;
596 num-chipselect = <4>;
597 bus-num = <0>;
598 /*32bit_access;*/
599 tx-dma-channel = <&pdma 16>;
600 rx-dma-channel = <&pdma 17>;
601 clocks = <&spi_m_clk>;
602 status = "disabled";
603 };
604
605 sdr: sdr@ffc25000 {
606 compatible = "altr,sdr-ctl", "syscon";
607 reg = <0xffcfb100 0x80>;
608 };
609
610 L2: l2-cache@fffff000 {
611 compatible = "arm,pl310-cache";
612 reg = <0xfffff000 0x1000>;
613 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
614 cache-unified;
615 cache-level = <2>;
616 prefetch-data = <1>;
617 prefetch-instr = <1>;
618 arm,shared-override;
619 };
620
621 mmc: dwmmc0@ff808000 {
622 #address-cells = <1>;
623 #size-cells = <0>;
624 compatible = "altr,socfpga-dw-mshc";
625 reg = <0xff808000 0x1000>;
626 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
627 fifo-depth = <0x400>;
628 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
629 clock-names = "biu", "ciu";
630 status = "disabled";
631 };
632
633 nand: nand@ffb90000 {
634 #address-cells = <1>;
635 #size-cells = <1>;
636 compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
637 reg = <0xffb90000 0x72000>,
638 <0xffb80000 0x10000>;
639 reg-names = "nand_data", "denali_reg";
640 interrupts = <0 99 4>;
641 dma-mask = <0xffffffff>;
642 clocks = <&nand_clk>;
643 status = "disabled";
644 };
645
646 ocram: sram@ffe00000 {
647 compatible = "mmio-sram";
648 reg = <0xffe00000 0x40000>;
649 };
650
651 eccmgr: eccmgr {
652 compatible = "altr,socfpga-a10-ecc-manager";
653 altr,sysmgr-syscon = <&sysmgr>;
654 #address-cells = <1>;
655 #size-cells = <1>;
656 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
657 <0 0 IRQ_TYPE_LEVEL_HIGH>;
658 interrupt-controller;
659 #interrupt-cells = <2>;
660 ranges;
661
662 sdramedac {
663 compatible = "altr,sdram-edac-a10";
664 altr,sdr-syscon = <&sdr>;
665 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
666 <49 IRQ_TYPE_LEVEL_HIGH>;
667 };
668
669 l2-ecc@ffd06010 {
670 compatible = "altr,socfpga-a10-l2-ecc";
671 reg = <0xffd06010 0x4>;
672 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
673 <32 IRQ_TYPE_LEVEL_HIGH>;
674 };
675
676 ocram-ecc@ff8c3000 {
677 compatible = "altr,socfpga-a10-ocram-ecc";
678 reg = <0xff8c3000 0x400>;
679 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
680 <33 IRQ_TYPE_LEVEL_HIGH>;
681 };
682
683 emac0-rx-ecc@ff8c0800 {
684 compatible = "altr,socfpga-eth-mac-ecc";
685 reg = <0xff8c0800 0x400>;
686 altr,ecc-parent = <&gmac0>;
687 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
688 <36 IRQ_TYPE_LEVEL_HIGH>;
689 };
690
691 emac0-tx-ecc@ff8c0c00 {
692 compatible = "altr,socfpga-eth-mac-ecc";
693 reg = <0xff8c0c00 0x400>;
694 altr,ecc-parent = <&gmac0>;
695 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
696 <37 IRQ_TYPE_LEVEL_HIGH>;
697 };
698
699 dma-ecc@ff8c8000 {
700 compatible = "altr,socfpga-dma-ecc";
701 reg = <0xff8c8000 0x400>;
702 altr,ecc-parent = <&pdma>;
703 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
704 <42 IRQ_TYPE_LEVEL_HIGH>;
705 };
706
707 usb0-ecc@ff8c8800 {
708 compatible = "altr,socfpga-usb-ecc";
709 reg = <0xff8c8800 0x400>;
710 altr,ecc-parent = <&usb0>;
711 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
712 <34 IRQ_TYPE_LEVEL_HIGH>;
713 };
714 };
715
716 qspi: spi@ff809000 {
717 compatible = "cdns,qspi-nor";
718 #address-cells = <1>;
719 #size-cells = <0>;
720 reg = <0xff809000 0x100>,
721 <0xffa00000 0x100000>;
722 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
723 cdns,fifo-depth = <128>;
724 cdns,fifo-width = <4>;
725 cdns,trigger-address = <0x00000000>;
726 clocks = <&qspi_clk>;
727 status = "disabled";
728 };
729
730 rst: rstmgr@ffd05000 {
731 #reset-cells = <1>;
732 compatible = "altr,rst-mgr";
733 reg = <0xffd05000 0x100>;
734 altr,modrst-offset = <0x20>;
735 };
736
737 scu: snoop-control-unit@ffffc000 {
738 compatible = "arm,cortex-a9-scu";
739 reg = <0xffffc000 0x100>;
740 };
741
742 sysmgr: sysmgr@ffd06000 {
743 compatible = "altr,sys-mgr", "syscon";
744 reg = <0xffd06000 0x300>;
745 cpu1-start-addr = <0xffd06230>;
746 };
747
748 /* Local timer */
749 timer@ffffc600 {
750 compatible = "arm,cortex-a9-twd-timer";
751 reg = <0xffffc600 0x100>;
752 interrupts = <1 13 0xf04>;
753 clocks = <&mpu_periph_clk>;
754 };
755
756 timer0: timer0@ffc02700 {
757 compatible = "snps,dw-apb-timer";
758 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
759 reg = <0xffc02700 0x100>;
760 clocks = <&l4_sp_clk>;
761 clock-names = "timer";
762 };
763
764 timer1: timer1@ffc02800 {
765 compatible = "snps,dw-apb-timer";
766 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
767 reg = <0xffc02800 0x100>;
768 clocks = <&l4_sp_clk>;
769 clock-names = "timer";
770 };
771
772 timer2: timer2@ffd00000 {
773 compatible = "snps,dw-apb-timer";
774 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
775 reg = <0xffd00000 0x100>;
776 clocks = <&l4_sys_free_clk>;
777 clock-names = "timer";
778 };
779
780 timer3: timer3@ffd00100 {
781 compatible = "snps,dw-apb-timer";
782 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
783 reg = <0xffd01000 0x100>;
784 clocks = <&l4_sys_free_clk>;
785 clock-names = "timer";
786 };
787
788 uart0: serial0@ffc02000 {
789 compatible = "snps,dw-apb-uart";
790 reg = <0xffc02000 0x100>;
791 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
792 reg-shift = <2>;
793 reg-io-width = <4>;
794 clocks = <&l4_sp_clk>;
795 status = "disabled";
796 };
797
798 uart1: serial1@ffc02100 {
799 compatible = "snps,dw-apb-uart";
800 reg = <0xffc02100 0x100>;
801 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
802 reg-shift = <2>;
803 reg-io-width = <4>;
804 clocks = <&l4_sp_clk>;
805 status = "disabled";
806 };
807
808 usbphy0: usbphy {
809 #phy-cells = <0>;
810 compatible = "usb-nop-xceiv";
811 status = "okay";
812 };
813
814 usb0: usb@ffb00000 {
815 compatible = "snps,dwc2";
816 reg = <0xffb00000 0xffff>;
817 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&usb_clk>;
819 clock-names = "otg";
820 resets = <&rst USB0_RESET>;
821 reset-names = "dwc2";
822 phys = <&usbphy0>;
823 phy-names = "usb2-phy";
824 status = "disabled";
825 };
826
827 usb1: usb@ffb40000 {
828 compatible = "snps,dwc2";
829 reg = <0xffb40000 0xffff>;
830 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&usb_clk>;
832 clock-names = "otg";
833 resets = <&rst USB1_RESET>;
834 reset-names = "dwc2";
835 phys = <&usbphy0>;
836 phy-names = "usb2-phy";
837 status = "disabled";
838 };
839
840 watchdog0: watchdog@ffd00200 {
841 compatible = "snps,dw-wdt";
842 reg = <0xffd00200 0x100>;
843 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&l4_sys_free_clk>;
845 status = "disabled";
846 };
847
848 watchdog1: watchdog@ffd00300 {
849 compatible = "snps,dw-wdt";
850 reg = <0xffd00300 0x100>;
851 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&l4_sys_free_clk>;
853 status = "disabled";
854 };
855 };
856};