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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/A1H RSK board
4 *
5 * Copyright (C) 2016 Renesas Electronics
6 */
7
8/dts-v1/;
9#include "r7s72100.dtsi"
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
13
14/ {
15 model = "RSKRZA1";
16 compatible = "renesas,rskrza1", "renesas,r7s72100";
17
18 aliases {
19 serial0 = &scif2;
20 };
21
22 chosen {
23 bootargs = "ignore_loglevel";
24 stdout-path = "serial0:115200n8";
25 };
26
27 memory@8000000 {
28 device_type = "memory";
29 reg = <0x08000000 0x02000000>;
30 };
31
32 keyboard {
33 compatible = "gpio-keys";
34
35 pinctrl-names = "default";
36 pinctrl-0 = <&keyboard_pins>;
37
38 key-1 {
39 interrupt-parent = <&irqc>;
40 interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
41 linux,code = <KEY_1>;
42 label = "SW1";
43 wakeup-source;
44 };
45
46 key-2 {
47 interrupt-parent = <&irqc>;
48 interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
49 linux,code = <KEY_2>;
50 label = "SW2";
51 wakeup-source;
52 };
53
54 key-3 {
55 interrupt-parent = <&irqc>;
56 interrupts = <5 IRQ_TYPE_EDGE_BOTH>;
57 linux,code = <KEY_3>;
58 label = "SW3";
59 wakeup-source;
60 };
61 };
62
63 lbsc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 };
67
68 leds {
69 compatible = "gpio-leds";
70
71 led0 {
72 gpios = <&port7 1 GPIO_ACTIVE_LOW>;
73 };
74
75 led1 {
76 gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>;
77 };
78
79 led2 {
80 gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>;
81 };
82
83 led3 {
84 gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>;
85 };
86 };
87};
88
89&extal_clk {
90 clock-frequency = <13330000>;
91};
92
93&i2c3 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&i2c3_pins>;
96 status = "okay";
97
98 clock-frequency = <400000>;
99
100 io_expander1: gpio@20 {
101 compatible = "onnn,cat9554";
102 reg = <0x20>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 };
106
107 io_expander2: gpio@21 {
108 compatible = "onnn,cat9554";
109 reg = <0x21>;
110 gpio-controller;
111 #gpio-cells = <2>;
112 };
113
114 eeprom@50 {
115 compatible = "renesas,r1ex24016", "atmel,24c16";
116 reg = <0x50>;
117 pagesize = <16>;
118 };
119};
120
121&usb_x1_clk {
122 clock-frequency = <48000000>;
123};
124
125&rtc_x1_clk {
126 clock-frequency = <32768>;
127};
128
129&pinctrl {
130 /* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */
131 i2c3_pins: i2c3 {
132 pinmux = <RZA1_PINMUX(1, 6, 1)>, /* RIIC3SCL */
133 <RZA1_PINMUX(1, 7, 1)>; /* RIIC3SDA */
134 };
135
136 keyboard_pins: keyboard {
137 pinmux = <RZA1_PINMUX(1, 9, 3)>, /* IRQ3 */
138 <RZA1_PINMUX(1, 8, 3)>, /* IRQ2 */
139 <RZA1_PINMUX(1, 11, 3)>; /* IRQ5 */
140 };
141
142 /* Serial Console */
143 scif2_pins: serial2 {
144 pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
145 <RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
146 };
147
148 /* Ethernet */
149 ether_pins: ether {
150 /* Ethernet on Ports 1,2,3,5 */
151 pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */
152 <RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */
153 <RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */
154 <RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */
155 <RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */
156 <RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */
157 <RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */
158 <RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */
159 <RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */
160 <RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */
161 <RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */
162 <RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */
163 <RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */
164 <RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */
165 <RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */
166 <RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */
167 <RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */
168 <RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */
169 };
170
171 /* SDHI ch1 on CN1 */
172 sdhi1_pins: sdhi1 {
173 pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */
174 <RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */
175 <RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */
176 <RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */
177 <RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */
178 <RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */
179 <RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */
180 <RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */
181 };
182};
183
184&mtu2 {
185 status = "okay";
186};
187
188ðer {
189 pinctrl-names = "default";
190 pinctrl-0 = <ðer_pins>;
191 status = "okay";
192 renesas,no-ether-link;
193 phy-handle = <&phy0>;
194 phy0: ethernet-phy@0 {
195 reg = <0>;
196 };
197};
198
199&sdhi1 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&sdhi1_pins>;
202 bus-width = <4>;
203 status = "okay";
204};
205
206&ostm0 {
207 status = "okay";
208};
209
210&ostm1 {
211 status = "okay";
212};
213
214&rtc {
215 status = "okay";
216};
217
218&scif2 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&scif2_pins>;
221 status = "okay";
222};
1/*
2 * Device Tree Source for the RZ/A1H RSK board
3 *
4 * Copyright (C) 2016 Renesas Electronics
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r7s72100.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
15
16/ {
17 model = "RSKRZA1";
18 compatible = "renesas,rskrza1", "renesas,r7s72100";
19
20 aliases {
21 serial0 = &scif2;
22 };
23
24 chosen {
25 bootargs = "ignore_loglevel";
26 stdout-path = "serial0:115200n8";
27 };
28
29 memory@8000000 {
30 device_type = "memory";
31 reg = <0x08000000 0x02000000>;
32 };
33
34 lbsc {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 };
38
39 leds {
40 status = "okay";
41 compatible = "gpio-leds";
42
43 led0 {
44 gpios = <&port7 1 GPIO_ACTIVE_LOW>;
45 };
46 };
47};
48
49&extal_clk {
50 clock-frequency = <13330000>;
51};
52
53&usb_x1_clk {
54 clock-frequency = <48000000>;
55};
56
57&rtc_x1_clk {
58 clock-frequency = <32768>;
59};
60
61&pinctrl {
62
63 /* Serial Console */
64 scif2_pins: serial2 {
65 pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
66 <RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
67 };
68
69 /* Ethernet */
70 ether_pins: ether {
71 /* Ethernet on Ports 1,2,3,5 */
72 pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */
73 <RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */
74 <RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */
75 <RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */
76 <RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */
77 <RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */
78 <RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */
79 <RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */
80 <RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */
81 <RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */
82 <RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */
83 <RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */
84 <RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */
85 <RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */
86 <RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */
87 <RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */
88 <RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */
89 <RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */
90 };
91
92 /* SDHI ch1 on CN1 */
93 sdhi1_pins: sdhi1 {
94 pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */
95 <RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */
96 <RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */
97 <RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */
98 <RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */
99 <RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */
100 <RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */
101 <RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */
102 };
103};
104
105&mtu2 {
106 status = "okay";
107};
108
109ðer {
110 pinctrl-names = "default";
111 pinctrl-0 = <ðer_pins>;
112 status = "okay";
113 renesas,no-ether-link;
114 phy-handle = <&phy0>;
115 phy0: ethernet-phy@0 {
116 reg = <0>;
117 };
118};
119
120&sdhi1 {
121 pinctrl-names = "default";
122 pinctrl-0 = <&sdhi1_pins>;
123 bus-width = <4>;
124 status = "okay";
125};
126
127&ostm0 {
128 status = "okay";
129};
130
131&ostm1 {
132 status = "okay";
133};
134
135&rtc {
136 status = "okay";
137};
138
139&scif2 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&scif2_pins>;
142 status = "okay";
143};